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2020-07-24Update language to comply with Android’s inclusive language guidanceIan Pedowitz
See https://source.android.com/setup/contribute/respectful-code for reference Bug: 161896447 Bug: 161850439 Bug: 161336379 Test: m -j checkbuild cts docs tests Change-Id: I32d869c274a5d9a3dac63221e25874fe685d38c4
2020-05-15Optimizing: Run gtests without creating the Runtime.Vladimir Marko
The only Optimizing test that actually needs a Runtime is the ReferenceTypePropagationTest, so we make it subclass CommonCompilerTest explicitly and change OptimizingUnitTest to subclass CommonArtTest for the other tests. On host, each test that initializes the Runtime takes ~220ms more than without initializing the Runtime. For example, the ConstantFoldingTest that has 10 individual tests previously took over 2.2s to run but without the Runtime initialization it takes around 3-5ms. On target, running 32-bit gtests on taimen with run-gtests.sh (single-threaded) goes from ~28m47s to ~26m13s, a reduction of ~9%. Test: m test-art-host-gtest Test: run-gtests.sh Change-Id: I43e50ed58e52cc0ad04cdb4d39801bfbae840a3d
2020-02-13Remove MIPS support from Optimizing.Vladimir Marko
Test: aosp_taimen-userdebug boots. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Bug: 147346243 Change-Id: I97fdc15e568ae3fe390efb1da690343025f84944
2019-11-20ARM64: Pass simd half floating point feature to VIXL macroassembler.Usama Arif
VIXL requires NEONHalf CPUFeature to emit half floating points NEON instructions. Test: codegen_test Change-Id: I797d7a27087103491871e86d283f9860d3f20624
2019-10-14Revert "Make compiler/optimizing/ symbols hidden."Vladimir Marko
This reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf. Reason for revert: Breaks ASAN tests (ODR violation). Bug: 142365358 Change-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4
2019-10-14Make compiler/optimizing/ symbols hidden.Vladimir Marko
Make symbols in compiler/optimizing hidden by a namespace attribute. The unit intrinsic_objects.{h,cc} is excluded as it is needed by dex2oat. As the symbols are no longer exported, gtests are now linked with the static version of the libartd-compiler library. libart-compiler.so size: - before: arm: 2396152 arm64: 3345280 - after: arm: 2016176 (-371KiB, -15.9%) arm64: 2874480 (-460KiB, -14.1%) Test: m test-art-host-gtest Test: testrunner.py --host --optimizing --jit Bug: 142365358 Change-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8
2019-08-02ART: ARM64: Optimize frame size for SIMD graphs.Artem Serov
For SIMD graphs allocate 64 bit instead of 128 bit on stack for each FP register to be preserved by the callee in the frame entry as ABI suggests (currently 64-bit registers are preserved but more space on stack is allocated). Note: slow paths still require spilling full 128-bit Q-Registers for SIMD graphs due to register allocator restrictions. Test: test-art-target. Change-Id: Ie0b12e4b769158445f3d0f4562c70d4fb0ea7744
2018-12-03ART: ARM64: Pass ISA features to VIXL macroassembler.Artem Serov
VIXL macroassembler should be initialized properly to support Armv8.X features in order to emit corresponding instructions. Test: codegen_test.cc, relative_patcher_arm64_test. Test: test-art-host, test-art-target. Change-Id: I2f9e155c28b4d2252a3cfb19717f5d25824d5e11
2018-08-20Fix longstanding bug around implicit NPEs and GC, version 2.Nicolas Geoffray
The TODO has been there since M (so forever :)): https://android-review.googlesource.com/c/platform/art/+/122794/13//COMMIT_MSG#13 We hardly see the issue in our tests as we need to have: 1) A GC happening while creating the NPE object. 2) ParallelMoves between the NullCheck and implicit null check operation that moves references. The CL piggy backs on the "IsEmittedAtUseSite" flag, to set implicit null checks with it. The liveness analysis then special cases implicit null checks to record environment uses at the location of the actual instruction that will do the implicit null check. Test: test.py --gcstress Test: run-libcore-tests --gcstress bug: 111545159 Change-Id: I3ecea4fe0d7e483e93db83281ca10db47da228c5
2018-06-25Move instruction_set_ to CompilerOptions.Vladimir Marko
Removes CompilerDriver dependency from ImageWriter and several other classes. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Test: Pixel 2 XL boots. Test: m test-art-target-gtest Test: testrunner.py --target --optimizing Change-Id: I3c5b8ff73732128b9c4fad9405231a216ea72465
2018-03-05Move most of runtime/base to libartbase/baseDavid Sehr
Enforce the layering that code in runtime/base should not depend on runtime by separating it into libartbase. Some of the code in runtime/base depends on the Runtime class, so it cannot be moved yet. Also, some of the tests depend on CommonRuntimeTest, which itself needs to be factored (in a subsequent CL). Bug: 22322814 Test: make -j 50 checkbuild make -j 50 test-art-host Change-Id: I8b096c1e2542f829eb456b4b057c71421b77d7e2
2018-01-13Change compiler tests to have aligned code itemMathieu Chartier
Previously, the code item was not necessarily 32 bit aligned. This caused bus errors on armv7. Also create a real dexfile object instead of casting 0 initialized memory to a dex file pointer. We just got lucky before that the cdex boolean was false. Test: test-art-target-gtest Bug: 63756964 Bug: 71605148 Change-Id: Ic7199f2b97bbd421de1d702efa5c6531ff45c022
2018-01-05Create dex subdirectoryDavid Sehr
Move all the DexFile related source to a common subdirectory dex/ of runtime. Bug: 71361973 Test: make -j 50 test-art-host Change-Id: I59e984ed660b93e0776556308be3d653722f5223
2017-11-02ART: Make InstructionSet an enum class and add kLast.Vladimir Marko
Adding InstructionSet::kLast shall make it easier to encode the InstructionSet in fewer bits using BitField<>. However, introducing `kLast` into the `art` namespace is not a good idea, so we change the InstructionSet to an enum class. This also uncovered a case of InstructionSet::kNone being erroneously used instead of vixl32::Condition::None(), so it's good to remove `kNone` from the `art` namespace. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Change-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6
2017-10-06ART: Use ScopedArenaAllocator for pass-local data.Vladimir Marko
Passes using local ArenaAllocator were hiding their memory usage from the allocation counting, making it difficult to track down where memory was used. Using ScopedArenaAllocator reveals the memory usage. This changes the HGraph constructor which requires a lot of changes in tests. Refactor these tests to limit the amount of work needed the next time we change that constructor. Test: m test-art-host-gtest Test: testrunner.py --host Test: Build with kArenaAllocatorCountAllocations = true. Bug: 64312607 Change-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a
2017-09-25ART: Introduce compiler data type.Vladimir Marko
Replace most uses of the runtime's Primitive in compiler with a new class DataType. This prepares for introducing new types, such as Uint8, that the runtime does not need to know about. Test: m test-art-host-gtest Test: testrunner.py --host Bug: 23964345 Change-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c
2017-07-14Remove the old ARM code generator from ART's Optimizing compiler.Roland Levillain
The AArch32 VIXL-based code generator has been the default ARM code generator in ART for some time now. The old ARM code generator does not compile anymore; retiring it. Test: test.py Bug: 63316036 Change-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db
2017-05-11Clean up some uses of "auto".Vladimir Marko
Make actual types more explicit, either by replacing "auto" with actual type or by assigning std::pair<> elements of an "auto" variable to typed variables. Avoid binding const references to temporaries. Avoid copying a container. Test: m test-art-host-gtest Change-Id: I1a59f9ba1ee15950cacfc5853bd010c1726de603
2017-05-03Improve the documentation of an ARM64 parallel move resolver corner case.Roland Levillain
Test: m test-art-host-gtest-codegen_test Bug: 34760542 Bug: 34834461 Change-Id: I7e716c4b665ed51af9908042f88fb2e4bcefb849
2017-04-10ARM64: Support 128-bit registers for SIMD.Artem Serov
Test: test-art-host, test-art-target Change-Id: Ifb931a99d34ea77602a0e0781040ed092de9faaa
2017-02-02Merge "AArch64: Add HInstruction scheduling support."Treehugger Robot
2017-01-30Handle cycles with double stack slots in ARM64 parallel moves.Roland Levillain
When acquiring a scratch register to emit a move between two double stack slots, ask for a FP register first, to avoid depleting the core scratch register pool, which is used in vixl::aarch64::MacroAssembler::LoadStoreMacro when the offset does not fit in the immediate field of the load instruction. Test: make test-art-target (on ARM64) Bug: 34760542 Change-Id: Ie9b37d007ed6ec5886931a35dcb22a9aff73bbbe
2017-01-25AArch64: Add HInstruction scheduling support.Alexandre Rames
This commit adds a new `HInstructionScheduling` pass that performs basic scheduling on the `HGraph`. Currently, scheduling is performed at the block level, so no `HInstruction` ever leaves its block in this pass. The scheduling process iterates through blocks in the graph. For blocks that we can and want to schedule: 1) Build a dependency graph for instructions. It includes data dependencies (inputs/uses), but also environment dependencies and side-effect dependencies. 2) Schedule the dependency graph. This is a topological sort of the dependency graph, using heuristics to decide what node to schedule first when there are multiple candidates. Currently the heuristics only consider instruction latencies and schedule first the instructions that are on the critical path. Test: m test-art-host Test: m test-art-target Change-Id: Iec103177d4f059666d7c9626e5770531fbc5ccdc
2017-01-09Fix some issues reported by ValgrindAnton Kirilov
* Update the target suppression file. * Disable the detection of mismatched free() / delete / delete [] calls, since it results in a lot of false positives (a known Valgrind limitation associated with asymmetric inlining of operator new() and operator delete()). * Avoid a memory leak in the code generator tests, caused by the fact that the VIXL-based ARM code generator does not always use the arena allocator. * Fix an access to uninitialized memory. Test: m valgrind-test-art-target Test: valgrind --leak-check=full --show-mismatched-frees=no \ --ignore-range-below-sp=1024-1 \ --suppressions=valgrind-target-suppressions.txt \ dalvikvm ... Change-Id: I891a3247aa9828226b4e62c69d6e1c8398d757b8
2017-01-05ARM: VIXL32: Fix crash in Exchange for stack slots.Artem Serov
In ParallelMoveResolverARMVIXL::Exchange(int mem1, int mem2) scratch general purpose register was used without any spilling (like in StoreToOffset) which led to lack of scratch register for VLDR with big offset. Now it uses two scratch S-registers. Test: ART_USE_VIXL_ARM_BACKEND=true m test-art-host Test: ART_USE_VIXL_ARM_BACKEND=true m test-art-target Change-Id: I0416a69e281d09a04dd1689efa5a8c1994c82638
2016-11-08ART: Fix tidy warningsAndreas Gampe
Switch to char versions of find variants. Add "explicit" constructor variants or refactor and remove defaults. Use const references. Bug: 32619234 Test: m test-art-host Change-Id: I970cc2f47d6cf8f0c74104b994b075b2fafb3d45
2016-10-18Delete unused blocked_register_pairs_ in code generatorsMathieu Chartier
Legacy code for compatibility with quick? Test: test-art-host CC Change-Id: I9de261daea67dfd9bd3df89826ba9d10f135e29e
2016-09-22Revert "Revert "ARM: VIXL32: Add an initial code generator that passes ↵Scott Wakeling
codegen_tests."" This VIXL32-based code generator is not enabled in the optimizing compiler by default. Changes in codegen_test.cc test it in parallel with the existing ARM backend. This patch provides a base for further work, the new backend will not be enabled in the optimizing compiler until parity is proven with the current ARM backend and assembler. Test: gtest-codegen_test on host and target This reverts commit 7863a2152865a12ad9593d8caad32698264153c1. Change-Id: Ia09627bac22e78732ca982d207dc0b00bda435bb
2016-09-21Merge "Revert "ARM: VIXL32: Add an initial code generator that passes ↵Nicolas Geoffray
codegen_tests.""
2016-09-21Revert "ARM: VIXL32: Add an initial code generator that passes codegen_tests."Nicolas Geoffray
Failing with: art/compiler/optimizing/code_generator_arm_vixl.cc:396:47: error: too few arguments to function call, expected 3, have 2 ValidateInvokeRuntime(instruction, slow_path); This reverts commit b138dfbd76f9d8b64fb9dbaf1a7c25e2549b2a8c. Change-Id: Idccfe076f5905ea92ecbe3afbc7c8c64ecda94be
2016-09-21Merge "ARM: VIXL32: Add an initial code generator that passes codegen_tests."Roland Levillain
2016-09-15ARM: VIXL32: Add an initial code generator that passes codegen_tests.Scott Wakeling
This VIXL32-based code generator is not enabled in the optimizing compiler by default. Changes in codegen_test.cc test it in parallel with the existing ARM backend. This patch provides a base for further work, the new backend will not be enabled in the optimizing compiler until parity is proven with the current ARM backend and assembler. Test: gtest-codegen_test on host and target Change-Id: Id556a975b2645bf1d98ab2984650e8435b2312c2
2016-09-14MIPS: Enable the ComparisonsLong test in the code generator test.Alexey Frunze
Test: test-art-host-gtest-codegen_test Test: test-art-target-gtest-codegen_test (MIPS32R2 & R6, MIPS64) Change-Id: Ieae0fdb2ed30f262baac0eb7c6b658341c511a47
2016-09-07Allow for testing alternative code generators in codegen_test.ccScott Wakeling
This will be used in a later patch to test a new VIXL32-based backend in parallel with the existing code_generator_arm. Test: gtest-codegen_test on host and target Change-Id: I0316da0430fa6da0a7c668315f531888d18e7eb3
2016-09-01MIPS32: Ensure preservation of RA in leaf methods if it's clobberedAlexey Frunze
Test: booted MIPS32 in QEMU Test: test-art-host-gtest Test: test-art-target-gtest-codegen_test in QEMU Test: test-art-target-run-test-optimizing on CI20 Change-Id: Ia3da5902d967cd7af313f03ebf414320b0063619
2016-08-19Fix building tests with partial arch codegen supportColin Cross
Add conditionals around more code that is only used for codegen for specific architectures, and move a few more files into the architecture-specific codegen lists. Tests: ART_HOST_CODEGEN_ARCHS="x86_64 mips" m -j ART_TARGET_CODEGEN_ARCHS=svelte test-art-host Bug: 30928847 Change-Id: I0444d15e1cafe4c9b13ff78718c3b13b544270e7
2016-08-11Use TestCodeGeneratorX86 in codegen unit testsMatthew Gharrity
The codegen unit tests are supposed to use special "test" code generators when targeting ARM and x86 (due to differing calling conventions between the C++ source code and the generated code), yet TestCodeGeneratorX86 was not being used. This fixes that. (The tests were only succeeding because the register allocator happened to not assign the EBX register.) Test: m test-art-host-gtest-codegen_test Change-Id: Ia3dd6998c38e9ff27b8c2734457f86b3fed44ab4
2016-07-20Refactor register allocation to be pluggableMatthew Gharrity
Allow alternate register allocation strategies to be implemented in subclasses of a common register allocation base class. Test: m test-art-host Change-Id: I7c5866aa9ddff8f53fcaf721bad47654ab221b4f
2016-07-15Rename current register allocator implementationMatthew Gharrity
This will allow a cleaner commit in an upcoming refactoring of register allocation. Test: m test-art-host Change-Id: If420c97b088b3c934411ff83373e024003120746
2016-02-15ART: Run SsaBuilder from HGraphBuilderDavid Brazdil
First step towards merging the two passes, which will later result in HGraphBuilder directly producing SSA form. This CL mostly just updates tests broken by not being able to inspect the pre-SSA form. Using HLocals outside the HGraphBuilder is now deprecated. Bug: 27150508 Change-Id: I00fb6050580f409dcc5aa5b5aa3a536d6e8d759e
2016-02-12ART: Remove HTemporaryDavid Brazdil
Change-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03
2016-01-28ART: Fix gtest after liveness CLDavid Brazdil
Change-Id: I2d029044cebe6e1ee7d7efb2e20541060f88c07c
2016-01-18ART: Remove Baseline compilerDavid Brazdil
We don't need Baseline any more and it hasn't been maintained for a while anyway. Let's remove it. Change-Id: I442ed26855527be2df3c79935403a25b1ee55df6
2015-11-06Revert "Revert "Introduce support for hardware simulators, starting with ARM64""Phil Wang
This reverts commit 4cd27d64b0bbdde61fa3f6674ceb24221853ac2c. This depends on VIXL 1.11. Change-Id: I402c1fd6bbb218ba80ef8e59af203c9276151059
2015-10-22MIPS: Initial version of optimizing compiler for MIPS32Goran Jakovljevic
Change-Id: I370388e8d5de52c7001552b513877ef5833aa621
2015-10-14Added support for unsigned comparisonsAart Bik
Rationale: even though not directly supported in input graph, having the ability to express unsigned comparisons in HIR is useful for all sorts of optimizations. Change-Id: I4543c96a8c1895c3d33aaf85685afbf80fe27d72
2015-10-08Add DCHECKs to ArenaVector and ScopedArenaVector.Vladimir Marko
Implement dchecked_vector<> template that DCHECK()s element access and insert()/emplace()/erase() positions. Change the ArenaVector<> and ScopedArenaVector<> aliases to use the new template instead of std::vector<>. Remove DCHECK()s that have now become unnecessary from the Optimizing compiler. Change-Id: Ib8506bd30d223f68f52bd4476c76d9991acacadc
2015-09-16Optimizing: Tag arena allocations in HGraph.Vladimir Marko
Replace GrowableArray with ArenaVector in HGraph and related classes HEnvironment, HLoopInformation, HInvoke and HPhi, and tag allocations with new arena allocation types. Change-Id: I3d79897af405b9a1a5b98bfc372e70fe0b3bc40d
2015-09-08Optimizing: Tag basic block allocations with their source.Vladimir Marko
Replace GrowableArray with ArenaVector in HBasicBlock and, to track the source of allocations, assign one new and two Quick's arena allocation types to these vectors. Rename kArenaAllocSuccessor to kArenaAllocSuccessors. Bug: 23736311 Change-Id: Ib52e51698890675bde61f007fe6039338cf1a025
2015-09-03Revert "Optimizing: Tag basic block allocations with their source."Vladimir Marko
Reverting so that we can have more discussion about the STL API. This reverts commit 91e11c0c840193c6822e66846020b6647de243d5. Change-Id: I187fe52f2c16b6e7c5c9d49c42921eb6c7063dba
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