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| author | Scott Wakeling <scott.wakeling@linaro.org> | 2016-07-26 10:33:29 +0100 |
|---|---|---|
| committer | Scott Wakeling <scott.wakeling@linaro.org> | 2016-09-15 16:17:01 +0100 |
| commit | b138dfbd76f9d8b64fb9dbaf1a7c25e2549b2a8c (patch) | |
| tree | a3765fd2bd7e5ddd7ec81adab1ec36859f193d94 /compiler/optimizing/codegen_test.cc | |
| parent | 5cfaafbda5d2de57e311cfc9051f8d817091e950 (diff) | |
ARM: VIXL32: Add an initial code generator that passes codegen_tests.
This VIXL32-based code generator is not enabled in the optimizing
compiler by default. Changes in codegen_test.cc test it in parallel
with the existing ARM backend.
This patch provides a base for further work, the new backend will not
be enabled in the optimizing compiler until parity is proven with the
current ARM backend and assembler.
Test: gtest-codegen_test on host and target
Change-Id: Id556a975b2645bf1d98ab2984650e8435b2312c2
Diffstat (limited to 'compiler/optimizing/codegen_test.cc')
| -rw-r--r-- | compiler/optimizing/codegen_test.cc | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/compiler/optimizing/codegen_test.cc b/compiler/optimizing/codegen_test.cc index d9347f604e..e8d6bae1b5 100644 --- a/compiler/optimizing/codegen_test.cc +++ b/compiler/optimizing/codegen_test.cc @@ -41,6 +41,7 @@ #include "register_allocator_linear_scan.h" #include "ssa_liveness_analysis.h" #include "utils.h" +#include "utils/arm/assembler_arm_vixl.h" #include "utils/arm/managed_register_arm.h" #include "utils/mips/managed_register_mips.h" #include "utils/mips64/managed_register_mips64.h" @@ -48,6 +49,7 @@ #ifdef ART_ENABLE_CODEGEN_arm #include "code_generator_arm.h" +#include "code_generator_arm_vixl.h" #endif #ifdef ART_ENABLE_CODEGEN_arm64 @@ -117,6 +119,28 @@ class TestCodeGeneratorARM : public arm::CodeGeneratorARM { blocked_register_pairs_[arm::R6_R7] = false; } }; + +// A way to test the VIXL32-based code generator on ARM. This will replace +// TestCodeGeneratorARM when the VIXL32-based backend replaces the existing one. +class TestCodeGeneratorARMVIXL : public arm::CodeGeneratorARMVIXL { + public: + TestCodeGeneratorARMVIXL(HGraph* graph, + const ArmInstructionSetFeatures& isa_features, + const CompilerOptions& compiler_options) + : arm::CodeGeneratorARMVIXL(graph, isa_features, compiler_options) { + AddAllocatedRegister(Location::RegisterLocation(arm::R6)); + AddAllocatedRegister(Location::RegisterLocation(arm::R7)); + } + + void SetupBlockedRegisters() const OVERRIDE { + arm::CodeGeneratorARMVIXL::SetupBlockedRegisters(); + blocked_core_registers_[arm::R4] = true; + blocked_core_registers_[arm::R6] = false; + blocked_core_registers_[arm::R7] = false; + // Makes pair R6-R7 available. + blocked_register_pairs_[arm::R6_R7] = false; + } +}; #endif #ifdef ART_ENABLE_CODEGEN_x86 @@ -296,6 +320,13 @@ CodeGenerator* create_codegen_arm(HGraph* graph, const CompilerOptions& compiler *features_arm.get(), compiler_options); } + +CodeGenerator* create_codegen_arm_vixl32(HGraph* graph, const CompilerOptions& compiler_options) { + std::unique_ptr<const ArmInstructionSetFeatures> features_arm( + ArmInstructionSetFeatures::FromCppDefines()); + return new (graph->GetArena()) + TestCodeGeneratorARMVIXL(graph, *features_arm.get(), compiler_options); +} #endif #ifdef ART_ENABLE_CODEGEN_arm64 @@ -351,6 +382,7 @@ static ::std::vector<CodegenTargetConfig> GetTargetConfigs() { #ifdef ART_ENABLE_CODEGEN_arm CodegenTargetConfig(kArm, create_codegen_arm), CodegenTargetConfig(kThumb2, create_codegen_arm), + CodegenTargetConfig(kArm, create_codegen_arm_vixl32), #endif #ifdef ART_ENABLE_CODEGEN_arm64 CodegenTargetConfig(kArm64, create_codegen_arm64), |