Remove MIPS support from Optimizing.

Test: aosp_taimen-userdebug boots.
Test: m test-art-host-gtest
Test: testrunner.py --host --optimizing
Bug: 147346243
Change-Id: I97fdc15e568ae3fe390efb1da690343025f84944

1 files changed, 0 insertions, 69 deletions

diff --git a/compiler/optimizing/codegen_test.cc b/compiler/optimizing/codegen_test.cc
index e562a8e34a..d9b4f79e8b 100644
--- a/compiler/optimizing/codegen_test.cc
+++ b/compiler/optimizing/codegen_test.cc
@@ -29,8 +29,6 @@
 #include "register_allocator_linear_scan.h"
 #include "utils/arm/assembler_arm_vixl.h"
 #include "utils/arm/managed_register_arm.h"
-#include "utils/mips/managed_register_mips.h"
-#include "utils/mips64/managed_register_mips64.h"
 #include "utils/x86/managed_register_x86.h"
 
 #include "gtest/gtest.h"
@@ -55,12 +53,6 @@ static ::std::vector<CodegenTargetConfig> GetTargetConfigs() {
 #ifdef ART_ENABLE_CODEGEN_x86_64
     CodegenTargetConfig(InstructionSet::kX86_64, create_codegen_x86_64),
 #endif
-#ifdef ART_ENABLE_CODEGEN_mips
-    CodegenTargetConfig(InstructionSet::kMips, create_codegen_mips),
-#endif
-#ifdef ART_ENABLE_CODEGEN_mips64
-    CodegenTargetConfig(InstructionSet::kMips64, create_codegen_mips64)
-#endif
   };
 
   for (const CodegenTargetConfig& test_config : test_config_candidates) {
@@ -897,65 +889,4 @@ TEST_F(CodegenTest, ARM64FrameSizeNoSIMD) {
 
 #endif
 
-#ifdef ART_ENABLE_CODEGEN_mips
-TEST_F(CodegenTest, MipsClobberRA) {
-  OverrideInstructionSetFeatures(InstructionSet::kMips, "mips32r");
-  CHECK(!instruction_set_features_->AsMipsInstructionSetFeatures()->IsR6());
-  if (!CanExecute(InstructionSet::kMips)) {
-    // HMipsComputeBaseMethodAddress and the NAL instruction behind it
-    // should only be generated on non-R6.
-    return;
-  }
-
-  HGraph* graph = CreateGraph();
-
-  HBasicBlock* entry_block = new (GetAllocator()) HBasicBlock(graph);
-  graph->AddBlock(entry_block);
-  graph->SetEntryBlock(entry_block);
-  entry_block->AddInstruction(new (GetAllocator()) HGoto());
-
-  HBasicBlock* block = new (GetAllocator()) HBasicBlock(graph);
-  graph->AddBlock(block);
-
-  HBasicBlock* exit_block = new (GetAllocator()) HBasicBlock(graph);
-  graph->AddBlock(exit_block);
-  graph->SetExitBlock(exit_block);
-  exit_block->AddInstruction(new (GetAllocator()) HExit());
-
-  entry_block->AddSuccessor(block);
-  block->AddSuccessor(exit_block);
-
-  // To simplify matters, don't create PC-relative HLoadClass or HLoadString.
-  // Instead, generate HMipsComputeBaseMethodAddress directly.
-  HMipsComputeBaseMethodAddress* base = new (GetAllocator()) HMipsComputeBaseMethodAddress();
-  block->AddInstruction(base);
-  // HMipsComputeBaseMethodAddress is defined as int, so just make the
-  // compiled method return it.
-  block->AddInstruction(new (GetAllocator()) HReturn(base));
-
-  graph->BuildDominatorTree();
-
-  mips::CodeGeneratorMIPS codegenMIPS(graph, *compiler_options_);
-  // Since there isn't HLoadClass or HLoadString, we need to manually indicate
-  // that RA is clobbered and the method entry code should generate a stack frame
-  // and preserve RA in it. And this is what we're testing here.
-  codegenMIPS.ClobberRA();
-  // Without ClobberRA() the code would be:
-  //   nal              # Sets RA to point to the jr instruction below
-  //   move  v0, ra     # and the CPU falls into an infinite loop.
-  //   jr    ra
-  //   nop
-  // The expected code is:
-  //   addiu sp, sp, -16
-  //   sw    ra, 12(sp)
-  //   sw    a0, 0(sp)
-  //   nal              # Sets RA to point to the lw instruction below.
-  //   move  v0, ra
-  //   lw    ra, 12(sp)
-  //   jr    ra
-  //   addiu sp, sp, 16
-  RunCode(&codegenMIPS, graph, [](HGraph*) {}, false, 0);
-}
-#endif
-
 }  // namespace art