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2015-09-03Optimizing: Tag basic block allocations with their source.Vladimir Marko
Replace GrowableArray with ArenaVector in HBasicBlock and, to track the source of allocations, assign one new and two Quick's arena allocation types to these vectors. Rename kArenaAllocSuccessor to kArenaAllocSuccessors. Bug: 23736311 Change-Id: I984aef6e615ae2380a532f5c6726af21015f43f5
2015-08-18Revert "Introduce support for hardware simulators, starting with ARM64"Alex Light
This reverts commit c2e1a5edc438274159c6ef8e65455ac73723a8f1. This breaks the build for x86_64 targets. This is because on target the libvixl is not included as a library for the libart.so target build. The build of non-x86_64 targets only works because the compilers removes the dead-code that contains the libvixl symbols. Bug: 23321940 Change-Id: I39e93ff05b887665c47fb0986867f1d13ca65b9b
2015-08-18Fix codegen_test.Roland Levillain
Allow the execution of Thumb-2 code on ARM32 hardware. Change-Id: I2fec71e39d538249569ffa88435f3198e8c28c01
2015-08-18Introduce support for hardware simulators, starting with ARM64Phil Wang
Simulator support for ARM64 is implemented with VIXL. Now codegen_test will also run on all supported hardware simulators. Change-Id: Idc740f566175d1a23c373ea9292b8fc5ba526d00
2015-06-24Fix codegen_test after DCE fix.Nicolas Geoffray
Change-Id: I16c64abc26c64815da4cb4034276d60e9bfb6996
2015-06-19MIPS: Initial version of optimizing compiler for MIPS64R6.Alexey Frunze
Bug: 21555893 Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com> Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
2015-05-11Add a parent environment to HEnvironment.Nicolas Geoffray
This code has no functionality change. It adds a placeholder for chaining inlined frames. Change-Id: I5ec57335af76ee406052345b947aad98a6a4423a
2015-04-20Fix codegen_test for long multiplication.Nicolas Geoffray
It seems like clang (that we use on the host) was *very* forgiving with this broken test: the code generated for for MulLong used ebx but this is a callee-save register in C but not ART. Also, the test was not properly written for handling longs, so it was taking unitialized stack entries. GCC on target is not as forgiving. Change-Id: I5d7a962f8a72b3ce407dce50ca50b4ffc690c99e
2015-04-15Move the linear order to the HGraph.Nicolas Geoffray
Bug found by Zheng Xu: SsaLivenessAnalysis being a stack allocated object, we should not refer to it in later phases of the compiler. Specifically, the code generator was using the linear order, which was stored in the liveness analysis object. Change-Id: I574641f522b7b86fc43f3914166108efc72edb3b
2015-04-01[optimizing] Implement x86/x86_64 math intrinsicsMark Mendell
Implement floor/ceil/round/RoundFloat on x86 and x86_64. Implement RoundDouble on x86_64. Add support for roundss and roundsd on both architectures. Support them in the disassembler as well. Add the instruction set features for x86, as the 'round' instruction is only supported if SSE4.1 is supported. Fix the tests to handle the addition of passing the instruction set features to x86 and x86_64. Add assembler tests for roundsd and roundss to x86_64 assembler tests. Change-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-03-26ART: Force constants into the entry blockDavid Brazdil
Optimizations such as GVN and BCE make the assumption that all constants are located in the entry block of the CFG, but not all passes adhere to this rule. This patch makes constructors of constants private and only accessible to friend classes - HGraph for int/long constants and SsaBuilder for float/double - which ensure that they are placed correctly and not duplicated. Note that the ArenaAllocatorAdapter was modified to not increment the ArenaAllocator's internal reference counter in order to allow for use of ArenaSafeMap inside an arena-allocated objects. Because their destructor is not called, the counter does not get decremented. Change-Id: I36a4fa29ae34fb905cdefd482ccbf386cff14166
2015-03-24ART: Fix crash in gtestsDavid Brazdil
SsaLivenessAnalysis was crashing after change of iteration order in 142377 because gtests do not always build reverse post order. Change-Id: If5ad5b7c52040b119c4415f0b942988049fa3c16
2015-03-02Opt Compiler: ARM64: Enable explicit memory barriers over acquire/releaseSerban Constantinescu
Implement remaining explicit memory barrier code paths and temporarily enable the use of explicit memory barriers for testing. This CL also enables the use of instruction set features in the ARM64 backend. kUseAcquireRelease has been replaced with PreferAcquireRelease(), which for now is statically set to false (prefer explicit memory barriers). Please note that we still prefer acquire-release for the ARM64 Optimizing Compiler, but we would like to exercise the explicit memory barrier code path too. Change-Id: I84e047ecd43b6fbefc5b82cf532e3f5c59076458 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
2015-02-04Create HGraph outside Builder, print timingsDavid Brazdil
This patch refactors the way HGraph objects are created, moving the instantiation out of the Builder class and creating the CodeGenerator earlier. The patch uses this to build a single interface for printing timings info and dumping the CFG. Change-Id: I2eb63eabf28e2d0f5cdc7affaa690c3a4b1bdd21
2015-01-26Fix lint error and typo.Nicolas Geoffray
Change-Id: Ie2787a4da5b2d76975664e64f443c081127b7cd9
2015-01-26Fix codegen_test.Nicolas Geoffray
Native and ART do not have the same calling convention for ART, so we need to adjust blocked and allocated registers. Change-Id: I606b2620c0e5a54bd60d6100a137c06616ad40b4
2015-01-16Add implicit null checks for the optimizing compilerCalin Juravle
- for backends: arm, arm64, x86, x86_64 - fixed parameter passing for CodeGenerator - 003-omnibus-opcodes test verifies that NullPointerExceptions work as expected Change-Id: I1b302acd353342504716c9169a80706cf3aba2c8
2015-01-06ART: Fix leak in codegen_testAndreas Gampe
Make sure the InstructionSetFeatures isn't leaked. Change-Id: Ide25773500c1513ecb204a380bb0a95513ff7276
2015-01-05Look at instruction set features when generating volatiles codeCalin Juravle
Change-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a
2014-12-10Opt compiler: Add arm64 support for register allocation.Alexandre Rames
Change-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7
2014-11-13Instruction set features for ARM64, MIPS and X86.Ian Rogers
Also, refactor how feature strings are handled so they are additive or subtractive. Make MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler rather than #ifdefs that wouldn't have worked in cross-compilation. Add SIMD features for x86/x86-64 proposed in: https://android-review.googlesource.com/#/c/112370/ Bug: 18056890 Change-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666
2014-11-11Revert "Revert "Add support for long-to-int in the optimizing compiler.""Roland Levillain
This reverts commit 3adfd1b4fb20ac2b0217b5d2737bfe30ad90257a. Change-Id: Iacf0c6492d49267e24f1b727dbf6379b21fd02db
2014-11-11Revert "Add support for long-to-int in the optimizing compiler."Roland Levillain
This reverts commit 647b96f29cb81832e698f863884fdba06674c9de. Change-Id: I552f23585463c676acbd547521b4d3ee5c0342eb
2014-11-11Fix lint error.Calin Juravle
Change-Id: Ief9b9fe6982e7e76aae74d6c909bd9f4b3f82673
2014-11-11Add support for long-to-int in the optimizing compiler.Roland Levillain
- Add support for the long-to-int Dex instruction in the optimizing compiler. - Generate x86, x86-64 and ARM (but not ARM64) code for long-to-int HTypeConversion nodes. - Add related tests to test/422-type-conversion. - Also fix comments in test/415-optimizing-arith-neg and in test/416-optimizing-arith-not. Change-Id: I3084af30f2a495d178362ae1154dc7ceb7bf3a58
2014-11-06Merge "[optimizing compiler] Add DIV_INT_2ADDR"Calin Juravle
2014-11-06[optimizing compiler] Add DIV_INT_2ADDRCalin Juravle
Change-Id: I38fc7e216f820d8ccc8bbf8b8e7a67b75fb9de87
2014-11-06Add support for not-long on ARM64 in the optimizing compiler.Roland Levillain
Change-Id: I3e98ff411ba358d92774def18a12daccdc4f558f
2014-11-06Fix failures after div support.Nicolas Geoffray
- We need to special case divide by -1 because of x86. - Disable div test on arm64, which does not support div yet. Change-Id: I07e137cb555a958b02a6c4070f296503b7e30bae
2014-11-06[optimizing compiler] Add div-int and exception handling.Calin Juravle
- for backends: arm, x86, x86_64 - fixed a register allocator bug: the request for a fixed register for the first input was ignored if the output was kSameAsFirstInput - added divide by zero exception - more tests - shuffle around some code in the builder to reduce the number of lines of code for a single function. Change-Id: Id3a515e02bfbc66cd9d16cb9746f7551bdab3d42
2014-11-04ART: More warningsAndreas Gampe
Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general, and -Wunused-but-set-parameter for GCC builds. Change-Id: I81bbdd762213444673c65d85edae594a523836e5
2014-10-29Opt compiler: Add ARM64 support for the Mul IR.Alexandre Rames
Also disable compilation and use of the boot image with the optimizing compiler: this won't work with the way we're bringing up arm64 and we need to find a better solution. Bug: 18147756 Change-Id: I6ec0de73681f9226d095bc3db92338dbd46499aa
2014-10-23ART: Add basic tests for materialized conditions.Alexandre Rames
Change-Id: I4acef30cc6a48b5fe07d55db6b9cf0d093b326ee
2014-10-23ART: optimizing compiler: initial support for ARM64.Alexandre Rames
The ARM64 port uses VIXL for code generation, to which it defers work like label binding and branch resolving, register type coherency checking, and immediate values handling. Change-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com> Signed-off-by: Alexandre Rames <alexandre.rames@arm.com>
2014-10-23Remove obsolete TODOs from codegen testsCalin Juravle
The features are already exercised by the art test 411-optimizing-arith. Change-Id: Id008931e0ed8206ced11ecc85a80a7e4aef3e68e
2014-10-23Implement int bit-wise not operation in the optimizing compiler.Roland Levillain
- Add support for the not-int (integer one's complement negate) instruction in the optimizing compiler. - Extend the HNot control-flow graph node type and make it inherit from HUnaryOperation. - Generate ARM, x86 and x86-64 code for integer HNeg nodes. - Exercise these additions in the codegen_test gtest, as there is not direct way to assess the support of not-int from a Java source. Indeed, compiling a Java expression such as `~a' using javac and then dx generates an xor-int/lit8 Dex instruction instead of the expected not-int Dex instruction. This is probably because the Java bytecode has an `ixor' instruction, but there's not instruction directly corresponding to a bit-wise not operation. Change-Id: I223aed75c4dac5785e04d99da0d22e8d699aee2b
2014-10-22Minor fix in codegen tests.Calin Juravle
Change-Id: I9b843536353d4f820b969895d5f75ee9b679aff0
2014-10-17Add multiplication for integral typesCalin Juravle
This also fixes an issue where we could allocate a pair register even if one of its parts was already blocked. Change-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01
2014-10-09Fix code generation of materialized conditions.Nicolas Geoffray
Move the logic for knowing if a condition needs to be materialized in an optimization pass (so that the information does not change as a side effect of another optimization). Also clean-up arm and x86_64 codegen: - arm: ldr and str are for power-users when a constant is in play. We should use LoadFromOffset and StoreToOffset. - x86_64: fix misuses of movq instead of movl. Change-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3
2014-09-16Revert "Revert "Implement suspend checks in new compiler.""Nicolas Geoffray
This reverts commit 7e3652c45c30c1f2f840e6088e24e2db716eaea7. Change-Id: Ib489440c34e41cba9e9e297054f9274f6e81a2d8
2014-09-11Fix builds on archs the compiler does not support.Nicolas Geoffray
Change-Id: Ibfc47026596c868fb6d48465a6e564a0b1e07fd0
2014-09-11Fix valgrind errors.Nicolas Geoffray
For now just stack allocate the code generator. Will think about cleaning up the root problem later (CodeGenerator being an arena object). Change-Id: I161a6f61c5f27ea88851b446f3c1e12ee9c594d7
2014-07-22Make unit test tell if a method is a leaf.Nicolas Geoffray
The runtime is not initialized completely in gtests, so we cannot run code (such as explicit stack overflow checks) that look at tls values. Change-Id: I74a4449b01eb203f1b411dda700e9459878d0d55
2014-07-16Use the thumb2 assembler for the optimizing compiler.Nicolas Geoffray
Change-Id: I2b058f4433504dc3299c06f5cb0b5ab12f34aa82
2014-06-26Re-enable tests with the optimizing compiler.Nicolas Geoffray
Tests run ok on my host/target. I reverted the move to using thumb2, because tests were crashing. But I could not reproduce file limits issues. Make SignalTest as crashing for optimizing. We need to implement stack overflow checks. Change-Id: Ieda575501eaf30af7aaa2c44e71544c9c467c24f
2014-06-25Revert "Re-enable tests with the optimizing compiler."Nicolas Geoffray
This reverts commit 20550910e608ed7d86db97927d2ce9d2191061a4. Change-Id: Ic28b719946c795378838a18162a2a2b2cf41a0e8
2014-06-25Re-enable tests with the optimizing compiler.Nicolas Geoffray
Tests run ok on my host/target. I reverted the move to using thumb2, because tests were crashing. But I could not reproduce file limits issues. Change-Id: I26bc4ec1eb6c227750d11210e012d9d3b1d824af
2014-06-24Add some more instruction support to optimizing compiler.Dave Allison
This adds a few more DEX instructions to the optimizing compiler's builder (constants, moves, if_xx, etc). Also: * Changes the codegen for IF_XX instructions to use a condition rather than comparing a value against 0. * Fixes some instructions in the ARM disassembler. * Fixes PushList and PopList in the thumb2 assembler. * Switches the assembler for the optimizing compiler to thumb2 rather than ARM. Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
2014-06-13Guard `Run` for platforms we're not compiling to, yet.Nicolas Geoffray
Change-Id: I0dc210d2734e95714bed6c481a31fa4daabb9332
2014-06-13Add x86_64 support to the optimizing compiler.Nicolas Geoffray
Change-Id: I4462d9ae15be56c4a3dc1bd4d1c0c6548c1b94be
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