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2015-01-30Use the non access check entrypoint when possible.Nicolas Geoffray
Change-Id: I0b53d63141395e26816d5d2ce3fa6a297bb39b54
2015-01-29Small optimization for recursive calls: avoid dex cache.Nicolas Geoffray
Change-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6
2015-01-26Fix codegen_test.Nicolas Geoffray
Native and ART do not have the same calling convention for ART, so we need to adjust blocked and allocated registers. Change-Id: I606b2620c0e5a54bd60d6100a137c06616ad40b4
2015-01-24Support callee-save registers on ARM.Nicolas Geoffray
Change-Id: I7c519b7a828c9891b1141a8e51e12d6a8bc84118
2015-01-23Support callee save floating point registers on x64.Nicolas Geoffray
- Share the computation of core_spill_mask and fpu_spill_mask between backends. - Remove explicit stack overflow check support: we need to adjust them and since they are not tested, they will easily bitrot. Change-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a
2015-01-21Enable core callee-save on x64.Nicolas Geoffray
Will work on other architectures and FP support in other CLs. Change-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d
2015-01-21Merge "Do not use HNot for creating !bool."Nicolas Geoffray
2015-01-21Do not use HNot for creating !bool.Nicolas Geoffray
HNot folds to ~, not !. Change-Id: I681f968449a2ade7110b2f316146ad16ba5da74c
2015-01-21Revert "Revert "Fully support pairs in the register allocator.""Nicolas Geoffray
This reverts commit c399fdc442db82dfda66e6c25518872ab0f1d24f. Change-Id: I19f8215c4b98f2f0827e04bf7806c3ca439794e5
2015-01-21Record implicit null checks at the actual invoke time.Calin Juravle
ImplicitNullChecks are recorded only for instructions directly (see NB below) preceeded by NullChecks in the graph. This way we avoid recording redundant safepoints and minimize the code size increase. NB: ParallalelMoves might be inserted by the register allocator between the NullChecks and their uses. These modify the environment and the correct action would be to reverse their modification. This will be addressed in a follow-up CL. Change-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898
2015-01-21Revert "Fully support pairs in the register allocator."Nicolas Geoffray
Libcore tests fail. This reverts commit 41aedbb684ccef76ff8373f39aba606ce4cb3194. Change-Id: I2572f120d4bbaeb7a4d4cbfd47ab00c9ea39ac6c
2015-01-21Fully support pairs in the register allocator.Nicolas Geoffray
Enabled on ARM for longs and doubles. Change-Id: Id8792d08bd7ca9fb049c5db8a40ae694bafc2d8b
2015-01-20Use CompilerOptions for implicit stack overflow checksCalin Juravle
Change-Id: I52744382a7e3d2c6c11a43e027d87bf43ec4e62b
2015-01-20Merge "Add implicit null checks for the optimizing compiler"Calin Juravle
2015-01-19Address review comments.Nicolas Geoffray
Comments were from: https://android-review.googlesource.com/#/c/121992. Change-Id: I8c59b30a356d606f12c50d0c8db916295a5c9e13
2015-01-19Do not use STMP, it conflicts with the calling convention.Nicolas Geoffray
Hard-float calling convention uses S14 and D7 for argument passing, so we cannot use them. Change-Id: I77a2d8c875677640204baebc24355051aa4175fd
2015-01-16Add implicit null checks for the optimizing compilerCalin Juravle
- for backends: arm, arm64, x86, x86_64 - fixed parameter passing for CodeGenerator - 003-omnibus-opcodes test verifies that NullPointerExceptions work as expected Change-Id: I1b302acd353342504716c9169a80706cf3aba2c8
2015-01-16Do not use register pair in a parallel move.Nicolas Geoffray
The ParallelMoveResolver does not work with pairs. Instead, decompose the pair into two individual moves. Change-Id: Ie9d3f0b078cef8dc20640c98b20bb20cc4971a7f
2015-01-15ART: Optimizing compiler intrinsicsAndreas Gampe
Add intrinsics infrastructure to the optimizing compiler. Add almost all intrinsics supported by Quick to the x86-64 backend. Further intrinsics require more assembler support. Change-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807
2015-01-14Merge "Implement ParallelMoveResolver::Swap for doubles on arm."Nicolas Geoffray
2015-01-14Implement ParallelMoveResolver::Swap for doubles on arm.Nicolas Geoffray
Currently reserve a global register DTMP for these operations. Change-Id: Ie88b4696af51834492fd062082335bc2e1137be2
2015-01-14Remove whitespace.Nicolas Geoffray
Change-Id: I82f51cff87765a3aeeb861d2ae64978f2e762c73
2015-01-13Skip r1 on arm if first parameter is a long.Nicolas Geoffray
Change-Id: I16d927ee0a0b55031ade4c92c0095fd74e18ed5b
2015-01-12Fix handling of long argument spanning register/memory.Nicolas Geoffray
Comment in arm_lir.h says: * If a 64-bit argument would span the register/memory argument * boundary, it will instead be fully passed in the frame. This change implements such logic for all platforms. We still need to pass the low part in register as well because I haven't ported the jni compilers (x86 and mips) to it. Once the jni compilers are updated, we can remove the register assignment. Note that this greatly simplifies optimizing's register allocator by not having to understand a long spanning register and memory. Change-Id: I59706ca5d47269fc46e5489ac99bd6576e87e7f3
2015-01-09Don't overwrite a register input.Nicolas Geoffray
`addr` is a register input, which can survive the current instruction, therefore we can't overwrite it. Change-Id: I6eaa60e5f91c2b7b9b31673457d2a0d63474e587
2015-01-08Implement double and float support for arm in register allocator.Nicolas Geoffray
The basic approach is: - An instruction that needs two registers gets two intervals. - When allocating the low part, we also allocate the high part. - When splitting a low (or high) interval, we also split the high (or low) equivalent. - Allocation follows the (S/D register) requirement that low registers are always even and the high equivalent is low + 1. Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
2015-01-06Merge "Look at instruction set features when generating volatiles code"Calin Juravle
2015-01-05Look at instruction set features when generating volatiles codeCalin Juravle
Change-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a
2014-12-29ART: Reorder entrypoint argument orderAndreas Gampe
Shuffle the ArtMethod* referrer backwards for easier removal. Clean up ARM & MIPS assembly code. Change some macros to make future changes easier. Change-Id: Ie2862b68bd6e519438e83eecd9e1611df51d7945
2014-12-19[optimizing compiler] Add support for volatileCalin Juravle
- for backends: arm, x86, x86_64 - added necessary instructions to assemblies - clean up code gen for field set/get - fixed InstructionDataEquals for some instructions - fixed comments in compiler_enums * 003-opcode test verifies basic volatile functionality Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
2014-12-18Merge "Revert "Don't block quick callee saved registers for optimizing.""Nicolas Geoffray
2014-12-18Revert "Don't block quick callee saved registers for optimizing."Nicolas Geoffray
X64 has one libcore test failing, and codegen_test on arm is failing. This reverts commit 6004796d6c630696127df2494dcd4f30d1367a34. Change-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f
2014-12-18Merge "Don't block quick callee saved registers for optimizing."Nicolas Geoffray
2014-12-18Don't block quick callee saved registers for optimizing.Nicolas Geoffray
This change builds on: https://android-review.googlesource.com/#/c/118983/ - Also fix x86_64 assembler bug triggered by this change. - Fix (and improve) x86's backend byte register usage. - Fix a bug in baseline register allocator: a fixed out register must prevent inputs from allocating it. Change-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad
2014-12-17Revert "Small optimization for recursive calls: avoid dex cache."Nicolas Geoffray
Fails on target. This reverts commit 390f59f9bec64fd81b05e796dfaeb03ab6d4cc81. Change-Id: Ic3865b8897068ba20df0fbc2bcf561faf6c290c1
2014-12-17Small optimization for recursive calls: avoid dex cache.Nicolas Geoffray
Change-Id: Ic4054b6c38f0a2a530ba6ef747647f86cee0b1b8
2014-12-15Inlining support in optimizing.Nicolas Geoffray
Currently only inlines simple things that don't require an environment, such as: - Returning a constant. - Returning a parameter. - Returning an arithmetic operation. Change-Id: Ie844950cb44f69e104774a3cf7a8dea66bc85661
2014-12-08[optimizing compiler] Add REM_FLOAT and REM_DOUBLECalin Juravle
- for arm, x86, x86_64 backends - reinstated fmod quick entry points for x86. This is a partial revert of bd3682eada753de52975ae2b4a712bd87dc139a6 which added inline assembly for floting point rem on x86. Note that Quick still uses the inline version. - fix rem tests for longs Change-Id: I73be19a9f2f2bcf3f718d9ca636e67bdd72b5440
2014-12-05Add support for double-to-int & double-to-long in optimizing.Roland Levillain
- Add support for the double-to-int and double-to-long Dex instructions in the optimizing compiler. - Add S1 to the list of ARM FPU parameter registers so that a double value can be passed as parameter during a call to the runtime through D0. - Have art::x86_64::X86_64Assembler::cvttsd2si work with 64-bit operands. - Generate x86, x86-64 and ARM (but not ARM64) code for double to int and double to long HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: Ic93b9ec6630c26e940f7966a3346ad3fd5a2ab3a
2014-12-04Add support for float-to-double & double-to-float in optimizing.Roland Levillain
Change-Id: I41b0fee5a28c83757697c8d000b7e224cf5a4534
2014-12-04Add support for float-to-long in the optimizing compiler.Roland Levillain
- Add support for the float-to-long Dex instruction in the optimizing compiler. - Add a Dex PC field to art::HTypeConversion to allow the x86 and ARM code generators to produce runtime calls. - Instruct art::CodeGenerator::RecordPcInfo not to record PC information for HTypeConversion instructions. - Add S0 to the list of ARM FPU parameter registers. - Have art::x86_64::X86_64Assembler::cvttss2si work with 64-bit operands. - Generate x86, x86-64 and ARM (but not ARM64) code for float to long HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: I954214f0d537187883f83f7a83a1bb2dd8a21fd4
2014-12-03Add support for float-to-int in the optimizing compiler.Roland Levillain
- Add support for the float-to-int Dex instruction in the optimizing compiler. - Factor type conversion related lines in compiler/optimizing/builder.cc. - Generate x86, x86-64 and ARM (but not ARM64) code for float to int HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: I2382dfc04bf394ed75f675148cfcf98216d65bc6
2014-12-01Remove type conversion nodes converting to the same type.Nicolas Geoffray
When optimizing, we ensure these conversions do not reach the code generators. When not optimizing, we cannot get such situations. Change-Id: I717247c957667675dc261183019c88efa3a38452
2014-11-28Don't use CanHoldArm in the code generator.Nicolas Geoffray
CanHoldArm was ARM32 specific. Instead use a virtual Assembler::ShifterOperandCanHold that both thumb2 and arm32 implement. Change-Id: I33794a93caf02ee5d78d32a8471d9fd6fe4f0a00
2014-11-27Add support for long-to-float in the optimizing compiler.Roland Levillain
- Add support for the long-to-float Dex instruction in the optimizing compiler. - Have art::x86_64::X86_64Assembler::cvtsi2ss work with 64-bit operands. - Generate x86, x86-64 and ARM (but not ARM64) code for long to float HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: Ic983cbeb1ae2051add40bc519a8f00a6196166c9
2014-11-27Wrap long lines in the optimizing compiler.Roland Levillain
Change-Id: I5dee0c65e6652de574ae952b1f1dfc7355859e45
2014-11-27Merge "Ensure opt. compiler doesn't get core & FP registers mixed up."Roland Levillain
2014-11-27Fix Move64 by using ParallelMoves.Nicolas Geoffray
Destination and source might overlap in a Move64, so we have to use a parallel move resolver. Change-Id: Ica6c72d91ab8e2e2ee4661b211ac1ee8f054b9ef
2014-11-27Ensure opt. compiler doesn't get core & FP registers mixed up.Roland Levillain
Replace Location::As<T>() with two method methods (Location::AsRegister<T>() and Location::AsFpuRegister<T>()) checking the kind of the location (register). Change-Id: I22b4abee1a124b684becd2dc1caf33652b911070
2014-11-27Merge "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}"Calin Juravle
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