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2017-07-14Remove the old ARM code generator from ART's Optimizing compiler.Roland Levillain
The AArch32 VIXL-based code generator has been the default ARM code generator in ART for some time now. The old ARM code generator does not compile anymore; retiring it. Test: test.py Bug: 63316036 Change-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db
2017-07-11Introduce a Marking Register in ARM64 code generation.Roland Levillain
When generating code for ARM64, maintain the status of Thread::Current()->GetIsGcMarking() in register X20, dubbed MR (Marking Register), and check the value of that register (instead of loading and checking a read barrier marking entrypoint) in read barriers. Test: m test-art-target Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false Test: ARM64 device boot test Bug: 37707231 Change-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b
2017-06-26Fix braino when handling branches fallthrough in arm backend.Nicolas Geoffray
bug: 62210114 Test: 657-branches Change-Id: I753a9a57e404c792cd4375ea66c91839684bdee2
2017-06-15Set the deopt flag after adjusting the stack pointer.Nicolas Geoffray
One should not write to something below the stack pointer, or it could be overwritten during an interrupt. Test: test.py Change-Id: Ie6c997b9f7548ca5844303d6a3fc0c531f469c6e
2017-06-08ART: Refactor bit_utils and stl_utilAndreas Gampe
Move iterator code from bit_utils.h into bit_utils_iterator.h. Move Identity into stl_util_identity.h. Remove now unnecessary includes, and fix up transitive users. Test: m Change-Id: Id1ce9cda66827c5d00584f39ed310b6b37629906
2017-06-07Use ArtMethod* .bss entries for HInvokeStaticOrDirect.Vladimir Marko
Test: m test-art-host-gtest Test: testrunner.py --host Test: testrunner.py --target Test: Nexus 6P boots. Test: Build aosp_mips64-userdebug. Bug: 30627598 Change-Id: I0e54fdd2e91e983d475b7a04d40815ba89ae3d4f
2017-06-07Merge "Replace invoke kind kDexCacheViaMethod with kRuntimeCall."Vladimir Marko
2017-06-06Replace invoke kind kDexCacheViaMethod with kRuntimeCall.Vladimir Marko
In preparation for replacing the dex cache method array with a hash-based array, get rid of one unnecessary use. This method load kind is currently used only on mips for irreducible loops and OSR, so this should have no impact on x86/x86-64/arm/arm64. Test: m test-art-host-gtest Test: testrunner.py --host Test: Repeat the above tests with manually changing kDexCachePcRelative to kRuntimeCall in sharpening.cc. (Ignore failures in 552-checker-sharpening.) Bug: 30627598 Change-Id: Ifce42645f2dcc350bbb88c2f4642e88fc5f98152
2017-06-05Merge "Revert "ART: Reference.getReferent intrinsic for arm and arm64""Vladimir Marko
2017-06-02Revert "ART: Reference.getReferent intrinsic for arm and arm64"Vladimir Marko
Reverting because GenerateCalleeMethodStaticOrDirectCall() prevents replacing kDexCacheViaMethod with kRuntimeCall where we would not retrieve the target method at all and leave the runtime to retrieve and call it just like for unresolved methods. The intrinsic should be re-implemented by loading the flags through HLoadClass. Note that the intrinsic was unimplemented for CC and a bit broken for non-CC, using LDR instead of LDRB for loading the flags. Test: Rely on TreeHugger. Bug: 32535355 Bug: 30627598 This reverts commit d8c052ac0aa3382c4807add33afa32580ffeecbb. Change-Id: I81fd14dac60c94ac543e336f4f3c888259fc8bd7
2017-06-02Rename kDexCacheViaMethod to kRuntimeCall for HLoadClass/String.Vladimir Marko
The old name does not reflect the actual code anymore. Test: testrunner.py --host Change-Id: I2e13cf727bba9d901c4d3fc821bb526d38a775b8
2017-05-23Merge "Use PC-relative pointer to boot image methods."Treehugger Robot
2017-05-22Use PC-relative pointer to boot image methods.Vladimir Marko
In preparation for adding ArtMethod entries to the .bss section, add direct PC-relative pointers to methods so that the number of needed .bss entries for boot image is small. Test: m test-art-host-gtest Test: testrunner.py --host Test: testrunner.py --target on Nexus 6P Test: Nexus 6P boots. Test: Build aosp_mips64-userdebug Bug: 30627598 Change-Id: Ia89f5f9975b741ddac2816e1570077ba4b4c020f
2017-05-22Revert "Revert "ARM: Improve the code generated for HCondition with a ↵Anton Kirilov
constant input"" This reverts commit 3082661d260449e1d773f077e914160c7ad58de5, and fixes the handling of HCondition with boolean inputs. Test: m test-art-target-run-test-409-materialized-condition Test: art/tools/run-libcore-tests.sh Change-Id: Ib21e3a81ba41ce20c06e9a9e454c4322af1513ae
2017-05-16Remove LoadString/Class kind kBootImageLinkTimeAddress.Vladimir Marko
We no longer support non-PIC boot image compilation. Also clean up some obsolete code for method patches and make JIT correctly report itself as non-PIC. Test: testrunner.py --host Test: testrunner.py --target Bug: 33192586 Change-Id: I593289c5c1b0e88b82b86a933038be97bbb15ad2
2017-05-11Merge "ARM64: Share address computation across SIMD LDRs/STRs."Treehugger Robot
2017-05-11Clean up some uses of "auto".Vladimir Marko
Make actual types more explicit, either by replacing "auto" with actual type or by assigning std::pair<> elements of an "auto" variable to typed variables. Avoid binding const references to temporaries. Avoid copying a container. Test: m test-art-host-gtest Change-Id: I1a59f9ba1ee15950cacfc5853bd010c1726de603
2017-05-11ARM64: Share address computation across SIMD LDRs/STRs.Artem Serov
For array accesses the element address has the following structure: Address = CONST_OFFSET + base_addr + index << ELEM_SHIFT Taking into account ARM64 LDR/STR addressing modes address part (CONST_OFFSET + index << ELEM_SHIFT) can be shared across array access with the same data type and index. For example, for the following loop 5 accesses can share address computation: void foo(int[] a, int[] b, int[] c) { for (i...) { a[i] = a[i] + 5; b[i] = b[i] + c[i]; } } Test: test-art-host, test-art-target Change-Id: I46af3b4e4a55004336672cdba3296b7622d815ca
2017-05-10Merge "ARM/AOT: Allow 16-bit LDR for Baker read barrier loads."Treehugger Robot
2017-05-10Merge "Revert "ARM: Improve the code generated for HCondition with a ↵Nicolas Geoffray
constant input""
2017-05-10Revert "ARM: Improve the code generated for HCondition with a constant input"Nicolas Geoffray
Reverting to see if that change is responsible for a crash. Will share with ARM if it is. This reverts commit b404f349d69f940ef2974915fe97c16070364efd. Change-Id: Idd04f9109447319445ff49f3fd7dc5b069b4883f
2017-05-10Merge "Add runtime reasons for deopt."Nicolas Geoffray
2017-05-10Add runtime reasons for deopt.Nicolas Geoffray
Currently to help investigate. Also: 1) Log when deoptimization happens (which method and what reason) 2) Trace when deoptimization happens (to make it visible in systrace) bug:37655083 Test: test-art-host test-art-target Change-Id: I0c2d87b40db09e8e475cf97a7c784a034c585e97
2017-05-09ARM/AOT: Allow 16-bit LDR for Baker read barrier loads.Vladimir Marko
Test: m test-art-target-gtest Test: testrunner.py --target on Nexus 6P. Test: testrunner.py --target on Nexus 6P with heap poisoning enabled. Test: Repeat the above tests with ART_USE_OLD_ARM_BACKEND=true. Bug: 29516974 Bug: 30126666 Bug: 36141117 Change-Id: I458f2ec5fe9abead4db06c7595d992945096fb68
2017-05-09Merge "ARM: Improve the code generated for HCondition with a constant input"Treehugger Robot
2017-05-08ARM: Improve the code generated for HCondition with a constant inputAnton Kirilov
Test: m test-art-target-run-test-409-materialized-condition Test: m test-art-target-run-test-570-checker-select Change-Id: Ie3418fbac1d2ecb4d7fc847d4722758e1e01bc2e
2017-05-08Merge "Improve the implementation of UnsafeCASObject with Baker read barriers."Roland Levillain
2017-05-05Improve the implementation of UnsafeCASObject with Baker read barriers.Roland Levillain
On ARM and ARM64, avoid loading the reference altogether when the GC is not marking. Also, extract the code logic for updating a reference field from GenerateReferenceLoadWithBakerReadBarrier routines and move it to new routines (UpdateReferenceFieldWithBakerReadBarrier), to make the implementation more legible. Test: Run ART target tests in Baker read barrier configuration. Bug: 29516974 Change-Id: I11c53f0607e997cd02ec7911725e98ef3dc97d90
2017-05-05ARM: Link-time generated thunks for Baker CC read barrier.Vladimir Marko
Remaining work for follow-up CLs: - use implicit null check in field thunk, - use 16-bit LDRs for fields and GC roots. Test: m test-art-target-gtest Test: testrunner.py --target on Nexus 6P. Test: testrunner.py --target on Nexus 6P with heap poisoning enabled. Test: Repeat the above tests with ART_USE_OLD_ARM_BACKEND=true. Bug: 29516974 Bug: 30126666 Bug: 36141117 Change-Id: Iad5addab72d790a9d61879f61f2e75b246bcdf5a
2017-05-02optimizing: constructor fence redundancy elimination - remove dmb after LSEIgor Murashkin
Part one of a few upcoming CLs to optimize constructor fences. This improves load-store-elimination; all singleton objects that are not returned will have their associated constructor fence removed. If the allocation is removed, so is the fence. Even if allocation is not removed, fences can sometimes be removed. This change is enabled by tracking the "this" object associated with the constructor fence as an input. Fence inputs are considered weak; they do not keep the "this" object alive; if the instructions for "this" are all deleted, the fence can also be deleted. Bug: 36656456 Test: art/test.py --host && art/test.py --target Change-Id: I05659ab07e20d6e2ecd4be051b722726776f4ab1
2017-03-27ART: Clean up field initializationAndreas Gampe
Add explicit field initialization to default value where necessary. Also clean up interpreter intrinsics header. Test: m Change-Id: I7a850ac30dcccfb523a5569fb8400b9ac892c8e5
2017-03-27Merge "ARM: Reduce the number of branches generated for HCondition and HSelect"Nicolas Geoffray
2017-03-23ARM: Improve the code generated for HInstanceOfAnton Kirilov
Test: m test-art-target-run-test-009-instanceof Test: m test-art-target-run-test-422-instanceof Test: m test-art-target-run-test-494-checker-instanceof-tests Test: m test-art-target-run-test-500-instanceof Test: m test-art-target-run-test-530-instanceof-checkcast Test: m test-art-target-run-test-603-checker-instanceof Change-Id: Ia5e1421403605659d0f53bc794acb5e5b0af0c5e
2017-03-22ARM: Reduce the number of branches generated for HCondition and HSelectAnton Kirilov
Test: m test-art-target-run-test-570-checker-select Change-Id: I87d2e87eb2fd30355101df07eb3754b013cedf63
2017-03-17ARM: Avoid branches to branchesAnton Kirilov
Generally speaking, this optimization applies to all code generation visitors ending with a call to Bind(), which includes intrinsics with kNoCall CallKind. However, no changes are done for slow paths (which frequently end with a branch to an exit label that is bound at the end of a visitor). Test: m test-art-target Change-Id: Ie1a0c8c54ef76b01e7f0b23962c56c29ca8984a9
2017-03-10Merge "ARM: VIXL32: Improve BoundsCheck for constant inputs."Treehugger Robot
2017-03-10ARM: Generate UBFX for HAndAnton Kirilov
Test: m test-art-target-run-test-538-checker-embed-constants Change-Id: I8e6af76b99543331e8ffec01bd8df3f09890708e
2017-03-10ARM: VIXL32: Improve BoundsCheck for constant inputs.Artem Serov
Test: mma test-art-host && mma test-art-target Change-Id: I05051c03dbd3684c674096def84020494d28364b
2017-03-09Merge "ARM(64): Improve the code generated for HSelect"Treehugger Robot
2017-03-09Merge changes Ia26b07f0,Id3d2758cRoland Levillain
* changes: Revert "Revert "Use the holder's gray bit in Baker read barrier slow paths (ARM, ARM64)."" Revert "Revert "Use the "GC is marking" information in compiler read barriers (ARM, ARM64).""
2017-03-09ARM(64): Improve the code generated for HSelectDonghui Bai
Test: m test-art-target-run-test-566-checker-codegen-select Test: m test-art-target-run-test-570-checker-select Change-Id: If0140892303490701782df9a818e6d8346bf3d6c Signed-off-by: Anton Kirilov <anton.kirilov@linaro.org>
2017-03-08Remove --include-patch-information option from dex2oat.Richard Uhler
Because we no longer support running patchoat on npic oat files, which means the included patch information is unused . Bug: 33192586 Test: m test-art-host Change-Id: I9e100c4e47dc24d91cd74226c84025e961d30f67
2017-03-06Revert "Revert "Use the holder's gray bit in Baker read barrier slow paths ↵Roland Levillain
(ARM, ARM64)."" This reverts commit 47b3ab2fd83aaa530b7d2c62bfc024209b8b6923. In compiler-generated code, when deciding whether to mark a heap reference or not in a read barrier, after checking whether the GC is currently marking, also check (in the slow path) whether the lock word of the reference's holder is gray, before actually marking the reference. This change is only for ARM and ARM64, as it does not benefit x86 nor x86-64. Change-Id: Ia26b07f0485e23589bfc0e65f83852f2795688c0 Test: Run ART tests in Baker read barrier configuration. Test: Boot a device in Baker read barrier configuration. Bug: 35780827 Bug: 29516974
2017-03-06Revert "Revert "Use the "GC is marking" information in compiler read ↵Roland Levillain
barriers (ARM, ARM64)."" This reverts commit 35345a555bd7928582a7ffa6369b374b3ddc379d. In compiler-generated code, when deciding whether to mark a heap reference or not in a read barrier, check whether the GC is currently marking, instead of checking the gray bit in the reference's holder's lock word. This change is only for ARM and ARM64, as it does not benefit x86 nor x86-64. Change-Id: Id3d2758c600115b2f07d345442cfa87edfc2792c Test: Run ART tests in Baker read barrier configuration. Test: Boot a device in Baker read barrier configuration. Bug: 35780827 Bug: 29516974
2017-02-27Revert "Use the "GC is marking" information in compiler read barriers (ARM, ↵Roland Levillain
ARM64)." This reverts commit 1372c9f40df1e47bf775f1466bbb96f472b6b9ed. This change (along with https://android-review.googlesource.com/#/c/342429/) creates null pointer dereferences. Bug: 35780827 Bug: 29516974 Change-Id: I2a9c4d0ad8d2ab870c2e0ddbff32152933c77abe
2017-02-27Revert "Use the holder's gray bit in Baker read barrier slow paths (ARM, ↵Roland Levillain
ARM64)." This reverts commit 27b1f9cbfc1409418eee4b0e22f29f033e10b64d. This change (along with https://android-review.googlesource.com/#/c/342428/) creates null pointer dereferences. Bug: 35780827 Bug: 29516974 Change-Id: If731960a405f9b89528f3daaf235da57cabc5c11
2017-02-23Use the holder's gray bit in Baker read barrier slow paths (ARM, ARM64).Roland Levillain
In compiler-generated code, when deciding whether to mark a heap reference or not in a read barrier, after checking whether the GC is currently marking, also check (in the slow path) whether the lock word of the reference's holder is gray, before actually marking the reference. This change is only for ARM and ARM64, as it does not benefit x86 nor x86-64. Test: Run ART tests in Baker read barrier configuration. Test: Boot a device in Baker read barrier configuration. Bug: 29516974 Change-Id: I60595a8f4987747faeaa359ad873e9758c1ded75
2017-02-23Use the "GC is marking" information in compiler read barriers (ARM, ARM64).Roland Levillain
In compiler-generated code, when deciding whether to mark a heap reference or not in a read barrier, check whether the GC is currently marking, instead of checking the gray bit in the reference's holder's lock word. This change is only for ARM and ARM64, as it does not benefit x86 nor x86-64. Test: Run ART tests in Baker read barrier configuration. Test: Boot a device in Baker read barrier configuration. Bug: 29516974 Change-Id: Ia5d90286bb9f753f3bbcb3a6254eb166523a2ff5
2017-02-17ARM: Merge data-processing instructions and shifts/(un)signed extensionsAnton Kirilov
This commit mirrors the work that has already been done for ARM64. Test: m test-art-target-run-test-551-checker-shifter-operand Change-Id: Iec8c1563b035f40f0e18dcffde28d91dc21922f8
2017-02-10Merge "Use entrypoint switching on x86 & x86-64 for GC root read barriers."Roland Levillain
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