diff options
Diffstat (limited to 'compiler/optimizing/code_generator_mips.cc')
| -rw-r--r-- | compiler/optimizing/code_generator_mips.cc | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/compiler/optimizing/code_generator_mips.cc b/compiler/optimizing/code_generator_mips.cc index 893692a04d..3ba107a283 100644 --- a/compiler/optimizing/code_generator_mips.cc +++ b/compiler/optimizing/code_generator_mips.cc @@ -6244,8 +6244,11 @@ void InstructionCodeGeneratorMIPS::HandleFieldGet(HInstruction* instruction, InvokeRuntimeCallingConvention calling_convention; __ Addiu32(locations->GetTemp(0).AsRegister<Register>(), obj, offset); // Do implicit Null check - __ Lw(ZERO, locations->GetTemp(0).AsRegister<Register>(), 0); - codegen_->RecordPcInfo(instruction, instruction->GetDexPc()); + __ LoadFromOffset(kLoadWord, + ZERO, + locations->GetTemp(0).AsRegister<Register>(), + 0, + null_checker); codegen_->InvokeRuntime(kQuickA64Load, instruction, dex_pc); CheckEntrypointTypes<kQuickA64Load, int64_t, volatile const int64_t*>(); if (type == DataType::Type::kFloat64) { @@ -6398,8 +6401,11 @@ void InstructionCodeGeneratorMIPS::HandleFieldSet(HInstruction* instruction, InvokeRuntimeCallingConvention calling_convention; __ Addiu32(locations->GetTemp(0).AsRegister<Register>(), obj, offset); // Do implicit Null check. - __ Lw(ZERO, locations->GetTemp(0).AsRegister<Register>(), 0); - codegen_->RecordPcInfo(instruction, instruction->GetDexPc()); + __ LoadFromOffset(kLoadWord, + ZERO, + locations->GetTemp(0).AsRegister<Register>(), + 0, + null_checker); if (type == DataType::Type::kFloat64) { // Pass FP parameters in core registers. if (value_location.IsFpuRegister()) { |