diff options
| author | Aart Bik <ajcbik@ajcbik2.mtv.corp.google.com> | 2017-05-10 10:49:22 -0700 |
|---|---|---|
| committer | Aart Bik <ajcbik@google.com> | 2017-05-15 11:44:58 -0700 |
| commit | c8e93c736c149ce41be073dd24324fb08afb9ae4 (patch) | |
| tree | 8e7154cf1bbcee8f5837ee9cb930174e2516ac03 /disassembler/disassembler_x86.cc | |
| parent | 92f4672f811a4eccdc596f7c2235804abd196fde (diff) | |
Min/max SIMDization support.
Rationale:
The more vectorized, the better!
Test: test-art-target, test-art-host
Change-Id: I758becca5beaa5b97fab2ab70f2e00cb53458703
Diffstat (limited to 'disassembler/disassembler_x86.cc')
| -rw-r--r-- | disassembler/disassembler_x86.cc | 66 |
1 files changed, 65 insertions, 1 deletions
diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc index e12bcec776..4824f70a28 100644 --- a/disassembler/disassembler_x86.cc +++ b/disassembler/disassembler_x86.cc @@ -581,13 +581,69 @@ DISASSEMBLER_ENTRY(cmp, load = true; src_reg_file = dst_reg_file = SSE; break; - case 0x39: + case 0x37: opcode1 = "pcmpgtq"; prefix[2] = 0; has_modrm = true; load = true; src_reg_file = dst_reg_file = SSE; break; + case 0x38: + opcode1 = "pminsb"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; + case 0x39: + opcode1 = "pminsd"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; + case 0x3A: + opcode1 = "pminuw"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; + case 0x3B: + opcode1 = "pminud"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; + case 0x3C: + opcode1 = "pmaxsb"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; + case 0x3D: + opcode1 = "pmaxsd"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; + case 0x3E: + opcode1 = "pmaxuw"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; + case 0x3F: + opcode1 = "pmaxud"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; case 0x40: opcode1 = "pmulld"; prefix[2] = 0; @@ -1133,8 +1189,12 @@ DISASSEMBLER_ENTRY(cmp, opcode1 = opcode_tmp.c_str(); } break; + case 0xDA: + case 0xDE: case 0xE0: case 0xE3: + case 0xEA: + case 0xEE: if (prefix[2] == 0x66) { src_reg_file = dst_reg_file = SSE; prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode @@ -1142,8 +1202,12 @@ DISASSEMBLER_ENTRY(cmp, src_reg_file = dst_reg_file = MMX; } switch (*instr) { + case 0xDA: opcode1 = "pminub"; break; + case 0xDE: opcode1 = "pmaxub"; break; case 0xE0: opcode1 = "pavgb"; break; case 0xE3: opcode1 = "pavgw"; break; + case 0xEA: opcode1 = "pminsw"; break; + case 0xEE: opcode1 = "pmaxsw"; break; } prefix[2] = 0; has_modrm = true; |