diff options
| author | Aart Bik <ajcbik@google.com> | 2017-03-31 15:11:53 -0700 |
|---|---|---|
| committer | Aart Bik <ajcbik@google.com> | 2017-03-31 15:11:53 -0700 |
| commit | 67d3fd77d1572e46f537dea2fd4ded3ecfd7c202 (patch) | |
| tree | 168e7ddf85cbe0710266dc501dac6d7717f25cf8 /disassembler/disassembler_x86.cc | |
| parent | 5b92c48f99391ae764e1699a22881f9d5cbce721 (diff) | |
SIMD pavgb,w for x86/x86_64
Rationale:
Break-out CL of ART Vectorizer.
Enables fast halving add with rounding
Bug: 34083438
Test: assembler_x86[_64]_test
Change-Id: I09173376b803d671a6b05a33e630f45f778cea52
Diffstat (limited to 'disassembler/disassembler_x86.cc')
| -rw-r--r-- | disassembler/disassembler_x86.cc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc index 77ed3c6a22..f5c3ad20cc 100644 --- a/disassembler/disassembler_x86.cc +++ b/disassembler/disassembler_x86.cc @@ -1101,6 +1101,22 @@ DISASSEMBLER_ENTRY(cmp, opcode1 = opcode_tmp.c_str(); } break; + case 0xE0: + case 0xE3: + if (prefix[2] == 0x66) { + src_reg_file = dst_reg_file = SSE; + prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode + } else { + src_reg_file = dst_reg_file = MMX; + } + switch (*instr) { + case 0xE0: opcode1 = "pavgb"; break; + case 0xE3: opcode1 = "pavgw"; break; + } + prefix[2] = 0; + has_modrm = true; + load = true; + break; case 0xEB: if (prefix[2] == 0x66) { src_reg_file = dst_reg_file = SSE; |