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| author | Roland Levillain <rpl@google.com> | 2016-10-20 11:59:42 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2016-10-20 11:59:43 +0000 |
| commit | 2f2533f686f759ccd29d2712da2c7610382fb59f (patch) | |
| tree | b4853d93d2427928bbf28aac135b939017360c9e /compiler/optimizing/code_generator_arm.cc | |
| parent | fc7a96464c58f2e3432cba2a3cfb19d84b033fdf (diff) | |
| parent | a7812ae7939b199392f874b24a52454bbd0c13f2 (diff) | |
Merge "ARM: VIXL32: Pass initial ART tests with new code generator."
Diffstat (limited to 'compiler/optimizing/code_generator_arm.cc')
| -rw-r--r-- | compiler/optimizing/code_generator_arm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/compiler/optimizing/code_generator_arm.cc b/compiler/optimizing/code_generator_arm.cc index 88bfad49c9..9f92b20929 100644 --- a/compiler/optimizing/code_generator_arm.cc +++ b/compiler/optimizing/code_generator_arm.cc @@ -107,7 +107,7 @@ static size_t SaveContiguousSRegisterList(size_t first, size_t number_of_d_regs = (last - first + 1) / 2; if (number_of_d_regs == 1) { - __ StoreDToOffset(d_reg, SP, stack_offset); + __ StoreDToOffset(d_reg, SP, stack_offset); } else if (number_of_d_regs > 1) { __ add(IP, SP, ShifterOperand(stack_offset)); __ vstmiad(IP, d_reg, number_of_d_regs); |