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authorScott Wakeling <scott.wakeling@linaro.org>2016-10-17 10:03:36 +0100
committerScott Wakeling <scott.wakeling@linaro.org>2016-10-17 13:41:40 +0100
commita7812ae7939b199392f874b24a52454bbd0c13f2 (patch)
treefcaff0417676c74ad7bf88e7c2571948e7eeef81 /compiler/optimizing/code_generator_arm.cc
parenta497095b67c4ba2969d0b2a13f6959125c89d2bc (diff)
ARM: VIXL32: Pass initial ART tests with new code generator.
- Implement enough codegen to pass ~70 art/tests. - When ART_USE_VIXL_ARM_BACKEND is defined: - Blacklist known-to-fail target tests - interpret-only everything except the tests themselves - Set a flag to use the VIXL based ARM backend Test: export ART_USE_VIXL_ARM_BACKEND=true && mma test-art-target && mma test-art-host Change-Id: Ic8bc095e8449f10f97fa0511284790f36c20e276
Diffstat (limited to 'compiler/optimizing/code_generator_arm.cc')
-rw-r--r--compiler/optimizing/code_generator_arm.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/compiler/optimizing/code_generator_arm.cc b/compiler/optimizing/code_generator_arm.cc
index 77d6f23fff..71aedec65a 100644
--- a/compiler/optimizing/code_generator_arm.cc
+++ b/compiler/optimizing/code_generator_arm.cc
@@ -107,7 +107,7 @@ static size_t SaveContiguousSRegisterList(size_t first,
size_t number_of_d_regs = (last - first + 1) / 2;
if (number_of_d_regs == 1) {
- __ StoreDToOffset(d_reg, SP, stack_offset);
+ __ StoreDToOffset(d_reg, SP, stack_offset);
} else if (number_of_d_regs > 1) {
__ add(IP, SP, ShifterOperand(stack_offset));
__ vstmiad(IP, d_reg, number_of_d_regs);