summaryrefslogtreecommitdiff
path: root/halimpl/libnfc-nxp_RF-PN557_example.conf
blob: 65b5638439e7e6b52d0999fc6db4d6a9cd1b9cfb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_1={
#}

###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_2={
#}

###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_3={
#}

###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_4={
#}

###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_5={
#}

###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_6={
#}

###############################################################################
# Core configuration extensions
# It includes
# Wired mode settings A0ED, A0EE
# Tag Detector A040, A041, A043
# Low Power mode A007
# Clock settings A002, A003
# PbF settings A008
# Clock timeout settings A004
# eSE (SVDD) PWR REQ settings A0F2
# How eSE connected to PN553 A012
# UICC bit rate A0D1
# SWP1A interface A0D4
# DWP intf behavior config, SVDD Load activated by default if set to 0x31 - A037
# For Symmetric baud rate  UICC's set A086 to 77
NXP_CORE_CONF_EXTN={20, 02, 21, 08,
    A0, EC, 01, 01,
    A0, ED, 01, 00,
    A0, 5E, 01, 01,
    A0, 40, 01, 01,
    A0, DD, 01, 2D,
    A0, D1, 01, 06,
    A0, D4, 01, 01,
    A0, 86, 01, 77
  }
#       A0, F2, 01, 01,
#       A0, 40, 01, 01,
#       A0, 41, 01, 02,
#       A0, 43, 01, 04,
#       A0, 02, 01, 01,
#       A0, 03, 01, 11,
#       A0, 07, 01, 03,
#       A0, 08, 01, 01
#       }

###############################################################################
# Core configuration settings
NXP_CORE_CONF={ 20, 02, 34, 10,
        28, 01, 00,
        21, 01, 00,
        30, 01, 08,
        31, 01, 03,
        32, 01, 60,
        38, 01, 01,
        33, 04, 01, 02, 03, 04,
        54, 01, 06,
        50, 01, 02,
        5B, 01, 00,
        80, 01, 01,
        81, 01, 01,
        82, 01, 0E,
        18, 01, 01,
        68, 01, 01,
        85, 01, 01
        }
###############################################################################