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+<title>Debugging with GDB: AArch64</title>
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+<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
+<a name="AArch64"></a>
+<div class="header">
+<p>
+Next: <a href="i386.html#i386" accesskey="n" rel="next">i386</a>, Up: <a href="Architectures.html#Architectures" accesskey="u" rel="up">Architectures</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
+</div>
+<hr>
+<a name="AArch64-1"></a>
+<h4 class="subsection">21.4.1 AArch64</h4>
+<a name="index-AArch64-support"></a>
+
+<p>When <small>GDB</small> is debugging the AArch64 architecture, it provides the
+following special commands:
+</p>
+<dl compact="compact">
+<dt><code>set debug aarch64</code></dt>
+<dd><a name="index-set-debug-aarch64"></a>
+<p>This command determines whether AArch64 architecture-specific debugging
+messages are to be displayed.
+</p>
+</dd>
+<dt><code>show debug aarch64</code></dt>
+<dd><p>Show whether AArch64 debugging messages are displayed.
+</p>
+</dd>
+</dl>
+
+<a name="AArch64-SVE_002e"></a>
+<h4 class="subsubsection">21.4.1.1 AArch64 SVE.</h4>
+<a name="index-AArch64-SVE_002e"></a>
+
+<p>When <small>GDB</small> is debugging the AArch64 architecture, if the Scalable Vector
+Extension (SVE) is present, then <small>GDB</small> will provide the vector registers
+<code>$z0</code> through <code>$z31</code>, vector predicate registers <code>$p0</code> through
+<code>$p15</code>, and the <code>$ffr</code> register. In addition, the pseudo register
+<code>$vg</code> will be provided. This is the vector granule for the current thread
+and represents the number of 64-bit chunks in an SVE <code>z</code> register.
+</p>
+<p>If the vector length changes, then the <code>$vg</code> register will be updated,
+but the lengths of the <code>z</code> and <code>p</code> registers will not change. This
+is a known limitation of <small>GDB</small> and does not affect the execution of the
+target process.
+</p>
+<a name="AArch64-Pointer-Authentication_002e"></a>
+<h4 class="subsubsection">21.4.1.2 AArch64 Pointer Authentication.</h4>
+<a name="index-AArch64-Pointer-Authentication_002e"></a>
+<a name="AArch64-PAC"></a>
+<p>When <small>GDB</small> is debugging the AArch64 architecture, and the program is
+using the v8.3-A feature Pointer Authentication (PAC), then whenever the link
+register <code>$lr</code> is pointing to an PAC function its value will be masked.
+When GDB prints a backtrace, any addresses that required unmasking will be
+postfixed with the marker [PAC]. When using the MI, this is printed as part
+of the <code>addr_flags</code> field.
+</p>
+<a name="AArch64-Memory-Tagging-Extension_002e"></a>
+<h4 class="subsubsection">21.4.1.3 AArch64 Memory Tagging Extension.</h4>
+<a name="index-AArch64-Memory-Tagging-Extension_002e"></a>
+
+<p>When <small>GDB</small> is debugging the AArch64 architecture, the program is
+using the v8.5-A feature Memory Tagging Extension (MTE) and there is support
+in the kernel for MTE, <small>GDB</small> will make memory tagging functionality
+available for inspection and editing of logical and allocation tags.
+See <a href="Memory-Tagging.html#Memory-Tagging">Memory Tagging</a>.
+</p>
+<p>To aid debugging, <small>GDB</small> will output additional information when SIGSEGV
+signals are generated as a result of memory tag failures.
+</p>
+<p>If the tag violation is synchronous, the following will be shown:
+</p>
+<div class="smallexample">
+<pre class="smallexample">Program received signal SIGSEGV, Segmentation fault
+Memory tag violation while accessing address 0x0500fffff7ff8000
+Allocation tag 0x1
+Logical tag 0x5.
+</pre></div>
+
+<p>If the tag violation is asynchronous, the fault address is not available.
+In this case <small>GDB</small> will show the following:
+</p>
+<div class="smallexample">
+<pre class="smallexample">Program received signal SIGSEGV, Segmentation fault
+Memory tag violation
+Fault address unavailable.
+</pre></div>
+
+<p>A special register, <code>tag_ctl</code>, is made available through the
+<code>org.gnu.gdb.aarch64.mte</code> feature. This register exposes some
+options that can be controlled at runtime and emulates the <code>prctl</code>
+option <code>PR_SET_TAGGED_ADDR_CTRL</code>. For further information, see the
+documentation in the Linux kernel.
+</p>
+<p><small>GDB</small> supports dumping memory tag data to core files through the
+<code>gcore</code> command and reading memory tag data from core files generated
+by the <code>gcore</code> command or the Linux kernel.
+</p>
+<p>When a process uses memory-mapped pages protected by memory tags (for
+example, AArch64 MTE), this additional information will be recorded in
+the core file in the event of a crash or if <small>GDB</small> generates a core file
+from the current process state.
+</p>
+<p>The memory tag data will be used so developers can display the memory
+tags from a particular memory region (using the &lsquo;<samp>m</samp>&rsquo; modifier to the
+<code>x</code> command, using the <code>print</code> command or using the various
+<code>memory-tag</code> subcommands.
+</p>
+<p>In the case of a crash, <small>GDB</small> will attempt to retrieve the memory tag
+information automatically from the core file, and will show one of the above
+messages depending on whether the synchronous or asynchronous mode is selected.
+See <a href="Memory-Tagging.html#Memory-Tagging">Memory Tagging</a>. See <a href="Memory.html#Memory">Memory</a>.
+</p>
+<hr>
+<div class="header">
+<p>
+Next: <a href="i386.html#i386" accesskey="n" rel="next">i386</a>, Up: <a href="Architectures.html#Architectures" accesskey="u" rel="up">Architectures</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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