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diff --git a/share/doc/gccint/MODE_005fCC-Condition-Codes.html b/share/doc/gccint/MODE_005fCC-Condition-Codes.html new file mode 100644 index 0000000..39726dc --- /dev/null +++ b/share/doc/gccint/MODE_005fCC-Condition-Codes.html @@ -0,0 +1,239 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html> +<!-- Copyright (C) 1988-2023 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being "Funding Free Software", the Front-Cover +Texts being (a) (see below), and with the Back-Cover Texts being (b) +(see below). A copy of the license is included in the section entitled +"GNU Free Documentation License". + +(a) The FSF's Front-Cover Text is: + +A GNU Manual + +(b) The FSF's Back-Cover Text is: + +You have freedom to copy and modify this GNU Manual, like GNU + software. Copies published by the Free Software Foundation raise + funds for GNU development. --> +<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> +<head> +<title>GNU Compiler Collection (GCC) Internals: MODE_CC Condition Codes</title> + +<meta name="description" content="GNU Compiler Collection (GCC) Internals: MODE_CC Condition Codes"> +<meta name="keywords" content="GNU Compiler Collection (GCC) Internals: MODE_CC Condition Codes"> +<meta name="resource-type" content="document"> +<meta name="distribution" content="global"> +<meta name="Generator" content="makeinfo"> +<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> +<link href="index.html#Top" rel="start" title="Top"> +<link href="Option-Index.html#Option-Index" rel="index" title="Option Index"> +<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> +<link href="Condition-Code.html#Condition-Code" rel="up" title="Condition Code"> +<link href="Costs.html#Costs" rel="next" title="Costs"> +<link href="Condition-Code.html#Condition-Code" rel="previous" title="Condition Code"> +<style type="text/css"> +<!-- +a.summary-letter {text-decoration: none} +blockquote.smallquotation {font-size: smaller} +div.display {margin-left: 3.2em} +div.example {margin-left: 3.2em} +div.indentedblock {margin-left: 3.2em} +div.lisp {margin-left: 3.2em} +div.smalldisplay {margin-left: 3.2em} +div.smallexample {margin-left: 3.2em} +div.smallindentedblock {margin-left: 3.2em; font-size: smaller} +div.smalllisp {margin-left: 3.2em} +kbd {font-style:oblique} +pre.display {font-family: inherit} +pre.format {font-family: inherit} +pre.menu-comment {font-family: serif} +pre.menu-preformatted {font-family: serif} +pre.smalldisplay {font-family: inherit; font-size: smaller} +pre.smallexample {font-size: smaller} +pre.smallformat {font-family: inherit; font-size: smaller} +pre.smalllisp {font-size: smaller} +span.nocodebreak {white-space:nowrap} +span.nolinebreak {white-space:nowrap} +span.roman {font-family:serif; font-weight:normal} +span.sansserif {font-family:sans-serif; font-weight:normal} +ul.no-bullet {list-style: none} +--> +</style> + + +</head> + +<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> +<a name="MODE_005fCC-Condition-Codes"></a> +<div class="header"> +<p> +Up: <a href="Condition-Code.html#Condition-Code" accesskey="u" rel="up">Condition Code</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p> +</div> +<hr> +<a name="Representation-of-condition-codes-using-registers"></a> +<h4 class="subsection">18.15.1 Representation of condition codes using registers</h4> +<a name="index-CCmode-1"></a> +<a name="index-MODE_005fCC-1"></a> + +<dl> +<dt><a name="index-SELECT_005fCC_005fMODE"></a>Macro: <strong>SELECT_CC_MODE</strong> <em>(<var>op</var>, <var>x</var>, <var>y</var>)</em></dt> +<dd><p>On many machines, the condition code may be produced by other instructions +than compares, for example the branch can use directly the condition +code set by a subtract instruction. However, on some machines +when the condition code is set this way some bits (such as the overflow +bit) are not set in the same way as a test instruction, so that a different +branch instruction must be used for some conditional branches. When +this happens, use the machine mode of the condition code register to +record different formats of the condition code register. Modes can +also be used to record which compare instruction (e.g. a signed or an +unsigned comparison) produced the condition codes. +</p> +<p>If other modes than <code>CCmode</code> are required, add them to +<samp><var>machine</var>-modes.def</samp> and define <code>SELECT_CC_MODE</code> to choose +a mode given an operand of a compare. This is needed because the modes +have to be chosen not only during RTL generation but also, for example, +by instruction combination. The result of <code>SELECT_CC_MODE</code> should +be consistent with the mode used in the patterns; for example to support +the case of the add on the SPARC discussed above, we have the pattern +</p> +<div class="smallexample"> +<pre class="smallexample">(define_insn "" + [(set (reg:CCNZ 0) + (compare:CCNZ + (plus:SI (match_operand:SI 0 "register_operand" "%r") + (match_operand:SI 1 "arith_operand" "rI")) + (const_int 0)))] + "" + "…") +</pre></div> + +<p>together with a <code>SELECT_CC_MODE</code> that returns <code>CCNZmode</code> +for comparisons whose argument is a <code>plus</code>: +</p> +<div class="smallexample"> +<pre class="smallexample">#define SELECT_CC_MODE(OP,X,Y) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + ? ((OP == LT || OP == LE || OP == GT || OP == GE) \ + ? CCFPEmode : CCFPmode) \ + : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ + || GET_CODE (X) == NEG || GET_CODE (x) == ASHIFT) \ + ? CCNZmode : CCmode)) +</pre></div> + +<p>Another reason to use modes is to retain information on which operands +were used by the comparison; see <code>REVERSIBLE_CC_MODE</code> later in +this section. +</p> +<p>You should define this macro if and only if you define extra CC modes +in <samp><var>machine</var>-modes.def</samp>. +</p></dd></dl> + +<dl> +<dt><a name="index-TARGET_005fCANONICALIZE_005fCOMPARISON"></a>Target Hook: <em>void</em> <strong>TARGET_CANONICALIZE_COMPARISON</strong> <em>(int *<var>code</var>, rtx *<var>op0</var>, rtx *<var>op1</var>, bool <var>op0_preserve_value</var>)</em></dt> +<dd><p>On some machines not all possible comparisons are defined, but you can +convert an invalid comparison into a valid one. For example, the Alpha +does not have a <code>GT</code> comparison, but you can use an <code>LT</code> +comparison instead and swap the order of the operands. +</p> +<p>On such machines, implement this hook to do any required conversions. +<var>code</var> is the initial comparison code and <var>op0</var> and <var>op1</var> +are the left and right operands of the comparison, respectively. If +<var>op0_preserve_value</var> is <code>true</code> the implementation is not +allowed to change the value of <var>op0</var> since the value might be used +in RTXs which aren’t comparisons. E.g. the implementation is not +allowed to swap operands in that case. +</p> +<p>GCC will not assume that the comparison resulting from this macro is +valid but will see if the resulting insn matches a pattern in the +<samp>md</samp> file. +</p> +<p>You need not to implement this hook if it would never change the +comparison code or operands. +</p></dd></dl> + +<dl> +<dt><a name="index-REVERSIBLE_005fCC_005fMODE"></a>Macro: <strong>REVERSIBLE_CC_MODE</strong> <em>(<var>mode</var>)</em></dt> +<dd><p>A C expression whose value is one if it is always safe to reverse a +comparison whose mode is <var>mode</var>. If <code>SELECT_CC_MODE</code> +can ever return <var>mode</var> for a floating-point inequality comparison, +then <code>REVERSIBLE_CC_MODE (<var>mode</var>)</code> must be zero. +</p> +<p>You need not define this macro if it would always returns zero or if the +floating-point format is anything other than <code>IEEE_FLOAT_FORMAT</code>. +For example, here is the definition used on the SPARC, where floating-point +inequality comparisons are given either <code>CCFPEmode</code> or <code>CCFPmode</code>: +</p> +<div class="smallexample"> +<pre class="smallexample">#define REVERSIBLE_CC_MODE(MODE) \ + ((MODE) != CCFPEmode && (MODE) != CCFPmode) +</pre></div> +</dd></dl> + +<dl> +<dt><a name="index-REVERSE_005fCONDITION"></a>Macro: <strong>REVERSE_CONDITION</strong> <em>(<var>code</var>, <var>mode</var>)</em></dt> +<dd><p>A C expression whose value is reversed condition code of the <var>code</var> for +comparison done in CC_MODE <var>mode</var>. The macro is used only in case +<code>REVERSIBLE_CC_MODE (<var>mode</var>)</code> is nonzero. Define this macro in case +machine has some non-standard way how to reverse certain conditionals. For +instance in case all floating point conditions are non-trapping, compiler may +freely convert unordered compares to ordered ones. Then definition may look +like: +</p> +<div class="smallexample"> +<pre class="smallexample">#define REVERSE_CONDITION(CODE, MODE) \ + ((MODE) != CCFPmode ? reverse_condition (CODE) \ + : reverse_condition_maybe_unordered (CODE)) +</pre></div> +</dd></dl> + +<dl> +<dt><a name="index-TARGET_005fFIXED_005fCONDITION_005fCODE_005fREGS"></a>Target Hook: <em>bool</em> <strong>TARGET_FIXED_CONDITION_CODE_REGS</strong> <em>(unsigned int *<var>p1</var>, unsigned int *<var>p2</var>)</em></dt> +<dd><p>On targets which use a hard +register rather than a pseudo-register to hold condition codes, the +regular CSE passes are often not able to identify cases in which the +hard register is set to a common value. Use this hook to enable a +small pass which optimizes such cases. This hook should return true +to enable this pass, and it should set the integers to which its +arguments point to the hard register numbers used for condition codes. +When there is only one such register, as is true on most systems, the +integer pointed to by <var>p2</var> should be set to +<code>INVALID_REGNUM</code>. +</p> +<p>The default version of this hook returns false. +</p></dd></dl> + +<dl> +<dt><a name="index-TARGET_005fCC_005fMODES_005fCOMPATIBLE"></a>Target Hook: <em>machine_mode</em> <strong>TARGET_CC_MODES_COMPATIBLE</strong> <em>(machine_mode <var>m1</var>, machine_mode <var>m2</var>)</em></dt> +<dd><p>On targets which use multiple condition code modes in class +<code>MODE_CC</code>, it is sometimes the case that a comparison can be +validly done in more than one mode. On such a system, define this +target hook to take two mode arguments and to return a mode in which +both comparisons may be validly done. If there is no such mode, +return <code>VOIDmode</code>. +</p> +<p>The default version of this hook checks whether the modes are the +same. If they are, it returns that mode. If they are different, it +returns <code>VOIDmode</code>. +</p></dd></dl> + +<dl> +<dt><a name="index-TARGET_005fFLAGS_005fREGNUM"></a>Target Hook: <em>unsigned int</em> <strong>TARGET_FLAGS_REGNUM</strong></dt> +<dd><p>If the target has a dedicated flags register, and it needs to use the +post-reload comparison elimination pass, or the delay slot filler pass, +then this value should be set appropriately. +</p></dd></dl> + +<hr> +<div class="header"> +<p> +Up: <a href="Condition-Code.html#Condition-Code" accesskey="u" rel="up">Condition Code</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p> +</div> + + + +</body> +</html> |