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+Next: <a href="Values-in-Registers.html#Values-in-Registers" accesskey="n" rel="next">Values in Registers</a>, Previous: <a href="Register-Basics.html#Register-Basics" accesskey="p" rel="previous">Register Basics</a>, Up: <a href="Registers.html#Registers" accesskey="u" rel="up">Registers</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
+</div>
+<hr>
+<a name="Order-of-Allocation-of-Registers"></a>
+<h4 class="subsection">18.7.2 Order of Allocation of Registers</h4>
+<a name="index-order-of-register-allocation"></a>
+<a name="index-register-allocation-order"></a>
+
+<p>Registers are allocated in order.
+</p>
+<dl>
+<dt><a name="index-REG_005fALLOC_005fORDER"></a>Macro: <strong>REG_ALLOC_ORDER</strong></dt>
+<dd><p>If defined, an initializer for a vector of integers, containing the
+numbers of hard registers in the order in which GCC should prefer
+to use them (from most preferred to least).
+</p>
+<p>If this macro is not defined, registers are used lowest numbered first
+(all else being equal).
+</p>
+<p>One use of this macro is on machines where the highest numbered
+registers must always be saved and the save-multiple-registers
+instruction supports only sequences of consecutive registers. On such
+machines, define <code>REG_ALLOC_ORDER</code> to be an initializer that lists
+the highest numbered allocable register first.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-ADJUST_005fREG_005fALLOC_005fORDER"></a>Macro: <strong>ADJUST_REG_ALLOC_ORDER</strong></dt>
+<dd><p>A C statement (sans semicolon) to choose the order in which to allocate
+hard registers for pseudo-registers local to a basic block.
+</p>
+<p>Store the desired register order in the array <code>reg_alloc_order</code>.
+Element 0 should be the register to allocate first; element 1, the next
+register; and so on.
+</p>
+<p>The macro body should not assume anything about the contents of
+<code>reg_alloc_order</code> before execution of the macro.
+</p>
+<p>On most machines, it is not necessary to define this macro.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-HONOR_005fREG_005fALLOC_005fORDER"></a>Macro: <strong>HONOR_REG_ALLOC_ORDER</strong></dt>
+<dd><p>Normally, IRA tries to estimate the costs for saving a register in the
+prologue and restoring it in the epilogue. This discourages it from
+using call-saved registers. If a machine wants to ensure that IRA
+allocates registers in the order given by REG_ALLOC_ORDER even if some
+call-saved registers appear earlier than call-used ones, then define this
+macro as a C expression to nonzero. Default is 0.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-IRA_005fHARD_005fREGNO_005fADD_005fCOST_005fMULTIPLIER"></a>Macro: <strong>IRA_HARD_REGNO_ADD_COST_MULTIPLIER</strong> <em>(<var>regno</var>)</em></dt>
+<dd><p>In some case register allocation order is not enough for the
+Integrated Register Allocator (<acronym>IRA</acronym>) to generate a good code.
+If this macro is defined, it should return a floating point value
+based on <var>regno</var>. The cost of using <var>regno</var> for a pseudo will
+be increased by approximately the pseudo&rsquo;s usage frequency times the
+value returned by this macro. Not defining this macro is equivalent
+to having it always return <code>0.0</code>.
+</p>
+<p>On most machines, it is not necessary to define this macro.
+</p></dd></dl>
+
+<hr>
+<div class="header">
+<p>
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