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diff --git a/share/doc/gcc/RL78-Options.html b/share/doc/gcc/RL78-Options.html new file mode 100644 index 0000000..3552824 --- /dev/null +++ b/share/doc/gcc/RL78-Options.html @@ -0,0 +1,199 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html> +<!-- This file documents the use of the GNU compilers. + +Copyright (C) 1988-2023 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being "Funding Free Software", the Front-Cover +Texts being (a) (see below), and with the Back-Cover Texts being (b) +(see below). A copy of the license is included in the section entitled +"GNU Free Documentation License". + +(a) The FSF's Front-Cover Text is: + +A GNU Manual + +(b) The FSF's Back-Cover Text is: + +You have freedom to copy and modify this GNU Manual, like GNU + software. Copies published by the Free Software Foundation raise + funds for GNU development. --> +<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> +<head> +<title>Using the GNU Compiler Collection (GCC): RL78 Options</title> + +<meta name="description" content="Using the GNU Compiler Collection (GCC): RL78 Options"> +<meta name="keywords" content="Using the GNU Compiler Collection (GCC): RL78 Options"> +<meta name="resource-type" content="document"> +<meta name="distribution" content="global"> +<meta name="Generator" content="makeinfo"> +<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> +<link href="index.html#Top" rel="start" title="Top"> +<link href="Indices.html#Indices" rel="index" title="Indices"> +<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> +<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options"> +<link href="RS_002f6000-and-PowerPC-Options.html#RS_002f6000-and-PowerPC-Options" rel="next" title="RS/6000 and PowerPC Options"> +<link href="RISC_002dV-Options.html#RISC_002dV-Options" rel="previous" title="RISC-V Options"> +<style type="text/css"> +<!-- +a.summary-letter {text-decoration: none} +blockquote.smallquotation {font-size: smaller} +div.display {margin-left: 3.2em} +div.example {margin-left: 3.2em} +div.indentedblock {margin-left: 3.2em} +div.lisp {margin-left: 3.2em} +div.smalldisplay {margin-left: 3.2em} +div.smallexample {margin-left: 3.2em} +div.smallindentedblock {margin-left: 3.2em; font-size: smaller} +div.smalllisp {margin-left: 3.2em} +kbd {font-style:oblique} +pre.display {font-family: inherit} +pre.format {font-family: inherit} +pre.menu-comment {font-family: serif} +pre.menu-preformatted {font-family: serif} +pre.smalldisplay {font-family: inherit; font-size: smaller} +pre.smallexample {font-size: smaller} +pre.smallformat {font-family: inherit; font-size: smaller} +pre.smalllisp {font-size: smaller} +span.nocodebreak {white-space:nowrap} +span.nolinebreak {white-space:nowrap} +span.roman {font-family:serif; font-weight:normal} +span.sansserif {font-family:sans-serif; font-weight:normal} +ul.no-bullet {list-style: none} +--> +</style> + + +</head> + +<body lang="en_US" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> +<a name="RL78-Options"></a> +<div class="header"> +<p> +Next: <a href="RS_002f6000-and-PowerPC-Options.html#RS_002f6000-and-PowerPC-Options" accesskey="n" rel="next">RS/6000 and PowerPC Options</a>, Previous: <a href="RISC_002dV-Options.html#RISC_002dV-Options" accesskey="p" rel="previous">RISC-V Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p> +</div> +<hr> +<a name="RL78-Options-1"></a> +<h4 class="subsection">3.19.41 RL78 Options</h4> +<a name="index-RL78-Options"></a> + +<dl compact="compact"> +<dd> +<a name="index-msim-6"></a> +</dd> +<dt><code>-msim</code></dt> +<dd><p>Links in additional target libraries to support operation within a +simulator. +</p> +<a name="index-mmul"></a> +</dd> +<dt><code>-mmul=none</code></dt> +<dt><code>-mmul=g10</code></dt> +<dt><code>-mmul=g13</code></dt> +<dt><code>-mmul=g14</code></dt> +<dt><code>-mmul=rl78</code></dt> +<dd><p>Specifies the type of hardware multiplication and division support to +be used. The simplest is <code>none</code>, which uses software for both +multiplication and division. This is the default. The <code>g13</code> +value is for the hardware multiply/divide peripheral found on the +RL78/G13 (S2 core) targets. The <code>g14</code> value selects the use of +the multiplication and division instructions supported by the RL78/G14 +(S3 core) parts. The value <code>rl78</code> is an alias for <code>g14</code> and +the value <code>mg10</code> is an alias for <code>none</code>. +</p> +<p>In addition a C preprocessor macro is defined, based upon the setting +of this option. Possible values are: <code>__RL78_MUL_NONE__</code>, +<code>__RL78_MUL_G13__</code> or <code>__RL78_MUL_G14__</code>. +</p> +<a name="index-mcpu-9"></a> +</dd> +<dt><code>-mcpu=g10</code></dt> +<dt><code>-mcpu=g13</code></dt> +<dt><code>-mcpu=g14</code></dt> +<dt><code>-mcpu=rl78</code></dt> +<dd><p>Specifies the RL78 core to target. The default is the G14 core, also +known as an S3 core or just RL78. The G13 or S2 core does not have +multiply or divide instructions, instead it uses a hardware peripheral +for these operations. The G10 or S1 core does not have register +banks, so it uses a different calling convention. +</p> +<p>If this option is set it also selects the type of hardware multiply +support to use, unless this is overridden by an explicit +<samp>-mmul=none</samp> option on the command line. Thus specifying +<samp>-mcpu=g13</samp> enables the use of the G13 hardware multiply +peripheral and specifying <samp>-mcpu=g10</samp> disables the use of +hardware multiplications altogether. +</p> +<p>Note, although the RL78/G14 core is the default target, specifying +<samp>-mcpu=g14</samp> or <samp>-mcpu=rl78</samp> on the command line does +change the behavior of the toolchain since it also enables G14 +hardware multiply support. If these options are not specified on the +command line then software multiplication routines will be used even +though the code targets the RL78 core. This is for backwards +compatibility with older toolchains which did not have hardware +multiply and divide support. +</p> +<p>In addition a C preprocessor macro is defined, based upon the setting +of this option. Possible values are: <code>__RL78_G10__</code>, +<code>__RL78_G13__</code> or <code>__RL78_G14__</code>. +</p> +<a name="index-mg10"></a> +<a name="index-mg13"></a> +<a name="index-mg14"></a> +<a name="index-mrl78"></a> +</dd> +<dt><code>-mg10</code></dt> +<dt><code>-mg13</code></dt> +<dt><code>-mg14</code></dt> +<dt><code>-mrl78</code></dt> +<dd><p>These are aliases for the corresponding <samp>-mcpu=</samp> option. They +are provided for backwards compatibility. +</p> +<a name="index-mallregs"></a> +</dd> +<dt><code>-mallregs</code></dt> +<dd><p>Allow the compiler to use all of the available registers. By default +registers <code>r24..r31</code> are reserved for use in interrupt handlers. +With this option enabled these registers can be used in ordinary +functions as well. +</p> +<a name="index-m64bit_002ddoubles"></a> +<a name="index-m32bit_002ddoubles"></a> +</dd> +<dt><code>-m64bit-doubles</code></dt> +<dt><code>-m32bit-doubles</code></dt> +<dd><p>Make the <code>double</code> data type be 64 bits (<samp>-m64bit-doubles</samp>) +or 32 bits (<samp>-m32bit-doubles</samp>) in size. The default is +<samp>-m32bit-doubles</samp>. +</p> +<a name="index-msave_002dmduc_002din_002dinterrupts"></a> +<a name="index-mno_002dsave_002dmduc_002din_002dinterrupts"></a> +</dd> +<dt><code>-msave-mduc-in-interrupts</code></dt> +<dt><code>-mno-save-mduc-in-interrupts</code></dt> +<dd><p>Specifies that interrupt handler functions should preserve the +MDUC registers. This is only necessary if normal code might use +the MDUC registers, for example because it performs multiplication +and division operations. The default is to ignore the MDUC registers +as this makes the interrupt handlers faster. The target option -mg13 +needs to be passed for this to work as this feature is only available +on the G13 target (S2 core). The MDUC registers will only be saved +if the interrupt handler performs a multiplication or division +operation or it calls another function. +</p> +</dd> +</dl> + +<hr> +<div class="header"> +<p> +Next: <a href="RS_002f6000-and-PowerPC-Options.html#RS_002f6000-and-PowerPC-Options" accesskey="n" rel="next">RS/6000 and PowerPC Options</a>, Previous: <a href="RISC_002dV-Options.html#RISC_002dV-Options" accesskey="p" rel="previous">RISC-V Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p> +</div> + + + +</body> +</html> |