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diff --git a/share/doc/gcc/RISC_002dV-Options.html b/share/doc/gcc/RISC_002dV-Options.html new file mode 100644 index 0000000..c568f87 --- /dev/null +++ b/share/doc/gcc/RISC_002dV-Options.html @@ -0,0 +1,346 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html> +<!-- This file documents the use of the GNU compilers. + +Copyright (C) 1988-2023 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being "Funding Free Software", the Front-Cover +Texts being (a) (see below), and with the Back-Cover Texts being (b) +(see below). A copy of the license is included in the section entitled +"GNU Free Documentation License". + +(a) The FSF's Front-Cover Text is: + +A GNU Manual + +(b) The FSF's Back-Cover Text is: + +You have freedom to copy and modify this GNU Manual, like GNU + software. Copies published by the Free Software Foundation raise + funds for GNU development. --> +<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> +<head> +<title>Using the GNU Compiler Collection (GCC): RISC-V Options</title> + +<meta name="description" content="Using the GNU Compiler Collection (GCC): RISC-V Options"> +<meta name="keywords" content="Using the GNU Compiler Collection (GCC): RISC-V Options"> +<meta name="resource-type" content="document"> +<meta name="distribution" content="global"> +<meta name="Generator" content="makeinfo"> +<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> +<link href="index.html#Top" rel="start" title="Top"> +<link href="Indices.html#Indices" rel="index" title="Indices"> +<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> +<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options"> +<link href="RL78-Options.html#RL78-Options" rel="next" title="RL78 Options"> +<link href="PRU-Options.html#PRU-Options" rel="previous" title="PRU Options"> +<style type="text/css"> +<!-- +a.summary-letter {text-decoration: none} +blockquote.smallquotation {font-size: smaller} +div.display {margin-left: 3.2em} +div.example {margin-left: 3.2em} +div.indentedblock {margin-left: 3.2em} +div.lisp {margin-left: 3.2em} +div.smalldisplay {margin-left: 3.2em} +div.smallexample {margin-left: 3.2em} +div.smallindentedblock {margin-left: 3.2em; font-size: smaller} +div.smalllisp {margin-left: 3.2em} +kbd {font-style:oblique} +pre.display {font-family: inherit} +pre.format {font-family: inherit} +pre.menu-comment {font-family: serif} +pre.menu-preformatted {font-family: serif} +pre.smalldisplay {font-family: inherit; font-size: smaller} +pre.smallexample {font-size: smaller} +pre.smallformat {font-family: inherit; font-size: smaller} +pre.smalllisp {font-size: smaller} +span.nocodebreak {white-space:nowrap} +span.nolinebreak {white-space:nowrap} +span.roman {font-family:serif; font-weight:normal} +span.sansserif {font-family:sans-serif; font-weight:normal} +ul.no-bullet {list-style: none} +--> +</style> + + +</head> + +<body lang="en_US" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> +<a name="RISC_002dV-Options"></a> +<div class="header"> +<p> +Next: <a href="RL78-Options.html#RL78-Options" accesskey="n" rel="next">RL78 Options</a>, Previous: <a href="PRU-Options.html#PRU-Options" accesskey="p" rel="previous">PRU Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p> +</div> +<hr> +<a name="RISC_002dV-Options-1"></a> +<h4 class="subsection">3.19.40 RISC-V Options</h4> +<a name="index-RISC_002dV-Options"></a> + +<p>These command-line options are defined for RISC-V targets: +</p> +<dl compact="compact"> +<dd><a name="index-mbranch_002dcost-4"></a> +</dd> +<dt><code>-mbranch-cost=<var>n</var></code></dt> +<dd><p>Set the cost of branches to roughly <var>n</var> instructions. +</p> +<a name="index-plt"></a> +</dd> +<dt><code>-mplt</code></dt> +<dt><code>-mno-plt</code></dt> +<dd><p>When generating PIC code, do or don’t allow the use of PLTs. Ignored for +non-PIC. The default is <samp>-mplt</samp>. +</p> +<a name="index-mabi-4"></a> +</dd> +<dt><code>-mabi=<var>ABI-string</var></code></dt> +<dd><p>Specify integer and floating-point calling convention. <var>ABI-string</var> +contains two parts: the size of integer types and the registers used for +floating-point types. For example ‘<samp>-march=rv64ifd -mabi=lp64d</samp>’ means that +‘<samp>long</samp>’ and pointers are 64-bit (implicitly defining ‘<samp>int</samp>’ to be +32-bit), and that floating-point values up to 64 bits wide are passed in F +registers. Contrast this with ‘<samp>-march=rv64ifd -mabi=lp64f</samp>’, which still +allows the compiler to generate code that uses the F and D extensions but only +allows floating-point values up to 32 bits long to be passed in registers; or +‘<samp>-march=rv64ifd -mabi=lp64</samp>’, in which no floating-point arguments will be +passed in registers. +</p> +<p>The default for this argument is system dependent, users who want a specific +calling convention should specify one explicitly. The valid calling +conventions are: ‘<samp>ilp32</samp>’, ‘<samp>ilp32f</samp>’, ‘<samp>ilp32d</samp>’, ‘<samp>lp64</samp>’, +‘<samp>lp64f</samp>’, and ‘<samp>lp64d</samp>’. Some calling conventions are impossible to +implement on some ISAs: for example, ‘<samp>-march=rv32if -mabi=ilp32d</samp>’ is +invalid because the ABI requires 64-bit values be passed in F registers, but F +registers are only 32 bits wide. There is also the ‘<samp>ilp32e</samp>’ ABI that can +only be used with the ‘<samp>rv32e</samp>’ architecture. This ABI is not well +specified at present, and is subject to change. +</p> +<a name="index-mfdiv"></a> +</dd> +<dt><code>-mfdiv</code></dt> +<dt><code>-mno-fdiv</code></dt> +<dd><p>Do or don’t use hardware floating-point divide and square root instructions. +This requires the F or D extensions for floating-point registers. The default +is to use them if the specified architecture has these instructions. +</p> +<a name="index-mdiv-3"></a> +</dd> +<dt><code>-mdiv</code></dt> +<dt><code>-mno-div</code></dt> +<dd><p>Do or don’t use hardware instructions for integer division. This requires the +M extension. The default is to use them if the specified architecture has +these instructions. +</p> +<a name="index-misa_002dspec"></a> +</dd> +<dt><code>-misa-spec=<var>ISA-spec-string</var></code></dt> +<dd><p>Specify the version of the RISC-V Unprivileged (formerly User-Level) +ISA specification to produce code conforming to. The possibilities +for <var>ISA-spec-string</var> are: +</p><dl compact="compact"> +<dt><code>2.2</code></dt> +<dd><p>Produce code conforming to version 2.2. +</p></dd> +<dt><code>20190608</code></dt> +<dd><p>Produce code conforming to version 20190608. +</p></dd> +<dt><code>20191213</code></dt> +<dd><p>Produce code conforming to version 20191213. +</p></dd> +</dl> +<p>The default is <samp>-misa-spec=20191213</samp> unless GCC has been configured +with <samp>--with-isa-spec=</samp> specifying a different default version. +</p> +<a name="index-march-14"></a> +</dd> +<dt><code>-march=<var>ISA-string</var></code></dt> +<dd><p>Generate code for given RISC-V ISA (e.g. ‘<samp>rv64im</samp>’). ISA strings must be +lower-case. Examples include ‘<samp>rv64i</samp>’, ‘<samp>rv32g</samp>’, ‘<samp>rv32e</samp>’, and +‘<samp>rv32imaf</samp>’. +</p> +<p>When <samp>-march=</samp> is not specified, use the setting from <samp>-mcpu</samp>. +</p> +<p>If both <samp>-march</samp> and <samp>-mcpu=</samp> are not specified, the default for +this argument is system dependent, users who want a specific architecture +extensions should specify one explicitly. +</p> +<a name="index-mcpu-8"></a> +</dd> +<dt><code>-mcpu=<var>processor-string</var></code></dt> +<dd><p>Use architecture of and optimize the output for the given processor, specified +by particular CPU name. +Permissible values for this option are: ‘<samp>sifive-e20</samp>’, ‘<samp>sifive-e21</samp>’, +‘<samp>sifive-e24</samp>’, ‘<samp>sifive-e31</samp>’, ‘<samp>sifive-e34</samp>’, ‘<samp>sifive-e76</samp>’, +‘<samp>sifive-s21</samp>’, ‘<samp>sifive-s51</samp>’, ‘<samp>sifive-s54</samp>’, ‘<samp>sifive-s76</samp>’, +‘<samp>sifive-u54</samp>’, and ‘<samp>sifive-u74</samp>’. +</p> +<a name="index-mtune-12"></a> +</dd> +<dt><code>-mtune=<var>processor-string</var></code></dt> +<dd><p>Optimize the output for the given processor, specified by microarchitecture or +particular CPU name. Permissible values for this option are: ‘<samp>rocket</samp>’, +‘<samp>sifive-3-series</samp>’, ‘<samp>sifive-5-series</samp>’, ‘<samp>sifive-7-series</samp>’, +‘<samp>thead-c906</samp>’, ‘<samp>size</samp>’, and all valid options for <samp>-mcpu=</samp>. +</p> +<p>When <samp>-mtune=</samp> is not specified, use the setting from <samp>-mcpu</samp>, +the default is ‘<samp>rocket</samp>’ if both are not specified. +</p> +<p>The ‘<samp>size</samp>’ choice is not intended for use by end-users. This is used +when <samp>-Os</samp> is specified. It overrides the instruction cost info +provided by <samp>-mtune=</samp>, but does not override the pipeline info. This +helps reduce code size while still giving good performance. +</p> +<a name="index-mpreferred_002dstack_002dboundary"></a> +</dd> +<dt><code>-mpreferred-stack-boundary=<var>num</var></code></dt> +<dd><p>Attempt to keep the stack boundary aligned to a 2 raised to <var>num</var> +byte boundary. If <samp>-mpreferred-stack-boundary</samp> is not specified, +the default is 4 (16 bytes or 128-bits). +</p> +<p><strong>Warning:</strong> If you use this switch, then you must build all modules with +the same value, including any libraries. This includes the system libraries +and startup modules. +</p> +<a name="index-msmall_002ddata_002dlimit-1"></a> +</dd> +<dt><code>-msmall-data-limit=<var>n</var></code></dt> +<dd><p>Put global and static data smaller than <var>n</var> bytes into a special section +(on some targets). +</p> +<a name="index-msave_002drestore"></a> +</dd> +<dt><code>-msave-restore</code></dt> +<dt><code>-mno-save-restore</code></dt> +<dd><p>Do or don’t use smaller but slower prologue and epilogue code that uses +library function calls. The default is to use fast inline prologues and +epilogues. +</p> +<a name="index-minline_002datomics"></a> +</dd> +<dt><code>-minline-atomics</code></dt> +<dt><code>-mno-inline-atomics</code></dt> +<dd><p>Do or don’t use smaller but slower subword atomic emulation code that uses +libatomic function calls. The default is to use fast inline subword atomics +that do not require libatomic. +</p> +<a name="index-mshorten_002dmemrefs"></a> +</dd> +<dt><code>-mshorten-memrefs</code></dt> +<dt><code>-mno-shorten-memrefs</code></dt> +<dd><p>Do or do not attempt to make more use of compressed load/store instructions by +replacing a load/store of ’base register + large offset’ with a new load/store +of ’new base + small offset’. If the new base gets stored in a compressed +register, then the new load/store can be compressed. Currently targets 32-bit +integer load/stores only. +</p> +<a name="index-mstrict_002dalign-3"></a> +</dd> +<dt><code>-mstrict-align</code></dt> +<dt><code>-mno-strict-align</code></dt> +<dd><p>Do not or do generate unaligned memory accesses. The default is set depending +on whether the processor we are optimizing for supports fast unaligned access +or not. +</p> +<a name="index-mcmodel_003dmedlow"></a> +</dd> +<dt><code>-mcmodel=medlow</code></dt> +<dd><p>Generate code for the medium-low code model. The program and its statically +defined symbols must lie within a single 2 GiB address range and must lie +between absolute addresses -2 GiB and +2 GiB. Programs can be +statically or dynamically linked. This is the default code model. +</p> +<a name="index-mcmodel_003dmedany"></a> +</dd> +<dt><code>-mcmodel=medany</code></dt> +<dd><p>Generate code for the medium-any code model. The program and its statically +defined symbols must be within any single 2 GiB address range. Programs can be +statically or dynamically linked. +</p> +<p>The code generated by the medium-any code model is position-independent, but is +not guaranteed to function correctly when linked into position-independent +executables or libraries. +</p> +</dd> +<dt><code>-mexplicit-relocs</code></dt> +<dt><code>-mno-exlicit-relocs</code></dt> +<dd><p>Use or do not use assembler relocation operators when dealing with symbolic +addresses. The alternative is to use assembler macros instead, which may +limit optimization. +</p> +<a name="index-mrelax-5"></a> +</dd> +<dt><code>-mrelax</code></dt> +<dt><code>-mno-relax</code></dt> +<dd><p>Take advantage of linker relaxations to reduce the number of instructions +required to materialize symbol addresses. The default is to take advantage of +linker relaxations. +</p> +<a name="index-mriscv_002dattribute"></a> +</dd> +<dt><code>-mriscv-attribute</code></dt> +<dt><code>-mno-riscv-attribute</code></dt> +<dd><p>Emit (do not emit) RISC-V attribute to record extra information into ELF +objects. This feature requires at least binutils 2.32. +</p> +<a name="index-mcsr_002dcheck"></a> +</dd> +<dt><code>-mcsr-check</code></dt> +<dt><code>-mno-csr-check</code></dt> +<dd><p>Enables or disables the CSR checking. +</p> +<a name="index-malign_002ddata"></a> +</dd> +<dt><code>-malign-data=<var>type</var></code></dt> +<dd><p>Control how GCC aligns variables and constants of array, structure, or union +types. Supported values for <var>type</var> are ‘<samp>xlen</samp>’ which uses x register +width as the alignment value, and ‘<samp>natural</samp>’ which uses natural alignment. +‘<samp>xlen</samp>’ is the default. +</p> +<a name="index-mbig_002dendian-10"></a> +</dd> +<dt><code>-mbig-endian</code></dt> +<dd><p>Generate big-endian code. This is the default when GCC is configured for a +‘<samp>riscv64be-*-*</samp>’ or ‘<samp>riscv32be-*-*</samp>’ target. +</p> +<a name="index-mlittle_002dendian-10"></a> +</dd> +<dt><code>-mlittle-endian</code></dt> +<dd><p>Generate little-endian code. This is the default when GCC is configured for a +‘<samp>riscv64-*-*</samp>’ or ‘<samp>riscv32-*-*</samp>’ but not a ‘<samp>riscv64be-*-*</samp>’ or +‘<samp>riscv32be-*-*</samp>’ target. +</p> +<a name="index-mstack_002dprotector_002dguard-2"></a> +<a name="index-mstack_002dprotector_002dguard_002dreg-1"></a> +<a name="index-mstack_002dprotector_002dguard_002doffset-2"></a> +</dd> +<dt><code>-mstack-protector-guard=<var>guard</var></code></dt> +<dt><code>-mstack-protector-guard-reg=<var>reg</var></code></dt> +<dt><code>-mstack-protector-guard-offset=<var>offset</var></code></dt> +<dd><p>Generate stack protection code using canary at <var>guard</var>. Supported +locations are ‘<samp>global</samp>’ for a global canary or ‘<samp>tls</samp>’ for per-thread +canary in the TLS block. +</p> +<p>With the latter choice the options +<samp>-mstack-protector-guard-reg=<var>reg</var></samp> and +<samp>-mstack-protector-guard-offset=<var>offset</var></samp> furthermore specify +which register to use as base register for reading the canary, +and from what offset from that base register. There is no default +register or offset as this is entirely for use within the Linux +kernel. +</p></dd> +</dl> + +<hr> +<div class="header"> +<p> +Next: <a href="RL78-Options.html#RL78-Options" accesskey="n" rel="next">RL78 Options</a>, Previous: <a href="PRU-Options.html#PRU-Options" accesskey="p" rel="previous">PRU Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p> +</div> + + + +</body> +</html> |