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diff --git a/share/doc/gcc/M680x0-Options.html b/share/doc/gcc/M680x0-Options.html new file mode 100644 index 0000000..f3fd91e --- /dev/null +++ b/share/doc/gcc/M680x0-Options.html @@ -0,0 +1,508 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html> +<!-- This file documents the use of the GNU compilers. + +Copyright (C) 1988-2023 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being "Funding Free Software", the Front-Cover +Texts being (a) (see below), and with the Back-Cover Texts being (b) +(see below). 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Permissible values of <var>arch</var> for M680x0 +architectures are: ‘<samp>68000</samp>’, ‘<samp>68010</samp>’, ‘<samp>68020</samp>’, +‘<samp>68030</samp>’, ‘<samp>68040</samp>’, ‘<samp>68060</samp>’ and ‘<samp>cpu32</samp>’. ColdFire +architectures are selected according to Freescale’s ISA classification +and the permissible values are: ‘<samp>isaa</samp>’, ‘<samp>isaaplus</samp>’, +‘<samp>isab</samp>’ and ‘<samp>isac</samp>’. +</p> +<p>GCC defines a macro <code>__mcf<var>arch</var>__</code> whenever it is generating +code for a ColdFire target. The <var>arch</var> in this macro is one of the +<samp>-march</samp> arguments given above. +</p> +<p>When used together, <samp>-march</samp> and <samp>-mtune</samp> select code +that runs on a family of similar processors but that is optimized +for a particular microarchitecture. +</p> +<a name="index-mcpu-7"></a> +</dd> +<dt><code>-mcpu=<var>cpu</var></code></dt> +<dd><p>Generate code for a specific M680x0 or ColdFire processor. +The M680x0 <var>cpu</var>s are: ‘<samp>68000</samp>’, ‘<samp>68010</samp>’, ‘<samp>68020</samp>’, +‘<samp>68030</samp>’, ‘<samp>68040</samp>’, ‘<samp>68060</samp>’, ‘<samp>68302</samp>’, ‘<samp>68332</samp>’ +and ‘<samp>cpu32</samp>’. The ColdFire <var>cpu</var>s are given by the table +below, which also classifies the CPUs into families: +</p> +<table> +<thead><tr><th width="20%"><strong>Family</strong></th><th width="80%"><strong>‘<samp>-mcpu</samp>’ arguments</strong></th></tr></thead> +<tr><td width="20%">‘<samp>51</samp>’</td><td width="80%">‘<samp>51</samp>’ ‘<samp>51ac</samp>’ ‘<samp>51ag</samp>’ ‘<samp>51cn</samp>’ ‘<samp>51em</samp>’ ‘<samp>51je</samp>’ ‘<samp>51jf</samp>’ ‘<samp>51jg</samp>’ ‘<samp>51jm</samp>’ ‘<samp>51mm</samp>’ ‘<samp>51qe</samp>’ ‘<samp>51qm</samp>’</td></tr> +<tr><td width="20%">‘<samp>5206</samp>’</td><td width="80%">‘<samp>5202</samp>’ ‘<samp>5204</samp>’ ‘<samp>5206</samp>’</td></tr> +<tr><td width="20%">‘<samp>5206e</samp>’</td><td width="80%">‘<samp>5206e</samp>’</td></tr> +<tr><td width="20%">‘<samp>5208</samp>’</td><td width="80%">‘<samp>5207</samp>’ ‘<samp>5208</samp>’</td></tr> +<tr><td width="20%">‘<samp>5211a</samp>’</td><td width="80%">‘<samp>5210a</samp>’ ‘<samp>5211a</samp>’</td></tr> +<tr><td width="20%">‘<samp>5213</samp>’</td><td width="80%">‘<samp>5211</samp>’ ‘<samp>5212</samp>’ ‘<samp>5213</samp>’</td></tr> +<tr><td width="20%">‘<samp>5216</samp>’</td><td width="80%">‘<samp>5214</samp>’ ‘<samp>5216</samp>’</td></tr> +<tr><td width="20%">‘<samp>52235</samp>’</td><td width="80%">‘<samp>52230</samp>’ ‘<samp>52231</samp>’ ‘<samp>52232</samp>’ ‘<samp>52233</samp>’ ‘<samp>52234</samp>’ ‘<samp>52235</samp>’</td></tr> +<tr><td width="20%">‘<samp>5225</samp>’</td><td width="80%">‘<samp>5224</samp>’ ‘<samp>5225</samp>’</td></tr> +<tr><td width="20%">‘<samp>52259</samp>’</td><td width="80%">‘<samp>52252</samp>’ ‘<samp>52254</samp>’ ‘<samp>52255</samp>’ ‘<samp>52256</samp>’ ‘<samp>52258</samp>’ ‘<samp>52259</samp>’</td></tr> +<tr><td width="20%">‘<samp>5235</samp>’</td><td width="80%">‘<samp>5232</samp>’ ‘<samp>5233</samp>’ ‘<samp>5234</samp>’ ‘<samp>5235</samp>’ ‘<samp>523x</samp>’</td></tr> +<tr><td width="20%">‘<samp>5249</samp>’</td><td width="80%">‘<samp>5249</samp>’</td></tr> +<tr><td width="20%">‘<samp>5250</samp>’</td><td width="80%">‘<samp>5250</samp>’</td></tr> +<tr><td width="20%">‘<samp>5271</samp>’</td><td width="80%">‘<samp>5270</samp>’ ‘<samp>5271</samp>’</td></tr> +<tr><td width="20%">‘<samp>5272</samp>’</td><td width="80%">‘<samp>5272</samp>’</td></tr> +<tr><td width="20%">‘<samp>5275</samp>’</td><td width="80%">‘<samp>5274</samp>’ ‘<samp>5275</samp>’</td></tr> +<tr><td width="20%">‘<samp>5282</samp>’</td><td width="80%">‘<samp>5280</samp>’ ‘<samp>5281</samp>’ ‘<samp>5282</samp>’ ‘<samp>528x</samp>’</td></tr> +<tr><td width="20%">‘<samp>53017</samp>’</td><td width="80%">‘<samp>53011</samp>’ ‘<samp>53012</samp>’ ‘<samp>53013</samp>’ ‘<samp>53014</samp>’ ‘<samp>53015</samp>’ ‘<samp>53016</samp>’ ‘<samp>53017</samp>’</td></tr> +<tr><td width="20%">‘<samp>5307</samp>’</td><td width="80%">‘<samp>5307</samp>’</td></tr> +<tr><td width="20%">‘<samp>5329</samp>’</td><td width="80%">‘<samp>5327</samp>’ ‘<samp>5328</samp>’ ‘<samp>5329</samp>’ ‘<samp>532x</samp>’</td></tr> +<tr><td width="20%">‘<samp>5373</samp>’</td><td width="80%">‘<samp>5372</samp>’ ‘<samp>5373</samp>’ ‘<samp>537x</samp>’</td></tr> +<tr><td width="20%">‘<samp>5407</samp>’</td><td width="80%">‘<samp>5407</samp>’</td></tr> +<tr><td width="20%">‘<samp>5475</samp>’</td><td width="80%">‘<samp>5470</samp>’ ‘<samp>5471</samp>’ ‘<samp>5472</samp>’ ‘<samp>5473</samp>’ ‘<samp>5474</samp>’ ‘<samp>5475</samp>’ ‘<samp>547x</samp>’ ‘<samp>5480</samp>’ ‘<samp>5481</samp>’ ‘<samp>5482</samp>’ ‘<samp>5483</samp>’ ‘<samp>5484</samp>’ ‘<samp>5485</samp>’</td></tr> +</table> + +<p><samp>-mcpu=<var>cpu</var></samp> overrides <samp>-march=<var>arch</var></samp> if +<var>arch</var> is compatible with <var>cpu</var>. Other combinations of +<samp>-mcpu</samp> and <samp>-march</samp> are rejected. +</p> +<p>GCC defines the macro <code>__mcf_cpu_<var>cpu</var></code> when ColdFire target +<var>cpu</var> is selected. It also defines <code>__mcf_family_<var>family</var></code>, +where the value of <var>family</var> is given by the table above. +</p> +<a name="index-mtune-9"></a> +</dd> +<dt><code>-mtune=<var>tune</var></code></dt> +<dd><p>Tune the code for a particular microarchitecture within the +constraints set by <samp>-march</samp> and <samp>-mcpu</samp>. +The M680x0 microarchitectures are: ‘<samp>68000</samp>’, ‘<samp>68010</samp>’, +‘<samp>68020</samp>’, ‘<samp>68030</samp>’, ‘<samp>68040</samp>’, ‘<samp>68060</samp>’ +and ‘<samp>cpu32</samp>’. The ColdFire microarchitectures +are: ‘<samp>cfv1</samp>’, ‘<samp>cfv2</samp>’, ‘<samp>cfv3</samp>’, ‘<samp>cfv4</samp>’ and ‘<samp>cfv4e</samp>’. +</p> +<p>You can also use <samp>-mtune=68020-40</samp> for code that needs +to run relatively well on 68020, 68030 and 68040 targets. +<samp>-mtune=68020-60</samp> is similar but includes 68060 targets +as well. These two options select the same tuning decisions as +<samp>-m68020-40</samp> and <samp>-m68020-60</samp> respectively. +</p> +<p>GCC defines the macros <code>__mc<var>arch</var></code> and <code>__mc<var>arch</var>__</code> +when tuning for 680x0 architecture <var>arch</var>. It also defines +<code>mc<var>arch</var></code> unless either <samp>-ansi</samp> or a non-GNU <samp>-std</samp> +option is used. If GCC is tuning for a range of architectures, +as selected by <samp>-mtune=68020-40</samp> or <samp>-mtune=68020-60</samp>, +it defines the macros for every architecture in the range. +</p> +<p>GCC also defines the macro <code>__m<var>uarch</var>__</code> when tuning for +ColdFire microarchitecture <var>uarch</var>, where <var>uarch</var> is one +of the arguments given above. +</p> +<a name="index-m68000"></a> +<a name="index-mc68000"></a> +</dd> +<dt><code>-m68000</code></dt> +<dt><code>-mc68000</code></dt> +<dd><p>Generate output for a 68000. This is the default +when the compiler is configured for 68000-based systems. +It is equivalent to <samp>-march=68000</samp>. +</p> +<p>Use this option for microcontrollers with a 68000 or EC000 core, +including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. +</p> +<a name="index-m68010"></a> +</dd> +<dt><code>-m68010</code></dt> +<dd><p>Generate output for a 68010. This is the default +when the compiler is configured for 68010-based systems. +It is equivalent to <samp>-march=68010</samp>. +</p> +<a name="index-m68020"></a> +<a name="index-mc68020"></a> +</dd> +<dt><code>-m68020</code></dt> +<dt><code>-mc68020</code></dt> +<dd><p>Generate output for a 68020. This is the default +when the compiler is configured for 68020-based systems. +It is equivalent to <samp>-march=68020</samp>. +</p> +<a name="index-m68030"></a> +</dd> +<dt><code>-m68030</code></dt> +<dd><p>Generate output for a 68030. This is the default when the compiler is +configured for 68030-based systems. It is equivalent to +<samp>-march=68030</samp>. +</p> +<a name="index-m68040"></a> +</dd> +<dt><code>-m68040</code></dt> +<dd><p>Generate output for a 68040. This is the default when the compiler is +configured for 68040-based systems. It is equivalent to +<samp>-march=68040</samp>. +</p> +<p>This option inhibits the use of 68881/68882 instructions that have to be +emulated by software on the 68040. Use this option if your 68040 does not +have code to emulate those instructions. +</p> +<a name="index-m68060"></a> +</dd> +<dt><code>-m68060</code></dt> +<dd><p>Generate output for a 68060. This is the default when the compiler is +configured for 68060-based systems. It is equivalent to +<samp>-march=68060</samp>. +</p> +<p>This option inhibits the use of 68020 and 68881/68882 instructions that +have to be emulated by software on the 68060. Use this option if your 68060 +does not have code to emulate those instructions. +</p> +<a name="index-mcpu32"></a> +</dd> +<dt><code>-mcpu32</code></dt> +<dd><p>Generate output for a CPU32. This is the default +when the compiler is configured for CPU32-based systems. +It is equivalent to <samp>-march=cpu32</samp>. +</p> +<p>Use this option for microcontrollers with a +CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334, +68336, 68340, 68341, 68349 and 68360. +</p> +<a name="index-m5200"></a> +</dd> +<dt><code>-m5200</code></dt> +<dd><p>Generate output for a 520X ColdFire CPU. This is the default +when the compiler is configured for 520X-based systems. +It is equivalent to <samp>-mcpu=5206</samp>, and is now deprecated +in favor of that option. +</p> +<p>Use this option for microcontroller with a 5200 core, including +the MCF5202, MCF5203, MCF5204 and MCF5206. +</p> +<a name="index-m5206e"></a> +</dd> +<dt><code>-m5206e</code></dt> +<dd><p>Generate output for a 5206e ColdFire CPU. The option is now +deprecated in favor of the equivalent <samp>-mcpu=5206e</samp>. +</p> +<a name="index-m528x"></a> +</dd> +<dt><code>-m528x</code></dt> +<dd><p>Generate output for a member of the ColdFire 528X family. +The option is now deprecated in favor of the equivalent +<samp>-mcpu=528x</samp>. +</p> +<a name="index-m5307"></a> +</dd> +<dt><code>-m5307</code></dt> +<dd><p>Generate output for a ColdFire 5307 CPU. The option is now deprecated +in favor of the equivalent <samp>-mcpu=5307</samp>. +</p> +<a name="index-m5407"></a> +</dd> +<dt><code>-m5407</code></dt> +<dd><p>Generate output for a ColdFire 5407 CPU. The option is now deprecated +in favor of the equivalent <samp>-mcpu=5407</samp>. +</p> +<a name="index-mcfv4e"></a> +</dd> +<dt><code>-mcfv4e</code></dt> +<dd><p>Generate output for a ColdFire V4e family CPU (e.g. 547x/548x). +This includes use of hardware floating-point instructions. +The option is equivalent to <samp>-mcpu=547x</samp>, and is now +deprecated in favor of that option. +</p> +<a name="index-m68020_002d40"></a> +</dd> +<dt><code>-m68020-40</code></dt> +<dd><p>Generate output for a 68040, without using any of the new instructions. +This results in code that can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68040. +</p> +<p>The option is equivalent to <samp>-march=68020</samp> <samp>-mtune=68020-40</samp>. +</p> +<a name="index-m68020_002d60"></a> +</dd> +<dt><code>-m68020-60</code></dt> +<dd><p>Generate output for a 68060, without using any of the new instructions. +This results in code that can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68060. +</p> +<p>The option is equivalent to <samp>-march=68020</samp> <samp>-mtune=68020-60</samp>. +</p> +<a name="index-mhard_002dfloat-2"></a> +<a name="index-m68881"></a> +</dd> +<dt><code>-mhard-float</code></dt> +<dt><code>-m68881</code></dt> +<dd><p>Generate floating-point instructions. This is the default for 68020 +and above, and for ColdFire devices that have an FPU. It defines the +macro <code>__HAVE_68881__</code> on M680x0 targets and <code>__mcffpu__</code> +on ColdFire targets. +</p> +<a name="index-msoft_002dfloat-6"></a> +</dd> +<dt><code>-msoft-float</code></dt> +<dd><p>Do not generate floating-point instructions; use library calls instead. +This is the default for 68000, 68010, and 68832 targets. It is also +the default for ColdFire devices that have no FPU. +</p> +<a name="index-mdiv-1"></a> +<a name="index-mno_002ddiv"></a> +</dd> +<dt><code>-mdiv</code></dt> +<dt><code>-mno-div</code></dt> +<dd><p>Generate (do not generate) ColdFire hardware divide and remainder +instructions. If <samp>-march</samp> is used without <samp>-mcpu</samp>, +the default is “on” for ColdFire architectures and “off” for M680x0 +architectures. Otherwise, the default is taken from the target CPU +(either the default CPU, or the one specified by <samp>-mcpu</samp>). For +example, the default is “off” for <samp>-mcpu=5206</samp> and “on” for +<samp>-mcpu=5206e</samp>. +</p> +<p>GCC defines the macro <code>__mcfhwdiv__</code> when this option is enabled. +</p> +<a name="index-mshort"></a> +</dd> +<dt><code>-mshort</code></dt> +<dd><p>Consider type <code>int</code> to be 16 bits wide, like <code>short int</code>. +Additionally, parameters passed on the stack are also aligned to a +16-bit boundary even on targets whose API mandates promotion to 32-bit. +</p> +<a name="index-mno_002dshort"></a> +</dd> +<dt><code>-mno-short</code></dt> +<dd><p>Do not consider type <code>int</code> to be 16 bits wide. This is the default. +</p> +<a name="index-mnobitfield"></a> +<a name="index-mno_002dbitfield"></a> +</dd> +<dt><code>-mnobitfield</code></dt> +<dt><code>-mno-bitfield</code></dt> +<dd><p>Do not use the bit-field instructions. The <samp>-m68000</samp>, <samp>-mcpu32</samp> +and <samp>-m5200</samp> options imply <samp><span class="nolinebreak">-mnobitfield</span></samp><!-- /@w -->. +</p> +<a name="index-mbitfield"></a> +</dd> +<dt><code>-mbitfield</code></dt> +<dd><p>Do use the bit-field instructions. The <samp>-m68020</samp> option implies +<samp>-mbitfield</samp>. This is the default if you use a configuration +designed for a 68020. +</p> +<a name="index-mrtd"></a> +</dd> +<dt><code>-mrtd</code></dt> +<dd><p>Use a different function-calling convention, in which functions +that take a fixed number of arguments return with the <code>rtd</code> +instruction, which pops their arguments while returning. This +saves one instruction in the caller since there is no need to pop +the arguments there. +</p> +<p>This calling convention is incompatible with the one normally +used on Unix, so you cannot use it if you need to call libraries +compiled with the Unix compiler. +</p> +<p>Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including <code>printf</code>); +otherwise incorrect code is generated for calls to those +functions. +</p> +<p>In addition, seriously incorrect code results if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +</p> +<p>The <code>rtd</code> instruction is supported by the 68010, 68020, 68030, +68040, 68060 and CPU32 processors, but not by the 68000 or 5200. +</p> +<p>The default is <samp>-mno-rtd</samp>. +</p> +<a name="index-malign_002dint"></a> +<a name="index-mno_002dalign_002dint"></a> +</dd> +<dt><code>-malign-int</code></dt> +<dt><code>-mno-align-int</code></dt> +<dd><p>Control whether GCC aligns <code>int</code>, <code>long</code>, <code>long long</code>, +<code>float</code>, <code>double</code>, and <code>long double</code> variables on a 32-bit +boundary (<samp>-malign-int</samp>) or a 16-bit boundary (<samp>-mno-align-int</samp>). +Aligning variables on 32-bit boundaries produces code that runs somewhat +faster on processors with 32-bit busses at the expense of more memory. +</p> +<p><strong>Warning:</strong> if you use the <samp>-malign-int</samp> switch, GCC +aligns structures containing the above types differently than +most published application binary interface specifications for the m68k. +</p> +<a name="index-mpcrel"></a> +<p>Use the pc-relative addressing mode of the 68000 directly, instead of +using a global offset table. At present, this option implies <samp>-fpic</samp>, +allowing at most a 16-bit offset for pc-relative addressing. <samp>-fPIC</samp> is +not presently supported with <samp>-mpcrel</samp>, though this could be supported for +68020 and higher processors. +</p> +<a name="index-mno_002dstrict_002dalign-1"></a> +<a name="index-mstrict_002dalign-2"></a> +</dd> +<dt><code>-mno-strict-align</code></dt> +<dt><code>-mstrict-align</code></dt> +<dd><p>Do not (do) assume that unaligned memory references are handled by +the system. +</p> +</dd> +<dt><code>-msep-data</code></dt> +<dd><p>Generate code that allows the data segment to be located in a different +area of memory from the text segment. This allows for execute-in-place in +an environment without virtual memory management. This option implies +<samp>-fPIC</samp>. +</p> +</dd> +<dt><code>-mno-sep-data</code></dt> +<dd><p>Generate code that assumes that the data segment follows the text segment. +This is the default. +</p> +</dd> +<dt><code>-mid-shared-library</code></dt> +<dd><p>Generate code that supports shared libraries via the library ID method. +This allows for execute-in-place and shared libraries in an environment +without virtual memory management. This option implies <samp>-fPIC</samp>. +</p> +</dd> +<dt><code>-mno-id-shared-library</code></dt> +<dd><p>Generate code that doesn’t assume ID-based shared libraries are being used. +This is the default. +</p> +</dd> +<dt><code>-mshared-library-id=n</code></dt> +<dd><p>Specifies the identification number of the ID-based shared library being +compiled. Specifying a value of 0 generates more compact code; specifying +other values forces the allocation of that number to the current +library, but is no more space- or time-efficient than omitting this option. +</p> +<a name="index-mxgot"></a> +<a name="index-mno_002dxgot"></a> +</dd> +<dt><code>-mxgot</code></dt> +<dt><code>-mno-xgot</code></dt> +<dd><p>When generating position-independent code for ColdFire, generate code +that works if the GOT has more than 8192 entries. This code is +larger and slower than code generated without this option. On M680x0 +processors, this option is not needed; <samp>-fPIC</samp> suffices. +</p> +<p>GCC normally uses a single instruction to load values from the GOT. +While this is relatively efficient, it only works if the GOT +is smaller than about 64k. Anything larger causes the linker +to report an error such as: +</p> +<a name="index-relocation-truncated-to-fit-_0028ColdFire_0029"></a> +<div class="smallexample"> +<pre class="smallexample">relocation truncated to fit: R_68K_GOT16O foobar +</pre></div> + +<p>If this happens, you should recompile your code with <samp>-mxgot</samp>. +It should then work with very large GOTs. However, code generated with +<samp>-mxgot</samp> is less efficient, since it takes 4 instructions to fetch +the value of a global symbol. +</p> +<p>Note that some linkers, including newer versions of the GNU linker, +can create multiple GOTs and sort GOT entries. If you have such a linker, +you should only need to use <samp>-mxgot</samp> when compiling a single +object file that accesses more than 8192 GOT entries. Very few do. +</p> +<p>These options have no effect unless GCC is generating +position-independent code. +</p> +<a name="index-mlong_002djump_002dtable_002doffsets"></a> +</dd> +<dt><code>-mlong-jump-table-offsets</code></dt> +<dd><p>Use 32-bit offsets in <code>switch</code> tables. The default is to use +16-bit offsets. +</p> +</dd> +</dl> + +<hr> +<div class="header"> +<p> +Next: <a href="MCore-Options.html#MCore-Options" accesskey="n" rel="next">MCore Options</a>, Previous: <a href="M32R_002fD-Options.html#M32R_002fD-Options" accesskey="p" rel="previous">M32R/D Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p> +</div> + + + +</body> +</html> |