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diff --git a/share/doc/gcc/ARM-Options.html b/share/doc/gcc/ARM-Options.html new file mode 100644 index 0000000..6b2d3af --- /dev/null +++ b/share/doc/gcc/ARM-Options.html @@ -0,0 +1,1370 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html> +<!-- This file documents the use of the GNU compilers. + +Copyright (C) 1988-2023 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being "Funding Free Software", the Front-Cover +Texts being (a) (see below), and with the Back-Cover Texts being (b) +(see below). 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Permissible values are: ‘<samp>apcs-gnu</samp>’, +‘<samp>atpcs</samp>’, ‘<samp>aapcs</samp>’, ‘<samp>aapcs-linux</samp>’ and ‘<samp>iwmmxt</samp>’. +</p> +<a name="index-mapcs_002dframe"></a> +</dd> +<dt><code>-mapcs-frame</code></dt> +<dd><p>Generate a stack frame that is compliant with the ARM Procedure Call +Standard for all functions, even if this is not strictly necessary for +correct execution of the code. Specifying <samp>-fomit-frame-pointer</samp> +with this option causes the stack frames not to be generated for +leaf functions. The default is <samp>-mno-apcs-frame</samp>. +This option is deprecated. +</p> +<a name="index-mapcs"></a> +</dd> +<dt><code>-mapcs</code></dt> +<dd><p>This is a synonym for <samp>-mapcs-frame</samp> and is deprecated. +</p> + +<a name="index-mthumb_002dinterwork"></a> +</dd> +<dt><code>-mthumb-interwork</code></dt> +<dd><p>Generate code that supports calling between the ARM and Thumb +instruction sets. Without this option, on pre-v5 architectures, the +two instruction sets cannot be reliably used inside one program. The +default is <samp>-mno-thumb-interwork</samp>, since slightly larger code +is generated when <samp>-mthumb-interwork</samp> is specified. In AAPCS +configurations this option is meaningless. +</p> +<a name="index-mno_002dsched_002dprolog"></a> +<a name="index-msched_002dprolog"></a> +</dd> +<dt><code>-mno-sched-prolog</code></dt> +<dd><p>Prevent the reordering of instructions in the function prologue, or the +merging of those instruction with the instructions in the function’s +body. This means that all functions start with a recognizable set +of instructions (or in fact one of a choice from a small set of +different function prologues), and this information can be used to +locate the start of functions inside an executable piece of code. The +default is <samp>-msched-prolog</samp>. +</p> +<a name="index-mfloat_002dabi"></a> +</dd> +<dt><code>-mfloat-abi=<var>name</var></code></dt> +<dd><p>Specifies which floating-point ABI to use. Permissible values +are: ‘<samp>soft</samp>’, ‘<samp>softfp</samp>’ and ‘<samp>hard</samp>’. +</p> +<p>Specifying ‘<samp>soft</samp>’ causes GCC to generate output containing +library calls for floating-point operations. +‘<samp>softfp</samp>’ allows the generation of code using hardware floating-point +instructions, but still uses the soft-float calling conventions. +‘<samp>hard</samp>’ allows generation of floating-point instructions +and uses FPU-specific calling conventions. +</p> +<p>The default depends on the specific target configuration. Note that +the hard-float and soft-float ABIs are not link-compatible; you must +compile your entire program with the same ABI, and link with a +compatible set of libraries. +</p> +<a name="index-mgeneral_002dregs_002donly-1"></a> +</dd> +<dt><code>-mgeneral-regs-only</code></dt> +<dd><p>Generate code which uses only the general-purpose registers. This will prevent +the compiler from using floating-point and Advanced SIMD registers but will not +impose any restrictions on the assembler. +</p> +<a name="index-mlittle_002dendian-2"></a> +</dd> +<dt><code>-mlittle-endian</code></dt> +<dd><p>Generate code for a processor running in little-endian mode. This is +the default for all standard configurations. +</p> +<a name="index-mbig_002dendian-2"></a> +</dd> +<dt><code>-mbig-endian</code></dt> +<dd><p>Generate code for a processor running in big-endian mode; the default is +to compile code for a little-endian processor. +</p> +<a name="index-mbe8"></a> +</dd> +<dt><code>-mbe8</code></dt> +<dt><code>-mbe32</code></dt> +<dd><p>When linking a big-endian image select between BE8 and BE32 formats. +The option has no effect for little-endian images and is ignored. The +default is dependent on the selected target architecture. For ARMv6 +and later architectures the default is BE8, for older architectures +the default is BE32. BE32 format has been deprecated by ARM. +</p> +<a name="index-march-2"></a> +</dd> +<dt><code>-march=<var>name</var><span class="roman">[</span>+extension…<span class="roman">]</span></code></dt> +<dd><p>This specifies the name of the target ARM architecture. GCC uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the <samp>-mcpu=</samp> option. +</p> +<p>Permissible names are: +‘<samp>armv4t</samp>’, +‘<samp>armv5t</samp>’, ‘<samp>armv5te</samp>’, +‘<samp>armv6</samp>’, ‘<samp>armv6j</samp>’, ‘<samp>armv6k</samp>’, ‘<samp>armv6kz</samp>’, ‘<samp>armv6t2</samp>’, +‘<samp>armv6z</samp>’, ‘<samp>armv6zk</samp>’, +‘<samp>armv7</samp>’, ‘<samp>armv7-a</samp>’, ‘<samp>armv7ve</samp>’, +‘<samp>armv8-a</samp>’, ‘<samp>armv8.1-a</samp>’, ‘<samp>armv8.2-a</samp>’, ‘<samp>armv8.3-a</samp>’, +‘<samp>armv8.4-a</samp>’, +‘<samp>armv8.5-a</samp>’, +‘<samp>armv8.6-a</samp>’, +‘<samp>armv9-a</samp>’, +‘<samp>armv7-r</samp>’, +‘<samp>armv8-r</samp>’, +‘<samp>armv6-m</samp>’, ‘<samp>armv6s-m</samp>’, +‘<samp>armv7-m</samp>’, ‘<samp>armv7e-m</samp>’, +‘<samp>armv8-m.base</samp>’, ‘<samp>armv8-m.main</samp>’, +‘<samp>armv8.1-m.main</samp>’, +‘<samp>armv9-a</samp>’, +‘<samp>iwmmxt</samp>’ and ‘<samp>iwmmxt2</samp>’. +</p> +<p>Additionally, the following architectures, which lack support for the +Thumb execution state, are recognized but support is deprecated: ‘<samp>armv4</samp>’. +</p> +<p>Many of the architectures support extensions. These can be added by +appending ‘<samp>+<var>extension</var></samp>’ to the architecture name. Extension +options are processed in order and capabilities accumulate. An extension +will also enable any necessary base extensions +upon which it depends. For example, the ‘<samp>+crypto</samp>’ extension +will always enable the ‘<samp>+simd</samp>’ extension. The exception to the +additive construction is for extensions that are prefixed with +‘<samp>+no…</samp>’: these extensions disable the specified option and +any other extensions that may depend on the presence of that +extension. +</p> +<p>For example, ‘<samp>-march=armv7-a+simd+nofp+vfpv4</samp>’ is equivalent to +writing ‘<samp>-march=armv7-a+vfpv4</samp>’ since the ‘<samp>+simd</samp>’ option is +entirely disabled by the ‘<samp>+nofp</samp>’ option that follows it. +</p> +<p>Most extension names are generically named, but have an effect that is +dependent upon the architecture to which it is applied. For example, +the ‘<samp>+simd</samp>’ option can be applied to both ‘<samp>armv7-a</samp>’ and +‘<samp>armv8-a</samp>’ architectures, but will enable the original ARMv7-A +Advanced SIMD (Neon) extensions for ‘<samp>armv7-a</samp>’ and the ARMv8-A +variant for ‘<samp>armv8-a</samp>’. +</p> +<p>The table below lists the supported extensions for each architecture. +Architectures not mentioned do not support any extensions. +</p> +<dl compact="compact"> +<dt>‘<samp>armv5te</samp>’</dt> +<dt>‘<samp>armv6</samp>’</dt> +<dt>‘<samp>armv6j</samp>’</dt> +<dt>‘<samp>armv6k</samp>’</dt> +<dt>‘<samp>armv6kz</samp>’</dt> +<dt>‘<samp>armv6t2</samp>’</dt> +<dt>‘<samp>armv6z</samp>’</dt> +<dt>‘<samp>armv6zk</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+fp</samp>’</dt> +<dd><p>The VFPv2 floating-point instructions. The extension ‘<samp>+vfpv2</samp>’ can be +used as an alias for this extension. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv7</samp>’</dt> +<dd><p>The common subset of the ARMv7-A, ARMv7-R and ARMv7-M architectures. +</p><dl compact="compact"> +<dt>‘<samp>+fp</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension ‘<samp>+vfpv3-d16</samp>’ can be used as an alias +for this extension. Note that floating-point is not supported by the +base ARMv7-M architecture, but is compatible with both the ARMv7-A and +ARMv7-R architectures. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv7-a</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+mp</samp>’</dt> +<dd><p>The multiprocessing extension. +</p> +</dd> +<dt>‘<samp>+sec</samp>’</dt> +<dd><p>The security extension. +</p> +</dd> +<dt>‘<samp>+fp</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension ‘<samp>+vfpv3-d16</samp>’ can be used as an alias +for this extension. +</p> +</dd> +<dt>‘<samp>+simd</samp>’</dt> +<dd><p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. +The extensions ‘<samp>+neon</samp>’ and ‘<samp>+neon-vfpv3</samp>’ can be used as aliases +for this extension. +</p> +</dd> +<dt>‘<samp>+vfpv3</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions, with 32 double-precision +registers. +</p> +</dd> +<dt>‘<samp>+vfpv3-d16-fp16</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. +</p> +</dd> +<dt>‘<samp>+vfpv3-fp16</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. +</p> +</dd> +<dt>‘<samp>+vfpv4-d16</samp>’</dt> +<dd><p>The VFPv4 floating-point instructions, with 16 double-precision +registers. +</p> +</dd> +<dt>‘<samp>+vfpv4</samp>’</dt> +<dd><p>The VFPv4 floating-point instructions, with 32 double-precision +registers. +</p> +</dd> +<dt>‘<samp>+neon-fp16</samp>’</dt> +<dd><p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. +</p> +</dd> +<dt>‘<samp>+neon-vfpv4</samp>’</dt> +<dd><p>The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. +</p> +</dd> +<dt>‘<samp>+nosimd</samp>’</dt> +<dd><p>Disable the Advanced SIMD instructions (does not disable floating point). +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point and Advanced SIMD instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv7ve</samp>’</dt> +<dd><p>The extended version of the ARMv7-A architecture with support for +virtualization. +</p><dl compact="compact"> +<dt>‘<samp>+fp</samp>’</dt> +<dd><p>The VFPv4 floating-point instructions, with 16 double-precision registers. +The extension ‘<samp>+vfpv4-d16</samp>’ can be used as an alias for this extension. +</p> +</dd> +<dt>‘<samp>+simd</samp>’</dt> +<dd><p>The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. The +extension ‘<samp>+neon-vfpv4</samp>’ can be used as an alias for this extension. +</p> +</dd> +<dt>‘<samp>+vfpv3-d16</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions, with 16 double-precision +registers. +</p> +</dd> +<dt>‘<samp>+vfpv3</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions, with 32 double-precision +registers. +</p> +</dd> +<dt>‘<samp>+vfpv3-d16-fp16</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. +</p> +</dd> +<dt>‘<samp>+vfpv3-fp16</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. +</p> +</dd> +<dt>‘<samp>+vfpv4-d16</samp>’</dt> +<dd><p>The VFPv4 floating-point instructions, with 16 double-precision +registers. +</p> +</dd> +<dt>‘<samp>+vfpv4</samp>’</dt> +<dd><p>The VFPv4 floating-point instructions, with 32 double-precision +registers. +</p> +</dd> +<dt>‘<samp>+neon</samp>’</dt> +<dd><p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. +The extension ‘<samp>+neon-vfpv3</samp>’ can be used as an alias for this extension. +</p> +</dd> +<dt>‘<samp>+neon-fp16</samp>’</dt> +<dd><p>The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. +</p> +</dd> +<dt>‘<samp>+nosimd</samp>’</dt> +<dd><p>Disable the Advanced SIMD instructions (does not disable floating point). +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point and Advanced SIMD instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv8-a</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+crc</samp>’</dt> +<dd><p>The Cyclic Redundancy Check (CRC) instructions. +</p></dd> +<dt>‘<samp>+simd</samp>’</dt> +<dd><p>The ARMv8-A Advanced SIMD and floating-point instructions. +</p></dd> +<dt>‘<samp>+crypto</samp>’</dt> +<dd><p>The cryptographic instructions. +</p></dd> +<dt>‘<samp>+nocrypto</samp>’</dt> +<dd><p>Disable the cryptographic instructions. +</p></dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions. +</p></dd> +<dt>‘<samp>+sb</samp>’</dt> +<dd><p>Speculation Barrier Instruction. +</p></dd> +<dt>‘<samp>+predres</samp>’</dt> +<dd><p>Execution and Data Prediction Restriction Instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv8.1-a</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+simd</samp>’</dt> +<dd><p>The ARMv8.1-A Advanced SIMD and floating-point instructions. +</p> +</dd> +<dt>‘<samp>+crypto</samp>’</dt> +<dd><p>The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions. +</p> +</dd> +<dt>‘<samp>+nocrypto</samp>’</dt> +<dd><p>Disable the cryptographic instructions. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions. +</p> +</dd> +<dt>‘<samp>+sb</samp>’</dt> +<dd><p>Speculation Barrier Instruction. +</p> +</dd> +<dt>‘<samp>+predres</samp>’</dt> +<dd><p>Execution and Data Prediction Restriction Instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv8.2-a</samp>’</dt> +<dt>‘<samp>armv8.3-a</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+fp16</samp>’</dt> +<dd><p>The half-precision floating-point data processing instructions. +This also enables the Advanced SIMD and floating-point instructions. +</p> +</dd> +<dt>‘<samp>+fp16fml</samp>’</dt> +<dd><p>The half-precision floating-point fmla extension. This also enables +the half-precision floating-point extension and Advanced SIMD and +floating-point instructions. +</p> +</dd> +<dt>‘<samp>+simd</samp>’</dt> +<dd><p>The ARMv8.1-A Advanced SIMD and floating-point instructions. +</p> +</dd> +<dt>‘<samp>+crypto</samp>’</dt> +<dd><p>The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions. +</p> +</dd> +<dt>‘<samp>+dotprod</samp>’</dt> +<dd><p>Enable the Dot Product extension. This also enables Advanced SIMD instructions. +</p> +</dd> +<dt>‘<samp>+nocrypto</samp>’</dt> +<dd><p>Disable the cryptographic extension. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions. +</p> +</dd> +<dt>‘<samp>+sb</samp>’</dt> +<dd><p>Speculation Barrier Instruction. +</p> +</dd> +<dt>‘<samp>+predres</samp>’</dt> +<dd><p>Execution and Data Prediction Restriction Instructions. +</p> +</dd> +<dt>‘<samp>+i8mm</samp>’</dt> +<dd><p>8-bit Integer Matrix Multiply instructions. +This also enables Advanced SIMD and floating-point instructions. +</p> +</dd> +<dt>‘<samp>+bf16</samp>’</dt> +<dd><p>Brain half-precision floating-point instructions. +This also enables Advanced SIMD and floating-point instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv8.4-a</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+fp16</samp>’</dt> +<dd><p>The half-precision floating-point data processing instructions. +This also enables the Advanced SIMD and floating-point instructions as well +as the Dot Product extension and the half-precision floating-point fmla +extension. +</p> +</dd> +<dt>‘<samp>+simd</samp>’</dt> +<dd><p>The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the +Dot Product extension. +</p> +</dd> +<dt>‘<samp>+crypto</samp>’</dt> +<dd><p>The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions as well as the Dot Product extension. +</p> +</dd> +<dt>‘<samp>+nocrypto</samp>’</dt> +<dd><p>Disable the cryptographic extension. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions. +</p> +</dd> +<dt>‘<samp>+sb</samp>’</dt> +<dd><p>Speculation Barrier Instruction. +</p> +</dd> +<dt>‘<samp>+predres</samp>’</dt> +<dd><p>Execution and Data Prediction Restriction Instructions. +</p> +</dd> +<dt>‘<samp>+i8mm</samp>’</dt> +<dd><p>8-bit Integer Matrix Multiply instructions. +This also enables Advanced SIMD and floating-point instructions. +</p> +</dd> +<dt>‘<samp>+bf16</samp>’</dt> +<dd><p>Brain half-precision floating-point instructions. +This also enables Advanced SIMD and floating-point instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv8.5-a</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+fp16</samp>’</dt> +<dd><p>The half-precision floating-point data processing instructions. +This also enables the Advanced SIMD and floating-point instructions as well +as the Dot Product extension and the half-precision floating-point fmla +extension. +</p> +</dd> +<dt>‘<samp>+simd</samp>’</dt> +<dd><p>The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the +Dot Product extension. +</p> +</dd> +<dt>‘<samp>+crypto</samp>’</dt> +<dd><p>The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions as well as the Dot Product extension. +</p> +</dd> +<dt>‘<samp>+nocrypto</samp>’</dt> +<dd><p>Disable the cryptographic extension. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions. +</p> +</dd> +<dt>‘<samp>+i8mm</samp>’</dt> +<dd><p>8-bit Integer Matrix Multiply instructions. +This also enables Advanced SIMD and floating-point instructions. +</p> +</dd> +<dt>‘<samp>+bf16</samp>’</dt> +<dd><p>Brain half-precision floating-point instructions. +This also enables Advanced SIMD and floating-point instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv8.6-a</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+fp16</samp>’</dt> +<dd><p>The half-precision floating-point data processing instructions. +This also enables the Advanced SIMD and floating-point instructions as well +as the Dot Product extension and the half-precision floating-point fmla +extension. +</p> +</dd> +<dt>‘<samp>+simd</samp>’</dt> +<dd><p>The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the +Dot Product extension. +</p> +</dd> +<dt>‘<samp>+crypto</samp>’</dt> +<dd><p>The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions as well as the Dot Product extension. +</p> +</dd> +<dt>‘<samp>+nocrypto</samp>’</dt> +<dd><p>Disable the cryptographic extension. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions. +</p> +</dd> +<dt>‘<samp>+i8mm</samp>’</dt> +<dd><p>8-bit Integer Matrix Multiply instructions. +This also enables Advanced SIMD and floating-point instructions. +</p> +</dd> +<dt>‘<samp>+bf16</samp>’</dt> +<dd><p>Brain half-precision floating-point instructions. +This also enables Advanced SIMD and floating-point instructions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv7-r</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+fp.sp</samp>’</dt> +<dd><p>The single-precision VFPv3 floating-point instructions. The extension +‘<samp>+vfpv3xd</samp>’ can be used as an alias for this extension. +</p> +</dd> +<dt>‘<samp>+fp</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions with 16 double-precision registers. +The extension +vfpv3-d16 can be used as an alias for this extension. +</p> +</dd> +<dt>‘<samp>+vfpv3xd-d16-fp16</samp>’</dt> +<dd><p>The single-precision VFPv3 floating-point instructions with 16 double-precision +registers and the half-precision floating-point conversion operations. +</p> +</dd> +<dt>‘<samp>+vfpv3-d16-fp16</samp>’</dt> +<dd><p>The VFPv3 floating-point instructions with 16 double-precision +registers and the half-precision floating-point conversion operations. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point extension. +</p> +</dd> +<dt>‘<samp>+idiv</samp>’</dt> +<dd><p>The ARM-state integer division instructions. +</p> +</dd> +<dt>‘<samp>+noidiv</samp>’</dt> +<dd><p>Disable the ARM-state integer division extension. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv7e-m</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+fp</samp>’</dt> +<dd><p>The single-precision VFPv4 floating-point instructions. +</p> +</dd> +<dt>‘<samp>+fpv5</samp>’</dt> +<dd><p>The single-precision FPv5 floating-point instructions. +</p> +</dd> +<dt>‘<samp>+fp.dp</samp>’</dt> +<dd><p>The single- and double-precision FPv5 floating-point instructions. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point extensions. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv8.1-m.main</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+dsp</samp>’</dt> +<dd><p>The DSP instructions. +</p> +</dd> +<dt>‘<samp>+mve</samp>’</dt> +<dd><p>The M-Profile Vector Extension (MVE) integer instructions. +</p> +</dd> +<dt>‘<samp>+mve.fp</samp>’</dt> +<dd><p>The M-Profile Vector Extension (MVE) integer and single precision +floating-point instructions. +</p> +</dd> +<dt>‘<samp>+fp</samp>’</dt> +<dd><p>The single-precision floating-point instructions. +</p> +</dd> +<dt>‘<samp>+fp.dp</samp>’</dt> +<dd><p>The single- and double-precision floating-point instructions. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point extension. +</p> +</dd> +<dt>‘<samp>+cdecp0, +cdecp1, ... , +cdecp7</samp>’</dt> +<dd><p>Enable the Custom Datapath Extension (CDE) on selected coprocessors according +to the numbers given in the options in the range 0 to 7. +</p> +</dd> +<dt>‘<samp>+pacbti</samp>’</dt> +<dd><p>Enable the Pointer Authentication and Branch Target Identification Extension. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv8-m.main</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+dsp</samp>’</dt> +<dd><p>The DSP instructions. +</p> +</dd> +<dt>‘<samp>+nodsp</samp>’</dt> +<dd><p>Disable the DSP extension. +</p> +</dd> +<dt>‘<samp>+fp</samp>’</dt> +<dd><p>The single-precision floating-point instructions. +</p> +</dd> +<dt>‘<samp>+fp.dp</samp>’</dt> +<dd><p>The single- and double-precision floating-point instructions. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point extension. +</p> +</dd> +<dt>‘<samp>+cdecp0, +cdecp1, ... , +cdecp7</samp>’</dt> +<dd><p>Enable the Custom Datapath Extension (CDE) on selected coprocessors according +to the numbers given in the options in the range 0 to 7. +</p></dd> +</dl> + +</dd> +<dt>‘<samp>armv8-r</samp>’</dt> +<dd><dl compact="compact"> +<dt>‘<samp>+crc</samp>’</dt> +<dd><p>The Cyclic Redundancy Check (CRC) instructions. +</p></dd> +<dt>‘<samp>+fp.sp</samp>’</dt> +<dd><p>The single-precision FPv5 floating-point instructions. +</p></dd> +<dt>‘<samp>+simd</samp>’</dt> +<dd><p>The ARMv8-A Advanced SIMD and floating-point instructions. +</p></dd> +<dt>‘<samp>+crypto</samp>’</dt> +<dd><p>The cryptographic instructions. +</p></dd> +<dt>‘<samp>+nocrypto</samp>’</dt> +<dd><p>Disable the cryptographic instructions. +</p></dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disable the floating-point, Advanced SIMD and cryptographic instructions. +</p></dd> +</dl> + +</dd> +</dl> + +<p><samp>-march=native</samp> causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. +</p> +<a name="index-mtune-4"></a> +</dd> +<dt><code>-mtune=<var>name</var></code></dt> +<dd><p>This option specifies the name of the target ARM processor for +which GCC should tune the performance of the code. +For some ARM implementations better performance can be obtained by using +this option. +Permissible names are: ‘<samp>arm7tdmi</samp>’, ‘<samp>arm7tdmi-s</samp>’, ‘<samp>arm710t</samp>’, +‘<samp>arm720t</samp>’, ‘<samp>arm740t</samp>’, ‘<samp>strongarm</samp>’, ‘<samp>strongarm110</samp>’, +‘<samp>strongarm1100</samp>’, ‘<samp>strongarm1110</samp>’, ‘<samp>arm8</samp>’, ‘<samp>arm810</samp>’, +‘<samp>arm9</samp>’, ‘<samp>arm9e</samp>’, ‘<samp>arm920</samp>’, ‘<samp>arm920t</samp>’, ‘<samp>arm922t</samp>’, +‘<samp>arm946e-s</samp>’, ‘<samp>arm966e-s</samp>’, ‘<samp>arm968e-s</samp>’, ‘<samp>arm926ej-s</samp>’, +‘<samp>arm940t</samp>’, ‘<samp>arm9tdmi</samp>’, ‘<samp>arm10tdmi</samp>’, ‘<samp>arm1020t</samp>’, +‘<samp>arm1026ej-s</samp>’, ‘<samp>arm10e</samp>’, ‘<samp>arm1020e</samp>’, ‘<samp>arm1022e</samp>’, +‘<samp>arm1136j-s</samp>’, ‘<samp>arm1136jf-s</samp>’, ‘<samp>mpcore</samp>’, ‘<samp>mpcorenovfp</samp>’, +‘<samp>arm1156t2-s</samp>’, ‘<samp>arm1156t2f-s</samp>’, ‘<samp>arm1176jz-s</samp>’, ‘<samp>arm1176jzf-s</samp>’, +‘<samp>generic-armv7-a</samp>’, ‘<samp>cortex-a5</samp>’, ‘<samp>cortex-a7</samp>’, ‘<samp>cortex-a8</samp>’, +‘<samp>cortex-a9</samp>’, ‘<samp>cortex-a12</samp>’, ‘<samp>cortex-a15</samp>’, ‘<samp>cortex-a17</samp>’, +‘<samp>cortex-a32</samp>’, ‘<samp>cortex-a35</samp>’, ‘<samp>cortex-a53</samp>’, ‘<samp>cortex-a55</samp>’, +‘<samp>cortex-a57</samp>’, ‘<samp>cortex-a72</samp>’, ‘<samp>cortex-a73</samp>’, ‘<samp>cortex-a75</samp>’, +‘<samp>cortex-a76</samp>’, ‘<samp>cortex-a76ae</samp>’, ‘<samp>cortex-a77</samp>’, +‘<samp>cortex-a78</samp>’, ‘<samp>cortex-a78ae</samp>’, ‘<samp>cortex-a78c</samp>’, ‘<samp>cortex-a710</samp>’, +‘<samp>ares</samp>’, ‘<samp>cortex-r4</samp>’, ‘<samp>cortex-r4f</samp>’, ‘<samp>cortex-r5</samp>’, +‘<samp>cortex-r7</samp>’, ‘<samp>cortex-r8</samp>’, ‘<samp>cortex-r52</samp>’, ‘<samp>cortex-r52plus</samp>’, +‘<samp>cortex-m0</samp>’, ‘<samp>cortex-m0plus</samp>’, ‘<samp>cortex-m1</samp>’, ‘<samp>cortex-m3</samp>’, +‘<samp>cortex-m4</samp>’, ‘<samp>cortex-m7</samp>’, ‘<samp>cortex-m23</samp>’, ‘<samp>cortex-m33</samp>’, +‘<samp>cortex-m35p</samp>’, ‘<samp>cortex-m55</samp>’, ‘<samp>cortex-m85</samp>’, ‘<samp>cortex-x1</samp>’, +‘<samp>cortex-x1c</samp>’, ‘<samp>cortex-m1.small-multiply</samp>’, ‘<samp>cortex-m0.small-multiply</samp>’, +‘<samp>cortex-m0plus.small-multiply</samp>’, ‘<samp>exynos-m1</samp>’, ‘<samp>marvell-pj4</samp>’, +‘<samp>neoverse-n1</samp>’, ‘<samp>neoverse-n2</samp>’, ‘<samp>neoverse-v1</samp>’, ‘<samp>xscale</samp>’, +‘<samp>iwmmxt</samp>’, ‘<samp>iwmmxt2</samp>’, ‘<samp>ep9312</samp>’, ‘<samp>fa526</samp>’, ‘<samp>fa626</samp>’, +‘<samp>fa606te</samp>’, ‘<samp>fa626te</samp>’, ‘<samp>fmp626</samp>’, ‘<samp>fa726te</samp>’, ‘<samp>star-mc1</samp>’, +‘<samp>xgene1</samp>’. +</p> +<p>Additionally, this option can specify that GCC should tune the performance +of the code for a big.LITTLE system. Permissible names are: +‘<samp>cortex-a15.cortex-a7</samp>’, ‘<samp>cortex-a17.cortex-a7</samp>’, +‘<samp>cortex-a57.cortex-a53</samp>’, ‘<samp>cortex-a72.cortex-a53</samp>’, +‘<samp>cortex-a72.cortex-a35</samp>’, ‘<samp>cortex-a73.cortex-a53</samp>’, +‘<samp>cortex-a75.cortex-a55</samp>’, ‘<samp>cortex-a76.cortex-a55</samp>’. +</p> +<p><samp>-mtune=generic-<var>arch</var></samp> specifies that GCC should tune the +performance for a blend of processors within architecture <var>arch</var>. +The aim is to generate code that run well on the current most popular +processors, balancing between optimizations that benefit some CPUs in the +range, and avoiding performance pitfalls of other CPUs. The effects of +this option may change in future GCC versions as CPU models come and go. +</p> +<p><samp>-mtune</samp> permits the same extension options as <samp>-mcpu</samp>, but +the extension options do not affect the tuning of the generated code. +</p> +<p><samp>-mtune=native</samp> causes the compiler to auto-detect the CPU +of the build computer. At present, this feature is only supported on +GNU/Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. +</p> +<a name="index-mcpu-2"></a> +</dd> +<dt><code>-mcpu=<var>name</var><span class="roman">[</span>+extension…<span class="roman">]</span></code></dt> +<dd><p>This specifies the name of the target ARM processor. GCC uses this name +to derive the name of the target ARM architecture (as if specified +by <samp>-march</samp>) and the ARM processor type for which to tune for +performance (as if specified by <samp>-mtune</samp>). Where this option +is used in conjunction with <samp>-march</samp> or <samp>-mtune</samp>, +those options take precedence over the appropriate part of this option. +</p> +<p>Many of the supported CPUs implement optional architectural +extensions. Where this is so the architectural extensions are +normally enabled by default. If implementations that lack the +extension exist, then the extension syntax can be used to disable +those extensions that have been omitted. For floating-point and +Advanced SIMD (Neon) instructions, the settings of the options +<samp>-mfloat-abi</samp> and <samp>-mfpu</samp> must also be considered: +floating-point and Advanced SIMD instructions will only be used if +<samp>-mfloat-abi</samp> is not set to ‘<samp>soft</samp>’; and any setting of +<samp>-mfpu</samp> other than ‘<samp>auto</samp>’ will override the available +floating-point and SIMD extension instructions. +</p> +<p>For example, ‘<samp>cortex-a9</samp>’ can be found in three major +configurations: integer only, with just a floating-point unit or with +floating-point and Advanced SIMD. The default is to enable all the +instructions, but the extensions ‘<samp>+nosimd</samp>’ and ‘<samp>+nofp</samp>’ can +be used to disable just the SIMD or both the SIMD and floating-point +instructions respectively. +</p> +<p>Permissible names for this option are the same as those for +<samp>-mtune</samp>. +</p> +<p>The following extension options are common to the listed CPUs: +</p> +<dl compact="compact"> +<dt>‘<samp>+nodsp</samp>’</dt> +<dd><p>Disable the DSP instructions on ‘<samp>cortex-m33</samp>’, ‘<samp>cortex-m35p</samp>’, +‘<samp>cortex-m55</samp>’ and ‘<samp>cortex-m85</samp>’. Also disable the M-Profile Vector +Extension (MVE) integer and single precision floating-point instructions on +‘<samp>cortex-m55</samp>’ and ‘<samp>cortex-m85</samp>’. +</p> +</dd> +<dt>‘<samp>+nopacbti</samp>’</dt> +<dd><p>Disable the Pointer Authentication and Branch Target Identification Extension +on ‘<samp>cortex-m85</samp>’. +</p> +</dd> +<dt>‘<samp>+nomve</samp>’</dt> +<dd><p>Disable the M-Profile Vector Extension (MVE) integer and single precision +floating-point instructions on ‘<samp>cortex-m55</samp>’ and ‘<samp>cortex-m85</samp>’. +</p> +</dd> +<dt>‘<samp>+nomve.fp</samp>’</dt> +<dd><p>Disable the M-Profile Vector Extension (MVE) single precision floating-point +instructions on ‘<samp>cortex-m55</samp>’ and ‘<samp>cortex-m85</samp>’. +</p> +</dd> +<dt>‘<samp>+cdecp0, +cdecp1, ... , +cdecp7</samp>’</dt> +<dd><p>Enable the Custom Datapath Extension (CDE) on selected coprocessors according +to the numbers given in the options in the range 0 to 7 on ‘<samp>cortex-m55</samp>’. +</p> +</dd> +<dt>‘<samp>+nofp</samp>’</dt> +<dd><p>Disables the floating-point instructions on ‘<samp>arm9e</samp>’, +‘<samp>arm946e-s</samp>’, ‘<samp>arm966e-s</samp>’, ‘<samp>arm968e-s</samp>’, ‘<samp>arm10e</samp>’, +‘<samp>arm1020e</samp>’, ‘<samp>arm1022e</samp>’, ‘<samp>arm926ej-s</samp>’, +‘<samp>arm1026ej-s</samp>’, ‘<samp>cortex-r5</samp>’, ‘<samp>cortex-r7</samp>’, ‘<samp>cortex-r8</samp>’, +‘<samp>cortex-m4</samp>’, ‘<samp>cortex-m7</samp>’, ‘<samp>cortex-m33</samp>’, ‘<samp>cortex-m35p</samp>’ +‘<samp>cortex-m4</samp>’, ‘<samp>cortex-m7</samp>’, ‘<samp>cortex-m33</samp>’, ‘<samp>cortex-m35p</samp>’, +‘<samp>cortex-m55</samp>’ and ‘<samp>cortex-m85</samp>’. +Disables the floating-point and SIMD instructions on +‘<samp>generic-armv7-a</samp>’, ‘<samp>cortex-a5</samp>’, ‘<samp>cortex-a7</samp>’, +‘<samp>cortex-a8</samp>’, ‘<samp>cortex-a9</samp>’, ‘<samp>cortex-a12</samp>’, +‘<samp>cortex-a15</samp>’, ‘<samp>cortex-a17</samp>’, ‘<samp>cortex-a15.cortex-a7</samp>’, +‘<samp>cortex-a17.cortex-a7</samp>’, ‘<samp>cortex-a32</samp>’, ‘<samp>cortex-a35</samp>’, +‘<samp>cortex-a53</samp>’ and ‘<samp>cortex-a55</samp>’. +</p> +</dd> +<dt>‘<samp>+nofp.dp</samp>’</dt> +<dd><p>Disables the double-precision component of the floating-point instructions +on ‘<samp>cortex-r5</samp>’, ‘<samp>cortex-r7</samp>’, ‘<samp>cortex-r8</samp>’, ‘<samp>cortex-r52</samp>’, +‘<samp>cortex-r52plus</samp>’ and ‘<samp>cortex-m7</samp>’. +</p> +</dd> +<dt>‘<samp>+nosimd</samp>’</dt> +<dd><p>Disables the SIMD (but not floating-point) instructions on +‘<samp>generic-armv7-a</samp>’, ‘<samp>cortex-a5</samp>’, ‘<samp>cortex-a7</samp>’ +and ‘<samp>cortex-a9</samp>’. +</p> +</dd> +<dt>‘<samp>+crypto</samp>’</dt> +<dd><p>Enables the cryptographic instructions on ‘<samp>cortex-a32</samp>’, +‘<samp>cortex-a35</samp>’, ‘<samp>cortex-a53</samp>’, ‘<samp>cortex-a55</samp>’, ‘<samp>cortex-a57</samp>’, +‘<samp>cortex-a72</samp>’, ‘<samp>cortex-a73</samp>’, ‘<samp>cortex-a75</samp>’, ‘<samp>exynos-m1</samp>’, +‘<samp>xgene1</samp>’, ‘<samp>cortex-a57.cortex-a53</samp>’, ‘<samp>cortex-a72.cortex-a53</samp>’, +‘<samp>cortex-a73.cortex-a35</samp>’, ‘<samp>cortex-a73.cortex-a53</samp>’ and +‘<samp>cortex-a75.cortex-a55</samp>’. +</p></dd> +</dl> + +<p>Additionally the ‘<samp>generic-armv7-a</samp>’ pseudo target defaults to +VFPv3 with 16 double-precision registers. It supports the following +extension options: ‘<samp>mp</samp>’, ‘<samp>sec</samp>’, ‘<samp>vfpv3-d16</samp>’, +‘<samp>vfpv3</samp>’, ‘<samp>vfpv3-d16-fp16</samp>’, ‘<samp>vfpv3-fp16</samp>’, +‘<samp>vfpv4-d16</samp>’, ‘<samp>vfpv4</samp>’, ‘<samp>neon</samp>’, ‘<samp>neon-vfpv3</samp>’, +‘<samp>neon-fp16</samp>’, ‘<samp>neon-vfpv4</samp>’. The meanings are the same as for +the extensions to <samp>-march=armv7-a</samp>. +</p> +<p><samp>-mcpu=generic-<var>arch</var></samp> is also permissible, and is +equivalent to <samp>-march=<var>arch</var> -mtune=generic-<var>arch</var></samp>. +See <samp>-mtune</samp> for more information. +</p> +<p><samp>-mcpu=native</samp> causes the compiler to auto-detect the CPU +of the build computer. At present, this feature is only supported on +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. +</p> +<a name="index-mfpu-1"></a> +</dd> +<dt><code>-mfpu=<var>name</var></code></dt> +<dd><p>This specifies what floating-point hardware (or hardware emulation) is +available on the target. Permissible names are: ‘<samp>auto</samp>’, ‘<samp>vfpv2</samp>’, +‘<samp>vfpv3</samp>’, +‘<samp>vfpv3-fp16</samp>’, ‘<samp>vfpv3-d16</samp>’, ‘<samp>vfpv3-d16-fp16</samp>’, ‘<samp>vfpv3xd</samp>’, +‘<samp>vfpv3xd-fp16</samp>’, ‘<samp>neon-vfpv3</samp>’, ‘<samp>neon-fp16</samp>’, ‘<samp>vfpv4</samp>’, +‘<samp>vfpv4-d16</samp>’, ‘<samp>fpv4-sp-d16</samp>’, ‘<samp>neon-vfpv4</samp>’, +‘<samp>fpv5-d16</samp>’, ‘<samp>fpv5-sp-d16</samp>’, +‘<samp>fp-armv8</samp>’, ‘<samp>neon-fp-armv8</samp>’ and ‘<samp>crypto-neon-fp-armv8</samp>’. +Note that ‘<samp>neon</samp>’ is an alias for ‘<samp>neon-vfpv3</samp>’ and ‘<samp>vfp</samp>’ +is an alias for ‘<samp>vfpv2</samp>’. +</p> +<p>The setting ‘<samp>auto</samp>’ is the default and is special. It causes the +compiler to select the floating-point and Advanced SIMD instructions +based on the settings of <samp>-mcpu</samp> and <samp>-march</samp>. +</p> +<p>If the selected floating-point hardware includes the NEON extension +(e.g. <samp>-mfpu=neon</samp>), note that floating-point +operations are not generated by GCC’s auto-vectorization pass unless +<samp>-funsafe-math-optimizations</samp> is also specified. This is +because NEON hardware does not fully implement the IEEE 754 standard for +floating-point arithmetic (in particular denormal values are treated as +zero), so the use of NEON instructions may lead to a loss of precision. +</p> +<p>You can also set the fpu name at function level by using the <code>target("fpu=")</code> function attributes (see <a href="ARM-Function-Attributes.html#ARM-Function-Attributes">ARM Function Attributes</a>) or pragmas (see <a href="Function-Specific-Option-Pragmas.html#Function-Specific-Option-Pragmas">Function Specific Option Pragmas</a>). +</p> +<a name="index-mfp16_002dformat"></a> +</dd> +<dt><code>-mfp16-format=<var>name</var></code></dt> +<dd><p>Specify the format of the <code>__fp16</code> half-precision floating-point type. +Permissible names are ‘<samp>none</samp>’, ‘<samp>ieee</samp>’, and ‘<samp>alternative</samp>’; +the default is ‘<samp>none</samp>’, in which case the <code>__fp16</code> type is not +defined. See <a href="Half_002dPrecision.html#Half_002dPrecision">Half-Precision</a>, for more information. +</p> +<a name="index-mstructure_002dsize_002dboundary"></a> +</dd> +<dt><code>-mstructure-size-boundary=<var>n</var></code></dt> +<dd><p>The sizes of all structures and unions are rounded up to a multiple +of the number of bits set by this option. Permissible values are 8, 32 +and 64. The default value varies for different toolchains. For the COFF +targeted toolchain the default value is 8. A value of 64 is only allowed +if the underlying ABI supports it. +</p> +<p>Specifying a larger number can produce faster, more efficient code, but +can also increase the size of the program. Different values are potentially +incompatible. Code compiled with one value cannot necessarily expect to +work with code or libraries compiled with another value, if they exchange +information using structures or unions. +</p> +<p>This option is deprecated. +</p> +<a name="index-mabort_002don_002dnoreturn"></a> +</dd> +<dt><code>-mabort-on-noreturn</code></dt> +<dd><p>Generate a call to the function <code>abort</code> at the end of a +<code>noreturn</code> function. It is executed if the function tries to +return. +</p> +<a name="index-mlong_002dcalls-2"></a> +<a name="index-mno_002dlong_002dcalls"></a> +</dd> +<dt><code>-mlong-calls</code></dt> +<dt><code>-mno-long-calls</code></dt> +<dd><p>Tells the compiler to perform function calls by first loading the +address of the function into a register and then performing a subroutine +call on this register. This switch is needed if the target function +lies outside of the 64-megabyte addressing range of the offset-based +version of subroutine call instruction. +</p> +<p>Even if this switch is enabled, not all function calls are turned +into long calls. The heuristic is that static functions, functions +that have the <code>short_call</code> attribute, functions that are inside +the scope of a <code>#pragma no_long_calls</code> directive, and functions whose +definitions have already been compiled within the current compilation +unit are not turned into long calls. The exceptions to this rule are +that weak function definitions, functions with the <code>long_call</code> +attribute or the <code>section</code> attribute, and functions that are within +the scope of a <code>#pragma long_calls</code> directive are always +turned into long calls. +</p> +<p>This feature is not enabled by default. Specifying +<samp>-mno-long-calls</samp> restores the default behavior, as does +placing the function calls within the scope of a <code>#pragma +long_calls_off</code> directive. Note these switches have no effect on how +the compiler generates code to handle function calls via function +pointers. +</p> +<a name="index-msingle_002dpic_002dbase"></a> +</dd> +<dt><code>-msingle-pic-base</code></dt> +<dd><p>Treat the register used for PIC addressing as read-only, rather than +loading it in the prologue for each function. The runtime system is +responsible for initializing this register with an appropriate value +before execution begins. +</p> +<a name="index-mpic_002dregister"></a> +</dd> +<dt><code>-mpic-register=<var>reg</var></code></dt> +<dd><p>Specify the register to be used for PIC addressing. +For standard PIC base case, the default is any suitable register +determined by compiler. For single PIC base case, the default is +‘<samp>R9</samp>’ if target is EABI based or stack-checking is enabled, +otherwise the default is ‘<samp>R10</samp>’. +</p> +<a name="index-mpic_002ddata_002dis_002dtext_002drelative"></a> +</dd> +<dt><code>-mpic-data-is-text-relative</code></dt> +<dd><p>Assume that the displacement between the text and data segments is fixed +at static link time. This permits using PC-relative addressing +operations to access data known to be in the data segment. For +non-VxWorks RTP targets, this option is enabled by default. When +disabled on such targets, it will enable <samp>-msingle-pic-base</samp> by +default. +</p> +<a name="index-mpoke_002dfunction_002dname"></a> +</dd> +<dt><code>-mpoke-function-name</code></dt> +<dd><p>Write the name of each function into the text section, directly +preceding the function prologue. The generated code is similar to this: +</p> +<div class="smallexample"> +<pre class="smallexample"> t0 + .ascii "arm_poke_function_name", 0 + .align + t1 + .word 0xff000000 + (t1 - t0) + arm_poke_function_name + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 +</pre></div> + +<p>When performing a stack backtrace, code can inspect the value of +<code>pc</code> stored at <code>fp + 0</code>. If the trace function then looks at +location <code>pc - 12</code> and the top 8 bits are set, then we know that +there is a function name embedded immediately preceding this location +and has length <code>((pc[-3]) & 0xff000000)</code>. +</p> +<a name="index-marm"></a> +<a name="index-mthumb"></a> +</dd> +<dt><code>-mthumb</code></dt> +<dt><code>-marm</code></dt> +<dd> +<p>Select between generating code that executes in ARM and Thumb +states. The default for most configurations is to generate code +that executes in ARM state, but the default can be changed by +configuring GCC with the <samp>--with-mode=</samp><var>state</var> +configure option. +</p> +<p>You can also override the ARM and Thumb mode for each function +by using the <code>target("thumb")</code> and <code>target("arm")</code> function attributes +(see <a href="ARM-Function-Attributes.html#ARM-Function-Attributes">ARM Function Attributes</a>) or pragmas (see <a href="Function-Specific-Option-Pragmas.html#Function-Specific-Option-Pragmas">Function Specific Option Pragmas</a>). +</p> +<a name="index-mflip_002dthumb"></a> +</dd> +<dt><code>-mflip-thumb</code></dt> +<dd><p>Switch ARM/Thumb modes on alternating functions. +This option is provided for regression testing of mixed Thumb/ARM code +generation, and is not intended for ordinary use in compiling code. +</p> +<a name="index-mtpcs_002dframe"></a> +</dd> +<dt><code>-mtpcs-frame</code></dt> +<dd><p>Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all non-leaf functions. (A leaf function is one that does +not call any other functions.) The default is <samp>-mno-tpcs-frame</samp>. +</p> +<a name="index-mtpcs_002dleaf_002dframe"></a> +</dd> +<dt><code>-mtpcs-leaf-frame</code></dt> +<dd><p>Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all leaf functions. (A leaf function is one that does +not call any other functions.) The default is <samp>-mno-apcs-leaf-frame</samp>. +</p> +<a name="index-mcallee_002dsuper_002dinterworking"></a> +</dd> +<dt><code>-mcallee-super-interworking</code></dt> +<dd><p>Gives all externally visible functions in the file being compiled an ARM +instruction set header which switches to Thumb mode before executing the +rest of the function. This allows these functions to be called from +non-interworking code. This option is not valid in AAPCS configurations +because interworking is enabled by default. +</p> +<a name="index-mcaller_002dsuper_002dinterworking"></a> +</dd> +<dt><code>-mcaller-super-interworking</code></dt> +<dd><p>Allows calls via function pointers (including virtual functions) to +execute correctly regardless of whether the target code has been +compiled for interworking or not. There is a small overhead in the cost +of executing a function pointer if this option is enabled. This option +is not valid in AAPCS configurations because interworking is enabled +by default. +</p> +<a name="index-mtp"></a> +</dd> +<dt><code>-mtp=<var>name</var></code></dt> +<dd><p>Specify the access model for the thread local storage pointer. The valid +models are ‘<samp>soft</samp>’, which generates calls to <code>__aeabi_read_tp</code>, +‘<samp>cp15</samp>’, which fetches the thread pointer from <code>cp15</code> directly +(supported in the arm6k architecture), and ‘<samp>auto</samp>’, which uses the +best available method for the selected processor. The default setting is +‘<samp>auto</samp>’. +</p> +<a name="index-mtls_002ddialect"></a> +</dd> +<dt><code>-mtls-dialect=<var>dialect</var></code></dt> +<dd><p>Specify the dialect to use for accessing thread local storage. Two +<var>dialect</var>s are supported—‘<samp>gnu</samp>’ and ‘<samp>gnu2</samp>’. The +‘<samp>gnu</samp>’ dialect selects the original GNU scheme for supporting +local and global dynamic TLS models. The ‘<samp>gnu2</samp>’ dialect +selects the GNU descriptor scheme, which provides better performance +for shared libraries. The GNU descriptor scheme is compatible with +the original scheme, but does require new assembler, linker and +library support. Initial and local exec TLS models are unaffected by +this option and always use the original scheme. +</p> +<a name="index-mword_002drelocations"></a> +</dd> +<dt><code>-mword-relocations</code></dt> +<dd><p>Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). +This is enabled by default on targets (uClinux, SymbianOS) where the runtime +loader imposes this restriction, and when <samp>-fpic</samp> or <samp>-fPIC</samp> +is specified. This option conflicts with <samp>-mslow-flash-data</samp>. +</p> +<a name="index-mfix_002dcortex_002dm3_002dldrd"></a> +</dd> +<dt><code>-mfix-cortex-m3-ldrd</code></dt> +<dd><p>Some Cortex-M3 cores can cause data corruption when <code>ldrd</code> instructions +with overlapping destination and base registers are used. This option avoids +generating these instructions. This option is enabled by default when +<samp>-mcpu=cortex-m3</samp> is specified. +</p> +</dd> +<dt><code>-mfix-cortex-a57-aes-1742098</code></dt> +<dt><code>-mno-fix-cortex-a57-aes-1742098</code></dt> +<dt><code>-mfix-cortex-a72-aes-1655431</code></dt> +<dt><code>-mno-fix-cortex-a72-aes-1655431</code></dt> +<dd><p>Enable (disable) mitigation for an erratum on Cortex-A57 and +Cortex-A72 that affects the AES cryptographic instructions. This +option is enabled by default when either <samp>-mcpu=cortex-a57</samp> or +<samp>-mcpu=cortex-a72</samp> is specified. +</p> +<a name="index-munaligned_002daccess"></a> +<a name="index-mno_002dunaligned_002daccess"></a> +</dd> +<dt><code>-munaligned-access</code></dt> +<dt><code>-mno-unaligned-access</code></dt> +<dd><p>Enables (or disables) reading and writing of 16- and 32- bit values +from addresses that are not 16- or 32- bit aligned. By default +unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for +ARMv8-M Baseline architectures, and enabled for all other +architectures. If unaligned access is not enabled then words in packed +data structures are accessed a byte at a time. +</p> +<p>The ARM attribute <code>Tag_CPU_unaligned_access</code> is set in the +generated object file to either true or false, depending upon the +setting of this option. If unaligned access is enabled then the +preprocessor symbol <code>__ARM_FEATURE_UNALIGNED</code> is also +defined. +</p> +<a name="index-mneon_002dfor_002d64bits"></a> +</dd> +<dt><code>-mneon-for-64bits</code></dt> +<dd><p>This option is deprecated and has no effect. +</p> +<a name="index-mslow_002dflash_002ddata"></a> +</dd> +<dt><code>-mslow-flash-data</code></dt> +<dd><p>Assume loading data from flash is slower than fetching instruction. +Therefore literal load is minimized for better performance. +This option is only supported when compiling for ARMv7 M-profile and +off by default. It conflicts with <samp>-mword-relocations</samp>. +</p> +<a name="index-masm_002dsyntax_002dunified"></a> +</dd> +<dt><code>-masm-syntax-unified</code></dt> +<dd><p>Assume inline assembler is using unified asm syntax. The default is +currently off which implies divided syntax. This option has no impact +on Thumb2. However, this may change in future releases of GCC. +Divided syntax should be considered deprecated. +</p> +<a name="index-mrestrict_002dit"></a> +</dd> +<dt><code>-mrestrict-it</code></dt> +<dd><p>Restricts generation of IT blocks to conform to the rules of ARMv8-A. +IT blocks can only contain a single 16-bit instruction from a select +set of instructions. This option is on by default for ARMv8-A Thumb mode. +</p> +<a name="index-mprint_002dtune_002dinfo"></a> +</dd> +<dt><code>-mprint-tune-info</code></dt> +<dd><p>Print CPU tuning information as comment in assembler file. This is +an option used only for regression testing of the compiler and not +intended for ordinary use in compiling code. This option is disabled +by default. +</p> +<a name="index-mverbose_002dcost_002ddump-1"></a> +</dd> +<dt><code>-mverbose-cost-dump</code></dt> +<dd><p>Enable verbose cost model dumping in the debug dump files. This option is +provided for use in debugging the compiler. +</p> +<a name="index-mpure_002dcode"></a> +</dd> +<dt><code>-mpure-code</code></dt> +<dd><p>Do not allow constant data to be placed in code sections. +Additionally, when compiling for ELF object format give all text sections the +ELF processor-specific section attribute <code>SHF_ARM_PURECODE</code>. This option +is only available when generating non-pic code for M-profile targets. +</p> +<a name="index-mcmse"></a> +</dd> +<dt><code>-mcmse</code></dt> +<dd><p>Generate secure code as per the "ARMv8-M Security Extensions: Requirements on +Development Tools Engineering Specification", which can be found on +<a href="https://developer.arm.com/documentation/ecm0359818/latest/">https://developer.arm.com/documentation/ecm0359818/latest/</a>. +</p> +<a name="index-mfix_002dcmse_002dcve_002d2021_002d35465"></a> +</dd> +<dt><code>-mfix-cmse-cve-2021-35465</code></dt> +<dd><p>Mitigate against a potential security issue with the <code>VLLDM</code> instruction +in some M-profile devices when using CMSE (CVE-2021-365465). This option is +enabled by default when the option <samp>-mcpu=</samp> is used with +<code>cortex-m33</code>, <code>cortex-m35p</code>, <code>cortex-m55</code>, <code>cortex-m85</code> +or <code>star-mc1</code>. The option <samp>-mno-fix-cmse-cve-2021-35465</samp> can be used +to disable the mitigation. +</p> +<a name="index-mstack_002dprotector_002dguard-1"></a> +<a name="index-mstack_002dprotector_002dguard_002doffset-1"></a> +</dd> +<dt><code>-mstack-protector-guard=<var>guard</var></code></dt> +<dt><code>-mstack-protector-guard-offset=<var>offset</var></code></dt> +<dd><p>Generate stack protection code using canary at <var>guard</var>. Supported +locations are ‘<samp>global</samp>’ for a global canary or ‘<samp>tls</samp>’ for a +canary accessible via the TLS register. The option +<samp>-mstack-protector-guard-offset=</samp> is for use with +<samp>-fstack-protector-guard=tls</samp> and not for use in user-land code. +</p> +<a name="index-mfdpic"></a> +<a name="index-mno_002dfdpic"></a> +</dd> +<dt><code>-mfdpic</code></dt> +<dt><code>-mno-fdpic</code></dt> +<dd><p>Select the FDPIC ABI, which uses 64-bit function descriptors to +represent pointers to functions. When the compiler is configured for +<code>arm-*-uclinuxfdpiceabi</code> targets, this option is on by default +and implies <samp>-fPIE</samp> if none of the PIC/PIE-related options is +provided. On other targets, it only enables the FDPIC-specific code +generation features, and the user should explicitly provide the +PIC/PIE-related options as needed. +</p> +<p>Note that static linking is not supported because it would still +involve the dynamic linker when the program self-relocates. If such +behavior is acceptable, use -static and -Wl,-dynamic-linker options. +</p> +<p>The opposite <samp>-mno-fdpic</samp> option is useful (and required) to +build the Linux kernel using the same (<code>arm-*-uclinuxfdpiceabi</code>) +toolchain as the one used to build the userland programs. +</p> +<a name="index-mbranch_002dprotection-1"></a> +</dd> +<dt><code>-mbranch-protection=<var>none</var>|<var>standard</var>|<var>pac-ret</var>[+<var>leaf</var>][+<var>bti</var>]|<var>bti</var>[+<var>pac-ret</var>[+<var>leaf</var>]]</code></dt> +<dd><p>Enable branch protection features (armv8.1-m.main only). +‘<samp>none</samp>’ generate code without branch protection or return address +signing. +‘<samp>standard[+<var>leaf</var>]</samp>’ generate code with all branch protection +features enabled at their standard level. +‘<samp>pac-ret[+<var>leaf</var>]</samp>’ generate code with return address signing +set to its standard level, which is to sign all functions that save +the return address to memory. +‘<samp>leaf</samp>’ When return address signing is enabled, also sign leaf +functions even if they do not write the return address to memory. ++‘<samp>bti</samp>’ Add landing-pad instructions at the permitted targets of +indirect branch instructions. +</p> +<p>If the ‘<samp>+pacbti</samp>’ architecture extension is not enabled, then all +branch protection and return address signing operations are +constrained to use only the instructions defined in the +architectural-NOP space. The generated code will remain +backwards-compatible with earlier versions of the architecture, but +the additional security can be enabled at run time on processors that +support the ‘<samp>PACBTI</samp>’ extension. +</p> +<p>Branch target enforcement using BTI can only be enabled at runtime if +all code in the application has been compiled with at least +‘<samp>-mbranch-protection=bti</samp>’. +</p> +<p>Any setting other than ‘<samp>none</samp>’ is supported only on armv8-m.main +or later. +</p> +<p>The default is to generate code without branch protection or return +address signing. +</p> +</dd> +</dl> + +<hr> +<div class="header"> +<p> +Next: <a href="AVR-Options.html#AVR-Options" accesskey="n" rel="next">AVR Options</a>, Previous: <a href="ARC-Options.html#ARC-Options" accesskey="p" rel="previous">ARC Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p> +</div> + + + +</body> +</html> |