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diff --git a/share/doc/gcc/AArch64-Options.html b/share/doc/gcc/AArch64-Options.html new file mode 100644 index 0000000..84b7532 --- /dev/null +++ b/share/doc/gcc/AArch64-Options.html @@ -0,0 +1,658 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html> +<!-- This file documents the use of the GNU compilers. + +Copyright (C) 1988-2023 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being "Funding Free Software", the Front-Cover +Texts being (a) (see below), and with the Back-Cover Texts being (b) +(see below). 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Permissible values +are ‘<samp>ilp32</samp>’ for SysV-like data model where int, long int and pointers +are 32 bits, and ‘<samp>lp64</samp>’ for SysV-like data model where int is 32 bits, +but long int and pointers are 64 bits. +</p> +<p>The default depends on the specific target configuration. Note that +the LP64 and ILP32 ABIs are not link-compatible; you must compile your +entire program with the same ABI, and link with a compatible set of libraries. +</p> +<a name="index-mbig_002dendian"></a> +</dd> +<dt><code>-mbig-endian</code></dt> +<dd><p>Generate big-endian code. This is the default when GCC is configured for an +‘<samp>aarch64_be-*-*</samp>’ target. +</p> +<a name="index-mgeneral_002dregs_002donly"></a> +</dd> +<dt><code>-mgeneral-regs-only</code></dt> +<dd><p>Generate code which uses only the general-purpose registers. This will prevent +the compiler from using floating-point and Advanced SIMD registers but will not +impose any restrictions on the assembler. +</p> +<a name="index-mlittle_002dendian"></a> +</dd> +<dt><code>-mlittle-endian</code></dt> +<dd><p>Generate little-endian code. This is the default when GCC is configured for an +‘<samp>aarch64-*-*</samp>’ but not an ‘<samp>aarch64_be-*-*</samp>’ target. +</p> +<a name="index-mcmodel_003dtiny"></a> +</dd> +<dt><code>-mcmodel=tiny</code></dt> +<dd><p>Generate code for the tiny code model. The program and its statically defined +symbols must be within 1MB of each other. Programs can be statically or +dynamically linked. +</p> +<a name="index-mcmodel_003dsmall"></a> +</dd> +<dt><code>-mcmodel=small</code></dt> +<dd><p>Generate code for the small code model. The program and its statically defined +symbols must be within 4GB of each other. Programs can be statically or +dynamically linked. This is the default code model. +</p> +<a name="index-mcmodel_003dlarge"></a> +</dd> +<dt><code>-mcmodel=large</code></dt> +<dd><p>Generate code for the large code model. This makes no assumptions about +addresses and sizes of sections. Programs can be statically linked only. The +<samp>-mcmodel=large</samp> option is incompatible with <samp>-mabi=ilp32</samp>, +<samp>-fpic</samp> and <samp>-fPIC</samp>. +</p> +<a name="index-mstrict_002dalign"></a> +<a name="index-mno_002dstrict_002dalign"></a> +</dd> +<dt><code>-mstrict-align</code></dt> +<dt><code>-mno-strict-align</code></dt> +<dd><p>Avoid or allow generating memory accesses that may not be aligned on a natural +object boundary as described in the architecture specification. +</p> +<a name="index-momit_002dleaf_002dframe_002dpointer"></a> +<a name="index-mno_002domit_002dleaf_002dframe_002dpointer"></a> +</dd> +<dt><code>-momit-leaf-frame-pointer</code></dt> +<dt><code>-mno-omit-leaf-frame-pointer</code></dt> +<dd><p>Omit or keep the frame pointer in leaf functions. The former behavior is the +default. +</p> +<a name="index-mstack_002dprotector_002dguard"></a> +<a name="index-mstack_002dprotector_002dguard_002dreg"></a> +<a name="index-mstack_002dprotector_002dguard_002doffset"></a> +</dd> +<dt><code>-mstack-protector-guard=<var>guard</var></code></dt> +<dt><code>-mstack-protector-guard-reg=<var>reg</var></code></dt> +<dt><code>-mstack-protector-guard-offset=<var>offset</var></code></dt> +<dd><p>Generate stack protection code using canary at <var>guard</var>. Supported +locations are ‘<samp>global</samp>’ for a global canary or ‘<samp>sysreg</samp>’ for a +canary in an appropriate system register. +</p> +<p>With the latter choice the options +<samp>-mstack-protector-guard-reg=<var>reg</var></samp> and +<samp>-mstack-protector-guard-offset=<var>offset</var></samp> furthermore specify +which system register to use as base register for reading the canary, +and from what offset from that base register. There is no default +register or offset as this is entirely for use within the Linux +kernel. +</p> +<a name="index-mtls_002ddialect_003ddesc"></a> +</dd> +<dt><code>-mtls-dialect=desc</code></dt> +<dd><p>Use TLS descriptors as the thread-local storage mechanism for dynamic accesses +of TLS variables. This is the default. +</p> +<a name="index-mtls_002ddialect_003dtraditional"></a> +</dd> +<dt><code>-mtls-dialect=traditional</code></dt> +<dd><p>Use traditional TLS as the thread-local storage mechanism for dynamic accesses +of TLS variables. +</p> +<a name="index-mtls_002dsize"></a> +</dd> +<dt><code>-mtls-size=<var>size</var></code></dt> +<dd><p>Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48. +This option requires binutils 2.26 or newer. +</p> +<a name="index-mfix_002dcortex_002da53_002d835769"></a> +<a name="index-mno_002dfix_002dcortex_002da53_002d835769"></a> +</dd> +<dt><code>-mfix-cortex-a53-835769</code></dt> +<dt><code>-mno-fix-cortex-a53-835769</code></dt> +<dd><p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. +This involves inserting a NOP instruction between memory instructions and +64-bit integer multiply-accumulate instructions. +</p> +<a name="index-mfix_002dcortex_002da53_002d843419"></a> +<a name="index-mno_002dfix_002dcortex_002da53_002d843419"></a> +</dd> +<dt><code>-mfix-cortex-a53-843419</code></dt> +<dt><code>-mno-fix-cortex-a53-843419</code></dt> +<dd><p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419. +This erratum workaround is made at link time and this will only pass the +corresponding flag to the linker. +</p> +<a name="index-mlow_002dprecision_002drecip_002dsqrt"></a> +<a name="index-mno_002dlow_002dprecision_002drecip_002dsqrt"></a> +</dd> +<dt><code>-mlow-precision-recip-sqrt</code></dt> +<dt><code>-mno-low-precision-recip-sqrt</code></dt> +<dd><p>Enable or disable the reciprocal square root approximation. +This option only has an effect if <samp>-ffast-math</samp> or +<samp>-funsafe-math-optimizations</samp> is used as well. Enabling this reduces +precision of reciprocal square root results to about 16 bits for +single precision and to 32 bits for double precision. +</p> +<a name="index-mlow_002dprecision_002dsqrt"></a> +<a name="index-mno_002dlow_002dprecision_002dsqrt"></a> +</dd> +<dt><code>-mlow-precision-sqrt</code></dt> +<dt><code>-mno-low-precision-sqrt</code></dt> +<dd><p>Enable or disable the square root approximation. +This option only has an effect if <samp>-ffast-math</samp> or +<samp>-funsafe-math-optimizations</samp> is used as well. Enabling this reduces +precision of square root results to about 16 bits for +single precision and to 32 bits for double precision. +If enabled, it implies <samp>-mlow-precision-recip-sqrt</samp>. +</p> +<a name="index-mlow_002dprecision_002ddiv"></a> +<a name="index-mno_002dlow_002dprecision_002ddiv"></a> +</dd> +<dt><code>-mlow-precision-div</code></dt> +<dt><code>-mno-low-precision-div</code></dt> +<dd><p>Enable or disable the division approximation. +This option only has an effect if <samp>-ffast-math</samp> or +<samp>-funsafe-math-optimizations</samp> is used as well. Enabling this reduces +precision of division results to about 16 bits for +single precision and to 32 bits for double precision. +</p> +</dd> +<dt><code>-mtrack-speculation</code></dt> +<dt><code>-mno-track-speculation</code></dt> +<dd><p>Enable or disable generation of additional code to track speculative +execution through conditional branches. The tracking state can then +be used by the compiler when expanding calls to +<code>__builtin_speculation_safe_copy</code> to permit a more efficient code +sequence to be generated. +</p> +</dd> +<dt><code>-moutline-atomics</code></dt> +<dt><code>-mno-outline-atomics</code></dt> +<dd><p>Enable or disable calls to out-of-line helpers to implement atomic operations. +These helpers will, at runtime, determine if the LSE instructions from +ARMv8.1-A can be used; if not, they will use the load/store-exclusive +instructions that are present in the base ARMv8.0 ISA. +</p> +<p>This option is only applicable when compiling for the base ARMv8.0 +instruction set. If using a later revision, e.g. <samp>-march=armv8.1-a</samp> +or <samp>-march=armv8-a+lse</samp>, the ARMv8.1-Atomics instructions will be +used directly. The same applies when using <samp>-mcpu=</samp> when the +selected cpu supports the ‘<samp>lse</samp>’ feature. +This option is on by default. +</p> +<a name="index-march"></a> +</dd> +<dt><code>-march=<var>name</var></code></dt> +<dd><p>Specify the name of the target architecture and, optionally, one or +more feature modifiers. This option has the form +<samp>-march=<var>arch</var><span class="roman">{</span>+<span class="roman">[</span>no<span class="roman">]</span><var>feature</var><span class="roman">}*</span></samp>. +</p> +<p>The table below summarizes the permissible values for <var>arch</var> +and the features that they enable by default: +</p> +<table> +<thead><tr><th width="20%"><var>arch</var> value</th><th width="20%">Architecture</th><th width="60%">Includes by default</th></tr></thead> +<tr><td width="20%">‘<samp>armv8-a</samp>’</td><td width="20%">Armv8-A</td><td width="60%">‘<samp>+fp</samp>’, ‘<samp>+simd</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv8.1-a</samp>’</td><td width="20%">Armv8.1-A</td><td width="60%">‘<samp>armv8-a</samp>’, ‘<samp>+crc</samp>’, ‘<samp>+lse</samp>’, ‘<samp>+rdma</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv8.2-a</samp>’</td><td width="20%">Armv8.2-A</td><td width="60%">‘<samp>armv8.1-a</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv8.3-a</samp>’</td><td width="20%">Armv8.3-A</td><td width="60%">‘<samp>armv8.2-a</samp>’, ‘<samp>+pauth</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv8.4-a</samp>’</td><td width="20%">Armv8.4-A</td><td width="60%">‘<samp>armv8.3-a</samp>’, ‘<samp>+flagm</samp>’, ‘<samp>+fp16fml</samp>’, ‘<samp>+dotprod</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv8.5-a</samp>’</td><td width="20%">Armv8.5-A</td><td width="60%">‘<samp>armv8.4-a</samp>’, ‘<samp>+sb</samp>’, ‘<samp>+ssbs</samp>’, ‘<samp>+predres</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv8.6-a</samp>’</td><td width="20%">Armv8.6-A</td><td width="60%">‘<samp>armv8.5-a</samp>’, ‘<samp>+bf16</samp>’, ‘<samp>+i8mm</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv8.7-a</samp>’</td><td width="20%">Armv8.7-A</td><td width="60%">‘<samp>armv8.6-a</samp>’, ‘<samp>+ls64</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv8.8-a</samp>’</td><td width="20%">Armv8.8-a</td><td width="60%">‘<samp>armv8.7-a</samp>’, ‘<samp>+mops</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv9-a</samp>’</td><td width="20%">Armv9-A</td><td width="60%">‘<samp>armv8.5-a</samp>’, ‘<samp>+sve</samp>’, ‘<samp>+sve2</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv9.1-a</samp>’</td><td width="20%">Armv9.1-A</td><td width="60%">‘<samp>armv9-a</samp>’, ‘<samp>+bf16</samp>’, ‘<samp>+i8mm</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv9.2-a</samp>’</td><td width="20%">Armv9.2-A</td><td width="60%">‘<samp>armv9.1-a</samp>’, ‘<samp>+ls64</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv9.3-a</samp>’</td><td width="20%">Armv9.3-A</td><td width="60%">‘<samp>armv9.2-a</samp>’, ‘<samp>+mops</samp>’</td></tr> +<tr><td width="20%">‘<samp>armv8-r</samp>’</td><td width="20%">Armv8-R</td><td width="60%">‘<samp>armv8-r</samp>’</td></tr> +</table> + +<p>The value ‘<samp>native</samp>’ is available on native AArch64 GNU/Linux and +causes the compiler to pick the architecture of the host system. This +option has no effect if the compiler is unable to recognize the +architecture of the host system, +</p> +<p>The permissible values for <var>feature</var> are listed in the sub-section +on <a href="#aarch64_002dfeature_002dmodifiers"><samp>-march</samp> and <samp>-mcpu</samp> +Feature Modifiers</a>. Where conflicting feature modifiers are +specified, the right-most feature is used. +</p> +<p>GCC uses <var>name</var> to determine what kind of instructions it can emit +when generating assembly code. If <samp>-march</samp> is specified +without either of <samp>-mtune</samp> or <samp>-mcpu</samp> also being +specified, the code is tuned to perform well across a range of target +processors implementing the target architecture. +</p> +<a name="index-mtune"></a> +</dd> +<dt><code>-mtune=<var>name</var></code></dt> +<dd><p>Specify the name of the target processor for which GCC should tune the +performance of the code. Permissible values for this option are: +‘<samp>generic</samp>’, ‘<samp>cortex-a35</samp>’, ‘<samp>cortex-a53</samp>’, ‘<samp>cortex-a55</samp>’, +‘<samp>cortex-a57</samp>’, ‘<samp>cortex-a72</samp>’, ‘<samp>cortex-a73</samp>’, ‘<samp>cortex-a75</samp>’, +‘<samp>cortex-a76</samp>’, ‘<samp>cortex-a76ae</samp>’, ‘<samp>cortex-a77</samp>’, +‘<samp>cortex-a65</samp>’, ‘<samp>cortex-a65ae</samp>’, ‘<samp>cortex-a34</samp>’, +‘<samp>cortex-a78</samp>’, ‘<samp>cortex-a78ae</samp>’, ‘<samp>cortex-a78c</samp>’, +‘<samp>ares</samp>’, ‘<samp>exynos-m1</samp>’, ‘<samp>emag</samp>’, ‘<samp>falkor</samp>’, +‘<samp>neoverse-512tvb</samp>’, ‘<samp>neoverse-e1</samp>’, ‘<samp>neoverse-n1</samp>’, +‘<samp>neoverse-n2</samp>’, ‘<samp>neoverse-v1</samp>’, ‘<samp>neoverse-v2</samp>’, ‘<samp>qdf24xx</samp>’, +‘<samp>saphira</samp>’, ‘<samp>phecda</samp>’, ‘<samp>xgene1</samp>’, ‘<samp>vulcan</samp>’, +‘<samp>octeontx</samp>’, ‘<samp>octeontx81</samp>’, ‘<samp>octeontx83</samp>’, +‘<samp>octeontx2</samp>’, ‘<samp>octeontx2t98</samp>’, ‘<samp>octeontx2t96</samp>’ +‘<samp>octeontx2t93</samp>’, ‘<samp>octeontx2f95</samp>’, ‘<samp>octeontx2f95n</samp>’, +‘<samp>octeontx2f95mm</samp>’, +‘<samp>a64fx</samp>’, +‘<samp>thunderx</samp>’, ‘<samp>thunderxt88</samp>’, +‘<samp>thunderxt88p1</samp>’, ‘<samp>thunderxt81</samp>’, ‘<samp>tsv110</samp>’, +‘<samp>thunderxt83</samp>’, ‘<samp>thunderx2t99</samp>’, ‘<samp>thunderx3t110</samp>’, ‘<samp>zeus</samp>’, +‘<samp>cortex-a57.cortex-a53</samp>’, ‘<samp>cortex-a72.cortex-a53</samp>’, +‘<samp>cortex-a73.cortex-a35</samp>’, ‘<samp>cortex-a73.cortex-a53</samp>’, +‘<samp>cortex-a75.cortex-a55</samp>’, ‘<samp>cortex-a76.cortex-a55</samp>’, +‘<samp>cortex-r82</samp>’, ‘<samp>cortex-x1</samp>’, ‘<samp>cortex-x1c</samp>’, ‘<samp>cortex-x2</samp>’, +‘<samp>cortex-x3</samp>’, ‘<samp>cortex-a510</samp>’, ‘<samp>cortex-a710</samp>’, ‘<samp>cortex-a715</samp>’, +‘<samp>ampere1</samp>’, ‘<samp>ampere1a</samp>’, and ‘<samp>native</samp>’. +</p> +<p>The values ‘<samp>cortex-a57.cortex-a53</samp>’, ‘<samp>cortex-a72.cortex-a53</samp>’, +‘<samp>cortex-a73.cortex-a35</samp>’, ‘<samp>cortex-a73.cortex-a53</samp>’, +‘<samp>cortex-a75.cortex-a55</samp>’, ‘<samp>cortex-a76.cortex-a55</samp>’ specify that GCC +should tune for a big.LITTLE system. +</p> +<p>The value ‘<samp>neoverse-512tvb</samp>’ specifies that GCC should tune +for Neoverse cores that (a) implement SVE and (b) have a total vector +bandwidth of 512 bits per cycle. In other words, the option tells GCC to +tune for Neoverse cores that can execute 4 128-bit Advanced SIMD arithmetic +instructions a cycle and that can execute an equivalent number of SVE +arithmetic instructions per cycle (2 for 256-bit SVE, 4 for 128-bit SVE). +This is more general than tuning for a specific core like Neoverse V1 +but is more specific than the default tuning described below. +</p> +<p>Additionally on native AArch64 GNU/Linux systems the value +‘<samp>native</samp>’ tunes performance to the host system. This option has no effect +if the compiler is unable to recognize the processor of the host system. +</p> +<p>Where none of <samp>-mtune=</samp>, <samp>-mcpu=</samp> or <samp>-march=</samp> +are specified, the code is tuned to perform well across a range +of target processors. +</p> +<p>This option cannot be suffixed by feature modifiers. +</p> +<a name="index-mcpu"></a> +</dd> +<dt><code>-mcpu=<var>name</var></code></dt> +<dd><p>Specify the name of the target processor, optionally suffixed by one +or more feature modifiers. This option has the form +<samp>-mcpu=<var>cpu</var><span class="roman">{</span>+<span class="roman">[</span>no<span class="roman">]</span><var>feature</var><span class="roman">}*</span></samp>, where +the permissible values for <var>cpu</var> are the same as those available +for <samp>-mtune</samp>. The permissible values for <var>feature</var> are +documented in the sub-section on +<a href="#aarch64_002dfeature_002dmodifiers"><samp>-march</samp> and <samp>-mcpu</samp> +Feature Modifiers</a>. Where conflicting feature modifiers are +specified, the right-most feature is used. +</p> +<p>GCC uses <var>name</var> to determine what kind of instructions it can emit when +generating assembly code (as if by <samp>-march</samp>) and to determine +the target processor for which to tune for performance (as if +by <samp>-mtune</samp>). Where this option is used in conjunction +with <samp>-march</samp> or <samp>-mtune</samp>, those options take precedence +over the appropriate part of this option. +</p> +<p><samp>-mcpu=neoverse-512tvb</samp> is special in that it does not refer +to a specific core, but instead refers to all Neoverse cores that +(a) implement SVE and (b) have a total vector bandwidth of 512 bits +a cycle. Unless overridden by <samp>-march</samp>, +<samp>-mcpu=neoverse-512tvb</samp> generates code that can run on a +Neoverse V1 core, since Neoverse V1 is the first Neoverse core with +these properties. Unless overridden by <samp>-mtune</samp>, +<samp>-mcpu=neoverse-512tvb</samp> tunes code in the same way as for +<samp>-mtune=neoverse-512tvb</samp>. +</p> +<a name="index-moverride"></a> +</dd> +<dt><code>-moverride=<var>string</var></code></dt> +<dd><p>Override tuning decisions made by the back-end in response to a +<samp>-mtune=</samp> switch. The syntax, semantics, and accepted values +for <var>string</var> in this option are not guaranteed to be consistent +across releases. +</p> +<p>This option is only intended to be useful when developing GCC. +</p> +<a name="index-mverbose_002dcost_002ddump"></a> +</dd> +<dt><code>-mverbose-cost-dump</code></dt> +<dd><p>Enable verbose cost model dumping in the debug dump files. This option is +provided for use in debugging the compiler. +</p> +<a name="index-mpc_002drelative_002dliteral_002dloads"></a> +<a name="index-mno_002dpc_002drelative_002dliteral_002dloads"></a> +</dd> +<dt><code>-mpc-relative-literal-loads</code></dt> +<dt><code>-mno-pc-relative-literal-loads</code></dt> +<dd><p>Enable or disable PC-relative literal loads. With this option literal pools are +accessed using a single instruction and emitted after each function. This +limits the maximum size of functions to 1MB. This is enabled by default for +<samp>-mcmodel=tiny</samp>. +</p> +<a name="index-msign_002dreturn_002daddress"></a> +</dd> +<dt><code>-msign-return-address=<var>scope</var></code></dt> +<dd><p>Select the function scope on which return address signing will be applied. +Permissible values are ‘<samp>none</samp>’, which disables return address signing, +‘<samp>non-leaf</samp>’, which enables pointer signing for functions which are not leaf +functions, and ‘<samp>all</samp>’, which enables pointer signing for all functions. The +default value is ‘<samp>none</samp>’. This option has been deprecated by +-mbranch-protection. +</p> +<a name="index-mbranch_002dprotection"></a> +</dd> +<dt><code>-mbranch-protection=<var>none</var>|<var>standard</var>|<var>pac-ret</var>[+<var>leaf</var>+<var>b-key</var>]|<var>bti</var></code></dt> +<dd><p>Select the branch protection features to use. +‘<samp>none</samp>’ is the default and turns off all types of branch protection. +‘<samp>standard</samp>’ turns on all types of branch protection features. If a feature +has additional tuning options, then ‘<samp>standard</samp>’ sets it to its standard +level. +‘<samp>pac-ret[+<var>leaf</var>]</samp>’ turns on return address signing to its standard +level: signing functions that save the return address to memory (non-leaf +functions will practically always do this) using the a-key. The optional +argument ‘<samp>leaf</samp>’ can be used to extend the signing to include leaf +functions. The optional argument ‘<samp>b-key</samp>’ can be used to sign the functions +with the B-key instead of the A-key. +‘<samp>bti</samp>’ turns on branch target identification mechanism. +</p> +<a name="index-mharden_002dsls"></a> +</dd> +<dt><code>-mharden-sls=<var>opts</var></code></dt> +<dd><p>Enable compiler hardening against straight line speculation (SLS). +<var>opts</var> is a comma-separated list of the following options: +</p><dl compact="compact"> +<dt>‘<samp>retbr</samp>’</dt> +<dt>‘<samp>blr</samp>’</dt> +</dl> +<p>In addition, ‘<samp>-mharden-sls=all</samp>’ enables all SLS hardening while +‘<samp>-mharden-sls=none</samp>’ disables all SLS hardening. +</p> +<a name="index-msve_002dvector_002dbits"></a> +</dd> +<dt><code>-msve-vector-bits=<var>bits</var></code></dt> +<dd><p>Specify the number of bits in an SVE vector register. This option only has +an effect when SVE is enabled. +</p> +<p>GCC supports two forms of SVE code generation: “vector-length +agnostic” output that works with any size of vector register and +“vector-length specific” output that allows GCC to make assumptions +about the vector length when it is useful for optimization reasons. +The possible values of ‘<samp>bits</samp>’ are: ‘<samp>scalable</samp>’, ‘<samp>128</samp>’, +‘<samp>256</samp>’, ‘<samp>512</samp>’, ‘<samp>1024</samp>’ and ‘<samp>2048</samp>’. +Specifying ‘<samp>scalable</samp>’ selects vector-length agnostic +output. At present ‘<samp>-msve-vector-bits=128</samp>’ also generates vector-length +agnostic output for big-endian targets. All other values generate +vector-length specific code. The behavior of these values may change +in future releases and no value except ‘<samp>scalable</samp>’ should be +relied on for producing code that is portable across different +hardware SVE vector lengths. +</p> +<p>The default is ‘<samp>-msve-vector-bits=scalable</samp>’, which produces +vector-length agnostic code. +</p></dd> +</dl> + +<a name="g_t_002dmarch-and-_002dmcpu-Feature-Modifiers"></a> +<h4 class="subsubsection">3.19.1.1 <samp>-march</samp> and <samp>-mcpu</samp> Feature Modifiers</h4> +<a name="aarch64_002dfeature_002dmodifiers"></a><a name="index-_002dmarch-feature-modifiers"></a> +<a name="index-_002dmcpu-feature-modifiers"></a> +<p>Feature modifiers used with <samp>-march</samp> and <samp>-mcpu</samp> can be any of +the following and their inverses <samp>no<var>feature</var></samp>: +</p> +<dl compact="compact"> +<dt>‘<samp>crc</samp>’</dt> +<dd><p>Enable CRC extension. This is on by default for +<samp>-march=armv8.1-a</samp>. +</p></dd> +<dt>‘<samp>crypto</samp>’</dt> +<dd><p>Enable Crypto extension. This also enables Advanced SIMD and floating-point +instructions. +</p></dd> +<dt>‘<samp>fp</samp>’</dt> +<dd><p>Enable floating-point instructions. This is on by default for all possible +values for options <samp>-march</samp> and <samp>-mcpu</samp>. +</p></dd> +<dt>‘<samp>simd</samp>’</dt> +<dd><p>Enable Advanced SIMD instructions. This also enables floating-point +instructions. This is on by default for all possible values for options +<samp>-march</samp> and <samp>-mcpu</samp>. +</p></dd> +<dt>‘<samp>sve</samp>’</dt> +<dd><p>Enable Scalable Vector Extension instructions. This also enables Advanced +SIMD and floating-point instructions. +</p></dd> +<dt>‘<samp>lse</samp>’</dt> +<dd><p>Enable Large System Extension instructions. This is on by default for +<samp>-march=armv8.1-a</samp>. +</p></dd> +<dt>‘<samp>rdma</samp>’</dt> +<dd><p>Enable Round Double Multiply Accumulate instructions. This is on by default +for <samp>-march=armv8.1-a</samp>. +</p></dd> +<dt>‘<samp>fp16</samp>’</dt> +<dd><p>Enable FP16 extension. This also enables floating-point instructions. +</p></dd> +<dt>‘<samp>fp16fml</samp>’</dt> +<dd><p>Enable FP16 fmla extension. This also enables FP16 extensions and +floating-point instructions. This option is enabled by default for <samp>-march=armv8.4-a</samp>. Use of this option with architectures prior to Armv8.2-A is not supported. +</p> +</dd> +<dt>‘<samp>rcpc</samp>’</dt> +<dd><p>Enable the RCpc extension. This enables the use of the LDAPR instructions for +load-acquire atomic semantics, and passes it on to the assembler, enabling +inline asm statements to use instructions from the RCpc extension. +</p></dd> +<dt>‘<samp>dotprod</samp>’</dt> +<dd><p>Enable the Dot Product extension. This also enables Advanced SIMD instructions. +</p></dd> +<dt>‘<samp>aes</samp>’</dt> +<dd><p>Enable the Armv8-a aes and pmull crypto extension. This also enables Advanced +SIMD instructions. +</p></dd> +<dt>‘<samp>sha2</samp>’</dt> +<dd><p>Enable the Armv8-a sha2 crypto extension. This also enables Advanced SIMD instructions. +</p></dd> +<dt>‘<samp>sha3</samp>’</dt> +<dd><p>Enable the sha512 and sha3 crypto extension. This also enables Advanced SIMD +instructions. Use of this option with architectures prior to Armv8.2-A is not supported. +</p></dd> +<dt>‘<samp>sm4</samp>’</dt> +<dd><p>Enable the sm3 and sm4 crypto extension. This also enables Advanced SIMD instructions. +Use of this option with architectures prior to Armv8.2-A is not supported. +</p></dd> +<dt>‘<samp>profile</samp>’</dt> +<dd><p>Enable the Statistical Profiling extension. This option is only to enable the +extension at the assembler level and does not affect code generation. +</p></dd> +<dt>‘<samp>rng</samp>’</dt> +<dd><p>Enable the Armv8.5-a Random Number instructions. This option is only to +enable the extension at the assembler level and does not affect code +generation. +</p></dd> +<dt>‘<samp>memtag</samp>’</dt> +<dd><p>Enable the Armv8.5-a Memory Tagging Extensions. +Use of this option with architectures prior to Armv8.5-A is not supported. +</p></dd> +<dt>‘<samp>sb</samp>’</dt> +<dd><p>Enable the Armv8-a Speculation Barrier instruction. This option is only to +enable the extension at the assembler level and does not affect code +generation. This option is enabled by default for <samp>-march=armv8.5-a</samp>. +</p></dd> +<dt>‘<samp>ssbs</samp>’</dt> +<dd><p>Enable the Armv8-a Speculative Store Bypass Safe instruction. This option +is only to enable the extension at the assembler level and does not affect code +generation. This option is enabled by default for <samp>-march=armv8.5-a</samp>. +</p></dd> +<dt>‘<samp>predres</samp>’</dt> +<dd><p>Enable the Armv8-a Execution and Data Prediction Restriction instructions. +This option is only to enable the extension at the assembler level and does +not affect code generation. This option is enabled by default for +<samp>-march=armv8.5-a</samp>. +</p></dd> +<dt>‘<samp>sve2</samp>’</dt> +<dd><p>Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE +instructions. +</p></dd> +<dt>‘<samp>sve2-bitperm</samp>’</dt> +<dd><p>Enable SVE2 bitperm instructions. This also enables SVE2 instructions. +</p></dd> +<dt>‘<samp>sve2-sm4</samp>’</dt> +<dd><p>Enable SVE2 sm4 instructions. This also enables SVE2 instructions. +</p></dd> +<dt>‘<samp>sve2-aes</samp>’</dt> +<dd><p>Enable SVE2 aes instructions. This also enables SVE2 instructions. +</p></dd> +<dt>‘<samp>sve2-sha3</samp>’</dt> +<dd><p>Enable SVE2 sha3 instructions. This also enables SVE2 instructions. +</p></dd> +<dt>‘<samp>tme</samp>’</dt> +<dd><p>Enable the Transactional Memory Extension. +</p></dd> +<dt>‘<samp>i8mm</samp>’</dt> +<dd><p>Enable 8-bit Integer Matrix Multiply instructions. This also enables +Advanced SIMD and floating-point instructions. This option is enabled by +default for <samp>-march=armv8.6-a</samp>. Use of this option with architectures +prior to Armv8.2-A is not supported. +</p></dd> +<dt>‘<samp>f32mm</samp>’</dt> +<dd><p>Enable 32-bit Floating point Matrix Multiply instructions. This also enables +SVE instructions. Use of this option with architectures prior to Armv8.2-A is +not supported. +</p></dd> +<dt>‘<samp>f64mm</samp>’</dt> +<dd><p>Enable 64-bit Floating point Matrix Multiply instructions. This also enables +SVE instructions. Use of this option with architectures prior to Armv8.2-A is +not supported. +</p></dd> +<dt>‘<samp>bf16</samp>’</dt> +<dd><p>Enable brain half-precision floating-point instructions. This also enables +Advanced SIMD and floating-point instructions. This option is enabled by +default for <samp>-march=armv8.6-a</samp>. Use of this option with architectures +prior to Armv8.2-A is not supported. +</p></dd> +<dt>‘<samp>ls64</samp>’</dt> +<dd><p>Enable the 64-byte atomic load and store instructions for accelerators. +This option is enabled by default for <samp>-march=armv8.7-a</samp>. +</p></dd> +<dt>‘<samp>mops</samp>’</dt> +<dd><p>Enable the instructions to accelerate memory operations like <code>memcpy</code>, +<code>memmove</code>, <code>memset</code>. This option is enabled by default for +<samp>-march=armv8.8-a</samp> +</p></dd> +<dt>‘<samp>flagm</samp>’</dt> +<dd><p>Enable the Flag Manipulation instructions Extension. +</p></dd> +<dt>‘<samp>pauth</samp>’</dt> +<dd><p>Enable the Pointer Authentication Extension. +</p></dd> +<dt>‘<samp>cssc</samp>’</dt> +<dd><p>Enable the Common Short Sequence Compression instructions. +</p> +</dd> +</dl> + +<p>Feature <samp>crypto</samp> implies <samp>aes</samp>, <samp>sha2</samp>, and <samp>simd</samp>, +which implies <samp>fp</samp>. +Conversely, <samp>nofp</samp> implies <samp>nosimd</samp>, which implies +<samp>nocrypto</samp>, <samp>noaes</samp> and <samp>nosha2</samp>. +</p> +<hr> +<div class="header"> +<p> +Next: <a href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" accesskey="n" rel="next">Adapteva Epiphany Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p> +</div> + + + +</body> +</html> |