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| author | alk3pInjection <webmaster@raspii.tech> | 2024-02-04 16:16:35 +0800 |
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| committer | alk3pInjection <webmaster@raspii.tech> | 2024-02-04 16:16:35 +0800 |
| commit | abdaadbcae30fe0c9a66c7516798279fdfd97750 (patch) | |
| tree | 00a54a6e25601e43876d03c1a4a12a749d4a914c /share/doc/gdb/RISC_002dV-Features.html | |
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads
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diff --git a/share/doc/gdb/RISC_002dV-Features.html b/share/doc/gdb/RISC_002dV-Features.html new file mode 100644 index 0000000..1c9850a --- /dev/null +++ b/share/doc/gdb/RISC_002dV-Features.html @@ -0,0 +1,121 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html> +<!-- Copyright (C) 1988-2023 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being "Free Software" and "Free Software Needs +Free Documentation", with the Front-Cover Texts being "A GNU Manual," +and with the Back-Cover Texts as in (a) below. + +(a) The FSF's Back-Cover Text is: "You are free to copy and modify +this GNU Manual. Buying copies from GNU Press supports the FSF in +developing GNU and promoting software freedom." --> +<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> +<head> +<title>Debugging with GDB: RISC-V Features</title> + +<meta name="description" content="Debugging with GDB: RISC-V Features"> +<meta name="keywords" content="Debugging with GDB: RISC-V Features"> +<meta name="resource-type" content="document"> +<meta name="distribution" content="global"> +<meta name="Generator" content="makeinfo"> +<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> +<link href="index.html#Top" rel="start" title="Top"> +<link href="Concept-Index.html#Concept-Index" rel="index" title="Concept Index"> +<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> +<link href="Standard-Target-Features.html#Standard-Target-Features" rel="up" title="Standard Target Features"> +<link href="RX-Features.html#RX-Features" rel="next" title="RX Features"> +<link href="PowerPC-Features.html#PowerPC-Features" rel="previous" title="PowerPC Features"> +<style type="text/css"> +<!-- +a.summary-letter {text-decoration: none} +blockquote.smallquotation {font-size: smaller} +div.display {margin-left: 3.2em} +div.example {margin-left: 3.2em} +div.indentedblock {margin-left: 3.2em} +div.lisp {margin-left: 3.2em} +div.smalldisplay {margin-left: 3.2em} +div.smallexample {margin-left: 3.2em} +div.smallindentedblock {margin-left: 3.2em; font-size: smaller} +div.smalllisp {margin-left: 3.2em} +kbd {font-style:oblique} +pre.display {font-family: inherit} +pre.format {font-family: inherit} +pre.menu-comment {font-family: serif} +pre.menu-preformatted {font-family: serif} +pre.smalldisplay {font-family: inherit; font-size: smaller} +pre.smallexample {font-size: smaller} +pre.smallformat {font-family: inherit; font-size: smaller} +pre.smalllisp {font-size: smaller} +span.nocodebreak {white-space:nowrap} +span.nolinebreak {white-space:nowrap} +span.roman {font-family:serif; font-weight:normal} +span.sansserif {font-family:sans-serif; font-weight:normal} +ul.no-bullet {list-style: none} +--> +</style> + + +</head> + +<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> +<a name="RISC_002dV-Features"></a> +<div class="header"> +<p> +Next: <a href="RX-Features.html#RX-Features" accesskey="n" rel="next">RX Features</a>, Previous: <a href="PowerPC-Features.html#PowerPC-Features" accesskey="p" rel="previous">PowerPC Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p> +</div> +<hr> +<a name="RISC_002dV-Features-1"></a> +<h4 class="subsection">G.5.13 RISC-V Features</h4> +<a name="index-target-descriptions_002c-RISC_002dV-Features"></a> + +<p>The ‘<samp>org.gnu.gdb.riscv.cpu</samp>’ feature is required for RISC-V +targets. It should contain the registers ‘<samp>x0</samp>’ through +‘<samp>x31</samp>’, and ‘<samp>pc</samp>’. Either the architectural names (‘<samp>x0</samp>’, +‘<samp>x1</samp>’, etc) can be used, or the ABI names (‘<samp>zero</samp>’, ‘<samp>ra</samp>’, +etc). +</p> +<p>The ‘<samp>org.gnu.gdb.riscv.fpu</samp>’ feature is optional. If present, it +should contain registers ‘<samp>f0</samp>’ through ‘<samp>f31</samp>’, ‘<samp>fflags</samp>’, +‘<samp>frm</samp>’, and ‘<samp>fcsr</samp>’. As with the cpu feature, either the +architectural register names, or the ABI names can be used. +</p> +<p>The ‘<samp>org.gnu.gdb.riscv.virtual</samp>’ feature is optional. If present, +it should contain registers that are not backed by real registers on +the target, but are instead virtual, where the register value is +derived from other target state. In many ways these are like +<small>GDB</small>s pseudo-registers, except implemented by the target. +Currently the only register expected in this set is the one byte +‘<samp>priv</samp>’ register that contains the target’s privilege level in the +least significant two bits. +</p> +<p>The ‘<samp>org.gnu.gdb.riscv.csr</samp>’ feature is optional. If present, it +should contain all of the target’s standard CSRs. Standard CSRs are +those defined in the RISC-V specification documents. There is some +overlap between this feature and the fpu feature; the ‘<samp>fflags</samp>’, +‘<samp>frm</samp>’, and ‘<samp>fcsr</samp>’ registers could be in either feature. The +expectation is that these registers will be in the fpu feature if the +target has floating point hardware, but can be moved into the csr +feature if the target has the floating point control registers, but no +other floating point hardware. +</p> +<p>The ‘<samp>org.gnu.gdb.riscv.vector</samp>’ feature is optional. If present, +it should contain registers ‘<samp>v0</samp>’ through ‘<samp>v31</samp>’, all of which +must be the same size. These requirements are based on the v0.10 +draft vector extension, as the vector extension is not yet final. In +the event that the register set of the vector extension changes for +the final specification, the requirements given here could change for +future releases of <small>GDB</small>. +</p> +<hr> +<div class="header"> +<p> +Next: <a href="RX-Features.html#RX-Features" accesskey="n" rel="next">RX Features</a>, Previous: <a href="PowerPC-Features.html#PowerPC-Features" accesskey="p" rel="previous">PowerPC Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p> +</div> + + + +</body> +</html> |