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authoralk3pInjection <webmaster@raspii.tech>2024-02-04 16:16:35 +0800
committeralk3pInjection <webmaster@raspii.tech>2024-02-04 16:16:35 +0800
commitabdaadbcae30fe0c9a66c7516798279fdfd97750 (patch)
tree00a54a6e25601e43876d03c1a4a12a749d4a914c /share/doc/gccint/RTL-SSA-Instructions.html
Import stripped Arm GNU Toolchain 13.2.Rel1HEADumineko
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads Change-Id: I7303388733328cd98ab9aa3c30236db67f2e9e9c
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+<title>GNU Compiler Collection (GCC) Internals: RTL SSA Instructions</title>
+
+<meta name="description" content="GNU Compiler Collection (GCC) Internals: RTL SSA Instructions">
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+<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
+<link href="RTL-SSA.html#RTL-SSA" rel="up" title="RTL SSA">
+<link href="RTL-SSA-Basic-Blocks.html#RTL-SSA-Basic-Blocks" rel="next" title="RTL SSA Basic Blocks">
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+<a name="RTL-SSA-Instructions"></a>
+<div class="header">
+<p>
+Next: <a href="RTL-SSA-Basic-Blocks.html#RTL-SSA-Basic-Blocks" accesskey="n" rel="next">RTL SSA Basic Blocks</a>, Previous: <a href="Using-RTL-SSA.html#Using-RTL-SSA" accesskey="p" rel="previous">Using RTL SSA</a>, Up: <a href="RTL-SSA.html#RTL-SSA" accesskey="u" rel="up">RTL SSA</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
+</div>
+<hr>
+<a name="RTL-SSA-Instructions-1"></a>
+<h4 class="subsection">14.21.2 RTL SSA Instructions</h4>
+
+<a name="index-RPO"></a>
+<a name="index-reverse-postorder"></a>
+<a name="index-instructions_002c-RTL-SSA"></a>
+<a name="index-rtl_005fssa_003a_003ainsn_005finfo"></a>
+<p>RTL SSA instructions are represented by an <code>rtl_ssa::insn_info</code>.
+These instructions are chained together in a single list that follows
+a reverse postorder (RPO) traversal of the function. This means that
+if any path through the function can execute an instruction <var>I1</var>
+and then later execute an instruction <var>I2</var> for the first time,
+<var>I1</var> appears before <var>I2</var> in the list<a name="DOCF4" href="#FOOT4"><sup>4</sup></a>.
+</p>
+<p>Two RTL SSA instructions can be compared to find which instruction
+occurs earlier than the other in the RPO. One way to do this is
+to use the C++ comparison operators, such as:
+</p>
+<div class="example">
+<pre class="example">*<var>insn1</var> &lt; *<var>insn2</var>
+</pre></div>
+
+<p>Another way is to use the <code>compare_with</code> function:
+</p>
+<div class="example">
+<pre class="example"><var>insn1</var>-&gt;compare_with (<var>insn2</var>)
+</pre></div>
+
+<p>This expression is greater than zero if <var>insn1</var> comes after <var>insn2</var>
+in the RPO, less than zero if <var>insn1</var> comes before <var>insn2</var> in the
+RPO, or zero if <var>insn1</var> and <var>insn2</var> are the same. This order is
+maintained even if instructions are added to the function or moved around.
+</p>
+<p>The main purpose of <code>rtl_ssa::insn_info</code> is to hold
+SSA information about an instruction. However, it also caches
+certain properties of the instruction, such as whether it is an
+inline assembly instruction, whether it has volatile accesses, and so on.
+</p>
+<div class="footnote">
+<hr>
+<h4 class="footnotes-heading">Footnotes</h4>
+
+<h3><a name="FOOT4" href="#DOCF4">(4)</a></h3>
+<p>Note that this
+order is different from the order of the underlying RTL instructions,
+which follow machine code order instead.</p>
+</div>
+
+
+
+</body>
+</html>