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authoralk3pInjection <webmaster@raspii.tech>2024-02-04 16:16:35 +0800
committeralk3pInjection <webmaster@raspii.tech>2024-02-04 16:16:35 +0800
commitabdaadbcae30fe0c9a66c7516798279fdfd97750 (patch)
tree00a54a6e25601e43876d03c1a4a12a749d4a914c /share/doc/gccint/Jump-Patterns.html
Import stripped Arm GNU Toolchain 13.2.Rel1HEADumineko
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads Change-Id: I7303388733328cd98ab9aa3c30236db67f2e9e9c
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+<title>GNU Compiler Collection (GCC) Internals: Jump Patterns</title>
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+<p>
+Next: <a href="Looping-Patterns.html#Looping-Patterns" accesskey="n" rel="next">Looping Patterns</a>, Previous: <a href="Dependent-Patterns.html#Dependent-Patterns" accesskey="p" rel="previous">Dependent Patterns</a>, Up: <a href="Machine-Desc.html#Machine-Desc" accesskey="u" rel="up">Machine Desc</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
+</div>
+<hr>
+<a name="Defining-Jump-Instruction-Patterns"></a>
+<h3 class="section">17.12 Defining Jump Instruction Patterns</h3>
+<a name="index-jump-instruction-patterns"></a>
+<a name="index-defining-jump-instruction-patterns"></a>
+
+<p>GCC does not assume anything about how the machine realizes jumps.
+The machine description should define a single pattern, usually
+a <code>define_expand</code>, which expands to all the required insns.
+</p>
+<p>Usually, this would be a comparison insn to set the condition code
+and a separate branch insn testing the condition code and branching
+or not according to its value. For many machines, however,
+separating compares and branches is limiting, which is why the
+more flexible approach with one <code>define_expand</code> is used in GCC.
+The machine description becomes clearer for architectures that
+have compare-and-branch instructions but no condition code. It also
+works better when different sets of comparison operators are supported
+by different kinds of conditional branches (e.g. integer vs.
+floating-point), or by conditional branches with respect to conditional stores.
+</p>
+<p>Two separate insns are always used on most machines that use a separate
+condition code register (see <a href="Condition-Code.html#Condition-Code">Condition Code</a>).
+</p>
+<p>Even in this case having a single entry point for conditional branches
+is advantageous, because it handles equally well the case where a single
+comparison instruction records the results of both signed and unsigned
+comparison of the given operands (with the branch insns coming in distinct
+signed and unsigned flavors) as in the x86 or SPARC, and the case where
+there are distinct signed and unsigned compare instructions and only
+one set of conditional branch instructions as in the PowerPC.
+</p>
+
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