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authoralk3pInjection <webmaster@raspii.tech>2024-02-04 16:16:35 +0800
committeralk3pInjection <webmaster@raspii.tech>2024-02-04 16:16:35 +0800
commitabdaadbcae30fe0c9a66c7516798279fdfd97750 (patch)
tree00a54a6e25601e43876d03c1a4a12a749d4a914c /share/doc/gccint/Delay-Slots.html
Import stripped Arm GNU Toolchain 13.2.Rel1HEADumineko
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads Change-Id: I7303388733328cd98ab9aa3c30236db67f2e9e9c
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+<title>GNU Compiler Collection (GCC) Internals: Delay Slots</title>
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+<a name="Delay-Slots"></a>
+<div class="header">
+<p>
+Next: <a href="Processor-pipeline-description.html#Processor-pipeline-description" accesskey="n" rel="next">Processor pipeline description</a>, Previous: <a href="Mnemonic-Attribute.html#Mnemonic-Attribute" accesskey="p" rel="previous">Mnemonic Attribute</a>, Up: <a href="Insn-Attributes.html#Insn-Attributes" accesskey="u" rel="up">Insn Attributes</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
+</div>
+<hr>
+<a name="Delay-Slot-Scheduling"></a>
+<h4 class="subsection">17.19.8 Delay Slot Scheduling</h4>
+<a name="index-delay-slots_002c-defining"></a>
+
+<p>The insn attribute mechanism can be used to specify the requirements for
+delay slots, if any, on a target machine. An instruction is said to
+require a <em>delay slot</em> if some instructions that are physically
+after the instruction are executed as if they were located before it.
+Classic examples are branch and call instructions, which often execute
+the following instruction before the branch or call is performed.
+</p>
+<p>On some machines, conditional branch instructions can optionally
+<em>annul</em> instructions in the delay slot. This means that the
+instruction will not be executed for certain branch outcomes. Both
+instructions that annul if the branch is true and instructions that
+annul if the branch is false are supported.
+</p>
+<p>Delay slot scheduling differs from instruction scheduling in that
+determining whether an instruction needs a delay slot is dependent only
+on the type of instruction being generated, not on data flow between the
+instructions. See the next section for a discussion of data-dependent
+instruction scheduling.
+</p>
+<a name="index-define_005fdelay"></a>
+<p>The requirement of an insn needing one or more delay slots is indicated
+via the <code>define_delay</code> expression. It has the following form:
+</p>
+<div class="smallexample">
+<pre class="smallexample">(define_delay <var>test</var>
+ [<var>delay-1</var> <var>annul-true-1</var> <var>annul-false-1</var>
+ <var>delay-2</var> <var>annul-true-2</var> <var>annul-false-2</var>
+ &hellip;])
+</pre></div>
+
+<p><var>test</var> is an attribute test that indicates whether this
+<code>define_delay</code> applies to a particular insn. If so, the number of
+required delay slots is determined by the length of the vector specified
+as the second argument. An insn placed in delay slot <var>n</var> must
+satisfy attribute test <var>delay-n</var>. <var>annul-true-n</var> is an
+attribute test that specifies which insns may be annulled if the branch
+is true. Similarly, <var>annul-false-n</var> specifies which insns in the
+delay slot may be annulled if the branch is false. If annulling is not
+supported for that delay slot, <code>(nil)</code> should be coded.
+</p>
+<p>For example, in the common case where branch and call insns require
+a single delay slot, which may contain any insn other than a branch or
+call, the following would be placed in the <samp>md</samp> file:
+</p>
+<div class="smallexample">
+<pre class="smallexample">(define_delay (eq_attr &quot;type&quot; &quot;branch,call&quot;)
+ [(eq_attr &quot;type&quot; &quot;!branch,call&quot;) (nil) (nil)])
+</pre></div>
+
+<p>Multiple <code>define_delay</code> expressions may be specified. In this
+case, each such expression specifies different delay slot requirements
+and there must be no insn for which tests in two <code>define_delay</code>
+expressions are both true.
+</p>
+<p>For example, if we have a machine that requires one delay slot for branches
+but two for calls, no delay slot can contain a branch or call insn,
+and any valid insn in the delay slot for the branch can be annulled if the
+branch is true, we might represent this as follows:
+</p>
+<div class="smallexample">
+<pre class="smallexample">(define_delay (eq_attr &quot;type&quot; &quot;branch&quot;)
+ [(eq_attr &quot;type&quot; &quot;!branch,call&quot;)
+ (eq_attr &quot;type&quot; &quot;!branch,call&quot;)
+ (nil)])
+
+(define_delay (eq_attr &quot;type&quot; &quot;call&quot;)
+ [(eq_attr &quot;type&quot; &quot;!branch,call&quot;) (nil) (nil)
+ (eq_attr &quot;type&quot; &quot;!branch,call&quot;) (nil) (nil)])
+</pre></div>
+
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