Import stripped Arm GNU Toolchain 13.2.Rel1HEAD umineko

https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads Change-Id: I7303388733328cd98ab9aa3c30236db67f2e9e9c
author: alk3pInjection <webmaster@raspii.tech> 2024-02-04 16:16:35 +0800
committer: alk3pInjection <webmaster@raspii.tech> 2024-02-04 16:16:35 +0800
commit: abdaadbcae30fe0c9a66c7516798279fdfd97750 (patch)
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+<a name="x86-transactional-memory-intrinsics"></a>
+<div class="header">
+<p>
+Next: <a href="x86-control_002dflow-protection-intrinsics.html#x86-control_002dflow-protection-intrinsics" accesskey="n" rel="next">x86 control-flow protection intrinsics</a>, Previous: <a href="x86-Built_002din-Functions.html#x86-Built_002din-Functions" accesskey="p" rel="previous">x86 Built-in Functions</a>, Up: <a href="Target-Builtins.html#Target-Builtins" accesskey="u" rel="up">Target Builtins</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p>
+</div>
+<hr>
+<a name="x86-Transactional-Memory-Intrinsics"></a>
+<h4 class="subsection">6.60.36 x86 Transactional Memory Intrinsics</h4>
+
+<p>These hardware transactional memory intrinsics for x86 allow you to use
+memory transactions with RTM (Restricted Transactional Memory).
+This support is enabled with the <samp>-mrtm</samp> option.
+For using HLE (Hardware Lock Elision) see 
+<a href="x86-specific-memory-model-extensions-for-transactional-memory.html#x86-specific-memory-model-extensions-for-transactional-memory">x86 specific memory model extensions for transactional memory</a> instead.
+</p>
+<p>A memory transaction commits all changes to memory in an atomic way,
+as visible to other threads. If the transaction fails it is rolled back
+and all side effects discarded.
+</p>
+<p>Generally there is no guarantee that a memory transaction ever succeeds
+and suitable fallback code always needs to be supplied.
+</p>
+<dl>
+<dt><a name="index-_005fxbegin"></a>RTM Function: <em>unsigned</em> <strong>_xbegin</strong> <em>()</em></dt>
+<dd><p>Start a RTM (Restricted Transactional Memory) transaction. 
+Returns <code>_XBEGIN_STARTED</code> when the transaction
+started successfully (note this is not 0, so the constant has to be 
+explicitly tested).  
+</p>
+<p>If the transaction aborts, all side effects
+are undone and an abort code encoded as a bit mask is returned.
+The following macros are defined:
+</p>
+<dl>
+<dt><a name="index-_005fXABORT_005fEXPLICIT"></a>Macro: <strong>_XABORT_EXPLICIT</strong></dt>
+<dd><p>Transaction was explicitly aborted with <code>_xabort</code>.  The parameter passed
+to <code>_xabort</code> is available with <code>_XABORT_CODE(status)</code>.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-_005fXABORT_005fRETRY"></a>Macro: <strong>_XABORT_RETRY</strong></dt>
+<dd><p>Transaction retry is possible.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-_005fXABORT_005fCONFLICT"></a>Macro: <strong>_XABORT_CONFLICT</strong></dt>
+<dd><p>Transaction abort due to a memory conflict with another thread.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-_005fXABORT_005fCAPACITY"></a>Macro: <strong>_XABORT_CAPACITY</strong></dt>
+<dd><p>Transaction abort due to the transaction using too much memory.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-_005fXABORT_005fDEBUG"></a>Macro: <strong>_XABORT_DEBUG</strong></dt>
+<dd><p>Transaction abort due to a debug trap.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-_005fXABORT_005fNESTED"></a>Macro: <strong>_XABORT_NESTED</strong></dt>
+<dd><p>Transaction abort in an inner nested transaction.
+</p></dd></dl>
+
+<p>There is no guarantee
+any transaction ever succeeds, so there always needs to be a valid
+fallback path.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-_005fxend"></a>RTM Function: <em>void</em> <strong>_xend</strong> <em>()</em></dt>
+<dd><p>Commit the current transaction. When no transaction is active this faults.
+All memory side effects of the transaction become visible
+to other threads in an atomic manner.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-_005fxtest"></a>RTM Function: <em>int</em> <strong>_xtest</strong> <em>()</em></dt>
+<dd><p>Return a nonzero value if a transaction is currently active, otherwise 0.
+</p></dd></dl>
+
+<dl>
+<dt><a name="index-_005fxabort"></a>RTM Function: <em>void</em> <strong>_xabort</strong> <em>(status)</em></dt>
+<dd><p>Abort the current transaction. When no transaction is active this is a no-op.
+The <var>status</var> is an 8-bit constant; its value is encoded in the return 
+value from <code>_xbegin</code>.
+</p></dd></dl>
+
+<p>Here is an example showing handling for <code>_XABORT_RETRY</code>
+and a fallback path for other failures:
+</p>
+<div class="smallexample">
+<pre class="smallexample">#include &lt;immintrin.h&gt;
+
+int n_tries, max_tries;
+unsigned status = _XABORT_EXPLICIT;
+...
+
+for (n_tries = 0; n_tries &lt; max_tries; n_tries++) 
+  {
+    status = _xbegin ();
+    if (status == _XBEGIN_STARTED || !(status &amp; _XABORT_RETRY))
+      break;
+  }
+if (status == _XBEGIN_STARTED) 
+  {
+    ... transaction code...
+    _xend ();
+  } 
+else 
+  {
+    ... non-transactional fallback path...
+  }
+</pre></div>
+
+<p>Note that, in most cases, the transactional and non-transactional code
+must synchronize together to ensure consistency.
+</p>
+<hr>
+<div class="header">
+<p>
+Next: <a href="x86-control_002dflow-protection-intrinsics.html#x86-control_002dflow-protection-intrinsics" accesskey="n" rel="next">x86 control-flow protection intrinsics</a>, Previous: <a href="x86-Built_002din-Functions.html#x86-Built_002din-Functions" accesskey="p" rel="previous">x86 Built-in Functions</a>, Up: <a href="Target-Builtins.html#Target-Builtins" accesskey="u" rel="up">Target Builtins</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p>
+</div>
+
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author	alk3pInjection <webmaster@raspii.tech>	2024-02-04 16:16:35 +0800
committer	alk3pInjection <webmaster@raspii.tech>	2024-02-04 16:16:35 +0800
commit	abdaadbcae30fe0c9a66c7516798279fdfd97750 (patch)
tree	00a54a6e25601e43876d03c1a4a12a749d4a914c /share/doc/gcc/x86-transactional-memory-intrinsics.html