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| author | alk3pInjection <webmaster@raspii.tech> | 2024-02-04 16:16:35 +0800 |
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| committer | alk3pInjection <webmaster@raspii.tech> | 2024-02-04 16:16:35 +0800 |
| commit | abdaadbcae30fe0c9a66c7516798279fdfd97750 (patch) | |
| tree | 00a54a6e25601e43876d03c1a4a12a749d4a914c /share/doc/gcc/LoongArch-Options.html | |
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads
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diff --git a/share/doc/gcc/LoongArch-Options.html b/share/doc/gcc/LoongArch-Options.html new file mode 100644 index 0000000..f165aee --- /dev/null +++ b/share/doc/gcc/LoongArch-Options.html @@ -0,0 +1,306 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html> +<!-- This file documents the use of the GNU compilers. + +Copyright (C) 1988-2023 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being "Funding Free Software", the Front-Cover +Texts being (a) (see below), and with the Back-Cover Texts being (b) +(see below). A copy of the license is included in the section entitled +"GNU Free Documentation License". + +(a) The FSF's Front-Cover Text is: + +A GNU Manual + +(b) The FSF's Back-Cover Text is: + +You have freedom to copy and modify this GNU Manual, like GNU + software. Copies published by the Free Software Foundation raise + funds for GNU development. --> +<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> +<head> +<title>Using the GNU Compiler Collection (GCC): LoongArch Options</title> + +<meta name="description" content="Using the GNU Compiler Collection (GCC): LoongArch Options"> +<meta name="keywords" content="Using the GNU Compiler Collection (GCC): LoongArch Options"> +<meta name="resource-type" content="document"> +<meta name="distribution" content="global"> +<meta name="Generator" content="makeinfo"> +<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> +<link href="index.html#Top" rel="start" title="Top"> +<link href="Indices.html#Indices" rel="index" title="Indices"> +<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> +<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options"> +<link href="M32C-Options.html#M32C-Options" rel="next" title="M32C Options"> +<link href="LM32-Options.html#LM32-Options" rel="previous" title="LM32 Options"> +<style type="text/css"> +<!-- +a.summary-letter {text-decoration: none} +blockquote.smallquotation {font-size: smaller} +div.display {margin-left: 3.2em} +div.example {margin-left: 3.2em} +div.indentedblock {margin-left: 3.2em} +div.lisp {margin-left: 3.2em} +div.smalldisplay {margin-left: 3.2em} +div.smallexample {margin-left: 3.2em} +div.smallindentedblock {margin-left: 3.2em; font-size: smaller} +div.smalllisp {margin-left: 3.2em} +kbd {font-style:oblique} +pre.display {font-family: inherit} +pre.format {font-family: inherit} +pre.menu-comment {font-family: serif} +pre.menu-preformatted {font-family: serif} +pre.smalldisplay {font-family: inherit; font-size: smaller} +pre.smallexample {font-size: smaller} +pre.smallformat {font-family: inherit; font-size: smaller} +pre.smalllisp {font-size: smaller} +span.nocodebreak {white-space:nowrap} +span.nolinebreak {white-space:nowrap} +span.roman {font-family:serif; font-weight:normal} +span.sansserif {font-family:sans-serif; font-weight:normal} +ul.no-bullet {list-style: none} +--> +</style> + + +</head> + +<body lang="en_US" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> +<a name="LoongArch-Options"></a> +<div class="header"> +<p> +Next: <a href="M32C-Options.html#M32C-Options" accesskey="n" rel="next">M32C Options</a>, Previous: <a href="LM32-Options.html#LM32-Options" accesskey="p" rel="previous">LM32 Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p> +</div> +<hr> +<a name="LoongArch-Options-1"></a> +<h4 class="subsection">3.19.22 LoongArch Options</h4> +<a name="index-LoongArch-Options"></a> + +<p>These command-line options are defined for LoongArch targets: +</p> +<dl compact="compact"> +<dd><a name="index-march-7"></a> +</dd> +<dt><code>-march=<var>cpu-type</var></code></dt> +<dd><p>Generate instructions for the machine type <var>cpu-type</var>. In contrast to +<samp>-mtune=<var>cpu-type</var></samp>, which merely tunes the generated code +for the specified <var>cpu-type</var>, <samp>-march=<var>cpu-type</var></samp> allows GCC +to generate code that may not run at all on processors other than the one +indicated. Specifying <samp>-march=<var>cpu-type</var></samp> implies +<samp>-mtune=<var>cpu-type</var></samp>, except where noted otherwise. +</p> +<p>The choices for <var>cpu-type</var> are: +</p> +<dl compact="compact"> +<dt>‘<samp>native</samp>’</dt> +<dd><p>This selects the CPU to generate code for at compilation time by determining +the processor type of the compiling machine. Using <samp>-march=native</samp> +enables all instruction subsets supported by the local machine (hence +the result might not run on different machines). Using <samp>-mtune=native</samp> +produces code optimized for the local machine under the constraints +of the selected instruction set. +</p></dd> +<dt>‘<samp>loongarch64</samp>’</dt> +<dd><p>A generic CPU with 64-bit extensions. +</p></dd> +<dt>‘<samp>la464</samp>’</dt> +<dd><p>LoongArch LA464 CPU with LBT, LSX, LASX, LVZ. +</p></dd> +</dl> + +<a name="index-mtune-8"></a> +</dd> +<dt><code>-mtune=<var>cpu-type</var></code></dt> +<dd><p>Optimize the output for the given processor, specified by microarchitecture +name. +</p> +<a name="index-mabi-2"></a> +</dd> +<dt><code>-mabi=<var>base-abi-type</var></code></dt> +<dd><p>Generate code for the specified calling convention. +<var>base-abi-type</var> can be one of: +</p><dl compact="compact"> +<dt>‘<samp>lp64d</samp>’</dt> +<dd><p>Uses 64-bit general purpose registers and 32/64-bit floating-point +registers for parameter passing. Data model is LP64, where ‘<samp>int</samp>’ +is 32 bits, while ‘<samp>long int</samp>’ and pointers are 64 bits. +</p></dd> +<dt>‘<samp>lp64f</samp>’</dt> +<dd><p>Uses 64-bit general purpose registers and 32-bit floating-point +registers for parameter passing. Data model is LP64, where ‘<samp>int</samp>’ +is 32 bits, while ‘<samp>long int</samp>’ and pointers are 64 bits. +</p></dd> +<dt>‘<samp>lp64s</samp>’</dt> +<dd><p>Uses 64-bit general purpose registers and no floating-point +registers for parameter passing. Data model is LP64, where ‘<samp>int</samp>’ +is 32 bits, while ‘<samp>long int</samp>’ and pointers are 64 bits. +</p></dd> +</dl> + +<a name="index-mfpu-2"></a> +</dd> +<dt><code>-mfpu=<var>fpu-type</var></code></dt> +<dd><p>Generate code for the specified FPU type, which can be one of: +</p><dl compact="compact"> +<dt>‘<samp>64</samp>’</dt> +<dd><p>Allow the use of hardware floating-point instructions for 32-bit +and 64-bit operations. +</p></dd> +<dt>‘<samp>32</samp>’</dt> +<dd><p>Allow the use of hardware floating-point instructions for 32-bit +operations. +</p></dd> +<dt>‘<samp>none</samp>’</dt> +<dt>‘<samp>0</samp>’</dt> +<dd><p>Prevent the use of hardware floating-point instructions. +</p></dd> +</dl> + +<a name="index-msoft_002dfloat-5"></a> +</dd> +<dt><code>-msoft-float</code></dt> +<dd><p>Force <samp>-mfpu=none</samp> and prevents the use of floating-point +registers for parameter passing. This option may change the target +ABI. +</p> +<a name="index-msingle_002dfloat"></a> +</dd> +<dt><code>-msingle-float</code></dt> +<dd><p>Force <samp>-mfpu=32</samp> and allow the use of 32-bit floating-point +registers for parameter passing. This option may change the target +ABI. +</p> +<a name="index-mdouble_002dfloat-1"></a> +</dd> +<dt><code>-mdouble-float</code></dt> +<dd><p>Force <samp>-mfpu=64</samp> and allow the use of 32/64-bit floating-point +registers for parameter passing. This option may change the target +ABI. +</p> +<a name="index-mbranch_002dcost-2"></a> +</dd> +<dt><code>-mbranch-cost=<var>n</var></code></dt> +<dd><p>Set the cost of branches to roughly <var>n</var> instructions. +</p> +<a name="index-mcheck_002dzero_002ddivision"></a> +</dd> +<dt><code>-mcheck-zero-division</code></dt> +<dt><code>-mno-check-zero-divison</code></dt> +<dd><p>Trap (do not trap) on integer division by zero. The default is +<samp>-mcheck-zero-division</samp> for <samp>-O0</samp> or <samp>-Og</samp>, and +<samp>-mno-check-zero-division</samp> for other optimization levels. +</p> +<a name="index-mcond_002dmove_002dint"></a> +</dd> +<dt><code>-mcond-move-int</code></dt> +<dt><code>-mno-cond-move-int</code></dt> +<dd><p>Conditional moves for integral data in general-purpose registers +are enabled (disabled). The default is <samp>-mcond-move-int</samp>. +</p> +<a name="index-mcond_002dmove_002dfloat"></a> +</dd> +<dt><code>-mcond-move-float</code></dt> +<dt><code>-mno-cond-move-float</code></dt> +<dd><p>Conditional moves for floating-point registers are enabled (disabled). +The default is <samp>-mcond-move-float</samp>. +</p> +<a name="index-mmemcpy"></a> +</dd> +<dt><code>-mmemcpy</code></dt> +<dt><code>-mno-memcpy</code></dt> +<dd><p>Force (do not force) the use of <code>memcpy</code> for non-trivial block moves. +The default is <samp>-mno-memcpy</samp>, which allows GCC to inline most +constant-sized copies. Setting optimization level to <samp>-Os</samp> also +forces the use of <code>memcpy</code>, but <samp>-mno-memcpy</samp> may override this +behavior if explicitly specified, regardless of the order these options on +the command line. +</p> +<a name="index-mstrict_002dalign-1"></a> +</dd> +<dt><code>-mstrict-align</code></dt> +<dt><code>-mno-strict-align</code></dt> +<dd><p>Avoid or allow generating memory accesses that may not be aligned on a natural +object boundary as described in the architecture specification. The default is +<samp>-mno-strict-align</samp>. +</p> +<a name="index-msmall_002ddata_002dlimit"></a> +</dd> +<dt><code>-msmall-data-limit=<var>number</var></code></dt> +<dd><p>Put global and static data smaller than <var>number</var> bytes into a special +section (on some targets). The default value is 0. +</p> +<a name="index-mmax_002dinline_002dmemcpy_002dsize"></a> +</dd> +<dt><code>-mmax-inline-memcpy-size=<var>n</var></code></dt> +<dd><p>Inline all block moves (such as calls to <code>memcpy</code> or structure copies) +less than or equal to <var>n</var> bytes. The default value of <var>n</var> is 1024. +</p> +</dd> +<dt><code>-mcmodel=<var>code-model</var></code></dt> +<dd><p>Set the code model to one of: +</p><dl compact="compact"> +<dt>‘<samp>tiny-static (Not implemented yet)</samp>’</dt> +<dt>‘<samp>tiny (Not implemented yet)</samp>’</dt> +<dt>‘<samp>normal</samp>’</dt> +<dd><p>The text segment must be within 128MB addressing space. The data segment must +be within 2GB addressing space. +</p> +</dd> +<dt>‘<samp>medium</samp>’</dt> +<dd><p>The text segment and data segment must be within 2GB addressing space. +</p> +</dd> +<dt>‘<samp>large (Not implemented yet)</samp>’</dt> +<dt>‘<samp>extreme</samp>’</dt> +<dd><p>This mode does not limit the size of the code segment and data segment. +The <samp>-mcmodel=extreme</samp> option is incompatible with <samp>-fplt</samp> and +<samp>-mno-explicit-relocs</samp>. +</p></dd> +</dl> +<p>The default code model is <code>normal</code>. +</p> +<a name="index-mexplicit_002drelocs-1"></a> +<a name="index-mno_002dexplicit_002drelocs-1"></a> +</dd> +<dt><code>-mexplicit-relocs</code></dt> +<dt><code>-mno-explicit-relocs</code></dt> +<dd><p>Use or do not use assembler relocation operators when dealing with symbolic +addresses. The alternative is to use assembler macros instead, which may +limit optimization. The default value for the option is determined during +GCC build-time by detecting corresponding assembler support: +<code>-mexplicit-relocs</code> if said support is present, +<code>-mno-explicit-relocs</code> otherwise. This option is mostly useful for +debugging, or interoperation with assemblers different from the build-time +one. +</p> +<a name="index-mdirect_002dextern_002daccess"></a> +</dd> +<dt><code>-mdirect-extern-access</code></dt> +<dt><code>-mno-direct-extern-access</code></dt> +<dd><p>Do not use or use GOT to access external symbols. The default is +<samp>-mno-direct-extern-access</samp>: GOT is used for external symbols with +default visibility, but not used for other external symbols. +</p> +<p>With <samp>-mdirect-extern-access</samp>, GOT is not used and all external +symbols are PC-relatively addressed. It is <strong>only</strong> suitable for +environments where no dynamic link is performed, like firmwares, OS +kernels, executables linked with <samp>-static</samp> or <samp>-static-pie</samp>. +<samp>-mdirect-extern-access</samp> is not compatible with <samp>-fPIC</samp> or +<samp>-fpic</samp>. +</p></dd> +</dl> + +<hr> +<div class="header"> +<p> +Next: <a href="M32C-Options.html#M32C-Options" accesskey="n" rel="next">M32C Options</a>, Previous: <a href="LM32-Options.html#LM32-Options" accesskey="p" rel="previous">LM32 Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p> +</div> + + + +</body> +</html> |