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| author | alk3pInjection <webmaster@raspii.tech> | 2024-02-04 16:16:35 +0800 |
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| committer | alk3pInjection <webmaster@raspii.tech> | 2024-02-04 16:16:35 +0800 |
| commit | abdaadbcae30fe0c9a66c7516798279fdfd97750 (patch) | |
| tree | 00a54a6e25601e43876d03c1a4a12a749d4a914c /share/doc/as.html | |
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads
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diff --git a/share/doc/as.html b/share/doc/as.html new file mode 100644 index 0000000..1041915 --- /dev/null +++ b/share/doc/as.html @@ -0,0 +1,40567 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html> +<!-- This file documents the GNU Assembler "as". + +Copyright (C) 1991-2023 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled "GNU Free Documentation License". + --> +<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> +<head> +<title>Using as</title> + +<meta name="description" content="Using as"> +<meta name="keywords" content="Using as"> +<meta name="resource-type" content="document"> +<meta name="distribution" content="global"> +<meta name="Generator" content="makeinfo"> +<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> +<link href="#Top" rel="start" title="Top"> +<link href="#AS-Index" rel="index" title="AS Index"> +<link href="#SEC_Contents" rel="contents" title="Table of Contents"> +<link href="dir.html#Top" rel="up" title="(dir)"> +<style type="text/css"> +<!-- +a.summary-letter {text-decoration: none} +blockquote.smallquotation {font-size: smaller} +div.display {margin-left: 3.2em} +div.example {margin-left: 3.2em} +div.indentedblock {margin-left: 3.2em} +div.lisp {margin-left: 3.2em} +div.smalldisplay {margin-left: 3.2em} +div.smallexample {margin-left: 3.2em} +div.smallindentedblock {margin-left: 3.2em; font-size: smaller} +div.smalllisp {margin-left: 3.2em} +kbd {font-style:oblique} +pre.display {font-family: inherit} +pre.format {font-family: inherit} +pre.menu-comment {font-family: serif} +pre.menu-preformatted {font-family: serif} +pre.smalldisplay {font-family: inherit; font-size: smaller} +pre.smallexample {font-size: smaller} +pre.smallformat {font-family: inherit; font-size: smaller} +pre.smalllisp {font-size: smaller} +span.nocodebreak {white-space:nowrap} +span.nolinebreak {white-space:nowrap} +span.roman {font-family:serif; font-weight:normal} +span.sansserif {font-family:sans-serif; font-weight:normal} +ul.no-bullet {list-style: none} +--> +</style> + + +</head> + +<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> +<h1 class="settitle" align="center">Using as</h1> + + + + + + + + + + + + + + +<a name="SEC_Contents"></a> +<h2 class="contents-heading">Table of Contents</h2> + +<div class="contents"> + +<ul class="no-bullet"> + <li><a name="toc-Overview-1" href="#Overview">1 Overview</a> + <ul class="no-bullet"> + <li><a name="toc-Structure-of-this-Manual" href="#Manual">1.1 Structure of this Manual</a></li> + <li><a name="toc-The-GNU-Assembler" href="#GNU-Assembler">1.2 The GNU Assembler</a></li> + <li><a name="toc-Object-File-Formats" href="#Object-Formats">1.3 Object File Formats</a></li> + <li><a name="toc-Command-Line-1" href="#Command-Line">1.4 Command Line</a></li> + <li><a name="toc-Input-Files-1" href="#Input-Files">1.5 Input Files</a></li> + <li><a name="toc-Output-_0028Object_0029-File" href="#Object">1.6 Output (Object) File</a></li> + <li><a name="toc-Error-and-Warning-Messages" href="#Errors">1.7 Error and Warning Messages</a></li> + </ul></li> + <li><a name="toc-Command_002dLine-Options" href="#Invoking">2 Command-Line Options</a> + <ul class="no-bullet"> + <li><a name="toc-Enable-Listings_003a-_002da_005bcdghlns_005d" href="#a">2.1 Enable Listings: <samp>-a[cdghlns]</samp></a></li> + <li><a name="toc-_002d_002dalternate" href="#alternate">2.2 <samp>--alternate</samp></a></li> + <li><a name="toc-_002dD" href="#D">2.3 <samp>-D</samp></a></li> + <li><a name="toc-Work-Faster_003a-_002df" href="#f">2.4 Work Faster: <samp>-f</samp></a></li> + <li><a name="toc-_002einclude-Search-Path_003a-_002dI-path" href="#I">2.5 <code>.include</code> Search Path: <samp>-I</samp> <var>path</var></a></li> + <li><a name="toc-Difference-Tables_003a-_002dK" href="#K">2.6 Difference Tables: <samp>-K</samp></a></li> + <li><a name="toc-Include-Local-Symbols_003a-_002dL" href="#L">2.7 Include Local Symbols: <samp>-L</samp></a></li> + <li><a name="toc-Configuring-listing-output_003a-_002d_002dlisting" href="#listing">2.8 Configuring listing output: <samp>--listing</samp></a></li> + <li><a name="toc-Assemble-in-MRI-Compatibility-Mode_003a-_002dM" href="#M">2.9 Assemble in MRI Compatibility Mode: <samp>-M</samp></a></li> + <li><a name="toc-Dependency-Tracking_003a-_002d_002dMD" href="#MD">2.10 Dependency Tracking: <samp>--MD</samp></a></li> + <li><a name="toc-Output-Section-Padding" href="#no_002dpad_002dsections">2.11 Output Section Padding</a></li> + <li><a name="toc-Name-the-Object-File_003a-_002do" href="#o">2.12 Name the Object File: <samp>-o</samp></a></li> + <li><a name="toc-Join-Data-and-Text-Sections_003a-_002dR" href="#R">2.13 Join Data and Text Sections: <samp>-R</samp></a></li> + <li><a name="toc-Display-Assembly-Statistics_003a-_002d_002dstatistics" href="#statistics">2.14 Display Assembly Statistics: <samp>--statistics</samp></a></li> + <li><a name="toc-Compatible-Output_003a-_002d_002dtraditional_002dformat" href="#traditional_002dformat">2.15 Compatible Output: <samp>--traditional-format</samp></a></li> + <li><a name="toc-Announce-Version_003a-_002dv" href="#v">2.16 Announce Version: <samp>-v</samp></a></li> + <li><a name="toc-Control-Warnings_003a-_002dW_002c-_002d_002dwarn_002c-_002d_002dno_002dwarn_002c-_002d_002dfatal_002dwarnings" href="#W">2.17 Control Warnings: <samp>-W</samp>, <samp>--warn</samp>, <samp>--no-warn</samp>, <samp>--fatal-warnings</samp></a></li> + <li><a name="toc-Generate-Object-File-in-Spite-of-Errors_003a-_002dZ" href="#Z">2.18 Generate Object File in Spite of Errors: <samp>-Z</samp></a></li> + </ul></li> + <li><a name="toc-Syntax-1" href="#Syntax">3 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Preprocessing-1" href="#Preprocessing">3.1 Preprocessing</a></li> + <li><a name="toc-Whitespace-1" href="#Whitespace">3.2 Whitespace</a></li> + <li><a name="toc-Comments-1" href="#Comments">3.3 Comments</a></li> + <li><a name="toc-Symbols-1" href="#Symbol-Intro">3.4 Symbols</a></li> + <li><a name="toc-Statements-1" href="#Statements">3.5 Statements</a></li> + <li><a name="toc-Constants-1" href="#Constants">3.6 Constants</a> + <ul class="no-bullet"> + <li><a name="toc-Character-Constants" href="#Characters">3.6.1 Character Constants</a> + <ul class="no-bullet"> + <li><a name="toc-Strings-1" href="#Strings">3.6.1.1 Strings</a></li> + <li><a name="toc-Characters-1" href="#Chars">3.6.1.2 Characters</a></li> + </ul></li> + <li><a name="toc-Number-Constants" href="#Numbers">3.6.2 Number Constants</a> + <ul class="no-bullet"> + <li><a name="toc-Integers-1" href="#Integers">3.6.2.1 Integers</a></li> + <li><a name="toc-Bignums-1" href="#Bignums">3.6.2.2 Bignums</a></li> + <li><a name="toc-Flonums-1" href="#Flonums">3.6.2.3 Flonums</a></li> + </ul></li> + </ul></li> + </ul></li> + <li><a name="toc-Sections-and-Relocation" href="#Sections">4 Sections and Relocation</a> + <ul class="no-bullet"> + <li><a name="toc-Background" href="#Secs-Background">4.1 Background</a></li> + <li><a name="toc-Linker-Sections" href="#Ld-Sections">4.2 Linker Sections</a></li> + <li><a name="toc-Assembler-Internal-Sections" href="#As-Sections">4.3 Assembler Internal Sections</a></li> + <li><a name="toc-Sub_002dSections-1" href="#Sub_002dSections">4.4 Sub-Sections</a></li> + <li><a name="toc-bss-Section" href="#bss">4.5 bss Section</a></li> + </ul></li> + <li><a name="toc-Symbols-2" href="#Symbols">5 Symbols</a> + <ul class="no-bullet"> + <li><a name="toc-Labels-1" href="#Labels">5.1 Labels</a></li> + <li><a name="toc-Giving-Symbols-Other-Values" href="#Setting-Symbols">5.2 Giving Symbols Other Values</a></li> + <li><a name="toc-Symbol-Names-1" href="#Symbol-Names">5.3 Symbol Names</a></li> + <li><a name="toc-The-Special-Dot-Symbol" href="#Dot">5.4 The Special Dot Symbol</a></li> + <li><a name="toc-Symbol-Attributes-1" href="#Symbol-Attributes">5.5 Symbol Attributes</a> + <ul class="no-bullet"> + <li><a name="toc-Value" href="#Symbol-Value">5.5.1 Value</a></li> + <li><a name="toc-Type-1" href="#Symbol-Type">5.5.2 Type</a></li> + <li><a name="toc-Symbol-Attributes_003a-a_002eout" href="#a_002eout-Symbols">5.5.3 Symbol Attributes: <code>a.out</code></a> + <ul class="no-bullet"> + <li><a name="toc-Descriptor" href="#Symbol-Desc">5.5.3.1 Descriptor</a></li> + <li><a name="toc-Other" href="#Symbol-Other">5.5.3.2 Other</a></li> + </ul></li> + <li><a name="toc-Symbol-Attributes-for-COFF" href="#COFF-Symbols">5.5.4 Symbol Attributes for COFF</a> + <ul class="no-bullet"> + <li><a name="toc-Primary-Attributes" href="#Primary-Attributes">5.5.4.1 Primary Attributes</a></li> + <li><a name="toc-Auxiliary-Attributes" href="#Auxiliary-Attributes">5.5.4.2 Auxiliary Attributes</a></li> + </ul></li> + <li><a name="toc-Symbol-Attributes-for-SOM" href="#SOM-Symbols">5.5.5 Symbol Attributes for SOM</a></li> + </ul></li> + </ul></li> + <li><a name="toc-Expressions-1" href="#Expressions">6 Expressions</a> + <ul class="no-bullet"> + <li><a name="toc-Empty-Expressions" href="#Empty-Exprs">6.1 Empty Expressions</a></li> + <li><a name="toc-Integer-Expressions" href="#Integer-Exprs">6.2 Integer Expressions</a> + <ul class="no-bullet"> + <li><a name="toc-Arguments-1" href="#Arguments">6.2.1 Arguments</a></li> + <li><a name="toc-Operators-1" href="#Operators">6.2.2 Operators</a></li> + <li><a name="toc-Prefix-Operator" href="#Prefix-Ops">6.2.3 Prefix Operator</a></li> + <li><a name="toc-Infix-Operators" href="#Infix-Ops">6.2.4 Infix Operators</a></li> + </ul></li> + </ul></li> + <li><a name="toc-Assembler-Directives" href="#Pseudo-Ops">7 Assembler Directives</a> + <ul class="no-bullet"> + <li><a name="toc-_002eabort" href="#Abort">7.1 <code>.abort</code></a></li> + <li><a name="toc-_002eABORT-_0028COFF_0029" href="#ABORT-_0028COFF_0029">7.2 <code>.ABORT</code> (COFF)</a></li> + <li><a name="toc-_002ealign-_005babs_002dexpr_005b_002c-abs_002dexpr_005b_002c-abs_002dexpr_005d_005d_005d" href="#Align">7.3 <code>.align [<var>abs-expr</var>[, <var>abs-expr</var>[, <var>abs-expr</var>]]]</code></a></li> + <li><a name="toc-_002ealtmacro" href="#Altmacro">7.4 <code>.altmacro</code></a></li> + <li><a name="toc-_002eascii-_0022string_0022_2026" href="#Ascii">7.5 <code>.ascii "<var>string</var>"</code>…</a></li> + <li><a name="toc-_002easciz-_0022string_0022_2026" href="#Asciz">7.6 <code>.asciz "<var>string</var>"</code>…</a></li> + <li><a name="toc-_002eattach_005fto_005fgroup-name" href="#Attach_005fto_005fgroup">7.7 <code>.attach_to_group <var>name</var></code></a></li> + <li><a name="toc-_002ebalign_005bwl_005d-_005babs_002dexpr_005b_002c-abs_002dexpr_005b_002c-abs_002dexpr_005d_005d_005d" href="#Balign">7.8 <code>.balign[wl] [<var>abs-expr</var>[, <var>abs-expr</var>[, <var>abs-expr</var>]]]</code></a></li> + <li><a name="toc-_002ebss-subsection" href="#Bss">7.9 <code>.bss <var>subsection</var></code></a></li> + <li><a name="toc-Bundle-directives-1" href="#Bundle-directives">7.10 Bundle directives</a> + <ul class="no-bullet"> + <li><a name="toc-_002ebundle_005falign_005fmode-abs_002dexpr" href="#g_t_002ebundle_005falign_005fmode-abs_002dexpr">7.10.1 <code>.bundle_align_mode <var>abs-expr</var></code></a></li> + <li><a name="toc-_002ebundle_005flock-and-_002ebundle_005funlock" href="#g_t_002ebundle_005flock-and-_002ebundle_005funlock">7.10.2 <code>.bundle_lock</code> and <code>.bundle_unlock</code></a></li> + </ul></li> + <li><a name="toc-_002ebyte-expressions" href="#Byte">7.11 <code>.byte <var>expressions</var></code></a></li> + <li><a name="toc-CFI-directives-1" href="#CFI-directives">7.12 CFI directives</a> + <ul class="no-bullet"> + <li><a name="toc-_002ecfi_005fsections-section_005flist" href="#g_t_002ecfi_005fsections-section_005flist">7.12.1 <code>.cfi_sections <var>section_list</var></code></a></li> + <li><a name="toc-_002ecfi_005fstartproc-_005bsimple_005d" href="#g_t_002ecfi_005fstartproc-_005bsimple_005d">7.12.2 <code>.cfi_startproc [simple]</code></a></li> + <li><a name="toc-_002ecfi_005fendproc" href="#g_t_002ecfi_005fendproc">7.12.3 <code>.cfi_endproc</code></a></li> + <li><a name="toc-_002ecfi_005fpersonality-encoding-_005b_002c-exp_005d" href="#g_t_002ecfi_005fpersonality-encoding-_005b_002c-exp_005d">7.12.4 <code>.cfi_personality <var>encoding</var> [, <var>exp</var>]</code></a></li> + <li><a name="toc-_002ecfi_005fpersonality_005fid-id" href="#g_t_002ecfi_005fpersonality_005fid-id">7.12.5 <code>.cfi_personality_id <var>id</var></code></a></li> + <li><a name="toc-_002ecfi_005ffde_005fdata-_005bopcode1-_005b_002c-_2026_005d_005d" href="#g_t_002ecfi_005ffde_005fdata-_005bopcode1-_005b_002c-_2026_005d_005d">7.12.6 <code>.cfi_fde_data [<var>opcode1</var> [, …]]</code></a></li> + <li><a name="toc-_002ecfi_005flsda-encoding-_005b_002c-exp_005d" href="#g_t_002ecfi_005flsda-encoding-_005b_002c-exp_005d">7.12.7 <code>.cfi_lsda <var>encoding</var> [, <var>exp</var>]</code></a></li> + <li><a name="toc-_002ecfi_005finline_005flsda-_005balign_005d" href="#g_t_002ecfi_005finline_005flsda-_005balign_005d">7.12.8 <code>.cfi_inline_lsda</code> [<var>align</var>]</a></li> + <li><a name="toc-_002ecfi_005fdef_005fcfa-register_002c-offset" href="#g_t_002ecfi_005fdef_005fcfa-register_002c-offset">7.12.9 <code>.cfi_def_cfa <var>register</var>, <var>offset</var></code></a></li> + <li><a name="toc-_002ecfi_005fdef_005fcfa_005fregister-register" href="#g_t_002ecfi_005fdef_005fcfa_005fregister-register">7.12.10 <code>.cfi_def_cfa_register <var>register</var></code></a></li> + <li><a name="toc-_002ecfi_005fdef_005fcfa_005foffset-offset" href="#g_t_002ecfi_005fdef_005fcfa_005foffset-offset">7.12.11 <code>.cfi_def_cfa_offset <var>offset</var></code></a></li> + <li><a name="toc-_002ecfi_005fadjust_005fcfa_005foffset-offset" href="#g_t_002ecfi_005fadjust_005fcfa_005foffset-offset">7.12.12 <code>.cfi_adjust_cfa_offset <var>offset</var></code></a></li> + <li><a name="toc-_002ecfi_005foffset-register_002c-offset" href="#g_t_002ecfi_005foffset-register_002c-offset">7.12.13 <code>.cfi_offset <var>register</var>, <var>offset</var></code></a></li> + <li><a name="toc-_002ecfi_005fval_005foffset-register_002c-offset" href="#g_t_002ecfi_005fval_005foffset-register_002c-offset">7.12.14 <code>.cfi_val_offset <var>register</var>, <var>offset</var></code></a></li> + <li><a name="toc-_002ecfi_005frel_005foffset-register_002c-offset" href="#g_t_002ecfi_005frel_005foffset-register_002c-offset">7.12.15 <code>.cfi_rel_offset <var>register</var>, <var>offset</var></code></a></li> + <li><a name="toc-_002ecfi_005fregister-register1_002c-register2" href="#g_t_002ecfi_005fregister-register1_002c-register2">7.12.16 <code>.cfi_register <var>register1</var>, <var>register2</var></code></a></li> + <li><a name="toc-_002ecfi_005frestore-register" href="#g_t_002ecfi_005frestore-register">7.12.17 <code>.cfi_restore <var>register</var></code></a></li> + <li><a name="toc-_002ecfi_005fundefined-register" href="#g_t_002ecfi_005fundefined-register">7.12.18 <code>.cfi_undefined <var>register</var></code></a></li> + <li><a name="toc-_002ecfi_005fsame_005fvalue-register" href="#g_t_002ecfi_005fsame_005fvalue-register">7.12.19 <code>.cfi_same_value <var>register</var></code></a></li> + <li><a name="toc-_002ecfi_005fremember_005fstate-and-_002ecfi_005frestore_005fstate" href="#g_t_002ecfi_005fremember_005fstate-and-_002ecfi_005frestore_005fstate">7.12.20 <code>.cfi_remember_state</code> and <code>.cfi_restore_state</code></a></li> + <li><a name="toc-_002ecfi_005freturn_005fcolumn-register" href="#g_t_002ecfi_005freturn_005fcolumn-register">7.12.21 <code>.cfi_return_column <var>register</var></code></a></li> + <li><a name="toc-_002ecfi_005fsignal_005fframe" href="#g_t_002ecfi_005fsignal_005fframe">7.12.22 <code>.cfi_signal_frame</code></a></li> + <li><a name="toc-_002ecfi_005fwindow_005fsave" href="#g_t_002ecfi_005fwindow_005fsave">7.12.23 <code>.cfi_window_save</code></a></li> + <li><a name="toc-_002ecfi_005fescape-expression_005b_002c-_2026_005d" href="#g_t_002ecfi_005fescape-expression_005b_002c-_2026_005d">7.12.24 <code>.cfi_escape</code> <var>expression</var>[, …]</a></li> + <li><a name="toc-_002ecfi_005fval_005fencoded_005faddr-register_002c-encoding_002c-label" href="#g_t_002ecfi_005fval_005fencoded_005faddr-register_002c-encoding_002c-label">7.12.25 <code>.cfi_val_encoded_addr <var>register</var>, <var>encoding</var>, <var>label</var></code></a></li> + </ul></li> + <li><a name="toc-_002ecomm-symbol-_002c-length-" href="#Comm">7.13 <code>.comm <var>symbol</var> , <var>length</var> </code></a></li> + <li><a name="toc-_002edata-subsection" href="#Data">7.14 <code>.data <var>subsection</var></code></a></li> + <li><a name="toc-_002edc_005bsize_005d-expressions" href="#Dc">7.15 <code>.dc[<var>size</var>] <var>expressions</var></code></a></li> + <li><a name="toc-_002edcb_005bsize_005d-number-_005b_002cfill_005d" href="#Dcb">7.16 <code>.dcb[<var>size</var>] <var>number</var> [,<var>fill</var>]</code></a></li> + <li><a name="toc-_002eds_005bsize_005d-number-_005b_002cfill_005d" href="#Ds">7.17 <code>.ds[<var>size</var>] <var>number</var> [,<var>fill</var>]</code></a></li> + <li><a name="toc-_002edef-name" href="#Def">7.18 <code>.def <var>name</var></code></a></li> + <li><a name="toc-_002edesc-symbol_002c-abs_002dexpression" href="#Desc">7.19 <code>.desc <var>symbol</var>, <var>abs-expression</var></code></a></li> + <li><a name="toc-_002edim" href="#Dim">7.20 <code>.dim</code></a></li> + <li><a name="toc-_002edouble-flonums" href="#Double">7.21 <code>.double <var>flonums</var></code></a></li> + <li><a name="toc-_002eeject" href="#Eject">7.22 <code>.eject</code></a></li> + <li><a name="toc-_002eelse" href="#Else">7.23 <code>.else</code></a></li> + <li><a name="toc-_002eelseif" href="#Elseif">7.24 <code>.elseif</code></a></li> + <li><a name="toc-_002eend" href="#End">7.25 <code>.end</code></a></li> + <li><a name="toc-_002eendef" href="#Endef">7.26 <code>.endef</code></a></li> + <li><a name="toc-_002eendfunc" href="#Endfunc">7.27 <code>.endfunc</code></a></li> + <li><a name="toc-_002eendif" href="#Endif">7.28 <code>.endif</code></a></li> + <li><a name="toc-_002eequ-symbol_002c-expression" href="#Equ">7.29 <code>.equ <var>symbol</var>, <var>expression</var></code></a></li> + <li><a name="toc-_002eequiv-symbol_002c-expression" href="#Equiv">7.30 <code>.equiv <var>symbol</var>, <var>expression</var></code></a></li> + <li><a name="toc-_002eeqv-symbol_002c-expression" href="#Eqv">7.31 <code>.eqv <var>symbol</var>, <var>expression</var></code></a></li> + <li><a name="toc-_002eerr" href="#Err">7.32 <code>.err</code></a></li> + <li><a name="toc-_002eerror-_0022string_0022" href="#Error">7.33 <code>.error "<var>string</var>"</code></a></li> + <li><a name="toc-_002eexitm" href="#Exitm">7.34 <code>.exitm</code></a></li> + <li><a name="toc-_002eextern" href="#Extern">7.35 <code>.extern</code></a></li> + <li><a name="toc-_002efail-expression" href="#Fail">7.36 <code>.fail <var>expression</var></code></a></li> + <li><a name="toc-_002efile" href="#File">7.37 <code>.file</code></a></li> + <li><a name="toc-_002efill-repeat-_002c-size-_002c-value" href="#Fill">7.38 <code>.fill <var>repeat</var> , <var>size</var> , <var>value</var></code></a></li> + <li><a name="toc-_002efloat-flonums" href="#Float">7.39 <code>.float <var>flonums</var></code></a></li> + <li><a name="toc-_002efunc-name_005b_002clabel_005d" href="#Func">7.40 <code>.func <var>name</var>[,<var>label</var>]</code></a></li> + <li><a name="toc-_002eglobal-symbol_002c-_002eglobl-symbol" href="#Global">7.41 <code>.global <var>symbol</var></code>, <code>.globl <var>symbol</var></code></a></li> + <li><a name="toc-_002egnu_005fattribute-tag_002cvalue" href="#Gnu_005fattribute">7.42 <code>.gnu_attribute <var>tag</var>,<var>value</var></code></a></li> + <li><a name="toc-_002ehidden-names" href="#Hidden">7.43 <code>.hidden <var>names</var></code></a></li> + <li><a name="toc-_002ehword-expressions" href="#hword">7.44 <code>.hword <var>expressions</var></code></a></li> + <li><a name="toc-_002eident" href="#Ident">7.45 <code>.ident</code></a></li> + <li><a name="toc-_002eif-absolute-expression" href="#If">7.46 <code>.if <var>absolute expression</var></code></a></li> + <li><a name="toc-_002eincbin-_0022file_0022_005b_002cskip_005b_002ccount_005d_005d" href="#Incbin">7.47 <code>.incbin "<var>file</var>"[,<var>skip</var>[,<var>count</var>]]</code></a></li> + <li><a name="toc-_002einclude-_0022file_0022" href="#Include">7.48 <code>.include "<var>file</var>"</code></a></li> + <li><a name="toc-_002eint-expressions" href="#Int">7.49 <code>.int <var>expressions</var></code></a></li> + <li><a name="toc-_002einternal-names" href="#Internal">7.50 <code>.internal <var>names</var></code></a></li> + <li><a name="toc-_002eirp-symbol_002cvalues_2026" href="#Irp">7.51 <code>.irp <var>symbol</var>,<var>values</var></code>…</a></li> + <li><a name="toc-_002eirpc-symbol_002cvalues_2026" href="#Irpc">7.52 <code>.irpc <var>symbol</var>,<var>values</var></code>…</a></li> + <li><a name="toc-_002elcomm-symbol-_002c-length" href="#Lcomm">7.53 <code>.lcomm <var>symbol</var> , <var>length</var></code></a></li> + <li><a name="toc-_002elflags" href="#Lflags">7.54 <code>.lflags</code></a></li> + <li><a name="toc-_002eline-line_002dnumber" href="#Line">7.55 <code>.line <var>line-number</var></code></a></li> + <li><a name="toc-_002elinkonce-_005btype_005d" href="#Linkonce">7.56 <code>.linkonce [<var>type</var>]</code></a></li> + <li><a name="toc-_002elist" href="#List">7.57 <code>.list</code></a></li> + <li><a name="toc-_002eln-line_002dnumber" href="#Ln">7.58 <code>.ln <var>line-number</var></code></a></li> + <li><a name="toc-_002eloc-fileno-lineno-_005bcolumn_005d-_005boptions_005d" href="#Loc">7.59 <code>.loc <var>fileno</var> <var>lineno</var> [<var>column</var>] [<var>options</var>]</code></a></li> + <li><a name="toc-_002eloc_005fmark_005flabels-enable" href="#Loc_005fmark_005flabels">7.60 <code>.loc_mark_labels <var>enable</var></code></a></li> + <li><a name="toc-_002elocal-names" href="#Local">7.61 <code>.local <var>names</var></code></a></li> + <li><a name="toc-_002elong-expressions" href="#Long">7.62 <code>.long <var>expressions</var></code></a></li> + <li><a name="toc-_002emacro" href="#Macro">7.63 <code>.macro</code></a></li> + <li><a name="toc-_002emri-val" href="#MRI">7.64 <code>.mri <var>val</var></code></a></li> + <li><a name="toc-_002enoaltmacro" href="#Noaltmacro">7.65 <code>.noaltmacro</code></a></li> + <li><a name="toc-_002enolist" href="#Nolist">7.66 <code>.nolist</code></a></li> + <li><a name="toc-_002enop-_005bsize_005d" href="#Nop">7.67 <code>.nop [<var>size</var>]</code></a></li> + <li><a name="toc-_002enops-size_005b_002c-control_005d" href="#Nops">7.68 <code>.nops <var>size</var>[, <var>control</var>]</code></a></li> + <li><a name="toc-_002eocta-bignums" href="#Octa">7.69 <code>.octa <var>bignums</var></code></a></li> + <li><a name="toc-_002eoffset-loc" href="#Offset">7.70 <code>.offset <var>loc</var></code></a></li> + <li><a name="toc-_002eorg-new_002dlc-_002c-fill" href="#Org">7.71 <code>.org <var>new-lc</var> , <var>fill</var></code></a></li> + <li><a name="toc-_002ep2align_005bwl_005d-_005babs_002dexpr_005b_002c-abs_002dexpr_005b_002c-abs_002dexpr_005d_005d_005d" href="#P2align">7.72 <code>.p2align[wl] [<var>abs-expr</var>[, <var>abs-expr</var>[, <var>abs-expr</var>]]]</code></a></li> + <li><a name="toc-_002epopsection" href="#PopSection">7.73 <code>.popsection</code></a></li> + <li><a name="toc-_002eprevious" href="#Previous">7.74 <code>.previous</code></a></li> + <li><a name="toc-_002eprint-string" href="#Print">7.75 <code>.print <var>string</var></code></a></li> + <li><a name="toc-_002eprotected-names" href="#Protected">7.76 <code>.protected <var>names</var></code></a></li> + <li><a name="toc-_002epsize-lines-_002c-columns" href="#Psize">7.77 <code>.psize <var>lines</var> , <var>columns</var></code></a></li> + <li><a name="toc-_002epurgem-name" href="#Purgem">7.78 <code>.purgem <var>name</var></code></a></li> + <li><a name="toc-_002epushsection-name-_005b_002c-subsection_005d-_005b_002c-_0022flags_0022_005b_002c-_0040type_005b_002carguments_005d_005d_005d" href="#PushSection">7.79 <code>.pushsection <var>name</var> [, <var>subsection</var>] [, "<var>flags</var>"[, @<var>type</var>[,<var>arguments</var>]]]</code></a></li> + <li><a name="toc-_002equad-expressions" href="#Quad">7.80 <code>.quad <var>expressions</var></code></a></li> + <li><a name="toc-_002ereloc-offset_002c-reloc_005fname_005b_002c-expression_005d" href="#Reloc">7.81 <code>.reloc <var>offset</var>, <var>reloc_name</var>[, <var>expression</var>]</code></a></li> + <li><a name="toc-_002erept-count" href="#Rept">7.82 <code>.rept <var>count</var></code></a></li> + <li><a name="toc-_002esbttl-_0022subheading_0022" href="#Sbttl">7.83 <code>.sbttl "<var>subheading</var>"</code></a></li> + <li><a name="toc-_002escl-class" href="#Scl">7.84 <code>.scl <var>class</var></code></a></li> + <li><a name="toc-_002esection-name" href="#Section">7.85 <code>.section <var>name</var></code></a></li> + <li><a name="toc-_002eset-symbol_002c-expression" href="#Set">7.86 <code>.set <var>symbol</var>, <var>expression</var></code></a></li> + <li><a name="toc-_002eshort-expressions" href="#Short">7.87 <code>.short <var>expressions</var></code></a></li> + <li><a name="toc-_002esingle-flonums" href="#Single">7.88 <code>.single <var>flonums</var></code></a></li> + <li><a name="toc-_002esize" href="#Size">7.89 <code>.size</code></a></li> + <li><a name="toc-_002eskip-size-_005b_002cfill_005d" href="#Skip">7.90 <code>.skip <var>size</var> [,<var>fill</var>]</code></a></li> + <li><a name="toc-_002esleb128-expressions" href="#Sleb128">7.91 <code>.sleb128 <var>expressions</var></code></a></li> + <li><a name="toc-_002espace-size-_005b_002cfill_005d" href="#Space">7.92 <code>.space <var>size</var> [,<var>fill</var>]</code></a></li> + <li><a name="toc-_002estabd_002c-_002estabn_002c-_002estabs" href="#Stab">7.93 <code>.stabd, .stabn, .stabs</code></a></li> + <li><a name="toc-_002estring-_0022str_0022_002c-_002estring8-_0022str_0022_002c-_002estring16" href="#String">7.94 <code>.string</code> "<var>str</var>", <code>.string8</code> "<var>str</var>", <code>.string16</code></a></li> + <li><a name="toc-_002estruct-expression" href="#Struct">7.95 <code>.struct <var>expression</var></code></a></li> + <li><a name="toc-_002esubsection-name" href="#SubSection">7.96 <code>.subsection <var>name</var></code></a></li> + <li><a name="toc-_002esymver" href="#Symver">7.97 <code>.symver</code></a></li> + <li><a name="toc-_002etag-structname" href="#Tag">7.98 <code>.tag <var>structname</var></code></a></li> + <li><a name="toc-_002etext-subsection" href="#Text">7.99 <code>.text <var>subsection</var></code></a></li> + <li><a name="toc-_002etitle-_0022heading_0022" href="#Title">7.100 <code>.title "<var>heading</var>"</code></a></li> + <li><a name="toc-_002etls_005fcommon-symbol_002c-length_005b_002c-alignment_005d" href="#Tls_005fcommon">7.101 <code>.tls_common <var>symbol</var>, <var>length</var>[, <var>alignment</var>]</code></a></li> + <li><a name="toc-_002etype" href="#Type">7.102 <code>.type</code></a></li> + <li><a name="toc-_002euleb128-expressions" href="#Uleb128">7.103 <code>.uleb128 <var>expressions</var></code></a></li> + <li><a name="toc-_002eval-addr" href="#Val">7.104 <code>.val <var>addr</var></code></a></li> + <li><a name="toc-_002eversion-_0022string_0022" href="#Version">7.105 <code>.version "<var>string</var>"</code></a></li> + <li><a name="toc-_002evtable_005fentry-table_002c-offset" href="#VTableEntry">7.106 <code>.vtable_entry <var>table</var>, <var>offset</var></code></a></li> + <li><a name="toc-_002evtable_005finherit-child_002c-parent" href="#VTableInherit">7.107 <code>.vtable_inherit <var>child</var>, <var>parent</var></code></a></li> + <li><a name="toc-_002ewarning-_0022string_0022" href="#Warning">7.108 <code>.warning "<var>string</var>"</code></a></li> + <li><a name="toc-_002eweak-names" href="#Weak">7.109 <code>.weak <var>names</var></code></a></li> + <li><a name="toc-_002eweakref-alias_002c-target" href="#Weakref">7.110 <code>.weakref <var>alias</var>, <var>target</var></code></a></li> + <li><a name="toc-_002eword-expressions" href="#Word">7.111 <code>.word <var>expressions</var></code></a></li> + <li><a name="toc-_002ezero-size" href="#Zero">7.112 <code>.zero <var>size</var></code></a></li> + <li><a name="toc-_002e2byte-expression-_005b_002c-expression_005d_002a" href="#g_t2byte">7.113 <code>.2byte <var>expression</var> [, <var>expression</var>]*</code></a></li> + <li><a name="toc-_002e4byte-expression-_005b_002c-expression_005d_002a" href="#g_t4byte">7.114 <code>.4byte <var>expression</var> [, <var>expression</var>]*</code></a></li> + <li><a name="toc-_002e8byte-expression-_005b_002c-expression_005d_002a" href="#g_t8byte">7.115 <code>.8byte <var>expression</var> [, <var>expression</var>]*</code></a></li> + <li><a name="toc-Deprecated-Directives" href="#Deprecated">7.116 Deprecated Directives</a></li> + </ul></li> + <li><a name="toc-Object-Attributes-1" href="#Object-Attributes">8 Object Attributes</a> + <ul class="no-bullet"> + <li><a name="toc-GNU-Object-Attributes-1" href="#GNU-Object-Attributes">8.1 <small>GNU</small> Object Attributes</a> + <ul class="no-bullet"> + <li><a name="toc-Common-GNU-attributes" href="#Common-GNU-attributes">8.1.1 Common <small>GNU</small> attributes</a></li> + <li><a name="toc-M680x0-Attributes" href="#M680x0-Attributes">8.1.2 M680x0 Attributes</a></li> + <li><a name="toc-MIPS-Attributes" href="#MIPS-Attributes">8.1.3 MIPS Attributes</a></li> + <li><a name="toc-PowerPC-Attributes" href="#PowerPC-Attributes">8.1.4 PowerPC Attributes</a></li> + <li><a name="toc-IBM-z-Systems-Attributes" href="#IBM-z-Systems-Attributes">8.1.5 IBM z Systems Attributes</a></li> + <li><a name="toc-MSP430-Attributes" href="#MSP430-Attributes">8.1.6 MSP430 Attributes</a></li> + </ul></li> + <li><a name="toc-Defining-New-Object-Attributes-1" href="#Defining-New-Object-Attributes">8.2 Defining New Object Attributes</a></li> + </ul></li> + <li><a name="toc-Machine-Dependent-Features" href="#Machine-Dependencies">9 Machine Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-AArch64-Dependent-Features" href="#AArch64_002dDependent">9.1 AArch64 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options" href="#AArch64-Options">9.1.1 Options</a></li> + <li><a name="toc-Architecture-Extensions" href="#AArch64-Extensions">9.1.2 Architecture Extensions</a></li> + <li><a name="toc-Syntax-2" href="#AArch64-Syntax">9.1.3 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters" href="#AArch64_002dChars">9.1.3.1 Special Characters</a></li> + <li><a name="toc-Register-Names" href="#AArch64_002dRegs">9.1.3.2 Register Names</a></li> + <li><a name="toc-Relocations" href="#AArch64_002dRelocations">9.1.3.3 Relocations</a></li> + </ul></li> + <li><a name="toc-Floating-Point" href="#AArch64-Floating-Point">9.1.4 Floating Point</a></li> + <li><a name="toc-AArch64-Machine-Directives" href="#AArch64-Directives">9.1.5 AArch64 Machine Directives</a></li> + <li><a name="toc-Opcodes" href="#AArch64-Opcodes">9.1.6 Opcodes</a></li> + <li><a name="toc-Mapping-Symbols" href="#AArch64-Mapping-Symbols">9.1.7 Mapping Symbols</a></li> + </ul></li> + <li><a name="toc-Alpha-Dependent-Features" href="#Alpha_002dDependent">9.2 Alpha Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Notes" href="#Alpha-Notes">9.2.1 Notes</a></li> + <li><a name="toc-Options-1" href="#Alpha-Options">9.2.2 Options</a></li> + <li><a name="toc-Syntax-3" href="#Alpha-Syntax">9.2.3 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-1" href="#Alpha_002dChars">9.2.3.1 Special Characters</a></li> + <li><a name="toc-Register-Names-1" href="#Alpha_002dRegs">9.2.3.2 Register Names</a></li> + <li><a name="toc-Relocations-1" href="#Alpha_002dRelocs">9.2.3.3 Relocations</a></li> + </ul></li> + <li><a name="toc-Floating-Point-1" href="#Alpha-Floating-Point">9.2.4 Floating Point</a></li> + <li><a name="toc-Alpha-Assembler-Directives" href="#Alpha-Directives">9.2.5 Alpha Assembler Directives</a></li> + <li><a name="toc-Opcodes-1" href="#Alpha-Opcodes">9.2.6 Opcodes</a></li> + </ul></li> + <li><a name="toc-ARC-Dependent-Features" href="#ARC_002dDependent">9.3 ARC Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-2" href="#ARC-Options">9.3.1 Options</a></li> + <li><a name="toc-Syntax-4" href="#ARC-Syntax">9.3.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-2" href="#ARC_002dChars">9.3.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-2" href="#ARC_002dRegs">9.3.2.2 Register Names</a></li> + </ul></li> + <li><a name="toc-ARC-Machine-Directives" href="#ARC-Directives">9.3.3 ARC Machine Directives</a></li> + <li><a name="toc-ARC-Assembler-Modifiers" href="#ARC-Modifiers">9.3.4 ARC Assembler Modifiers</a></li> + <li><a name="toc-ARC-Pre_002ddefined-Symbols" href="#ARC-Symbols">9.3.5 ARC Pre-defined Symbols</a></li> + <li><a name="toc-Opcodes-2" href="#ARC-Opcodes">9.3.6 Opcodes</a></li> + </ul></li> + <li><a name="toc-ARM-Dependent-Features" href="#ARM_002dDependent">9.4 ARM Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-3" href="#ARM-Options">9.4.1 Options</a></li> + <li><a name="toc-Syntax-5" href="#ARM-Syntax">9.4.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Instruction-Set-Syntax" href="#ARM_002dInstruction_002dSet">9.4.2.1 Instruction Set Syntax</a></li> + <li><a name="toc-Special-Characters-3" href="#ARM_002dChars">9.4.2.2 Special Characters</a></li> + <li><a name="toc-Register-Names-3" href="#ARM_002dRegs">9.4.2.3 Register Names</a></li> + <li><a name="toc-ARM-relocation-generation" href="#ARM_002dRelocations">9.4.2.4 ARM relocation generation</a></li> + <li><a name="toc-NEON-Alignment-Specifiers" href="#ARM_002dNeon_002dAlignment">9.4.2.5 NEON Alignment Specifiers</a></li> + </ul></li> + <li><a name="toc-Floating-Point-2" href="#ARM-Floating-Point">9.4.3 Floating Point</a></li> + <li><a name="toc-ARM-Machine-Directives" href="#ARM-Directives">9.4.4 ARM Machine Directives</a></li> + <li><a name="toc-Opcodes-3" href="#ARM-Opcodes">9.4.5 Opcodes</a></li> + <li><a name="toc-Mapping-Symbols-1" href="#ARM-Mapping-Symbols">9.4.6 Mapping Symbols</a></li> + <li><a name="toc-Unwinding" href="#ARM-Unwinding-Tutorial">9.4.7 Unwinding</a></li> + </ul></li> + <li><a name="toc-AVR-Dependent-Features" href="#AVR_002dDependent">9.5 AVR Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-4" href="#AVR-Options">9.5.1 Options</a></li> + <li><a name="toc-Syntax-6" href="#AVR-Syntax">9.5.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-4" href="#AVR_002dChars">9.5.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-4" href="#AVR_002dRegs">9.5.2.2 Register Names</a></li> + <li><a name="toc-Relocatable-Expression-Modifiers" href="#AVR_002dModifiers">9.5.2.3 Relocatable Expression Modifiers</a></li> + </ul></li> + <li><a name="toc-Opcodes-4" href="#AVR-Opcodes">9.5.3 Opcodes</a></li> + <li><a name="toc-Pseudo-Instructions" href="#AVR-Pseudo-Instructions">9.5.4 Pseudo Instructions</a></li> + </ul></li> + <li><a name="toc-Blackfin-Dependent-Features" href="#Blackfin_002dDependent">9.6 Blackfin Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-5" href="#Blackfin-Options">9.6.1 Options</a></li> + <li><a name="toc-Syntax-7" href="#Blackfin-Syntax">9.6.2 Syntax</a></li> + <li><a name="toc-Directives" href="#Blackfin-Directives">9.6.3 Directives</a></li> + </ul></li> + <li><a name="toc-BPF-Dependent-Features" href="#BPF_002dDependent">9.7 BPF Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-6" href="#BPF-Options">9.7.1 Options</a></li> + <li><a name="toc-Syntax-8" href="#BPF-Syntax">9.7.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-5" href="#BPF_002dChars">9.7.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-5" href="#BPF_002dRegs">9.7.2.2 Register Names</a></li> + <li><a name="toc-Pseudo-Maps" href="#BPF_002dPseudo_002dMaps">9.7.2.3 Pseudo Maps</a></li> + </ul></li> + <li><a name="toc-Machine-Directives" href="#BPF-Directives">9.7.3 Machine Directives</a></li> + <li><a name="toc-Opcodes-5" href="#BPF-Opcodes">9.7.4 Opcodes</a> + <ul class="no-bullet"> + <li><a name="toc-Arithmetic-instructions" href="#Arithmetic-instructions">9.7.4.1 Arithmetic instructions</a></li> + <li><a name="toc-32_002dbit-arithmetic-instructions" href="#g_t32_002dbit-arithmetic-instructions">9.7.4.2 32-bit arithmetic instructions</a></li> + <li><a name="toc-Endianness-conversion-instructions" href="#Endianness-conversion-instructions">9.7.4.3 Endianness conversion instructions</a></li> + <li><a name="toc-64_002dbit-load-and-pseudo-maps" href="#g_t64_002dbit-load-and-pseudo-maps">9.7.4.4 64-bit load and pseudo maps</a></li> + <li><a name="toc-Load-instructions-for-socket-filters" href="#Load-instructions-for-socket-filters">9.7.4.5 Load instructions for socket filters</a></li> + <li><a name="toc-Generic-load_002fstore-instructions" href="#Generic-load_002fstore-instructions">9.7.4.6 Generic load/store instructions</a></li> + <li><a name="toc-Jump-instructions" href="#Jump-instructions">9.7.4.7 Jump instructions</a></li> + <li><a name="toc-Atomic-instructions" href="#Atomic-instructions">9.7.4.8 Atomic instructions</a></li> + </ul></li> + <li><a name="toc-BPF-Pseudo_002dC-Syntax-1" href="#BPF-Pseudo_002dC-Syntax">9.7.5 BPF Pseudo-C Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Pseudo_002dC-Register-Names" href="#Pseudo_002dC-Register-Names">9.7.5.1 Pseudo-C Register Names</a></li> + <li><a name="toc-Arithmetic-instructions-1" href="#Arithmetic-instructions-1">9.7.5.2 Arithmetic instructions</a></li> + <li><a name="toc-Endianness-conversion-instructions-1" href="#Endianness-conversion-instructions-1">9.7.5.3 Endianness conversion instructions</a></li> + <li><a name="toc-64_002dbit-load-and-pseudo-maps-1" href="#g_t64_002dbit-load-and-pseudo-maps-1">9.7.5.4 64-bit load and pseudo maps</a></li> + <li><a name="toc-Load-instructions-for-socket-filters-1" href="#Load-instructions-for-socket-filters-1">9.7.5.5 Load instructions for socket filters</a></li> + <li><a name="toc-Generic-load_002fstore-instructions-1" href="#Generic-load_002fstore-instructions-1">9.7.5.6 Generic load/store instructions</a></li> + <li><a name="toc-Jump-instructions-1" href="#Jump-instructions-1">9.7.5.7 Jump instructions</a></li> + <li><a name="toc-Atomic-instructions-1" href="#Atomic-instructions-1">9.7.5.8 Atomic instructions</a></li> + </ul></li> + </ul></li> + <li><a name="toc-CR16-Dependent-Features" href="#CR16_002dDependent">9.8 CR16 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-CR16-Operand-Qualifiers-1" href="#CR16-Operand-Qualifiers">9.8.1 CR16 Operand Qualifiers</a></li> + <li><a name="toc-CR16-Syntax-1" href="#CR16-Syntax">9.8.2 CR16 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-6" href="#CR16_002dChars">9.8.2.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-CRIS-Dependent-Features" href="#CRIS_002dDependent">9.9 CRIS Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Command_002dline-Options" href="#CRIS_002dOpts">9.9.1 Command-line Options</a></li> + <li><a name="toc-Instruction-expansion" href="#CRIS_002dExpand">9.9.2 Instruction expansion</a></li> + <li><a name="toc-Symbols-3" href="#CRIS_002dSymbols">9.9.3 Symbols</a></li> + <li><a name="toc-Syntax-9" href="#CRIS_002dSyntax">9.9.4 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-7" href="#CRIS_002dChars">9.9.4.1 Special Characters</a></li> + <li><a name="toc-Symbols-in-position_002dindependent-code" href="#CRIS_002dPic">9.9.4.2 Symbols in position-independent code</a></li> + <li><a name="toc-Register-names" href="#CRIS_002dRegs">9.9.4.3 Register names</a></li> + <li><a name="toc-Assembler-Directives-1" href="#CRIS_002dPseudos">9.9.4.4 Assembler Directives</a></li> + </ul></li> + </ul></li> + <li><a name="toc-C_002dSKY-Dependent-Features" href="#C_002dSKY_002dDependent">9.10 C-SKY Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-7" href="#C_002dSKY-Options">9.10.1 Options</a></li> + <li><a name="toc-Syntax-10" href="#C_002dSKY-Syntax">9.10.2 Syntax</a></li> + </ul></li> + <li><a name="toc-D10V-Dependent-Features" href="#D10V_002dDependent">9.11 D10V Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-D10V-Options" href="#D10V_002dOpts">9.11.1 D10V Options</a></li> + <li><a name="toc-Syntax-11" href="#D10V_002dSyntax">9.11.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Size-Modifiers" href="#D10V_002dSize">9.11.2.1 Size Modifiers</a></li> + <li><a name="toc-Sub_002dInstructions" href="#D10V_002dSubs">9.11.2.2 Sub-Instructions</a></li> + <li><a name="toc-Special-Characters-8" href="#D10V_002dChars">9.11.2.3 Special Characters</a></li> + <li><a name="toc-Register-Names-6" href="#D10V_002dRegs">9.11.2.4 Register Names</a></li> + <li><a name="toc-Addressing-Modes" href="#D10V_002dAddressing">9.11.2.5 Addressing Modes</a></li> + <li><a name="toc-_0040WORD-Modifier" href="#D10V_002dWord">9.11.2.6 @WORD Modifier</a></li> + </ul></li> + <li><a name="toc-Floating-Point-3" href="#D10V_002dFloat">9.11.3 Floating Point</a></li> + <li><a name="toc-Opcodes-6" href="#D10V_002dOpcodes">9.11.4 Opcodes</a></li> + </ul></li> + <li><a name="toc-D30V-Dependent-Features" href="#D30V_002dDependent">9.12 D30V Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-D30V-Options" href="#D30V_002dOpts">9.12.1 D30V Options</a></li> + <li><a name="toc-Syntax-12" href="#D30V_002dSyntax">9.12.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Size-Modifiers-1" href="#D30V_002dSize">9.12.2.1 Size Modifiers</a></li> + <li><a name="toc-Sub_002dInstructions-1" href="#D30V_002dSubs">9.12.2.2 Sub-Instructions</a></li> + <li><a name="toc-Special-Characters-9" href="#D30V_002dChars">9.12.2.3 Special Characters</a></li> + <li><a name="toc-Guarded-Execution" href="#D30V_002dGuarded">9.12.2.4 Guarded Execution</a></li> + <li><a name="toc-Register-Names-7" href="#D30V_002dRegs">9.12.2.5 Register Names</a></li> + <li><a name="toc-Addressing-Modes-1" href="#D30V_002dAddressing">9.12.2.6 Addressing Modes</a></li> + </ul></li> + <li><a name="toc-Floating-Point-4" href="#D30V_002dFloat">9.12.3 Floating Point</a></li> + <li><a name="toc-Opcodes-7" href="#D30V_002dOpcodes">9.12.4 Opcodes</a></li> + </ul></li> + <li><a name="toc-Epiphany-Dependent-Features" href="#Epiphany_002dDependent">9.13 Epiphany Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-8" href="#Epiphany-Options">9.13.1 Options</a></li> + <li><a name="toc-Epiphany-Syntax-1" href="#Epiphany-Syntax">9.13.2 Epiphany Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-10" href="#Epiphany_002dChars">9.13.2.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-H8_002f300-Dependent-Features" href="#H8_002f300_002dDependent">9.14 H8/300 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-9" href="#H8_002f300-Options">9.14.1 Options</a></li> + <li><a name="toc-Syntax-13" href="#H8_002f300-Syntax">9.14.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-11" href="#H8_002f300_002dChars">9.14.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-8" href="#H8_002f300_002dRegs">9.14.2.2 Register Names</a></li> + <li><a name="toc-Addressing-Modes-2" href="#H8_002f300_002dAddressing">9.14.2.3 Addressing Modes</a></li> + </ul></li> + <li><a name="toc-Floating-Point-5" href="#H8_002f300-Floating-Point">9.14.3 Floating Point</a></li> + <li><a name="toc-H8_002f300-Machine-Directives" href="#H8_002f300-Directives">9.14.4 H8/300 Machine Directives</a></li> + <li><a name="toc-Opcodes-8" href="#H8_002f300-Opcodes">9.14.5 Opcodes</a></li> + </ul></li> + <li><a name="toc-HPPA-Dependent-Features" href="#HPPA_002dDependent">9.15 HPPA Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Notes-1" href="#HPPA-Notes">9.15.1 Notes</a></li> + <li><a name="toc-Options-10" href="#HPPA-Options">9.15.2 Options</a></li> + <li><a name="toc-Syntax-14" href="#HPPA-Syntax">9.15.3 Syntax</a></li> + <li><a name="toc-Floating-Point-6" href="#HPPA-Floating-Point">9.15.4 Floating Point</a></li> + <li><a name="toc-HPPA-Assembler-Directives" href="#HPPA-Directives">9.15.5 HPPA Assembler Directives</a></li> + <li><a name="toc-Opcodes-9" href="#HPPA-Opcodes">9.15.6 Opcodes</a></li> + </ul></li> + <li><a name="toc-80386-Dependent-Features" href="#i386_002dDependent">9.16 80386 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-11" href="#i386_002dOptions">9.16.1 Options</a></li> + <li><a name="toc-x86-specific-Directives" href="#i386_002dDirectives">9.16.2 x86 specific Directives</a></li> + <li><a name="toc-i386-Syntactical-Considerations" href="#i386_002dSyntax">9.16.3 i386 Syntactical Considerations</a> + <ul class="no-bullet"> + <li><a name="toc-AT_0026T-Syntax-versus-Intel-Syntax" href="#i386_002dVariations">9.16.3.1 AT&T Syntax versus Intel Syntax</a></li> + <li><a name="toc-Special-Characters-12" href="#i386_002dChars">9.16.3.2 Special Characters</a></li> + </ul></li> + <li><a name="toc-i386_002dMnemonics-1" href="#i386_002dMnemonics">9.16.4 i386-Mnemonics</a> + <ul class="no-bullet"> + <li><a name="toc-Instruction-Naming" href="#Instruction-Naming">9.16.4.1 Instruction Naming</a></li> + <li><a name="toc-AT_0026T-Mnemonic-versus-Intel-Mnemonic" href="#AT_0026T-Mnemonic-versus-Intel-Mnemonic">9.16.4.2 AT&T Mnemonic versus Intel Mnemonic</a></li> + </ul></li> + <li><a name="toc-Register-Naming" href="#i386_002dRegs">9.16.5 Register Naming</a></li> + <li><a name="toc-Instruction-Prefixes" href="#i386_002dPrefixes">9.16.6 Instruction Prefixes</a></li> + <li><a name="toc-Memory-References" href="#i386_002dMemory">9.16.7 Memory References</a></li> + <li><a name="toc-Handling-of-Jump-Instructions" href="#i386_002dJumps">9.16.8 Handling of Jump Instructions</a></li> + <li><a name="toc-Floating-Point-7" href="#i386_002dFloat">9.16.9 Floating Point</a></li> + <li><a name="toc-Intel_0027s-MMX-and-AMD_0027s-3DNow_0021-SIMD-Operations" href="#i386_002dSIMD">9.16.10 Intel’s MMX and AMD’s 3DNow! SIMD Operations</a></li> + <li><a name="toc-AMD_0027s-Lightweight-Profiling-Instructions" href="#i386_002dLWP">9.16.11 AMD’s Lightweight Profiling Instructions</a></li> + <li><a name="toc-Bit-Manipulation-Instructions" href="#i386_002dBMI">9.16.12 Bit Manipulation Instructions</a></li> + <li><a name="toc-AMD_0027s-Trailing-Bit-Manipulation-Instructions" href="#i386_002dTBM">9.16.13 AMD’s Trailing Bit Manipulation Instructions</a></li> + <li><a name="toc-Writing-16_002dbit-Code" href="#i386_002d16bit">9.16.14 Writing 16-bit Code</a></li> + <li><a name="toc-Specifying-CPU-Architecture" href="#i386_002dArch">9.16.15 Specifying CPU Architecture</a></li> + <li><a name="toc-AMD64-ISA-vs_002e-Intel64-ISA" href="#i386_002dISA">9.16.16 AMD64 ISA vs. Intel64 ISA</a></li> + <li><a name="toc-AT_0026T-Syntax-bugs" href="#i386_002dBugs">9.16.17 AT&T Syntax bugs</a></li> + <li><a name="toc-Notes-2" href="#i386_002dNotes">9.16.18 Notes</a></li> + </ul></li> + <li><a name="toc-IA_002d64-Dependent-Features" href="#IA_002d64_002dDependent">9.17 IA-64 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-12" href="#IA_002d64-Options">9.17.1 Options</a></li> + <li><a name="toc-Syntax-15" href="#IA_002d64-Syntax">9.17.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-13" href="#IA_002d64_002dChars">9.17.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-9" href="#IA_002d64_002dRegs">9.17.2.2 Register Names</a></li> + <li><a name="toc-IA_002d64-Processor_002dStatus_002dRegister-_0028PSR_0029-Bit-Names" href="#IA_002d64_002dBits">9.17.2.3 IA-64 Processor-Status-Register (PSR) Bit Names</a></li> + <li><a name="toc-Relocations-2" href="#IA_002d64_002dRelocs">9.17.2.4 Relocations</a></li> + </ul></li> + <li><a name="toc-Opcodes-10" href="#IA_002d64-Opcodes">9.17.3 Opcodes</a></li> + </ul></li> + <li><a name="toc-IP2K-Dependent-Features" href="#IP2K_002dDependent">9.18 IP2K Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-IP2K-Options" href="#IP2K_002dOpts">9.18.1 IP2K Options</a></li> + <li><a name="toc-IP2K-Syntax" href="#IP2K_002dSyntax">9.18.2 IP2K Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-14" href="#IP2K_002dChars">9.18.2.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-LM32-Dependent-Features" href="#LM32_002dDependent">9.19 LM32 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-13" href="#LM32-Options">9.19.1 Options</a></li> + <li><a name="toc-Syntax-16" href="#LM32-Syntax">9.19.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Register-Names-10" href="#LM32_002dRegs">9.19.2.1 Register Names</a></li> + <li><a name="toc-Relocatable-Expression-Modifiers-1" href="#LM32_002dModifiers">9.19.2.2 Relocatable Expression Modifiers</a></li> + <li><a name="toc-Special-Characters-15" href="#LM32_002dChars">9.19.2.3 Special Characters</a></li> + </ul></li> + <li><a name="toc-Opcodes-11" href="#LM32-Opcodes">9.19.3 Opcodes</a></li> + </ul></li> + <li><a name="toc-M32C-Dependent-Features" href="#M32C_002dDependent">9.20 M32C Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-M32C-Options" href="#M32C_002dOpts">9.20.1 M32C Options</a></li> + <li><a name="toc-M32C-Syntax" href="#M32C_002dSyntax">9.20.2 M32C Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Symbolic-Operand-Modifiers" href="#M32C_002dModifiers">9.20.2.1 Symbolic Operand Modifiers</a></li> + <li><a name="toc-Special-Characters-16" href="#M32C_002dChars">9.20.2.2 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-M32R-Dependent-Features" href="#M32R_002dDependent">9.21 M32R Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-M32R-Options" href="#M32R_002dOpts">9.21.1 M32R Options</a></li> + <li><a name="toc-M32R-Directives" href="#M32R_002dDirectives">9.21.2 M32R Directives</a></li> + <li><a name="toc-M32R-Warnings" href="#M32R_002dWarnings">9.21.3 M32R Warnings</a></li> + </ul></li> + <li><a name="toc-M680x0-Dependent-Features" href="#M68K_002dDependent">9.22 M680x0 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-M680x0-Options" href="#M68K_002dOpts">9.22.1 M680x0 Options</a></li> + <li><a name="toc-Syntax-17" href="#M68K_002dSyntax">9.22.2 Syntax</a></li> + <li><a name="toc-Motorola-Syntax" href="#M68K_002dMoto_002dSyntax">9.22.3 Motorola Syntax</a></li> + <li><a name="toc-Floating-Point-8" href="#M68K_002dFloat">9.22.4 Floating Point</a></li> + <li><a name="toc-680x0-Machine-Directives" href="#M68K_002dDirectives">9.22.5 680x0 Machine Directives</a></li> + <li><a name="toc-Opcodes-12" href="#M68K_002dopcodes">9.22.6 Opcodes</a> + <ul class="no-bullet"> + <li><a name="toc-Branch-Improvement" href="#M68K_002dBranch">9.22.6.1 Branch Improvement</a></li> + <li><a name="toc-Special-Characters-17" href="#M68K_002dChars">9.22.6.2 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-M68HC11-and-M68HC12-Dependent-Features" href="#M68HC11_002dDependent">9.23 M68HC11 and M68HC12 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-M68HC11-and-M68HC12-Options" href="#M68HC11_002dOpts">9.23.1 M68HC11 and M68HC12 Options</a></li> + <li><a name="toc-Syntax-18" href="#M68HC11_002dSyntax">9.23.2 Syntax</a></li> + <li><a name="toc-Symbolic-Operand-Modifiers-1" href="#M68HC11_002dModifiers">9.23.3 Symbolic Operand Modifiers</a></li> + <li><a name="toc-Assembler-Directives-2" href="#M68HC11_002dDirectives">9.23.4 Assembler Directives</a></li> + <li><a name="toc-Floating-Point-9" href="#M68HC11_002dFloat">9.23.5 Floating Point</a></li> + <li><a name="toc-Opcodes-13" href="#M68HC11_002dopcodes">9.23.6 Opcodes</a> + <ul class="no-bullet"> + <li><a name="toc-Branch-Improvement-1" href="#M68HC11_002dBranch">9.23.6.1 Branch Improvement</a></li> + </ul></li> + </ul></li> + <li><a name="toc-S12Z-Dependent-Features" href="#S12Z_002dDependent">9.24 S12Z Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-S12Z-Options-1" href="#S12Z-Options">9.24.1 S12Z Options</a></li> + <li><a name="toc-Syntax-19" href="#S12Z-Syntax">9.24.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Overview-2" href="#S12Z-Syntax-Overview">9.24.2.1 Overview</a></li> + <li><a name="toc-Addressing-Modes-3" href="#S12Z-Addressing-Modes">9.24.2.2 Addressing Modes</a></li> + <li><a name="toc-Register-Notation" href="#S12Z-Register-Notation">9.24.2.3 Register Notation</a></li> + </ul></li> + </ul></li> + <li><a name="toc-Meta-Dependent-Features" href="#Meta_002dDependent">9.25 Meta Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-14" href="#Meta-Options">9.25.1 Options</a></li> + <li><a name="toc-Syntax-20" href="#Meta-Syntax">9.25.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-18" href="#Meta_002dChars">9.25.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-11" href="#Meta_002dRegs">9.25.2.2 Register Names</a></li> + </ul></li> + </ul></li> + <li><a name="toc-MicroBlaze-Dependent-Features" href="#MicroBlaze_002dDependent">9.26 MicroBlaze Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Directives-1" href="#MicroBlaze-Directives">9.26.1 Directives</a></li> + <li><a name="toc-Syntax-for-the-MicroBlaze" href="#MicroBlaze-Syntax">9.26.2 Syntax for the MicroBlaze</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-19" href="#MicroBlaze_002dChars">9.26.2.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-MIPS-Dependent-Features" href="#MIPS_002dDependent">9.27 MIPS Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Assembler-options" href="#MIPS-Options">9.27.1 Assembler options</a></li> + <li><a name="toc-High_002dlevel-assembly-macros" href="#MIPS-Macros">9.27.2 High-level assembly macros</a></li> + <li><a name="toc-Directives-to-override-the-size-of-symbols" href="#MIPS-Symbol-Sizes">9.27.3 Directives to override the size of symbols</a></li> + <li><a name="toc-Controlling-the-use-of-small-data-accesses" href="#MIPS-Small-Data">9.27.4 Controlling the use of small data accesses</a></li> + <li><a name="toc-Directives-to-override-the-ISA-level" href="#MIPS-ISA">9.27.5 Directives to override the ISA level</a></li> + <li><a name="toc-Directives-to-control-code-generation" href="#MIPS-assembly-options">9.27.6 Directives to control code generation</a></li> + <li><a name="toc-Directives-for-extending-MIPS-16-bit-instructions" href="#MIPS-autoextend">9.27.7 Directives for extending MIPS 16 bit instructions</a></li> + <li><a name="toc-Directive-to-mark-data-as-an-instruction" href="#MIPS-insn">9.27.8 Directive to mark data as an instruction</a></li> + <li><a name="toc-Directives-to-control-the-FP-ABI" href="#MIPS-FP-ABIs">9.27.9 Directives to control the FP ABI</a> + <ul class="no-bullet"> + <li><a name="toc-History-of-FP-ABIs" href="#MIPS-FP-ABI-History">9.27.9.1 History of FP ABIs</a></li> + <li><a name="toc-Supported-FP-ABIs" href="#MIPS-FP-ABI-Variants">9.27.9.2 Supported FP ABIs</a></li> + <li><a name="toc-Automatic-selection-of-FP-ABI" href="#MIPS-FP-ABI-Selection">9.27.9.3 Automatic selection of FP ABI</a></li> + <li><a name="toc-Linking-different-FP-ABI-variants" href="#MIPS-FP-ABI-Compatibility">9.27.9.4 Linking different FP ABI variants</a></li> + </ul></li> + <li><a name="toc-Directives-to-record-which-NaN-encoding-is-being-used" href="#MIPS-NaN-Encodings">9.27.10 Directives to record which NaN encoding is being used</a></li> + <li><a name="toc-Directives-to-save-and-restore-options" href="#MIPS-Option-Stack">9.27.11 Directives to save and restore options</a></li> + <li><a name="toc-Directives-to-control-generation-of-MIPS-ASE-instructions" href="#MIPS-ASE-Instruction-Generation-Overrides">9.27.12 Directives to control generation of MIPS ASE instructions</a></li> + <li><a name="toc-Directives-to-override-floating_002dpoint-options" href="#MIPS-Floating_002dPoint">9.27.13 Directives to override floating-point options</a></li> + <li><a name="toc-Syntactical-considerations-for-the-MIPS-assembler" href="#MIPS-Syntax">9.27.14 Syntactical considerations for the MIPS assembler</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-20" href="#MIPS_002dChars">9.27.14.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-MMIX-Dependent-Features" href="#MMIX_002dDependent">9.28 MMIX Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Command_002dline-Options-1" href="#MMIX_002dOpts">9.28.1 Command-line Options</a></li> + <li><a name="toc-Instruction-expansion-1" href="#MMIX_002dExpand">9.28.2 Instruction expansion</a></li> + <li><a name="toc-Syntax-21" href="#MMIX_002dSyntax">9.28.3 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-21" href="#MMIX_002dChars">9.28.3.1 Special Characters</a></li> + <li><a name="toc-Symbols-4" href="#MMIX_002dSymbols">9.28.3.2 Symbols</a></li> + <li><a name="toc-Register-names-1" href="#MMIX_002dRegs">9.28.3.3 Register names</a></li> + <li><a name="toc-Assembler-Directives-3" href="#MMIX_002dPseudos">9.28.3.4 Assembler Directives</a></li> + </ul></li> + <li><a name="toc-Differences-to-mmixal" href="#MMIX_002dmmixal">9.28.4 Differences to <code>mmixal</code></a></li> + </ul></li> + <li><a name="toc-MSP-430-Dependent-Features" href="#MSP430_002dDependent">9.29 MSP 430 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-15" href="#MSP430-Options">9.29.1 Options</a></li> + <li><a name="toc-Syntax-22" href="#MSP430-Syntax">9.29.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Macros" href="#MSP430_002dMacros">9.29.2.1 Macros</a></li> + <li><a name="toc-Special-Characters-22" href="#MSP430_002dChars">9.29.2.2 Special Characters</a></li> + <li><a name="toc-Register-Names-12" href="#MSP430_002dRegs">9.29.2.3 Register Names</a></li> + <li><a name="toc-Assembler-Extensions" href="#MSP430_002dExt">9.29.2.4 Assembler Extensions</a></li> + </ul></li> + <li><a name="toc-Floating-Point-10" href="#MSP430-Floating-Point">9.29.3 Floating Point</a></li> + <li><a name="toc-MSP-430-Machine-Directives" href="#MSP430-Directives">9.29.4 MSP 430 Machine Directives</a></li> + <li><a name="toc-Opcodes-14" href="#MSP430-Opcodes">9.29.5 Opcodes</a></li> + <li><a name="toc-Profiling-Capability" href="#MSP430-Profiling-Capability">9.29.6 Profiling Capability</a></li> + </ul></li> + <li><a name="toc-NDS32-Dependent-Features" href="#NDS32_002dDependent">9.30 NDS32 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-NDS32-Options-1" href="#NDS32-Options">9.30.1 NDS32 Options</a></li> + <li><a name="toc-Syntax-23" href="#NDS32-Syntax">9.30.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-23" href="#NDS32_002dChars">9.30.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-13" href="#NDS32_002dRegs">9.30.2.2 Register Names</a></li> + <li><a name="toc-Pseudo-Instructions-1" href="#NDS32_002dOps">9.30.2.3 Pseudo Instructions</a></li> + </ul></li> + </ul></li> + <li><a name="toc-Nios-II-Dependent-Features" href="#NiosII_002dDependent">9.31 Nios II Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-16" href="#Nios-II-Options">9.31.1 Options</a></li> + <li><a name="toc-Syntax-24" href="#Nios-II-Syntax">9.31.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-24" href="#Nios-II-Chars">9.31.2.1 Special Characters</a></li> + </ul></li> + <li><a name="toc-Nios-II-Machine-Relocations" href="#Nios-II-Relocations">9.31.3 Nios II Machine Relocations</a></li> + <li><a name="toc-Nios-II-Machine-Directives" href="#Nios-II-Directives">9.31.4 Nios II Machine Directives</a></li> + <li><a name="toc-Opcodes-15" href="#Nios-II-Opcodes">9.31.5 Opcodes</a></li> + </ul></li> + <li><a name="toc-NS32K-Dependent-Features" href="#NS32K_002dDependent">9.32 NS32K Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Syntax-25" href="#NS32K-Syntax">9.32.1 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-25" href="#NS32K_002dChars">9.32.1.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-OPENRISC-Dependent-Features" href="#OpenRISC_002dDependent">9.33 OPENRISC Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-OpenRISC-Syntax" href="#OpenRISC_002dSyntax">9.33.1 OpenRISC Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-26" href="#OpenRISC_002dChars">9.33.1.1 Special Characters</a></li> + <li><a name="toc-Register-Names-14" href="#OpenRISC_002dRegs">9.33.1.2 Register Names</a></li> + <li><a name="toc-Relocations-3" href="#OpenRISC_002dRelocs">9.33.1.3 Relocations</a></li> + </ul></li> + <li><a name="toc-Floating-Point-11" href="#OpenRISC_002dFloat">9.33.2 Floating Point</a></li> + <li><a name="toc-OpenRISC-Machine-Directives" href="#OpenRISC_002dDirectives">9.33.3 OpenRISC Machine Directives</a></li> + <li><a name="toc-Opcodes-16" href="#OpenRISC_002dOpcodes">9.33.4 Opcodes</a></li> + </ul></li> + <li><a name="toc-PDP_002d11-Dependent-Features" href="#PDP_002d11_002dDependent">9.34 PDP-11 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-17" href="#PDP_002d11_002dOptions">9.34.1 Options</a> + <ul class="no-bullet"> + <li><a name="toc-Code-Generation-Options" href="#Code-Generation-Options">9.34.1.1 Code Generation Options</a></li> + <li><a name="toc-Instruction-Set-Extension-Options" href="#Instruction-Set-Extension-Options">9.34.1.2 Instruction Set Extension Options</a></li> + <li><a name="toc-CPU-Model-Options" href="#CPU-Model-Options">9.34.1.3 CPU Model Options</a></li> + <li><a name="toc-Machine-Model-Options" href="#Machine-Model-Options">9.34.1.4 Machine Model Options</a></li> + </ul></li> + <li><a name="toc-Assembler-Directives-4" href="#PDP_002d11_002dPseudos">9.34.2 Assembler Directives</a></li> + <li><a name="toc-PDP_002d11-Assembly-Language-Syntax" href="#PDP_002d11_002dSyntax">9.34.3 PDP-11 Assembly Language Syntax</a></li> + <li><a name="toc-Instruction-Naming-1" href="#PDP_002d11_002dMnemonics">9.34.4 Instruction Naming</a></li> + <li><a name="toc-Synthetic-Instructions" href="#PDP_002d11_002dSynthetic">9.34.5 Synthetic Instructions</a></li> + </ul></li> + <li><a name="toc-picoJava-Dependent-Features" href="#PJ_002dDependent">9.35 picoJava Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-18" href="#PJ-Options">9.35.1 Options</a></li> + <li><a name="toc-PJ-Syntax-1" href="#PJ-Syntax">9.35.2 PJ Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-27" href="#PJ_002dChars">9.35.2.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-PowerPC-Dependent-Features" href="#PPC_002dDependent">9.36 PowerPC Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-19" href="#PowerPC_002dOpts">9.36.1 Options</a></li> + <li><a name="toc-PowerPC-Assembler-Directives" href="#PowerPC_002dPseudo">9.36.2 PowerPC Assembler Directives</a></li> + <li><a name="toc-PowerPC-Syntax" href="#PowerPC_002dSyntax">9.36.3 PowerPC Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-28" href="#PowerPC_002dChars">9.36.3.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-PRU-Dependent-Features" href="#PRU_002dDependent">9.37 PRU Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-20" href="#PRU-Options">9.37.1 Options</a></li> + <li><a name="toc-Syntax-26" href="#PRU-Syntax">9.37.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-29" href="#PRU-Chars">9.37.2.1 Special Characters</a></li> + </ul></li> + <li><a name="toc-PRU-Machine-Relocations" href="#PRU-Relocations">9.37.3 PRU Machine Relocations</a></li> + <li><a name="toc-PRU-Machine-Directives" href="#PRU-Directives">9.37.4 PRU Machine Directives</a></li> + <li><a name="toc-Opcodes-17" href="#PRU-Opcodes">9.37.5 Opcodes</a></li> + </ul></li> + <li><a name="toc-RISC_002dV-Dependent-Features" href="#RISC_002dV_002dDependent">9.38 RISC-V Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-RISC_002dV-Options" href="#RISC_002dV_002dOptions">9.38.1 RISC-V Options</a></li> + <li><a name="toc-RISC_002dV-Directives" href="#RISC_002dV_002dDirectives">9.38.2 RISC-V Directives</a></li> + <li><a name="toc-RISC_002dV-Assembler-Modifiers" href="#RISC_002dV_002dModifiers">9.38.3 RISC-V Assembler Modifiers</a></li> + <li><a name="toc-RISC_002dV-Floating-Point" href="#RISC_002dV_002dFloating_002dPoint">9.38.4 RISC-V Floating Point</a></li> + <li><a name="toc-RISC_002dV-Instruction-Formats" href="#RISC_002dV_002dFormats">9.38.5 RISC-V Instruction Formats</a></li> + <li><a name="toc-RISC_002dV-Object-Attribute" href="#RISC_002dV_002dATTRIBUTE">9.38.6 RISC-V Object Attribute</a></li> + <li><a name="toc-RISC_002dV-Custom-_0028Vendor_002dDefined_0029-Extensions" href="#RISC_002dV_002dCustomExts">9.38.7 RISC-V Custom (Vendor-Defined) Extensions</a></li> + </ul></li> + <li><a name="toc-RL78-Dependent-Features" href="#RL78_002dDependent">9.39 RL78 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-RL78-Options" href="#RL78_002dOpts">9.39.1 RL78 Options</a></li> + <li><a name="toc-Symbolic-Operand-Modifiers-2" href="#RL78_002dModifiers">9.39.2 Symbolic Operand Modifiers</a></li> + <li><a name="toc-Assembler-Directives-5" href="#RL78_002dDirectives">9.39.3 Assembler Directives</a></li> + <li><a name="toc-Syntax-for-the-RL78" href="#RL78_002dSyntax">9.39.4 Syntax for the RL78</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-30" href="#RL78_002dChars">9.39.4.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-RX-Dependent-Features" href="#RX_002dDependent">9.40 RX Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-RX-Options" href="#RX_002dOpts">9.40.1 RX Options</a></li> + <li><a name="toc-Symbolic-Operand-Modifiers-3" href="#RX_002dModifiers">9.40.2 Symbolic Operand Modifiers</a></li> + <li><a name="toc-Assembler-Directives-6" href="#RX_002dDirectives">9.40.3 Assembler Directives</a></li> + <li><a name="toc-Floating-Point-12" href="#RX_002dFloat">9.40.4 Floating Point</a></li> + <li><a name="toc-Syntax-for-the-RX" href="#RX_002dSyntax">9.40.5 Syntax for the RX</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-31" href="#RX_002dChars">9.40.5.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-IBM-S_002f390-Dependent-Features" href="#S_002f390_002dDependent">9.41 IBM S/390 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-21" href="#s390-Options">9.41.1 Options</a></li> + <li><a name="toc-Special-Characters-32" href="#s390-Characters">9.41.2 Special Characters</a></li> + <li><a name="toc-Instruction-syntax" href="#s390-Syntax">9.41.3 Instruction syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Register-naming" href="#s390-Register">9.41.3.1 Register naming</a></li> + <li><a name="toc-Instruction-Mnemonics" href="#s390-Mnemonics">9.41.3.2 Instruction Mnemonics</a></li> + <li><a name="toc-Instruction-Operands" href="#s390-Operands">9.41.3.3 Instruction Operands</a></li> + <li><a name="toc-Instruction-Formats" href="#s390-Formats">9.41.3.4 Instruction Formats</a></li> + <li><a name="toc-Instruction-Aliases" href="#s390-Aliases">9.41.3.5 Instruction Aliases</a></li> + <li><a name="toc-Instruction-Operand-Modifier" href="#s390-Operand-Modifier">9.41.3.6 Instruction Operand Modifier</a></li> + <li><a name="toc-Instruction-Marker" href="#s390-Instruction-Marker">9.41.3.7 Instruction Marker</a></li> + <li><a name="toc-Literal-Pool-Entries" href="#s390-Literal-Pool-Entries">9.41.3.8 Literal Pool Entries</a></li> + </ul></li> + <li><a name="toc-Assembler-Directives-7" href="#s390-Directives">9.41.4 Assembler Directives</a></li> + <li><a name="toc-Floating-Point-13" href="#s390-Floating-Point">9.41.5 Floating Point</a></li> + </ul></li> + <li><a name="toc-SCORE-Dependent-Features" href="#SCORE_002dDependent">9.42 SCORE Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-22" href="#SCORE_002dOpts">9.42.1 Options</a></li> + <li><a name="toc-SCORE-Assembler-Directives" href="#SCORE_002dPseudo">9.42.2 SCORE Assembler Directives</a></li> + <li><a name="toc-SCORE-Syntax" href="#SCORE_002dSyntax">9.42.3 SCORE Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-33" href="#SCORE_002dChars">9.42.3.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-Renesas-_002f-SuperH-SH-Dependent-Features" href="#SH_002dDependent">9.43 Renesas / SuperH SH Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-23" href="#SH-Options">9.43.1 Options</a></li> + <li><a name="toc-Syntax-27" href="#SH-Syntax">9.43.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-34" href="#SH_002dChars">9.43.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-15" href="#SH_002dRegs">9.43.2.2 Register Names</a></li> + <li><a name="toc-Addressing-Modes-4" href="#SH_002dAddressing">9.43.2.3 Addressing Modes</a></li> + </ul></li> + <li><a name="toc-Floating-Point-14" href="#SH-Floating-Point">9.43.3 Floating Point</a></li> + <li><a name="toc-SH-Machine-Directives" href="#SH-Directives">9.43.4 SH Machine Directives</a></li> + <li><a name="toc-Opcodes-18" href="#SH-Opcodes">9.43.5 Opcodes</a></li> + </ul></li> + <li><a name="toc-SPARC-Dependent-Features" href="#Sparc_002dDependent">9.44 SPARC Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-24" href="#Sparc_002dOpts">9.44.1 Options</a></li> + <li><a name="toc-Enforcing-aligned-data" href="#Sparc_002dAligned_002dData">9.44.2 Enforcing aligned data</a></li> + <li><a name="toc-Sparc-Syntax" href="#Sparc_002dSyntax">9.44.3 Sparc Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-35" href="#Sparc_002dChars">9.44.3.1 Special Characters</a></li> + <li><a name="toc-Register-Names-16" href="#Sparc_002dRegs">9.44.3.2 Register Names</a></li> + <li><a name="toc-Constants-2" href="#Sparc_002dConstants">9.44.3.3 Constants</a></li> + <li><a name="toc-Relocations-4" href="#Sparc_002dRelocs">9.44.3.4 Relocations</a></li> + <li><a name="toc-Size-Translations" href="#Sparc_002dSize_002dTranslations">9.44.3.5 Size Translations</a></li> + </ul></li> + <li><a name="toc-Floating-Point-15" href="#Sparc_002dFloat">9.44.4 Floating Point</a></li> + <li><a name="toc-Sparc-Machine-Directives" href="#Sparc_002dDirectives">9.44.5 Sparc Machine Directives</a></li> + </ul></li> + <li><a name="toc-TIC54X-Dependent-Features" href="#TIC54X_002dDependent">9.45 TIC54X Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-25" href="#TIC54X_002dOpts">9.45.1 Options</a></li> + <li><a name="toc-Blocking" href="#TIC54X_002dBlock">9.45.2 Blocking</a></li> + <li><a name="toc-Environment-Settings" href="#TIC54X_002dEnv">9.45.3 Environment Settings</a></li> + <li><a name="toc-Constants-Syntax" href="#TIC54X_002dConstants">9.45.4 Constants Syntax</a></li> + <li><a name="toc-String-Substitution" href="#TIC54X_002dSubsyms">9.45.5 String Substitution</a></li> + <li><a name="toc-Local-Labels" href="#TIC54X_002dLocals">9.45.6 Local Labels</a></li> + <li><a name="toc-Math-Builtins" href="#TIC54X_002dBuiltins">9.45.7 Math Builtins</a></li> + <li><a name="toc-Extended-Addressing" href="#TIC54X_002dExt">9.45.8 Extended Addressing</a></li> + <li><a name="toc-Directives-2" href="#TIC54X_002dDirectives">9.45.9 Directives</a></li> + <li><a name="toc-Macros-1" href="#TIC54X_002dMacros">9.45.10 Macros</a></li> + <li><a name="toc-Memory_002dmapped-Registers" href="#TIC54X_002dMMRegs">9.45.11 Memory-mapped Registers</a></li> + <li><a name="toc-TIC54X-Syntax" href="#TIC54X_002dSyntax">9.45.12 TIC54X Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-36" href="#TIC54X_002dChars">9.45.12.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-TIC6X-Dependent-Features" href="#TIC6X_002dDependent">9.46 TIC6X Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-TIC6X-Options-1" href="#TIC6X-Options">9.46.1 TIC6X Options</a></li> + <li><a name="toc-TIC6X-Syntax-1" href="#TIC6X-Syntax">9.46.2 TIC6X Syntax</a></li> + <li><a name="toc-TIC6X-Directives-1" href="#TIC6X-Directives">9.46.3 TIC6X Directives</a></li> + </ul></li> + <li><a name="toc-TILE_002dGx-Dependent-Features" href="#TILE_002dGx_002dDependent">9.47 TILE-Gx Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-26" href="#TILE_002dGx-Options">9.47.1 Options</a></li> + <li><a name="toc-Syntax-28" href="#TILE_002dGx-Syntax">9.47.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Opcode-Names" href="#TILE_002dGx-Opcodes">9.47.2.1 Opcode Names</a></li> + <li><a name="toc-Register-Names-17" href="#TILE_002dGx-Registers">9.47.2.2 Register Names</a></li> + <li><a name="toc-Symbolic-Operand-Modifiers-4" href="#TILE_002dGx-Modifiers">9.47.2.3 Symbolic Operand Modifiers</a></li> + </ul></li> + <li><a name="toc-TILE_002dGx-Directives-1" href="#TILE_002dGx-Directives">9.47.3 TILE-Gx Directives</a></li> + </ul></li> + <li><a name="toc-TILEPro-Dependent-Features" href="#TILEPro_002dDependent">9.48 TILEPro Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-27" href="#TILEPro-Options">9.48.1 Options</a></li> + <li><a name="toc-Syntax-29" href="#TILEPro-Syntax">9.48.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Opcode-Names-1" href="#TILEPro-Opcodes">9.48.2.1 Opcode Names</a></li> + <li><a name="toc-Register-Names-18" href="#TILEPro-Registers">9.48.2.2 Register Names</a></li> + <li><a name="toc-Symbolic-Operand-Modifiers-5" href="#TILEPro-Modifiers">9.48.2.3 Symbolic Operand Modifiers</a></li> + </ul></li> + <li><a name="toc-TILEPro-Directives-1" href="#TILEPro-Directives">9.48.3 TILEPro Directives</a></li> + </ul></li> + <li><a name="toc-v850-Dependent-Features" href="#V850_002dDependent">9.49 v850 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-28" href="#V850-Options">9.49.1 Options</a></li> + <li><a name="toc-Syntax-30" href="#V850-Syntax">9.49.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-37" href="#V850_002dChars">9.49.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-19" href="#V850_002dRegs">9.49.2.2 Register Names</a></li> + </ul></li> + <li><a name="toc-Floating-Point-16" href="#V850-Floating-Point">9.49.3 Floating Point</a></li> + <li><a name="toc-V850-Machine-Directives" href="#V850-Directives">9.49.4 V850 Machine Directives</a></li> + <li><a name="toc-Opcodes-19" href="#V850-Opcodes">9.49.5 Opcodes</a></li> + </ul></li> + <li><a name="toc-VAX-Dependent-Features" href="#Vax_002dDependent">9.50 VAX Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-VAX-Command_002dLine-Options" href="#VAX_002dOpts">9.50.1 VAX Command-Line Options</a></li> + <li><a name="toc-VAX-Floating-Point" href="#VAX_002dfloat">9.50.2 VAX Floating Point</a></li> + <li><a name="toc-Vax-Machine-Directives" href="#VAX_002ddirectives">9.50.3 Vax Machine Directives</a></li> + <li><a name="toc-VAX-Opcodes" href="#VAX_002dopcodes">9.50.4 VAX Opcodes</a></li> + <li><a name="toc-VAX-Branch-Improvement" href="#VAX_002dbranch">9.50.5 VAX Branch Improvement</a></li> + <li><a name="toc-VAX-Operands" href="#VAX_002doperands">9.50.6 VAX Operands</a></li> + <li><a name="toc-Not-Supported-on-VAX" href="#VAX_002dno">9.50.7 Not Supported on VAX</a></li> + <li><a name="toc-VAX-Syntax" href="#VAX_002dSyntax">9.50.8 VAX Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-38" href="#VAX_002dChars">9.50.8.1 Special Characters</a></li> + </ul></li> + </ul></li> + <li><a name="toc-Visium-Dependent-Features" href="#Visium_002dDependent">9.51 Visium Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-29" href="#Visium-Options">9.51.1 Options</a></li> + <li><a name="toc-Syntax-31" href="#Visium-Syntax">9.51.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-39" href="#Visium-Characters">9.51.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-20" href="#Visium-Registers">9.51.2.2 Register Names</a></li> + </ul></li> + <li><a name="toc-Opcodes-20" href="#Visium-Opcodes">9.51.3 Opcodes</a></li> + </ul></li> + <li><a name="toc-WebAssembly-Dependent-Features" href="#WebAssembly_002dDependent">9.52 WebAssembly Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Notes-3" href="#WebAssembly_002dNotes">9.52.1 Notes</a></li> + <li><a name="toc-Syntax-32" href="#WebAssembly_002dSyntax">9.52.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-40" href="#WebAssembly_002dChars">9.52.2.1 Special Characters</a></li> + <li><a name="toc-Relocations-5" href="#WebAssembly_002dRelocs">9.52.2.2 Relocations</a></li> + <li><a name="toc-Signatures" href="#WebAssembly_002dSignatures">9.52.2.3 Signatures</a></li> + </ul></li> + <li><a name="toc-Floating-Point-17" href="#WebAssembly_002dFloating_002dPoint">9.52.3 Floating Point</a></li> + <li><a name="toc-Regular-Opcodes" href="#WebAssembly_002dOpcodes">9.52.4 Regular Opcodes</a></li> + <li><a name="toc-WebAssembly-Module-Layout" href="#WebAssembly_002dmodule_002dlayout">9.52.5 WebAssembly Module Layout</a></li> + </ul></li> + <li><a name="toc-XGATE-Dependent-Features" href="#XGATE_002dDependent">9.53 XGATE Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-XGATE-Options" href="#XGATE_002dOpts">9.53.1 XGATE Options</a></li> + <li><a name="toc-Syntax-33" href="#XGATE_002dSyntax">9.53.2 Syntax</a></li> + <li><a name="toc-Assembler-Directives-8" href="#XGATE_002dDirectives">9.53.3 Assembler Directives</a></li> + <li><a name="toc-Floating-Point-18" href="#XGATE_002dFloat">9.53.4 Floating Point</a></li> + <li><a name="toc-Opcodes-21" href="#XGATE_002dopcodes">9.53.5 Opcodes</a></li> + </ul></li> + <li><a name="toc-XStormy16-Dependent-Features" href="#XSTORMY16_002dDependent">9.54 XStormy16 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Syntax-34" href="#XStormy16-Syntax">9.54.1 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-41" href="#XStormy16_002dChars">9.54.1.1 Special Characters</a></li> + </ul></li> + <li><a name="toc-XStormy16-Machine-Directives" href="#XStormy16-Directives">9.54.2 XStormy16 Machine Directives</a></li> + <li><a name="toc-XStormy16-Pseudo_002dOpcodes" href="#XStormy16-Opcodes">9.54.3 XStormy16 Pseudo-Opcodes</a></li> + </ul></li> + <li><a name="toc-Xtensa-Dependent-Features" href="#Xtensa_002dDependent">9.55 Xtensa Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Command_002dline-Options-2" href="#Xtensa-Options">9.55.1 Command-line Options</a></li> + <li><a name="toc-Assembler-Syntax" href="#Xtensa-Syntax">9.55.2 Assembler Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Opcode-Names-2" href="#Xtensa-Opcodes">9.55.2.1 Opcode Names</a></li> + <li><a name="toc-Register-Names-21" href="#Xtensa-Registers">9.55.2.2 Register Names</a></li> + </ul></li> + <li><a name="toc-Xtensa-Optimizations-1" href="#Xtensa-Optimizations">9.55.3 Xtensa Optimizations</a> + <ul class="no-bullet"> + <li><a name="toc-Using-Density-Instructions" href="#Density-Instructions">9.55.3.1 Using Density Instructions</a></li> + <li><a name="toc-Automatic-Instruction-Alignment" href="#Xtensa-Automatic-Alignment">9.55.3.2 Automatic Instruction Alignment</a></li> + </ul></li> + <li><a name="toc-Xtensa-Relaxation-1" href="#Xtensa-Relaxation">9.55.4 Xtensa Relaxation</a> + <ul class="no-bullet"> + <li><a name="toc-Conditional-Branch-Relaxation" href="#Xtensa-Branch-Relaxation">9.55.4.1 Conditional Branch Relaxation</a></li> + <li><a name="toc-Function-Call-Relaxation" href="#Xtensa-Call-Relaxation">9.55.4.2 Function Call Relaxation</a></li> + <li><a name="toc-Jump-Relaxation" href="#Xtensa-Jump-Relaxation">9.55.4.3 Jump Relaxation</a></li> + <li><a name="toc-Other-Immediate-Field-Relaxation" href="#Xtensa-Immediate-Relaxation">9.55.4.4 Other Immediate Field Relaxation</a></li> + </ul></li> + <li><a name="toc-Directives-3" href="#Xtensa-Directives">9.55.5 Directives</a> + <ul class="no-bullet"> + <li><a name="toc-schedule" href="#Schedule-Directive">9.55.5.1 schedule</a></li> + <li><a name="toc-longcalls" href="#Longcalls-Directive">9.55.5.2 longcalls</a></li> + <li><a name="toc-transform" href="#Transform-Directive">9.55.5.3 transform</a></li> + <li><a name="toc-literal" href="#Literal-Directive">9.55.5.4 literal</a></li> + <li><a name="toc-literal_005fposition" href="#Literal-Position-Directive">9.55.5.5 literal_position</a></li> + <li><a name="toc-literal_005fprefix" href="#Literal-Prefix-Directive">9.55.5.6 literal_prefix</a></li> + <li><a name="toc-absolute_002dliterals" href="#Absolute-Literals-Directive">9.55.5.7 absolute-literals</a></li> + </ul></li> + </ul></li> + <li><a name="toc-Z80-Dependent-Features" href="#Z80_002dDependent">9.56 Z80 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Command_002dline-Options-3" href="#Z80-Options">9.56.1 Command-line Options</a></li> + <li><a name="toc-Syntax-35" href="#Z80-Syntax">9.56.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-42" href="#Z80_002dChars">9.56.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-22" href="#Z80_002dRegs">9.56.2.2 Register Names</a></li> + <li><a name="toc-Case-Sensitivity" href="#Z80_002dCase">9.56.2.3 Case Sensitivity</a></li> + <li><a name="toc-Labels-2" href="#Z80_002dLabels">9.56.2.4 Labels</a></li> + </ul></li> + <li><a name="toc-Floating-Point-19" href="#Z80-Floating-Point">9.56.3 Floating Point</a></li> + <li><a name="toc-Z80-Assembler-Directives" href="#Z80-Directives">9.56.4 Z80 Assembler Directives</a></li> + <li><a name="toc-Opcodes-22" href="#Z80-Opcodes">9.56.5 Opcodes</a></li> + </ul></li> + <li><a name="toc-Z8000-Dependent-Features" href="#Z8000_002dDependent">9.57 Z8000 Dependent Features</a> + <ul class="no-bullet"> + <li><a name="toc-Options-30" href="#Z8000-Options">9.57.1 Options</a></li> + <li><a name="toc-Syntax-36" href="#Z8000-Syntax">9.57.2 Syntax</a> + <ul class="no-bullet"> + <li><a name="toc-Special-Characters-43" href="#Z8000_002dChars">9.57.2.1 Special Characters</a></li> + <li><a name="toc-Register-Names-23" href="#Z8000_002dRegs">9.57.2.2 Register Names</a></li> + <li><a name="toc-Addressing-Modes-5" href="#Z8000_002dAddressing">9.57.2.3 Addressing Modes</a></li> + </ul></li> + <li><a name="toc-Assembler-Directives-for-the-Z8000" href="#Z8000-Directives">9.57.3 Assembler Directives for the Z8000</a></li> + <li><a name="toc-Opcodes-23" href="#Z8000-Opcodes">9.57.4 Opcodes</a></li> + </ul></li> + </ul></li> + <li><a name="toc-Reporting-Bugs-1" href="#Reporting-Bugs">10 Reporting Bugs</a> + <ul class="no-bullet"> + <li><a name="toc-Have-You-Found-a-Bug_003f" href="#Bug-Criteria">10.1 Have You Found a Bug?</a></li> + <li><a name="toc-How-to-Report-Bugs" href="#Bug-Reporting">10.2 How to Report Bugs</a></li> + </ul></li> + <li><a name="toc-Acknowledgements-1" href="#Acknowledgements">11 Acknowledgements</a></li> + <li><a name="toc-GNU-Free-Documentation-License-1" href="#GNU-Free-Documentation-License">Appendix A GNU Free Documentation License</a></li> + <li><a name="toc-AS-Index-1" href="#AS-Index">AS Index</a></li> +</ul> +</div> + + +<a name="Top"></a> +<div class="header"> +<p> +Next: <a href="#Overview" accesskey="n" rel="next">Overview</a>, Up: <a href="dir.html#Top" accesskey="u" rel="up">(dir)</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Using-as"></a> +<h1 class="top">Using as</h1> + +<p>This file is a user guide to the <small>GNU</small> assembler <code>as</code> +(Arm GNU Toolchain 13.2.rel1 (Build arm-13.7)) +version 2.41.0. +</p> +<p>This document is distributed under the terms of the GNU Free +Documentation License. A copy of the license is included in the +section entitled “GNU Free Documentation License”. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Overview" accesskey="1">Overview</a>:</td><td> </td><td align="left" valign="top">Overview +</td></tr> +<tr><td align="left" valign="top">• <a href="#Invoking" accesskey="2">Invoking</a>:</td><td> </td><td align="left" valign="top">Command-Line Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#Syntax" accesskey="3">Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sections" accesskey="4">Sections</a>:</td><td> </td><td align="left" valign="top">Sections and Relocation +</td></tr> +<tr><td align="left" valign="top">• <a href="#Symbols" accesskey="5">Symbols</a>:</td><td> </td><td align="left" valign="top">Symbols +</td></tr> +<tr><td align="left" valign="top">• <a href="#Expressions" accesskey="6">Expressions</a>:</td><td> </td><td align="left" valign="top">Expressions +</td></tr> +<tr><td align="left" valign="top">• <a href="#Pseudo-Ops" accesskey="7">Pseudo Ops</a>:</td><td> </td><td align="left" valign="top">Assembler Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#Object-Attributes" accesskey="8">Object Attributes</a>:</td><td> </td><td align="left" valign="top">Object Attributes +</td></tr> +<tr><td align="left" valign="top">• <a href="#Machine-Dependencies" accesskey="9">Machine Dependencies</a>:</td><td> </td><td align="left" valign="top">Machine Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Reporting-Bugs">Reporting Bugs</a>:</td><td> </td><td align="left" valign="top">Reporting Bugs +</td></tr> +<tr><td align="left" valign="top">• <a href="#Acknowledgements">Acknowledgements</a>:</td><td> </td><td align="left" valign="top">Who Did What +</td></tr> +<tr><td align="left" valign="top">• <a href="#GNU-Free-Documentation-License">GNU Free Documentation License</a>:</td><td> </td><td align="left" valign="top">GNU Free Documentation License +</td></tr> +<tr><td align="left" valign="top">• <a href="#AS-Index">AS Index</a>:</td><td> </td><td align="left" valign="top">AS Index +</td></tr> +</table> + +<hr> +<a name="Overview"></a> +<div class="header"> +<p> +Next: <a href="#Invoking" accesskey="n" rel="next">Invoking</a>, Previous: <a href="#Top" accesskey="p" rel="previous">Top</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Overview-1"></a> +<h2 class="chapter">1 Overview</h2> + +<a name="index-invocation-summary"></a> +<a name="index-option-summary"></a> +<a name="index-summary-of-options"></a> +<p>Here is a brief summary of how to invoke <code>as</code>. For details, +see <a href="#Invoking">Command-Line Options</a>. +</p> + + +<div class="smallexample"> +<pre class="smallexample">as [<b>-a</b>[<b>cdghlns</b>][=<var>file</var>]] + [<b>–alternate</b>] + [<b>–compress-debug-sections</b>] [<b>–nocompress-debug-sections</b>] + [<b>-D</b>] + [<b>–dump-config</b>] + [<b>–debug-prefix-map</b> <var>old</var>=<var>new</var>] + [<b>–defsym</b> <var>sym</var>=<var>val</var>] + [<b>–elf-stt-common=[no|yes]</b>] + [<b>–emulation</b>=<var>name</var>] + [<b>-f</b>] + [<b>-g</b>] [<b>–gstabs</b>] [<b>–gstabs+</b>] + [<b>–gdwarf-<N></b>] [<b>–gdwarf-sections</b>] + [<b>–gdwarf-cie-version</b>=<var>VERSION</var>] + [<b>–generate-missing-build-notes=[no|yes]</b>] + [<b>–gsframe</b>] + [<b>–hash-size</b>=<var>N</var>] + [<b>–help</b>] [<b>–target-help</b>] + [<b>-I</b> <var>dir</var>] + [<b>-J</b>] + [<b>-K</b>] + [<b>–keep-locals</b>] + [<b>-L</b>] + [<b>–listing-lhs-width</b>=<var>NUM</var>] + [<b>–listing-lhs-width2</b>=<var>NUM</var>] + [<b>–listing-rhs-width</b>=<var>NUM</var>] + [<b>–listing-cont-lines</b>=<var>NUM</var>] + [<b>–multibyte-handling=[allow|warn|warn-sym-only]</b>] + [<b>–no-pad-sections</b>] + [<b>-o</b> <var>objfile</var>] [<b>-R</b>] + [<b>–sectname-subst</b>] + [<b>–size-check=[error|warning]</b>] + [<b>–statistics</b>] + [<b>-v</b>] [<b>-version</b>] [<b>–version</b>] + [<b>-W</b>] [<b>–warn</b>] [<b>–fatal-warnings</b>] [<b>-w</b>] [<b>-x</b>] + [<b>-Z</b>] [<b>@<var>FILE</var></b>] + [<var>target-options</var>] + [<b>–</b>|<var>files</var> …] + +<em>Target AArch64 options:</em> + [<b>-EB</b>|<b>-EL</b>] + [<b>-mabi</b>=<var>ABI</var>] + +<em>Target Alpha options:</em> + [<b>-m<var>cpu</var></b>] + [<b>-mdebug</b> | <b>-no-mdebug</b>] + [<b>-replace</b> | <b>-noreplace</b>] + [<b>-relax</b>] [<b>-g</b>] [<b>-G<var>size</var></b>] + [<b>-F</b>] [<b>-32addr</b>] + +<em>Target ARC options:</em> + [<b>-mcpu=<var>cpu</var></b>] + [<b>-mA6</b>|<b>-mARC600</b>|<b>-mARC601</b>|<b>-mA7</b>|<b>-mARC700</b>|<b>-mEM</b>|<b>-mHS</b>] + [<b>-mcode-density</b>] + [<b>-mrelax</b>] + [<b>-EB</b>|<b>-EL</b>] + +<em>Target ARM options:</em> + [<b>-mcpu</b>=<var>processor</var>[+<var>extension</var>…]] + [<b>-march</b>=<var>architecture</var>[+<var>extension</var>…]] + [<b>-mfpu</b>=<var>floating-point-format</var>] + [<b>-mfloat-abi</b>=<var>abi</var>] + [<b>-meabi</b>=<var>ver</var>] + [<b>-mthumb</b>] + [<b>-EB</b>|<b>-EL</b>] + [<b>-mapcs-32</b>|<b>-mapcs-26</b>|<b>-mapcs-float</b>| + <b>-mapcs-reentrant</b>] + [<b>-mthumb-interwork</b>] [<b>-k</b>] + +<em>Target Blackfin options:</em> + [<b>-mcpu</b>=<var>processor</var>[-<var>sirevision</var>]] + [<b>-mfdpic</b>] + [<b>-mno-fdpic</b>] + [<b>-mnopic</b>] + +<em>Target BPF options:</em> + [<b>-EL</b>] [<b>-EB</b>] + +<em>Target CRIS options:</em> + [<b>–underscore</b> | <b>–no-underscore</b>] + [<b>–pic</b>] [<b>-N</b>] + [<b>–emulation=criself</b> | <b>–emulation=crisaout</b>] + [<b>–march=v0_v10</b> | <b>–march=v10</b> | <b>–march=v32</b> | <b>–march=common_v10_v32</b>] + +<em>Target C-SKY options:</em> + [<b>-march=<var>arch</var></b>] [<b>-mcpu=<var>cpu</var></b>] + [<b>-EL</b>] [<b>-mlittle-endian</b>] [<b>-EB</b>] [<b>-mbig-endian</b>] + [<b>-fpic</b>] [<b>-pic</b>] + [<b>-mljump</b>] [<b>-mno-ljump</b>] + [<b>-force2bsr</b>] [<b>-mforce2bsr</b>] [<b>-no-force2bsr</b>] [<b>-mno-force2bsr</b>] + [<b>-jsri2bsr</b>] [<b>-mjsri2bsr</b>] [<b>-no-jsri2bsr </b>] [<b>-mno-jsri2bsr</b>] + [<b>-mnolrw </b>] [<b>-mno-lrw</b>] + [<b>-melrw</b>] [<b>-mno-elrw</b>] + [<b>-mlaf </b>] [<b>-mliterals-after-func</b>] + [<b>-mno-laf</b>] [<b>-mno-literals-after-func</b>] + [<b>-mlabr</b>] [<b>-mliterals-after-br</b>] + [<b>-mno-labr</b>] [<b>-mnoliterals-after-br</b>] + [<b>-mistack</b>] [<b>-mno-istack</b>] + [<b>-mhard-float</b>] [<b>-mmp</b>] [<b>-mcp</b>] [<b>-mcache</b>] + [<b>-msecurity</b>] [<b>-mtrust</b>] + [<b>-mdsp</b>] [<b>-medsp</b>] [<b>-mvdsp</b>] + +<em>Target D10V options:</em> + [<b>-O</b>] + +<em>Target D30V options:</em> + [<b>-O</b>|<b>-n</b>|<b>-N</b>] + +<em>Target EPIPHANY options:</em> + [<b>-mepiphany</b>|<b>-mepiphany16</b>] + +<em>Target H8/300 options:</em> + [-h-tick-hex] + +<em>Target i386 options:</em> + [<b>–32</b>|<b>–x32</b>|<b>–64</b>] [<b>-n</b>] + [<b>-march</b>=<var>CPU</var>[+<var>EXTENSION</var>…]] [<b>-mtune</b>=<var>CPU</var>] + +<em>Target IA-64 options:</em> + [<b>-mconstant-gp</b>|<b>-mauto-pic</b>] + [<b>-milp32</b>|<b>-milp64</b>|<b>-mlp64</b>|<b>-mp64</b>] + [<b>-mle</b>|<b>mbe</b>] + [<b>-mtune=itanium1</b>|<b>-mtune=itanium2</b>] + [<b>-munwind-check=warning</b>|<b>-munwind-check=error</b>] + [<b>-mhint.b=ok</b>|<b>-mhint.b=warning</b>|<b>-mhint.b=error</b>] + [<b>-x</b>|<b>-xexplicit</b>] [<b>-xauto</b>] [<b>-xdebug</b>] + +<em>Target IP2K options:</em> + [<b>-mip2022</b>|<b>-mip2022ext</b>] + +<em>Target M32C options:</em> + [<b>-m32c</b>|<b>-m16c</b>] [-relax] [-h-tick-hex] + +<em>Target M32R options:</em> + [<b>–m32rx</b>|<b>–[no-]warn-explicit-parallel-conflicts</b>| + <b>–W[n]p</b>] + +<em>Target M680X0 options:</em> + [<b>-l</b>] [<b>-m68000</b>|<b>-m68010</b>|<b>-m68020</b>|…] + +<em>Target M68HC11 options:</em> + [<b>-m68hc11</b>|<b>-m68hc12</b>|<b>-m68hcs12</b>|<b>-mm9s12x</b>|<b>-mm9s12xg</b>] + [<b>-mshort</b>|<b>-mlong</b>] + [<b>-mshort-double</b>|<b>-mlong-double</b>] + [<b>–force-long-branches</b>] [<b>–short-branches</b>] + [<b>–strict-direct-mode</b>] [<b>–print-insn-syntax</b>] + [<b>–print-opcodes</b>] [<b>–generate-example</b>] + +<em>Target MCORE options:</em> + [<b>-jsri2bsr</b>] [<b>-sifilter</b>] [<b>-relax</b>] + [<b>-mcpu=[210|340]</b>] + +<em>Target Meta options:</em> + [<b>-mcpu=<var>cpu</var></b>] [<b>-mfpu=<var>cpu</var></b>] [<b>-mdsp=<var>cpu</var></b>] +<em>Target MICROBLAZE options:</em> + +<em>Target MIPS options:</em> + [<b>-nocpp</b>] [<b>-EL</b>] [<b>-EB</b>] [<b>-O</b>[<var>optimization level</var>]] + [<b>-g</b>[<var>debug level</var>]] [<b>-G</b> <var>num</var>] [<b>-KPIC</b>] [<b>-call_shared</b>] + [<b>-non_shared</b>] [<b>-xgot</b> [<b>-mvxworks-pic</b>] + [<b>-mabi</b>=<var>ABI</var>] [<b>-32</b>] [<b>-n32</b>] [<b>-64</b>] [<b>-mfp32</b>] [<b>-mgp32</b>] + [<b>-mfp64</b>] [<b>-mgp64</b>] [<b>-mfpxx</b>] + [<b>-modd-spreg</b>] [<b>-mno-odd-spreg</b>] + [<b>-march</b>=<var>CPU</var>] [<b>-mtune</b>=<var>CPU</var>] [<b>-mips1</b>] [<b>-mips2</b>] + [<b>-mips3</b>] [<b>-mips4</b>] [<b>-mips5</b>] [<b>-mips32</b>] [<b>-mips32r2</b>] + [<b>-mips32r3</b>] [<b>-mips32r5</b>] [<b>-mips32r6</b>] [<b>-mips64</b>] [<b>-mips64r2</b>] + [<b>-mips64r3</b>] [<b>-mips64r5</b>] [<b>-mips64r6</b>] + [<b>-construct-floats</b>] [<b>-no-construct-floats</b>] + [<b>-mignore-branch-isa</b>] [<b>-mno-ignore-branch-isa</b>] + [<b>-mnan=<var>encoding</var></b>] + [<b>-trap</b>] [<b>-no-break</b>] [<b>-break</b>] [<b>-no-trap</b>] + [<b>-mips16</b>] [<b>-no-mips16</b>] + [<b>-mmips16e2</b>] [<b>-mno-mips16e2</b>] + [<b>-mmicromips</b>] [<b>-mno-micromips</b>] + [<b>-msmartmips</b>] [<b>-mno-smartmips</b>] + [<b>-mips3d</b>] [<b>-no-mips3d</b>] + [<b>-mdmx</b>] [<b>-no-mdmx</b>] + [<b>-mdsp</b>] [<b>-mno-dsp</b>] + [<b>-mdspr2</b>] [<b>-mno-dspr2</b>] + [<b>-mdspr3</b>] [<b>-mno-dspr3</b>] + [<b>-mmsa</b>] [<b>-mno-msa</b>] + [<b>-mxpa</b>] [<b>-mno-xpa</b>] + [<b>-mmt</b>] [<b>-mno-mt</b>] + [<b>-mmcu</b>] [<b>-mno-mcu</b>] + [<b>-mcrc</b>] [<b>-mno-crc</b>] + [<b>-mginv</b>] [<b>-mno-ginv</b>] + [<b>-mloongson-mmi</b>] [<b>-mno-loongson-mmi</b>] + [<b>-mloongson-cam</b>] [<b>-mno-loongson-cam</b>] + [<b>-mloongson-ext</b>] [<b>-mno-loongson-ext</b>] + [<b>-mloongson-ext2</b>] [<b>-mno-loongson-ext2</b>] + [<b>-minsn32</b>] [<b>-mno-insn32</b>] + [<b>-mfix7000</b>] [<b>-mno-fix7000</b>] + [<b>-mfix-rm7000</b>] [<b>-mno-fix-rm7000</b>] + [<b>-mfix-vr4120</b>] [<b>-mno-fix-vr4120</b>] + [<b>-mfix-vr4130</b>] [<b>-mno-fix-vr4130</b>] + [<b>-mfix-r5900</b>] [<b>-mno-fix-r5900</b>] + [<b>-mdebug</b>] [<b>-no-mdebug</b>] + [<b>-mpdr</b>] [<b>-mno-pdr</b>] + +<em>Target MMIX options:</em> + [<b>–fixed-special-register-names</b>] [<b>–globalize-symbols</b>] + [<b>–gnu-syntax</b>] [<b>–relax</b>] [<b>–no-predefined-symbols</b>] + [<b>–no-expand</b>] [<b>–no-merge-gregs</b>] [<b>-x</b>] + [<b>–linker-allocated-gregs</b>] + +<em>Target Nios II options:</em> + [<b>-relax-all</b>] [<b>-relax-section</b>] [<b>-no-relax</b>] + [<b>-EB</b>] [<b>-EL</b>] + +<em>Target NDS32 options:</em> + [<b>-EL</b>] [<b>-EB</b>] [<b>-O</b>] [<b>-Os</b>] [<b>-mcpu=<var>cpu</var></b>] + [<b>-misa=<var>isa</var></b>] [<b>-mabi=<var>abi</var></b>] [<b>-mall-ext</b>] + [<b>-m[no-]16-bit</b>] [<b>-m[no-]perf-ext</b>] [<b>-m[no-]perf2-ext</b>] + [<b>-m[no-]string-ext</b>] [<b>-m[no-]dsp-ext</b>] [<b>-m[no-]mac</b>] [<b>-m[no-]div</b>] + [<b>-m[no-]audio-isa-ext</b>] [<b>-m[no-]fpu-sp-ext</b>] [<b>-m[no-]fpu-dp-ext</b>] + [<b>-m[no-]fpu-fma</b>] [<b>-mfpu-freg=<var>FREG</var></b>] [<b>-mreduced-regs</b>] + [<b>-mfull-regs</b>] [<b>-m[no-]dx-regs</b>] [<b>-mpic</b>] [<b>-mno-relax</b>] + [<b>-mb2bb</b>] + +<em>Target PDP11 options:</em> + [<b>-mpic</b>|<b>-mno-pic</b>] [<b>-mall</b>] [<b>-mno-extensions</b>] + [<b>-m</b><var>extension</var>|<b>-mno-</b><var>extension</var>] + [<b>-m</b><var>cpu</var>] [<b>-m</b><var>machine</var>] + +<em>Target picoJava options:</em> + [<b>-mb</b>|<b>-me</b>] + +<em>Target PowerPC options:</em> + [<b>-a32</b>|<b>-a64</b>] + [<b>-mpwrx</b>|<b>-mpwr2</b>|<b>-mpwr</b>|<b>-m601</b>|<b>-mppc</b>|<b>-mppc32</b>|<b>-m603</b>|<b>-m604</b>|<b>-m403</b>|<b>-m405</b>| + <b>-m440</b>|<b>-m464</b>|<b>-m476</b>|<b>-m7400</b>|<b>-m7410</b>|<b>-m7450</b>|<b>-m7455</b>|<b>-m750cl</b>|<b>-mgekko</b>| + <b>-mbroadway</b>|<b>-mppc64</b>|<b>-m620</b>|<b>-me500</b>|<b>-e500x2</b>|<b>-me500mc</b>|<b>-me500mc64</b>|<b>-me5500</b>| + <b>-me6500</b>|<b>-mppc64bridge</b>|<b>-mbooke</b>|<b>-mpower4</b>|<b>-mpwr4</b>|<b>-mpower5</b>|<b>-mpwr5</b>|<b>-mpwr5x</b>| + <b>-mpower6</b>|<b>-mpwr6</b>|<b>-mpower7</b>|<b>-mpwr7</b>|<b>-mpower8</b>|<b>-mpwr8</b>|<b>-mpower9</b>|<b>-mpwr9</b><b>-ma2</b>| + <b>-mcell</b>|<b>-mspe</b>|<b>-mspe2</b>|<b>-mtitan</b>|<b>-me300</b>|<b>-mcom</b>] + [<b>-many</b>] [<b>-maltivec</b>|<b>-mvsx</b>|<b>-mhtm</b>|<b>-mvle</b>] + [<b>-mregnames</b>|<b>-mno-regnames</b>] + [<b>-mrelocatable</b>|<b>-mrelocatable-lib</b>|<b>-K PIC</b>] [<b>-memb</b>] + [<b>-mlittle</b>|<b>-mlittle-endian</b>|<b>-le</b>|<b>-mbig</b>|<b>-mbig-endian</b>|<b>-be</b>] + [<b>-msolaris</b>|<b>-mno-solaris</b>] + [<b>-nops=<var>count</var></b>] + +<em>Target PRU options:</em> + [<b>-link-relax</b>] + [<b>-mnolink-relax</b>] + [<b>-mno-warn-regname-label</b>] + +<em>Target RISC-V options:</em> + [<b>-fpic</b>|<b>-fPIC</b>|<b>-fno-pic</b>] + [<b>-march</b>=<var>ISA</var>] + [<b>-mabi</b>=<var>ABI</var>] + [<b>-mlittle-endian</b>|<b>-mbig-endian</b>] + +<em>Target RL78 options:</em> + [<b>-mg10</b>] + [<b>-m32bit-doubles</b>|<b>-m64bit-doubles</b>] + +<em>Target RX options:</em> + [<b>-mlittle-endian</b>|<b>-mbig-endian</b>] + [<b>-m32bit-doubles</b>|<b>-m64bit-doubles</b>] + [<b>-muse-conventional-section-names</b>] + [<b>-msmall-data-limit</b>] + [<b>-mpid</b>] + [<b>-mrelax</b>] + [<b>-mint-register=<var>number</var></b>] + [<b>-mgcc-abi</b>|<b>-mrx-abi</b>] + +<em>Target s390 options:</em> + [<b>-m31</b>|<b>-m64</b>] [<b>-mesa</b>|<b>-mzarch</b>] [<b>-march</b>=<var>CPU</var>] + [<b>-mregnames</b>|<b>-mno-regnames</b>] + [<b>-mwarn-areg-zero</b>] + +<em>Target SCORE options:</em> + [<b>-EB</b>][<b>-EL</b>][<b>-FIXDD</b>][<b>-NWARN</b>] + [<b>-SCORE5</b>][<b>-SCORE5U</b>][<b>-SCORE7</b>][<b>-SCORE3</b>] + [<b>-march=score7</b>][<b>-march=score3</b>] + [<b>-USE_R1</b>][<b>-KPIC</b>][<b>-O0</b>][<b>-G</b> <var>num</var>][<b>-V</b>] + +<em>Target SPARC options:</em> + [<b>-Av6</b>|<b>-Av7</b>|<b>-Av8</b>|<b>-Aleon</b>|<b>-Asparclet</b>|<b>-Asparclite</b> + <b>-Av8plus</b>|<b>-Av8plusa</b>|<b>-Av8plusb</b>|<b>-Av8plusc</b>|<b>-Av8plusd</b> + <b>-Av8plusv</b>|<b>-Av8plusm</b>|<b>-Av9</b>|<b>-Av9a</b>|<b>-Av9b</b>|<b>-Av9c</b> + <b>-Av9d</b>|<b>-Av9e</b>|<b>-Av9v</b>|<b>-Av9m</b>|<b>-Asparc</b>|<b>-Asparcvis</b> + <b>-Asparcvis2</b>|<b>-Asparcfmaf</b>|<b>-Asparcima</b>|<b>-Asparcvis3</b> + <b>-Asparcvisr</b>|<b>-Asparc5</b>] + [<b>-xarch=v8plus</b>|<b>-xarch=v8plusa</b>]|<b>-xarch=v8plusb</b>|<b>-xarch=v8plusc</b> + <b>-xarch=v8plusd</b>|<b>-xarch=v8plusv</b>|<b>-xarch=v8plusm</b>|<b>-xarch=v9</b> + <b>-xarch=v9a</b>|<b>-xarch=v9b</b>|<b>-xarch=v9c</b>|<b>-xarch=v9d</b>|<b>-xarch=v9e</b> + <b>-xarch=v9v</b>|<b>-xarch=v9m</b>|<b>-xarch=sparc</b>|<b>-xarch=sparcvis</b> + <b>-xarch=sparcvis2</b>|<b>-xarch=sparcfmaf</b>|<b>-xarch=sparcima</b> + <b>-xarch=sparcvis3</b>|<b>-xarch=sparcvisr</b>|<b>-xarch=sparc5</b> + <b>-bump</b>] + [<b>-32</b>|<b>-64</b>] + [<b>–enforce-aligned-data</b>][<b>–dcti-couples-detect</b>] + +<em>Target TIC54X options:</em> + [<b>-mcpu=54[123589]</b>|<b>-mcpu=54[56]lp</b>] [<b>-mfar-mode</b>|<b>-mf</b>] + [<b>-merrors-to-file</b> <var><filename></var>|<b>-me</b> <var><filename></var>] + +<em>Target TIC6X options:</em> + [<b>-march=<var>arch</var></b>] [<b>-mbig-endian</b>|<b>-mlittle-endian</b>] + [<b>-mdsbt</b>|<b>-mno-dsbt</b>] [<b>-mpid=no</b>|<b>-mpid=near</b>|<b>-mpid=far</b>] + [<b>-mpic</b>|<b>-mno-pic</b>] + +<em>Target TILE-Gx options:</em> + [<b>-m32</b>|<b>-m64</b>][<b>-EB</b>][<b>-EL</b>] + +<em>Target Visium options:</em> + [<b>-mtune=<var>arch</var></b>] + +<em>Target Xtensa options:</em> + [<b>–[no-]text-section-literals</b>] [<b>–[no-]auto-litpools</b>] + [<b>–[no-]absolute-literals</b>] + [<b>–[no-]target-align</b>] [<b>–[no-]longcalls</b>] + [<b>–[no-]transform</b>] + [<b>–rename-section</b> <var>oldname</var>=<var>newname</var>] + [<b>–[no-]trampolines</b>] + [<b>–abi-windowed</b>|<b>–abi-call0</b>] + +<em>Target Z80 options:</em> + [<b>-march=<var>CPU</var><var>[-EXT]</var><var>[+EXT]</var></b>] + [<b>-local-prefix=</b><var>PREFIX</var>] + [<b>-colonless</b>] + [<b>-sdcc</b>] + [<b>-fp-s=</b><var>FORMAT</var>] + [<b>-fp-d=</b><var>FORMAT</var>] + + +</pre></div> + + +<dl compact="compact"> +<dt><code>@<var>file</var></code></dt> +<dd><p>Read command-line options from <var>file</var>. The options read are +inserted in place of the original @<var>file</var> option. If <var>file</var> +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +</p> +<p>Options in <var>file</var> are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The <var>file</var> may itself contain additional +@<var>file</var> options; any such options will be processed recursively. +</p> +</dd> +<dt><code>-a[cdghlmns]</code></dt> +<dd><p>Turn on listings, in any of a variety of ways: +</p> +<dl compact="compact"> +<dt><code>-ac</code></dt> +<dd><p>omit false conditionals +</p> +</dd> +<dt><code>-ad</code></dt> +<dd><p>omit debugging directives +</p> +</dd> +<dt><code>-ag</code></dt> +<dd><p>include general information, like as version and options passed +</p> +</dd> +<dt><code>-ah</code></dt> +<dd><p>include high-level source +</p> +</dd> +<dt><code>-al</code></dt> +<dd><p>include assembly +</p> +</dd> +<dt><code>-am</code></dt> +<dd><p>include macro expansions +</p> +</dd> +<dt><code>-an</code></dt> +<dd><p>omit forms processing +</p> +</dd> +<dt><code>-as</code></dt> +<dd><p>include symbols +</p> +</dd> +<dt><code>=file</code></dt> +<dd><p>set the name of the listing file +</p></dd> +</dl> + +<p>You may combine these options; for example, use ‘<samp>-aln</samp>’ for assembly +listing without forms processing. The ‘<samp>=file</samp>’ option, if used, must be +the last one. By itself, ‘<samp>-a</samp>’ defaults to ‘<samp>-ahls</samp>’. +</p> +</dd> +<dt><code>--alternate</code></dt> +<dd><p>Begin in alternate macro mode. +See <a href="#Altmacro"><code>.altmacro</code></a>. +</p> +</dd> +<dt><code>--compress-debug-sections</code></dt> +<dd><p>Compress DWARF debug sections using zlib with SHF_COMPRESSED from the +ELF ABI. The resulting object file may not be compatible with older +linkers and object file utilities. Note if compression would make a +given section <em>larger</em> then it is not compressed. +</p> +<a name="index-_002d_002dcompress_002ddebug_002dsections_003d-option"></a> +</dd> +<dt><code>--compress-debug-sections=none</code></dt> +<dt><code>--compress-debug-sections=zlib</code></dt> +<dt><code>--compress-debug-sections=zlib-gnu</code></dt> +<dt><code>--compress-debug-sections=zlib-gabi</code></dt> +<dt><code>--compress-debug-sections=zstd</code></dt> +<dd><p>These options control how DWARF debug sections are compressed. +<samp>--compress-debug-sections=none</samp> is equivalent to +<samp>--nocompress-debug-sections</samp>. +<samp>--compress-debug-sections=zlib</samp> and +<samp>--compress-debug-sections=zlib-gabi</samp> are equivalent to +<samp>--compress-debug-sections</samp>. +<samp>--compress-debug-sections=zlib-gnu</samp> compresses DWARF debug sections +using the obsoleted zlib-gnu format. The debug sections are renamed to begin +with ‘<samp>.zdebug</samp>’. +<samp>--compress-debug-sections=zstd</samp> compresses DWARF debug +sections using zstd. Note - if compression would actually make a section +<em>larger</em>, then it is not compressed nor renamed. +</p> + +</dd> +<dt><code>--nocompress-debug-sections</code></dt> +<dd><p>Do not compress DWARF debug sections. This is usually the default for all +targets except the x86/x86_64, but a configure time option can be used to +override this. +</p> +</dd> +<dt><code>-D</code></dt> +<dd><p>Enable denugging in target specific backends, if supported. Otherwise ignored. +Even if ignored, this option is accepted for script compatibility with calls to +other assemblers. +</p> +</dd> +<dt><code>--debug-prefix-map <var>old</var>=<var>new</var></code></dt> +<dd><p>When assembling files in directory <samp><var>old</var></samp>, record debugging +information describing them as in <samp><var>new</var></samp> instead. +</p> +</dd> +<dt><code>--defsym <var>sym</var>=<var>value</var></code></dt> +<dd><p>Define the symbol <var>sym</var> to be <var>value</var> before assembling the input file. +<var>value</var> must be an integer constant. As in C, a leading ‘<samp>0x</samp>’ +indicates a hexadecimal value, and a leading ‘<samp>0</samp>’ indicates an octal +value. The value of the symbol can be overridden inside a source file via the +use of a <code>.set</code> pseudo-op. +</p> +</dd> +<dt><code>--dump-config</code></dt> +<dd><p>Displays how the assembler is configured and then exits. +</p> +</dd> +<dt><code>--elf-stt-common=no</code></dt> +<dt><code>--elf-stt-common=yes</code></dt> +<dd><p>These options control whether the ELF assembler should generate common +symbols with the <code>STT_COMMON</code> type. The default can be controlled +by a configure option <samp>--enable-elf-stt-common</samp>. +</p> +</dd> +<dt><code>--emulation=<var>name</var></code></dt> +<dd><p>If the assembler is configured to support multiple different target +configurations then this option can be used to select the desired form. +</p> +</dd> +<dt><code>-f</code></dt> +<dd><p>“fast”—skip whitespace and comment preprocessing (assume source is +compiler output). +</p> +</dd> +<dt><code>-g</code></dt> +<dt><code>--gen-debug</code></dt> +<dd><p>Generate debugging information for each assembler source line using whichever +debug format is preferred by the target. This currently means either STABS, +ECOFF or DWARF2. When the debug format is DWARF then a <code>.debug_info</code> and +<code>.debug_line</code> section is only emitted when the assembly file doesn’t +generate one itself. +</p> +</dd> +<dt><code>--gstabs</code></dt> +<dd><p>Generate stabs debugging information for each assembler line. This +may help debugging assembler code, if the debugger can handle it. +</p> +</dd> +<dt><code>--gstabs+</code></dt> +<dd><p>Generate stabs debugging information for each assembler line, with GNU +extensions that probably only gdb can handle, and that could make other +debuggers crash or refuse to read your program. This +may help debugging assembler code. Currently the only GNU extension is +the location of the current working directory at assembling time. +</p> +</dd> +<dt><code>--gdwarf-2</code></dt> +<dd><p>Generate DWARF2 debugging information for each assembler line. This +may help debugging assembler code, if the debugger can handle it. Note—this +option is only supported by some targets, not all of them. +</p> +</dd> +<dt><code>--gdwarf-3</code></dt> +<dd><p>This option is the same as the <samp>--gdwarf-2</samp> option, except that it +allows for the possibility of the generation of extra debug information as per +version 3 of the DWARF specification. Note - enabling this option does not +guarantee the generation of any extra information, the choice to do so is on a +per target basis. +</p> +</dd> +<dt><code>--gdwarf-4</code></dt> +<dd><p>This option is the same as the <samp>--gdwarf-2</samp> option, except that it +allows for the possibility of the generation of extra debug information as per +version 4 of the DWARF specification. Note - enabling this option does not +guarantee the generation of any extra information, the choice to do so is on a +per target basis. +</p> +</dd> +<dt><code>--gdwarf-5</code></dt> +<dd><p>This option is the same as the <samp>--gdwarf-2</samp> option, except that it +allows for the possibility of the generation of extra debug information as per +version 5 of the DWARF specification. Note - enabling this option does not +guarantee the generation of any extra information, the choice to do so is on a +per target basis. +</p> +</dd> +<dt><code>--gdwarf-sections</code></dt> +<dd><p>Instead of creating a .debug_line section, create a series of +.debug_line.<var>foo</var> sections where <var>foo</var> is the name of the +corresponding code section. For example a code section called <var>.text.func</var> +will have its dwarf line number information placed into a section called +<var>.debug_line.text.func</var>. If the code section is just called <var>.text</var> +then debug line section will still be called just <var>.debug_line</var> without any +suffix. +</p> +</dd> +<dt><code>--gdwarf-cie-version=<var>version</var></code></dt> +<dd><p>Control which version of DWARF Common Information Entries (CIEs) are produced. +When this flag is not specificed the default is version 1, though some targets +can modify this default. Other possible values for <var>version</var> are 3 or 4. +</p> +</dd> +<dt><code>--generate-missing-build-notes=yes</code></dt> +<dt><code>--generate-missing-build-notes=no</code></dt> +<dd><p>These options control whether the ELF assembler should generate GNU Build +attribute notes if none are present in the input sources. +The default can be controlled by the <samp>--enable-generate-build-notes</samp> +configure option. +</p> +</dd> +<dt><code>--gsframe</code></dt> +<dt><code>--gsframe</code></dt> +<dd><p>Create <var>.sframe</var> section from CFI directives. +</p> + +</dd> +<dt><code>--hash-size <var>N</var></code></dt> +<dd><p>Ignored. Supported for command line compatibility with other assemblers. +</p> +</dd> +<dt><code>--help</code></dt> +<dd><p>Print a summary of the command-line options and exit. +</p> +</dd> +<dt><code>--target-help</code></dt> +<dd><p>Print a summary of all target specific options and exit. +</p> +</dd> +<dt><code>-I <var>dir</var></code></dt> +<dd><p>Add directory <var>dir</var> to the search list for <code>.include</code> directives. +</p> +</dd> +<dt><code>-J</code></dt> +<dd><p>Don’t warn about signed overflow. +</p> +</dd> +<dt><code>-K</code></dt> +<dd><p>Issue warnings when difference tables altered for long displacements. +</p> +</dd> +<dt><code>-L</code></dt> +<dt><code>--keep-locals</code></dt> +<dd><p>Keep (in the symbol table) local symbols. These symbols start with +system-specific local label prefixes, typically ‘<samp>.L</samp>’ for ELF systems +or ‘<samp>L</samp>’ for traditional a.out systems. +See <a href="#Symbol-Names">Symbol Names</a>. +</p> +</dd> +<dt><code>--listing-lhs-width=<var>number</var></code></dt> +<dd><p>Set the maximum width, in words, of the output data column for an assembler +listing to <var>number</var>. +</p> +</dd> +<dt><code>--listing-lhs-width2=<var>number</var></code></dt> +<dd><p>Set the maximum width, in words, of the output data column for continuation +lines in an assembler listing to <var>number</var>. +</p> +</dd> +<dt><code>--listing-rhs-width=<var>number</var></code></dt> +<dd><p>Set the maximum width of an input source line, as displayed in a listing, to +<var>number</var> bytes. +</p> +</dd> +<dt><code>--listing-cont-lines=<var>number</var></code></dt> +<dd><p>Set the maximum number of lines printed in a listing for a single line of input +to <var>number</var> + 1. +</p> +</dd> +<dt><code>--multibyte-handling=allow</code></dt> +<dt><code>--multibyte-handling=warn</code></dt> +<dt><code>--multibyte-handling=warn-sym-only</code></dt> +<dt><code>--multibyte-handling=warn_sym_only</code></dt> +<dd><p>Controls how the assembler handles multibyte characters in the input. The +default (which can be restored by using the <samp>allow</samp> argument) is to +allow such characters without complaint. Using the <samp>warn</samp> argument will +make the assembler generate a warning message whenever any multibyte character +is encountered. Using the <samp>warn-sym-only</samp> argument will only cause a +warning to be generated when a symbol is defined with a name that contains +multibyte characters. (References to undefined symbols will not generate a +warning). +</p> +</dd> +<dt><code>--no-pad-sections</code></dt> +<dd><p>Stop the assembler for padding the ends of output sections to the alignment +of that section. The default is to pad the sections, but this can waste space +which might be needed on targets which have tight memory constraints. +</p> +</dd> +<dt><code>-o <var>objfile</var></code></dt> +<dd><p>Name the object-file output from <code>as</code> <var>objfile</var>. +</p> +</dd> +<dt><code>-R</code></dt> +<dd><p>Fold the data section into the text section. +</p> +</dd> +<dt><code>--reduce-memory-overheads</code></dt> +<dd><p>Ignored. Supported for compatibility with tools that apss the same option to +both the assembler and the linker. +</p> +</dd> +<dt><code>--sectname-subst</code></dt> +<dd><p>Honor substitution sequences in section names. +See <a href="#Section-Name-Substitutions"><code>.section <var>name</var></code></a>. +</p> +</dd> +<dt><code>--size-check=error</code></dt> +<dt><code>--size-check=warning</code></dt> +<dd><p>Issue an error or warning for invalid ELF .size directive. +</p> +</dd> +<dt><code>--statistics</code></dt> +<dd><p>Print the maximum space (in bytes) and total time (in seconds) used by +assembly. +</p> +</dd> +<dt><code>--strip-local-absolute</code></dt> +<dd><p>Remove local absolute symbols from the outgoing symbol table. +</p> +</dd> +<dt><code>-v</code></dt> +<dt><code>-version</code></dt> +<dd><p>Print the <code>as</code> version. +</p> +</dd> +<dt><code>--version</code></dt> +<dd><p>Print the <code>as</code> version and exit. +</p> +</dd> +<dt><code>-W</code></dt> +<dt><code>--no-warn</code></dt> +<dd><p>Suppress warning messages. +</p> +</dd> +<dt><code>--fatal-warnings</code></dt> +<dd><p>Treat warnings as errors. +</p> +</dd> +<dt><code>--warn</code></dt> +<dd><p>Don’t suppress warning messages or treat them as errors. +</p> +</dd> +<dt><code>-w</code></dt> +<dd><p>Ignored. +</p> +</dd> +<dt><code>-x</code></dt> +<dd><p>Ignored. +</p> +</dd> +<dt><code>-Z</code></dt> +<dd><p>Generate an object file even after errors. +</p> +</dd> +<dt><code>-- | <var>files</var> …</code></dt> +<dd><p>Standard input, or source files to assemble. +</p> +</dd> +</dl> + + +<p>See <a href="#AArch64-Options">AArch64 Options</a>, for the options available when as is configured +for the 64-bit mode of the ARM Architecture (AArch64). +</p> + + + +<p>See <a href="#Alpha-Options">Alpha Options</a>, for the options available when as is configured +for an Alpha processor. +</p> + + +<p>The following options are available when as is configured for an ARC +processor. +</p> +<dl compact="compact"> +<dt><code>-mcpu=<var>cpu</var></code></dt> +<dd><p>This option selects the core processor variant. +</p></dd> +<dt><code>-EB | -EL</code></dt> +<dd><p>Select either big-endian (-EB) or little-endian (-EL) output. +</p></dd> +<dt><code>-mcode-density</code></dt> +<dd><p>Enable Code Density extension instructions. +</p></dd> +</dl> + +<p>The following options are available when as is configured for the ARM +processor family. +</p> +<dl compact="compact"> +<dt><code>-mcpu=<var>processor</var>[+<var>extension</var>…]</code></dt> +<dd><p>Specify which ARM processor variant is the target. +</p></dd> +<dt><code>-march=<var>architecture</var>[+<var>extension</var>…]</code></dt> +<dd><p>Specify which ARM architecture variant is used by the target. +</p></dd> +<dt><code>-mfpu=<var>floating-point-format</var></code></dt> +<dd><p>Select which Floating Point architecture is the target. +</p></dd> +<dt><code>-mfloat-abi=<var>abi</var></code></dt> +<dd><p>Select which floating point ABI is in use. +</p></dd> +<dt><code>-mthumb</code></dt> +<dd><p>Enable Thumb only instruction decoding. +</p></dd> +<dt><code>-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant</code></dt> +<dd><p>Select which procedure calling convention is in use. +</p></dd> +<dt><code>-EB | -EL</code></dt> +<dd><p>Select either big-endian (-EB) or little-endian (-EL) output. +</p></dd> +<dt><code>-mthumb-interwork</code></dt> +<dd><p>Specify that the code has been generated with interworking between Thumb and +ARM code in mind. +</p></dd> +<dt><code>-mccs</code></dt> +<dd><p>Turns on CodeComposer Studio assembly syntax compatibility mode. +</p></dd> +<dt><code>-k</code></dt> +<dd><p>Specify that PIC code has been generated. +</p></dd> +</dl> + + +<p>See <a href="#Blackfin-Options">Blackfin Options</a>, for the options available when as is +configured for the Blackfin processor family. +</p> + + + +<p>See <a href="#BPF-Options">BPF Options</a>, for the options available when as is +configured for the Linux kernel BPF processor family. +</p> + + +<p>See the info pages for documentation of the CRIS-specific options. +</p> + +<p>See <a href="#C_002dSKY-Options">C-SKY Options</a>, for the options available when as is +configured for the C-SKY processor family. +</p> + + +<p>The following options are available when as is configured for +a D10V processor. +</p><dl compact="compact"> +<dd><a name="index-D10V-optimization"></a> +<a name="index-optimization_002c-D10V"></a> +</dd> +<dt><code>-O</code></dt> +<dd><p>Optimize output by parallelizing instructions. +</p></dd> +</dl> + +<p>The following options are available when as is configured for a D30V +processor. +</p><dl compact="compact"> +<dd><a name="index-D30V-optimization"></a> +<a name="index-optimization_002c-D30V"></a> +</dd> +<dt><code>-O</code></dt> +<dd><p>Optimize output by parallelizing instructions. +</p> +<a name="index-D30V-nops"></a> +</dd> +<dt><code>-n</code></dt> +<dd><p>Warn when nops are generated. +</p> +<a name="index-D30V-nops-after-32_002dbit-multiply"></a> +</dd> +<dt><code>-N</code></dt> +<dd><p>Warn when a nop after a 32-bit multiply instruction is generated. +</p></dd> +</dl> + +<p>The following options are available when as is configured for the +Adapteva EPIPHANY series. +</p> +<p>See <a href="#Epiphany-Options">Epiphany Options</a>, for the options available when as is +configured for an Epiphany processor. +</p> + + + + +<p>See <a href="#i386_002dOptions">i386-Options</a>, for the options available when as is +configured for an i386 processor. +</p> + + +<p>The following options are available when as is configured for the +Ubicom IP2K series. +</p> +<dl compact="compact"> +<dt><code>-mip2022ext</code></dt> +<dd><p>Specifies that the extended IP2022 instructions are allowed. +</p> +</dd> +<dt><code>-mip2022</code></dt> +<dd><p>Restores the default behaviour, which restricts the permitted instructions to +just the basic IP2022 ones. +</p> +</dd> +</dl> + +<p>The following options are available when as is configured for the +Renesas M32C and M16C processors. +</p> +<dl compact="compact"> +<dt><code>-m32c</code></dt> +<dd><p>Assemble M32C instructions. +</p> +</dd> +<dt><code>-m16c</code></dt> +<dd><p>Assemble M16C instructions (the default). +</p> +</dd> +<dt><code>-relax</code></dt> +<dd><p>Enable support for link-time relaxations. +</p> +</dd> +<dt><code>-h-tick-hex</code></dt> +<dd><p>Support H’00 style hex constants in addition to 0x00 style. +</p> +</dd> +</dl> + +<p>The following options are available when as is configured for the +Renesas M32R (formerly Mitsubishi M32R) series. +</p> +<dl compact="compact"> +<dt><code>--m32rx</code></dt> +<dd><p>Specify which processor in the M32R family is the target. The default +is normally the M32R, but this option changes it to the M32RX. +</p> +</dd> +<dt><code>--warn-explicit-parallel-conflicts or --Wp</code></dt> +<dd><p>Produce warning messages when questionable parallel constructs are +encountered. +</p> +</dd> +<dt><code>--no-warn-explicit-parallel-conflicts or --Wnp</code></dt> +<dd><p>Do not produce warning messages when questionable parallel constructs are +encountered. +</p> +</dd> +</dl> + +<p>The following options are available when as is configured for the +Motorola 68000 series. +</p> +<dl compact="compact"> +<dt><code>-l</code></dt> +<dd><p>Shorten references to undefined symbols, to one word instead of two. +</p> +</dd> +<dt><code>-m68000 | -m68008 | -m68010 | -m68020 | -m68030</code></dt> +<dt><code>| -m68040 | -m68060 | -m68302 | -m68331 | -m68332</code></dt> +<dt><code>| -m68333 | -m68340 | -mcpu32 | -m5200</code></dt> +<dd><p>Specify what processor in the 68000 family is the target. The default +is normally the 68020, but this can be changed at configuration time. +</p> +</dd> +<dt><code>-m68881 | -m68882 | -mno-68881 | -mno-68882</code></dt> +<dd><p>The target machine does (or does not) have a floating-point coprocessor. +The default is to assume a coprocessor for 68020, 68030, and cpu32. Although +the basic 68000 is not compatible with the 68881, a combination of the +two can be specified, since it’s possible to do emulation of the +coprocessor instructions with the main processor. +</p> +</dd> +<dt><code>-m68851 | -mno-68851</code></dt> +<dd><p>The target machine does (or does not) have a memory-management +unit coprocessor. The default is to assume an MMU for 68020 and up. +</p> +</dd> +</dl> + + +<p>See <a href="#Nios-II-Options">Nios II Options</a>, for the options available when as is configured +for an Altera Nios II processor. +</p> + + +<p>For details about the PDP-11 machine dependent features options, +see <a href="#PDP_002d11_002dOptions">PDP-11-Options</a>. +</p> +<dl compact="compact"> +<dt><code>-mpic | -mno-pic</code></dt> +<dd><p>Generate position-independent (or position-dependent) code. The +default is <samp>-mpic</samp>. +</p> +</dd> +<dt><code>-mall</code></dt> +<dt><code>-mall-extensions</code></dt> +<dd><p>Enable all instruction set extensions. This is the default. +</p> +</dd> +<dt><code>-mno-extensions</code></dt> +<dd><p>Disable all instruction set extensions. +</p> +</dd> +<dt><code>-m<var>extension</var> | -mno-<var>extension</var></code></dt> +<dd><p>Enable (or disable) a particular instruction set extension. +</p> +</dd> +<dt><code>-m<var>cpu</var></code></dt> +<dd><p>Enable the instruction set extensions supported by a particular CPU, and +disable all other extensions. +</p> +</dd> +<dt><code>-m<var>machine</var></code></dt> +<dd><p>Enable the instruction set extensions supported by a particular machine +model, and disable all other extensions. +</p></dd> +</dl> + + +<p>The following options are available when as is configured for +a picoJava processor. +</p> +<dl compact="compact"> +<dd> +<a name="index-PJ-endianness"></a> +<a name="index-endianness_002c-PJ"></a> +<a name="index-big-endian-output_002c-PJ"></a> +</dd> +<dt><code>-mb</code></dt> +<dd><p>Generate “big endian” format output. +</p> +<a name="index-little-endian-output_002c-PJ"></a> +</dd> +<dt><code>-ml</code></dt> +<dd><p>Generate “little endian” format output. +</p> +</dd> +</dl> + + +<p>See <a href="#PRU-Options">PRU Options</a>, for the options available when as is configured +for a PRU processor. +</p> + +<p>The following options are available when as is configured for the +Motorola 68HC11 or 68HC12 series. +</p> +<dl compact="compact"> +<dt><code>-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg</code></dt> +<dd><p>Specify what processor is the target. The default is +defined by the configuration option when building the assembler. +</p> +</dd> +<dt><code>--xgate-ramoffset</code></dt> +<dd><p>Instruct the linker to offset RAM addresses from S12X address space into +XGATE address space. +</p> +</dd> +<dt><code>-mshort</code></dt> +<dd><p>Specify to use the 16-bit integer ABI. +</p> +</dd> +<dt><code>-mlong</code></dt> +<dd><p>Specify to use the 32-bit integer ABI. +</p> +</dd> +<dt><code>-mshort-double</code></dt> +<dd><p>Specify to use the 32-bit double ABI. +</p> +</dd> +<dt><code>-mlong-double</code></dt> +<dd><p>Specify to use the 64-bit double ABI. +</p> +</dd> +<dt><code>--force-long-branches</code></dt> +<dd><p>Relative branches are turned into absolute ones. This concerns +conditional branches, unconditional branches and branches to a +sub routine. +</p> +</dd> +<dt><code>-S | --short-branches</code></dt> +<dd><p>Do not turn relative branches into absolute ones +when the offset is out of range. +</p> +</dd> +<dt><code>--strict-direct-mode</code></dt> +<dd><p>Do not turn the direct addressing mode into extended addressing mode +when the instruction does not support direct addressing mode. +</p> +</dd> +<dt><code>--print-insn-syntax</code></dt> +<dd><p>Print the syntax of instruction in case of error. +</p> +</dd> +<dt><code>--print-opcodes</code></dt> +<dd><p>Print the list of instructions with syntax and then exit. +</p> +</dd> +<dt><code>--generate-example</code></dt> +<dd><p>Print an example of instruction for each possible instruction and then exit. +This option is only useful for testing <code>as</code>. +</p> +</dd> +</dl> + +<p>The following options are available when <code>as</code> is configured +for the SPARC architecture: +</p> +<dl compact="compact"> +<dt><code>-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite</code></dt> +<dt><code>-Av8plus | -Av8plusa | -Av9 | -Av9a</code></dt> +<dd><p>Explicitly select a variant of the SPARC architecture. +</p> +<p>‘<samp>-Av8plus</samp>’ and ‘<samp>-Av8plusa</samp>’ select a 32 bit environment. +‘<samp>-Av9</samp>’ and ‘<samp>-Av9a</samp>’ select a 64 bit environment. +</p> +<p>‘<samp>-Av8plusa</samp>’ and ‘<samp>-Av9a</samp>’ enable the SPARC V9 instruction set with +UltraSPARC extensions. +</p> +</dd> +<dt><code>-xarch=v8plus | -xarch=v8plusa</code></dt> +<dd><p>For compatibility with the Solaris v9 assembler. These options are +equivalent to -Av8plus and -Av8plusa, respectively. +</p> +</dd> +<dt><code>-bump</code></dt> +<dd><p>Warn when the assembler switches to another architecture. +</p></dd> +</dl> + +<p>The following options are available when as is configured for the ’c54x +architecture. +</p> +<dl compact="compact"> +<dt><code>-mfar-mode</code></dt> +<dd><p>Enable extended addressing mode. All addresses and relocations will assume +extended addressing (usually 23 bits). +</p></dd> +<dt><code>-mcpu=<var>CPU_VERSION</var></code></dt> +<dd><p>Sets the CPU version being compiled for. +</p></dd> +<dt><code>-merrors-to-file <var>FILENAME</var></code></dt> +<dd><p>Redirect error output to a file, for broken systems which don’t support such +behaviour in the shell. +</p></dd> +</dl> + +<p>The following options are available when as is configured for +a MIPS processor. +</p> +<dl compact="compact"> +<dt><code>-G <var>num</var></code></dt> +<dd><p>This option sets the largest size of an object that can be referenced +implicitly with the <code>gp</code> register. It is only accepted for targets that +use ECOFF format, such as a DECstation running Ultrix. The default value is 8. +</p> +<a name="index-MIPS-endianness"></a> +<a name="index-endianness_002c-MIPS"></a> +<a name="index-big-endian-output_002c-MIPS"></a> +</dd> +<dt><code>-EB</code></dt> +<dd><p>Generate “big endian” format output. +</p> +<a name="index-little-endian-output_002c-MIPS"></a> +</dd> +<dt><code>-EL</code></dt> +<dd><p>Generate “little endian” format output. +</p> +<a name="index-MIPS-ISA"></a> +</dd> +<dt><code>-mips1</code></dt> +<dt><code>-mips2</code></dt> +<dt><code>-mips3</code></dt> +<dt><code>-mips4</code></dt> +<dt><code>-mips5</code></dt> +<dt><code>-mips32</code></dt> +<dt><code>-mips32r2</code></dt> +<dt><code>-mips32r3</code></dt> +<dt><code>-mips32r5</code></dt> +<dt><code>-mips32r6</code></dt> +<dt><code>-mips64</code></dt> +<dt><code>-mips64r2</code></dt> +<dt><code>-mips64r3</code></dt> +<dt><code>-mips64r5</code></dt> +<dt><code>-mips64r6</code></dt> +<dd><p>Generate code for a particular MIPS Instruction Set Architecture level. +‘<samp>-mips1</samp>’ is an alias for ‘<samp>-march=r3000</samp>’, ‘<samp>-mips2</samp>’ is an +alias for ‘<samp>-march=r6000</samp>’, ‘<samp>-mips3</samp>’ is an alias for +‘<samp>-march=r4000</samp>’ and ‘<samp>-mips4</samp>’ is an alias for ‘<samp>-march=r8000</samp>’. +‘<samp>-mips5</samp>’, ‘<samp>-mips32</samp>’, ‘<samp>-mips32r2</samp>’, ‘<samp>-mips32r3</samp>’, +‘<samp>-mips32r5</samp>’, ‘<samp>-mips32r6</samp>’, ‘<samp>-mips64</samp>’, ‘<samp>-mips64r2</samp>’, +‘<samp>-mips64r3</samp>’, ‘<samp>-mips64r5</samp>’, and ‘<samp>-mips64r6</samp>’ correspond to generic +MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 +Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and +MIPS64 Release 6 ISA processors, respectively. +</p> +</dd> +<dt><code>-march=<var>cpu</var></code></dt> +<dd><p>Generate code for a particular MIPS CPU. +</p> +</dd> +<dt><code>-mtune=<var>cpu</var></code></dt> +<dd><p>Schedule and tune for a particular MIPS CPU. +</p> +</dd> +<dt><code>-mfix7000</code></dt> +<dt><code>-mno-fix7000</code></dt> +<dd><p>Cause nops to be inserted if the read of the destination register +of an mfhi or mflo instruction occurs in the following two instructions. +</p> +</dd> +<dt><code>-mfix-rm7000</code></dt> +<dt><code>-mno-fix-rm7000</code></dt> +<dd><p>Cause nops to be inserted if a dmult or dmultu instruction is +followed by a load instruction. +</p> +</dd> +<dt><code>-mfix-r5900</code></dt> +<dt><code>-mno-fix-r5900</code></dt> +<dd><p>Do not attempt to schedule the preceding instruction into the delay slot +of a branch instruction placed at the end of a short loop of six +instructions or fewer and always schedule a <code>nop</code> instruction there +instead. The short loop bug under certain conditions causes loops to +execute only once or twice, due to a hardware bug in the R5900 chip. +</p> +</dd> +<dt><code>-mdebug</code></dt> +<dt><code>-no-mdebug</code></dt> +<dd><p>Cause stabs-style debugging output to go into an ECOFF-style .mdebug +section instead of the standard ELF .stabs sections. +</p> +</dd> +<dt><code>-mpdr</code></dt> +<dt><code>-mno-pdr</code></dt> +<dd><p>Control generation of <code>.pdr</code> sections. +</p> +</dd> +<dt><code>-mgp32</code></dt> +<dt><code>-mfp32</code></dt> +<dd><p>The register sizes are normally inferred from the ISA and ABI, but these +flags force a certain group of registers to be treated as 32 bits wide at +all times. ‘<samp>-mgp32</samp>’ controls the size of general-purpose registers +and ‘<samp>-mfp32</samp>’ controls the size of floating-point registers. +</p> +</dd> +<dt><code>-mgp64</code></dt> +<dt><code>-mfp64</code></dt> +<dd><p>The register sizes are normally inferred from the ISA and ABI, but these +flags force a certain group of registers to be treated as 64 bits wide at +all times. ‘<samp>-mgp64</samp>’ controls the size of general-purpose registers +and ‘<samp>-mfp64</samp>’ controls the size of floating-point registers. +</p> +</dd> +<dt><code>-mfpxx</code></dt> +<dd><p>The register sizes are normally inferred from the ISA and ABI, but using +this flag in combination with ‘<samp>-mabi=32</samp>’ enables an ABI variant +which will operate correctly with floating-point registers which are +32 or 64 bits wide. +</p> +</dd> +<dt><code>-modd-spreg</code></dt> +<dt><code>-mno-odd-spreg</code></dt> +<dd><p>Enable use of floating-point operations on odd-numbered single-precision +registers when supported by the ISA. ‘<samp>-mfpxx</samp>’ implies +‘<samp>-mno-odd-spreg</samp>’, otherwise the default is ‘<samp>-modd-spreg</samp>’. +</p> +</dd> +<dt><code>-mips16</code></dt> +<dt><code>-no-mips16</code></dt> +<dd><p>Generate code for the MIPS 16 processor. This is equivalent to putting +<code>.module mips16</code> at the start of the assembly file. ‘<samp>-no-mips16</samp>’ +turns off this option. +</p> +</dd> +<dt><code>-mmips16e2</code></dt> +<dt><code>-mno-mips16e2</code></dt> +<dd><p>Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent +to putting <code>.module mips16e2</code> at the start of the assembly file. +‘<samp>-mno-mips16e2</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mmicromips</code></dt> +<dt><code>-mno-micromips</code></dt> +<dd><p>Generate code for the microMIPS processor. This is equivalent to putting +<code>.module micromips</code> at the start of the assembly file. +‘<samp>-mno-micromips</samp>’ turns off this option. This is equivalent to putting +<code>.module nomicromips</code> at the start of the assembly file. +</p> +</dd> +<dt><code>-msmartmips</code></dt> +<dt><code>-mno-smartmips</code></dt> +<dd><p>Enables the SmartMIPS extension to the MIPS32 instruction set. This is +equivalent to putting <code>.module smartmips</code> at the start of the assembly +file. ‘<samp>-mno-smartmips</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mips3d</code></dt> +<dt><code>-no-mips3d</code></dt> +<dd><p>Generate code for the MIPS-3D Application Specific Extension. +This tells the assembler to accept MIPS-3D instructions. +‘<samp>-no-mips3d</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mdmx</code></dt> +<dt><code>-no-mdmx</code></dt> +<dd><p>Generate code for the MDMX Application Specific Extension. +This tells the assembler to accept MDMX instructions. +‘<samp>-no-mdmx</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mdsp</code></dt> +<dt><code>-mno-dsp</code></dt> +<dd><p>Generate code for the DSP Release 1 Application Specific Extension. +This tells the assembler to accept DSP Release 1 instructions. +‘<samp>-mno-dsp</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mdspr2</code></dt> +<dt><code>-mno-dspr2</code></dt> +<dd><p>Generate code for the DSP Release 2 Application Specific Extension. +This option implies ‘<samp>-mdsp</samp>’. +This tells the assembler to accept DSP Release 2 instructions. +‘<samp>-mno-dspr2</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mdspr3</code></dt> +<dt><code>-mno-dspr3</code></dt> +<dd><p>Generate code for the DSP Release 3 Application Specific Extension. +This option implies ‘<samp>-mdsp</samp>’ and ‘<samp>-mdspr2</samp>’. +This tells the assembler to accept DSP Release 3 instructions. +‘<samp>-mno-dspr3</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mmsa</code></dt> +<dt><code>-mno-msa</code></dt> +<dd><p>Generate code for the MIPS SIMD Architecture Extension. +This tells the assembler to accept MSA instructions. +‘<samp>-mno-msa</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mxpa</code></dt> +<dt><code>-mno-xpa</code></dt> +<dd><p>Generate code for the MIPS eXtended Physical Address (XPA) Extension. +This tells the assembler to accept XPA instructions. +‘<samp>-mno-xpa</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mmt</code></dt> +<dt><code>-mno-mt</code></dt> +<dd><p>Generate code for the MT Application Specific Extension. +This tells the assembler to accept MT instructions. +‘<samp>-mno-mt</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mmcu</code></dt> +<dt><code>-mno-mcu</code></dt> +<dd><p>Generate code for the MCU Application Specific Extension. +This tells the assembler to accept MCU instructions. +‘<samp>-mno-mcu</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mcrc</code></dt> +<dt><code>-mno-crc</code></dt> +<dd><p>Generate code for the MIPS cyclic redundancy check (CRC) Application +Specific Extension. This tells the assembler to accept CRC instructions. +‘<samp>-mno-crc</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mginv</code></dt> +<dt><code>-mno-ginv</code></dt> +<dd><p>Generate code for the Global INValidate (GINV) Application Specific +Extension. This tells the assembler to accept GINV instructions. +‘<samp>-mno-ginv</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mloongson-mmi</code></dt> +<dt><code>-mno-loongson-mmi</code></dt> +<dd><p>Generate code for the Loongson MultiMedia extensions Instructions (MMI) +Application Specific Extension. This tells the assembler to accept MMI +instructions. +‘<samp>-mno-loongson-mmi</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mloongson-cam</code></dt> +<dt><code>-mno-loongson-cam</code></dt> +<dd><p>Generate code for the Loongson Content Address Memory (CAM) instructions. +This tells the assembler to accept Loongson CAM instructions. +‘<samp>-mno-loongson-cam</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mloongson-ext</code></dt> +<dt><code>-mno-loongson-ext</code></dt> +<dd><p>Generate code for the Loongson EXTensions (EXT) instructions. +This tells the assembler to accept Loongson EXT instructions. +‘<samp>-mno-loongson-ext</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mloongson-ext2</code></dt> +<dt><code>-mno-loongson-ext2</code></dt> +<dd><p>Generate code for the Loongson EXTensions R2 (EXT2) instructions. +This option implies ‘<samp>-mloongson-ext</samp>’. +This tells the assembler to accept Loongson EXT2 instructions. +‘<samp>-mno-loongson-ext2</samp>’ turns off this option. +</p> +</dd> +<dt><code>-minsn32</code></dt> +<dt><code>-mno-insn32</code></dt> +<dd><p>Only use 32-bit instruction encodings when generating code for the +microMIPS processor. This option inhibits the use of any 16-bit +instructions. This is equivalent to putting <code>.set insn32</code> at +the start of the assembly file. ‘<samp>-mno-insn32</samp>’ turns off this +option. This is equivalent to putting <code>.set noinsn32</code> at the +start of the assembly file. By default ‘<samp>-mno-insn32</samp>’ is +selected, allowing all instructions to be used. +</p> +</dd> +<dt><code>--construct-floats</code></dt> +<dt><code>--no-construct-floats</code></dt> +<dd><p>The ‘<samp>--no-construct-floats</samp>’ option disables the construction of +double width floating point constants by loading the two halves of the +value into the two single width floating point registers that make up +the double width register. By default ‘<samp>--construct-floats</samp>’ is +selected, allowing construction of these floating point constants. +</p> +</dd> +<dt><code>--relax-branch</code></dt> +<dt><code>--no-relax-branch</code></dt> +<dd><p>The ‘<samp>--relax-branch</samp>’ option enables the relaxation of out-of-range +branches. By default ‘<samp>--no-relax-branch</samp>’ is selected, causing any +out-of-range branches to produce an error. +</p> +</dd> +<dt><code>-mignore-branch-isa</code></dt> +<dt><code>-mno-ignore-branch-isa</code></dt> +<dd><p>Ignore branch checks for invalid transitions between ISA modes. The +semantics of branches does not provide for an ISA mode switch, so in +most cases the ISA mode a branch has been encoded for has to be the +same as the ISA mode of the branch’s target label. Therefore GAS has +checks implemented that verify in branch assembly that the two ISA +modes match. ‘<samp>-mignore-branch-isa</samp>’ disables these checks. By +default ‘<samp>-mno-ignore-branch-isa</samp>’ is selected, causing any invalid +branch requiring a transition between ISA modes to produce an error. +</p> +</dd> +<dt><code>-mnan=<var>encoding</var></code></dt> +<dd><p>Select between the IEEE 754-2008 (<samp>-mnan=2008</samp>) or the legacy +(<samp>-mnan=legacy</samp>) NaN encoding format. The latter is the default. +</p> +<a name="index-emulation"></a> +</dd> +<dt><code>--emulation=<var>name</var></code></dt> +<dd><p>This option was formerly used to switch between ELF and ECOFF output +on targets like IRIX 5 that supported both. MIPS ECOFF support was +removed in GAS 2.24, so the option now serves little purpose. +It is retained for backwards compatibility. +</p> +<p>The available configuration names are: ‘<samp>mipself</samp>’, ‘<samp>mipslelf</samp>’ and +‘<samp>mipsbelf</samp>’. Choosing ‘<samp>mipself</samp>’ now has no effect, since the output +is always ELF. ‘<samp>mipslelf</samp>’ and ‘<samp>mipsbelf</samp>’ select little- and +big-endian output respectively, but ‘<samp>-EL</samp>’ and ‘<samp>-EB</samp>’ are now the +preferred options instead. +</p> +</dd> +<dt><code>-nocpp</code></dt> +<dd><p><code>as</code> ignores this option. It is accepted for compatibility with +the native tools. +</p> +</dd> +<dt><code>--trap</code></dt> +<dt><code>--no-trap</code></dt> +<dt><code>--break</code></dt> +<dt><code>--no-break</code></dt> +<dd><p>Control how to deal with multiplication overflow and division by zero. +‘<samp>--trap</samp>’ or ‘<samp>--no-break</samp>’ (which are synonyms) take a trap exception +(and only work for Instruction Set Architecture level 2 and higher); +‘<samp>--break</samp>’ or ‘<samp>--no-trap</samp>’ (also synonyms, and the default) take a +break exception. +</p> +</dd> +<dt><code>-n</code></dt> +<dd><p>When this option is used, <code>as</code> will issue a warning every +time it generates a nop instruction from a macro. +</p></dd> +</dl> + +<p>The following options are available when as is configured for +an MCore processor. +</p> +<dl compact="compact"> +<dt><code>-jsri2bsr</code></dt> +<dt><code>-nojsri2bsr</code></dt> +<dd><p>Enable or disable the JSRI to BSR transformation. By default this is enabled. +The command-line option ‘<samp>-nojsri2bsr</samp>’ can be used to disable it. +</p> +</dd> +<dt><code>-sifilter</code></dt> +<dt><code>-nosifilter</code></dt> +<dd><p>Enable or disable the silicon filter behaviour. By default this is disabled. +The default can be overridden by the ‘<samp>-sifilter</samp>’ command-line option. +</p> +</dd> +<dt><code>-relax</code></dt> +<dd><p>Alter jump instructions for long displacements. +</p> +</dd> +<dt><code>-mcpu=[210|340]</code></dt> +<dd><p>Select the cpu type on the target hardware. This controls which instructions +can be assembled. +</p> +</dd> +<dt><code>-EB</code></dt> +<dd><p>Assemble for a big endian target. +</p> +</dd> +<dt><code>-EL</code></dt> +<dd><p>Assemble for a little endian target. +</p> +</dd> +</dl> + + + +<p>See <a href="#Meta-Options">Meta Options</a>, for the options available when as is configured +for a Meta processor. +</p> + + +<p>See the info pages for documentation of the MMIX-specific options. +</p> + +<p>See <a href="#NDS32-Options">NDS32 Options</a>, for the options available when as is configured +for a NDS32 processor. +</p> + + +<p>See <a href="#PowerPC_002dOpts">PowerPC-Opts</a>, for the options available when as is configured +for a PowerPC processor. +</p> + + + +<p>See <a href="#RISC_002dV_002dOptions">RISC-V-Options</a>, for the options available when as is configured +for a RISC-V processor. +</p> + + +<p>See the info pages for documentation of the RX-specific options. +</p> +<p>The following options are available when as is configured for the s390 +processor family. +</p> +<dl compact="compact"> +<dt><code>-m31</code></dt> +<dt><code>-m64</code></dt> +<dd><p>Select the word size, either 31/32 bits or 64 bits. +</p></dd> +<dt><code>-mesa</code></dt> +<dt><code>-mzarch</code></dt> +<dd><p>Select the architecture mode, either the Enterprise System +Architecture (esa) or the z/Architecture mode (zarch). +</p></dd> +<dt><code>-march=<var>processor</var></code></dt> +<dd><p>Specify which s390 processor variant is the target, ‘<samp>g5</samp>’ (or +‘<samp>arch3</samp>’), ‘<samp>g6</samp>’, ‘<samp>z900</samp>’ (or ‘<samp>arch5</samp>’), ‘<samp>z990</samp>’ (or +‘<samp>arch6</samp>’), ‘<samp>z9-109</samp>’, ‘<samp>z9-ec</samp>’ (or ‘<samp>arch7</samp>’), ‘<samp>z10</samp>’ (or +‘<samp>arch8</samp>’), ‘<samp>z196</samp>’ (or ‘<samp>arch9</samp>’), ‘<samp>zEC12</samp>’ (or ‘<samp>arch10</samp>’), +‘<samp>z13</samp>’ (or ‘<samp>arch11</samp>’), ‘<samp>z14</samp>’ (or ‘<samp>arch12</samp>’), ‘<samp>z15</samp>’ +(or ‘<samp>arch13</samp>’), or ‘<samp>z16</samp>’ (or ‘<samp>arch14</samp>’). +</p></dd> +<dt><code>-mregnames</code></dt> +<dt><code>-mno-regnames</code></dt> +<dd><p>Allow or disallow symbolic names for registers. +</p></dd> +<dt><code>-mwarn-areg-zero</code></dt> +<dd><p>Warn whenever the operand for a base or index register has been specified +but evaluates to zero. +</p></dd> +</dl> + + +<p>See <a href="#TIC6X-Options">TIC6X Options</a>, for the options available when as is configured +for a TMS320C6000 processor. +</p> + + + +<p>See <a href="#TILE_002dGx-Options">TILE-Gx Options</a>, for the options available when as is configured +for a TILE-Gx processor. +</p> + + + +<p>See <a href="#Visium-Options">Visium Options</a>, for the options available when as is configured +for a Visium processor. +</p> + + + +<p>See <a href="#Xtensa-Options">Xtensa Options</a>, for the options available when as is configured +for an Xtensa processor. +</p> + + + +<p>See <a href="#Z80-Options">Z80 Options</a>, for the options available when as is configured +for an Z80 processor. +</p> + + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Manual" accesskey="1">Manual</a>:</td><td> </td><td align="left" valign="top">Structure of this Manual +</td></tr> +<tr><td align="left" valign="top">• <a href="#GNU-Assembler" accesskey="2">GNU Assembler</a>:</td><td> </td><td align="left" valign="top">The GNU Assembler +</td></tr> +<tr><td align="left" valign="top">• <a href="#Object-Formats" accesskey="3">Object Formats</a>:</td><td> </td><td align="left" valign="top">Object File Formats +</td></tr> +<tr><td align="left" valign="top">• <a href="#Command-Line" accesskey="4">Command Line</a>:</td><td> </td><td align="left" valign="top">Command Line +</td></tr> +<tr><td align="left" valign="top">• <a href="#Input-Files" accesskey="5">Input Files</a>:</td><td> </td><td align="left" valign="top">Input Files +</td></tr> +<tr><td align="left" valign="top">• <a href="#Object" accesskey="6">Object</a>:</td><td> </td><td align="left" valign="top">Output (Object) File +</td></tr> +<tr><td align="left" valign="top">• <a href="#Errors" accesskey="7">Errors</a>:</td><td> </td><td align="left" valign="top">Error and Warning Messages +</td></tr> +</table> + +<hr> +<a name="Manual"></a> +<div class="header"> +<p> +Next: <a href="#GNU-Assembler" accesskey="n" rel="next">GNU Assembler</a>, Up: <a href="#Overview" accesskey="u" rel="up">Overview</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Structure-of-this-Manual"></a> +<h3 class="section">1.1 Structure of this Manual</h3> + +<a name="index-manual_002c-structure-and-purpose"></a> +<p>This manual is intended to describe what you need to know to use +<small>GNU</small> <code>as</code>. We cover the syntax expected in source files, including +notation for symbols, constants, and expressions; the directives that +<code>as</code> understands; and of course how to invoke <code>as</code>. +</p> +<p>This manual also describes some of the machine-dependent features of +various flavors of the assembler. +</p> +<a name="index-machine-instructions-_0028not-covered_0029"></a> +<p>On the other hand, this manual is <em>not</em> intended as an introduction +to programming in assembly language—let alone programming in general! +In a similar vein, we make no attempt to introduce the machine +architecture; we do <em>not</em> describe the instruction set, standard +mnemonics, registers or addressing modes that are standard to a +particular architecture. +You may want to consult the manufacturer’s +machine architecture manual for this information. +</p> + + +<hr> +<a name="GNU-Assembler"></a> +<div class="header"> +<p> +Next: <a href="#Object-Formats" accesskey="n" rel="next">Object Formats</a>, Previous: <a href="#Manual" accesskey="p" rel="previous">Manual</a>, Up: <a href="#Overview" accesskey="u" rel="up">Overview</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="The-GNU-Assembler"></a> +<h3 class="section">1.2 The GNU Assembler</h3> + + +<p><small>GNU</small> <code>as</code> is really a family of assemblers. +If you use (or have used) the <small>GNU</small> assembler on one architecture, you +should find a fairly similar environment when you use it on another +architecture. Each version has much in common with the others, +including object file formats, most assembler directives (often called +<em>pseudo-ops</em>) and assembler syntax. +</p> +<a name="index-purpose-of-GNU-assembler"></a> +<p><code>as</code> is primarily intended to assemble the output of the +<small>GNU</small> C compiler <code>gcc</code> for use by the linker +<code>ld</code>. Nevertheless, we’ve tried to make <code>as</code> +assemble correctly everything that other assemblers for the same +machine would assemble. +Any exceptions are documented explicitly (see <a href="#Machine-Dependencies">Machine Dependencies</a>). +This doesn’t mean <code>as</code> always uses the same syntax as another +assembler for the same architecture; for example, we know of several +incompatible versions of 680x0 assembly language syntax. +</p> + +<p>Unlike older assemblers, <code>as</code> is designed to assemble a source +program in one pass of the source file. This has a subtle impact on the +<kbd>.org</kbd> directive (see <a href="#Org"><code>.org</code></a>). +</p> +<hr> +<a name="Object-Formats"></a> +<div class="header"> +<p> +Next: <a href="#Command-Line" accesskey="n" rel="next">Command Line</a>, Previous: <a href="#GNU-Assembler" accesskey="p" rel="previous">GNU Assembler</a>, Up: <a href="#Overview" accesskey="u" rel="up">Overview</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Object-File-Formats"></a> +<h3 class="section">1.3 Object File Formats</h3> + +<a name="index-object-file-format"></a> +<p>The <small>GNU</small> assembler can be configured to produce several alternative +object file formats. For the most part, this does not affect how you +write assembly language programs; but directives for debugging symbols +are typically different in different file formats. See <a href="#Symbol-Attributes">Symbol Attributes</a>. +</p> +<hr> +<a name="Command-Line"></a> +<div class="header"> +<p> +Next: <a href="#Input-Files" accesskey="n" rel="next">Input Files</a>, Previous: <a href="#Object-Formats" accesskey="p" rel="previous">Object Formats</a>, Up: <a href="#Overview" accesskey="u" rel="up">Overview</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Command-Line-1"></a> +<h3 class="section">1.4 Command Line</h3> + +<a name="index-command-line-conventions"></a> + +<p>After the program name <code>as</code>, the command line may contain +options and file names. Options may appear in any order, and may be +before, after, or between file names. The order of file names is +significant. +</p> +<a name="index-standard-input_002c-as-input-file"></a> +<a name="index-_002d_002d"></a> +<p><samp>--</samp> (two hyphens) by itself names the standard input file +explicitly, as one of the files for <code>as</code> to assemble. +</p> +<a name="index-options_002c-command-line"></a> +<p>Except for ‘<samp>--</samp>’ any command-line argument that begins with a +hyphen (‘<samp>-</samp>’) is an option. Each option changes the behavior of +<code>as</code>. No option changes the way another option works. An +option is a ‘<samp>-</samp>’ followed by one or more letters; the case of +the letter is important. All options are optional. +</p> +<p>Some options expect exactly one file name to follow them. The file +name may either immediately follow the option’s letter (compatible +with older assemblers) or it may be the next command argument (<small>GNU</small> +standard). These two command lines are equivalent: +</p> +<div class="smallexample"> +<pre class="smallexample">as -o my-object-file.o mumble.s +as -omy-object-file.o mumble.s +</pre></div> + +<hr> +<a name="Input-Files"></a> +<div class="header"> +<p> +Next: <a href="#Object" accesskey="n" rel="next">Object</a>, Previous: <a href="#Command-Line" accesskey="p" rel="previous">Command Line</a>, Up: <a href="#Overview" accesskey="u" rel="up">Overview</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Input-Files-1"></a> +<h3 class="section">1.5 Input Files</h3> + +<a name="index-input"></a> +<a name="index-source-program"></a> +<a name="index-files_002c-input"></a> +<p>We use the phrase <em>source program</em>, abbreviated <em>source</em>, to +describe the program input to one run of <code>as</code>. The program may +be in one or more files; how the source is partitioned into files +doesn’t change the meaning of the source. +</p> +<p>The source program is a concatenation of the text in all the files, in the +order specified. +</p> +<p>Each time you run <code>as</code> it assembles exactly one source +program. The source program is made up of one or more files. +(The standard input is also a file.) +</p> +<p>You give <code>as</code> a command line that has zero or more input file +names. The input files are read (from left file name to right). A +command-line argument (in any position) that has no special meaning +is taken to be an input file name. +</p> +<p>If you give <code>as</code> no file names it attempts to read one input file +from the <code>as</code> standard input, which is normally your terminal. You +may have to type <tt class="key">ctl-D</tt> to tell <code>as</code> there is no more program +to assemble. +</p> +<p>Use ‘<samp>--</samp>’ if you need to explicitly name the standard input file +in your command line. +</p> +<p>If the source is empty, <code>as</code> produces a small, empty object +file. +</p> + +<a name="Filenames-and-Line_002dnumbers"></a> +<h4 class="subheading">Filenames and Line-numbers</h4> + +<a name="index-input-file-linenumbers"></a> +<a name="index-line-numbers_002c-in-input-files"></a> +<p>There are two ways of locating a line in the input file (or files) and +either may be used in reporting error messages. One way refers to a line +number in a physical file; the other refers to a line number in a +“logical” file. See <a href="#Errors">Error and Warning Messages</a>. +</p> +<p><em>Physical files</em> are those files named in the command line given +to <code>as</code>. +</p> +<p><em>Logical files</em> are simply names declared explicitly by assembler +directives; they bear no relation to physical files. Logical file names help +error messages reflect the original source file, when <code>as</code> source +is itself synthesized from other files. <code>as</code> understands the +‘<samp>#</samp>’ directives emitted by the <code>gcc</code> preprocessor. See also +<a href="#File"><code>.file</code></a>. +</p> +<hr> +<a name="Object"></a> +<div class="header"> +<p> +Next: <a href="#Errors" accesskey="n" rel="next">Errors</a>, Previous: <a href="#Input-Files" accesskey="p" rel="previous">Input Files</a>, Up: <a href="#Overview" accesskey="u" rel="up">Overview</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Output-_0028Object_0029-File"></a> +<h3 class="section">1.6 Output (Object) File</h3> + +<a name="index-object-file"></a> +<a name="index-output-file"></a> +<a name="index-a_002eout"></a> +<a name="index-_002eo"></a> +<p>Every time you run <code>as</code> it produces an output file, which is +your assembly language program translated into numbers. This file +is the object file. Its default name is <code>a.out</code>. +You can give it another name by using the <samp>-o</samp> option. Conventionally, +object file names end with <samp>.o</samp>. The default name is used for historical +reasons: older assemblers were capable of assembling self-contained programs +directly into a runnable program. (For some formats, this isn’t currently +possible, but it can be done for the <code>a.out</code> format.) +</p> +<a name="index-linker"></a> +<a name="index-ld"></a> +<p>The object file is meant for input to the linker <code>ld</code>. It contains +assembled program code, information to help <code>ld</code> integrate +the assembled program into a runnable file, and (optionally) symbolic +information for the debugger. +</p> + +<hr> +<a name="Errors"></a> +<div class="header"> +<p> +Previous: <a href="#Object" accesskey="p" rel="previous">Object</a>, Up: <a href="#Overview" accesskey="u" rel="up">Overview</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Error-and-Warning-Messages"></a> +<h3 class="section">1.7 Error and Warning Messages</h3> + + +<a name="index-error-messages"></a> +<a name="index-warning-messages"></a> +<a name="index-messages-from-assembler"></a> +<p><code>as</code> may write warnings and error messages to the standard error +file (usually your terminal). This should not happen when a compiler +runs <code>as</code> automatically. Warnings report an assumption made so +that <code>as</code> could keep assembling a flawed program; errors report a +grave problem that stops the assembly. +</p> + +<a name="index-format-of-warning-messages"></a> +<p>Warning messages have the format +</p> +<div class="smallexample"> +<pre class="smallexample">file_name:<b>NNN</b>:Warning Message Text +</pre></div> + +<a name="index-file-names-and-line-numbers_002c-in-warnings_002ferrors"></a> +<p>(where <b>NNN</b> is a line number). If both a logical file name +(see <a href="#File"><code>.file</code></a>) and a logical line number +(see <a href="#Line"><code>.line</code></a>) +have been given then they will be used, otherwise the file name and line number +in the current assembler source file will be used. The message text is +intended to be self explanatory (in the grand Unix tradition). +</p> +<p>Note the file name must be set via the logical version of the <code>.file</code> +directive, not the DWARF2 version of the <code>.file</code> directive. For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> .file 2 "bar.c" + error_assembler_source + .file "foo.c" + .line 30 + error_c_source +</pre></div> + +<p>produces this output: +</p> +<div class="smallexample"> +<pre class="smallexample"> Assembler messages: + asm.s:2: Error: no such instruction: `error_assembler_source' + foo.c:31: Error: no such instruction: `error_c_source' +</pre></div> + +<a name="index-format-of-error-messages"></a> +<p>Error messages have the format +</p> +<div class="smallexample"> +<pre class="smallexample">file_name:<b>NNN</b>:FATAL:Error Message Text +</pre></div> + +<p>The file name and line number are derived as for warning +messages. The actual message text may be rather less explanatory +because many of them aren’t supposed to happen. +</p> +<hr> +<a name="Invoking"></a> +<div class="header"> +<p> +Next: <a href="#Syntax" accesskey="n" rel="next">Syntax</a>, Previous: <a href="#Overview" accesskey="p" rel="previous">Overview</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Command_002dLine-Options"></a> +<h2 class="chapter">2 Command-Line Options</h2> + +<a name="index-options_002c-all-versions-of-assembler"></a> +<p>This chapter describes command-line options available in <em>all</em> +versions of the <small>GNU</small> assembler; see <a href="#Machine-Dependencies">Machine Dependencies</a>, +for options specific +to particular machine architectures. +</p> + +<p>If you are invoking <code>as</code> via the <small>GNU</small> C compiler, +you can use the ‘<samp>-Wa</samp>’ option to pass arguments through to the assembler. +The assembler arguments must be separated from each other (and the ‘<samp>-Wa</samp>’) +by commas. For example: +</p> +<div class="smallexample"> +<pre class="smallexample">gcc -c -g -O -Wa,-alh,-L file.c +</pre></div> + +<p>This passes two options to the assembler: ‘<samp>-alh</samp>’ (emit a listing to +standard output with high-level and assembly source) and ‘<samp>-L</samp>’ (retain +local symbols in the symbol table). +</p> +<p>Usually you do not need to use this ‘<samp>-Wa</samp>’ mechanism, since many compiler +command-line options are automatically passed to the assembler by the compiler. +(You can call the <small>GNU</small> compiler driver with the ‘<samp>-v</samp>’ option to see +precisely what options it passes to each compilation pass, including the +assembler.) +</p> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#a" accesskey="1">a</a>:</td><td> </td><td align="left" valign="top">-a[cdghlns] enable listings +</td></tr> +<tr><td align="left" valign="top">• <a href="#alternate" accesskey="2">alternate</a>:</td><td> </td><td align="left" valign="top">–alternate enable alternate macro syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#D" accesskey="3">D</a>:</td><td> </td><td align="left" valign="top">-D for compatibility and debugging +</td></tr> +<tr><td align="left" valign="top">• <a href="#f" accesskey="4">f</a>:</td><td> </td><td align="left" valign="top">-f to work faster +</td></tr> +<tr><td align="left" valign="top">• <a href="#I" accesskey="5">I</a>:</td><td> </td><td align="left" valign="top">-I for .include search path +</td></tr> +<tr><td align="left" valign="top">• <a href="#K" accesskey="6">K</a>:</td><td> </td><td align="left" valign="top">-K for difference tables +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#L" accesskey="7">L</a>:</td><td> </td><td align="left" valign="top">-L to retain local symbols +</td></tr> +<tr><td align="left" valign="top">• <a href="#listing" accesskey="8">listing</a>:</td><td> </td><td align="left" valign="top">–listing-XXX to configure listing output +</td></tr> +<tr><td align="left" valign="top">• <a href="#M" accesskey="9">M</a>:</td><td> </td><td align="left" valign="top">-M or –mri to assemble in MRI compatibility mode +</td></tr> +<tr><td align="left" valign="top">• <a href="#MD">MD</a>:</td><td> </td><td align="left" valign="top">–MD for dependency tracking +</td></tr> +<tr><td align="left" valign="top">• <a href="#no_002dpad_002dsections">no-pad-sections</a>:</td><td> </td><td align="left" valign="top">–no-pad-sections to stop section padding +</td></tr> +<tr><td align="left" valign="top">• <a href="#o">o</a>:</td><td> </td><td align="left" valign="top">-o to name the object file +</td></tr> +<tr><td align="left" valign="top">• <a href="#R">R</a>:</td><td> </td><td align="left" valign="top">-R to join data and text sections +</td></tr> +<tr><td align="left" valign="top">• <a href="#statistics">statistics</a>:</td><td> </td><td align="left" valign="top">–statistics to see statistics about assembly +</td></tr> +<tr><td align="left" valign="top">• <a href="#traditional_002dformat">traditional-format</a>:</td><td> </td><td align="left" valign="top">–traditional-format for compatible output +</td></tr> +<tr><td align="left" valign="top">• <a href="#v">v</a>:</td><td> </td><td align="left" valign="top">-v to announce version +</td></tr> +<tr><td align="left" valign="top">• <a href="#W">W</a>:</td><td> </td><td align="left" valign="top">-W, –no-warn, –warn, –fatal-warnings to control warnings +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z">Z</a>:</td><td> </td><td align="left" valign="top">-Z to make object file even after errors +</td></tr> +</table> + +<hr> +<a name="a"></a> +<div class="header"> +<p> +Next: <a href="#alternate" accesskey="n" rel="next">alternate</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Enable-Listings_003a-_002da_005bcdghlns_005d"></a> +<h3 class="section">2.1 Enable Listings: <samp>-a[cdghlns]</samp></h3> + +<a name="index-_002da"></a> +<a name="index-_002dac"></a> +<a name="index-_002dad"></a> +<a name="index-_002dag"></a> +<a name="index-_002dah"></a> +<a name="index-_002dal"></a> +<a name="index-_002dan"></a> +<a name="index-_002das"></a> +<a name="index-listings_002c-enabling"></a> +<a name="index-assembly-listings_002c-enabling"></a> + +<p>These options enable listing output from the assembler. By itself, +‘<samp>-a</samp>’ requests high-level, assembly, and symbols listing. +You can use other letters to select specific options for the list: +‘<samp>-ah</samp>’ requests a high-level language listing, +‘<samp>-al</samp>’ requests an output-program assembly listing, and +‘<samp>-as</samp>’ requests a symbol table listing. +High-level listings require that a compiler debugging option like +‘<samp>-g</samp>’ be used, and that assembly listings (‘<samp>-al</samp>’) be requested +also. +</p> +<p>Use the ‘<samp>-ag</samp>’ option to print a first section with general assembly +information, like as version, switches passed, or time stamp. +</p> +<p>Use the ‘<samp>-ac</samp>’ option to omit false conditionals from a listing. Any lines +which are not assembled because of a false <code>.if</code> (or <code>.ifdef</code>, or any +other conditional), or a true <code>.if</code> followed by an <code>.else</code>, will be +omitted from the listing. +</p> +<p>Use the ‘<samp>-ad</samp>’ option to omit debugging directives from the +listing. +</p> +<p>Once you have specified one of these options, you can further control +listing output and its appearance using the directives <code>.list</code>, +<code>.nolist</code>, <code>.psize</code>, <code>.eject</code>, <code>.title</code>, and +<code>.sbttl</code>. +The ‘<samp>-an</samp>’ option turns off all forms processing. +If you do not request listing output with one of the ‘<samp>-a</samp>’ options, the +listing-control directives have no effect. +</p> +<p>The letters after ‘<samp>-a</samp>’ may be combined into one option, +<em>e.g.</em>, ‘<samp>-aln</samp>’. +</p> +<p>Note if the assembler source is coming from the standard input (e.g., +because it +is being created by <code>gcc</code> and the ‘<samp>-pipe</samp>’ command-line switch +is being used) then the listing will not contain any comments or preprocessor +directives. This is because the listing code buffers input source lines from +stdin only after they have been preprocessed by the assembler. This reduces +memory usage and makes the code more efficient. +</p> +<hr> +<a name="alternate"></a> +<div class="header"> +<p> +Next: <a href="#D" accesskey="n" rel="next">D</a>, Previous: <a href="#a" accesskey="p" rel="previous">a</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002d_002dalternate"></a> +<h3 class="section">2.2 <samp>--alternate</samp></h3> + +<a name="index-_002d_002dalternate"></a> +<p>Begin in alternate macro mode, see <a href="#Altmacro"><code>.altmacro</code></a>. +</p> +<hr> +<a name="D"></a> +<div class="header"> +<p> +Next: <a href="#f" accesskey="n" rel="next">f</a>, Previous: <a href="#alternate" accesskey="p" rel="previous">alternate</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002dD"></a> +<h3 class="section">2.3 <samp>-D</samp></h3> + +<a name="index-_002dD"></a> +<p>This option enables debugging, if it is supported by the assembler’s +configuration. Otherwise it does nothing as is ignored. This allows scripts +designed to work with other assemblers to also work with GAS. +<code>as</code>. +</p> +<hr> +<a name="f"></a> +<div class="header"> +<p> +Next: <a href="#I" accesskey="n" rel="next">I</a>, Previous: <a href="#D" accesskey="p" rel="previous">D</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Work-Faster_003a-_002df"></a> +<h3 class="section">2.4 Work Faster: <samp>-f</samp></h3> + +<a name="index-_002df"></a> +<a name="index-trusted-compiler"></a> +<a name="index-faster-processing-_0028_002df_0029"></a> +<p>‘<samp>-f</samp>’ should only be used when assembling programs written by a +(trusted) compiler. ‘<samp>-f</samp>’ stops the assembler from doing whitespace +and comment preprocessing on +the input file(s) before assembling them. See <a href="#Preprocessing">Preprocessing</a>. +</p> +<blockquote> +<p><em>Warning:</em> if you use ‘<samp>-f</samp>’ when the files actually need to be +preprocessed (if they contain comments, for example), <code>as</code> does +not work correctly. +</p></blockquote> + +<hr> +<a name="I"></a> +<div class="header"> +<p> +Next: <a href="#K" accesskey="n" rel="next">K</a>, Previous: <a href="#f" accesskey="p" rel="previous">f</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002einclude-Search-Path_003a-_002dI-path"></a> +<h3 class="section">2.5 <code>.include</code> Search Path: <samp>-I</samp> <var>path</var></h3> + +<a name="index-_002dI-path"></a> +<a name="index-paths-for-_002einclude"></a> +<a name="index-search-path-for-_002einclude"></a> +<a name="index-include-directive-search-path"></a> +<p>Use this option to add a <var>path</var> to the list of directories +<code>as</code> searches for files specified in <code>.include</code> +directives (see <a href="#Include"><code>.include</code></a>). You may use <samp>-I</samp> as +many times as necessary to include a variety of paths. The current +working directory is always searched first; after that, <code>as</code> +searches any ‘<samp>-I</samp>’ directories in the same order as they were +specified (left to right) on the command line. +</p> +<hr> +<a name="K"></a> +<div class="header"> +<p> +Next: <a href="#L" accesskey="n" rel="next">L</a>, Previous: <a href="#I" accesskey="p" rel="previous">I</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Difference-Tables_003a-_002dK"></a> +<h3 class="section">2.6 Difference Tables: <samp>-K</samp></h3> + +<a name="index-_002dK"></a> + +<a name="index-difference-tables_002c-warning"></a> +<a name="index-warning-for-altered-difference-tables"></a> +<p><code>as</code> sometimes alters the code emitted for directives of the +form ‘<samp>.word <var>sym1</var>-<var>sym2</var></samp>’. See <a href="#Word"><code>.word</code></a>. +You can use the ‘<samp>-K</samp>’ option if you want a warning issued when this +is done. +</p> +<hr> +<a name="L"></a> +<div class="header"> +<p> +Next: <a href="#listing" accesskey="n" rel="next">listing</a>, Previous: <a href="#K" accesskey="p" rel="previous">K</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Include-Local-Symbols_003a-_002dL"></a> +<h3 class="section">2.7 Include Local Symbols: <samp>-L</samp></h3> + +<a name="index-_002dL"></a> +<a name="index-local-symbols_002c-retaining-in-output"></a> +<p>Symbols beginning with system-specific local label prefixes, typically +‘<samp>.L</samp>’ for ELF systems or ‘<samp>L</samp>’ for traditional a.out systems, are +called <em>local symbols</em>. See <a href="#Symbol-Names">Symbol Names</a>. Normally you do not see +such symbols when debugging, because they are intended for the use of +programs (like compilers) that compose assembler programs, not for your +notice. Normally both <code>as</code> and <code>ld</code> discard +such symbols, so you do not normally debug with them. +</p> +<p>This option tells <code>as</code> to retain those local symbols +in the object file. Usually if you do this you also tell the linker +<code>ld</code> to preserve those symbols. +</p> +<hr> +<a name="listing"></a> +<div class="header"> +<p> +Next: <a href="#M" accesskey="n" rel="next">M</a>, Previous: <a href="#L" accesskey="p" rel="previous">L</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Configuring-listing-output_003a-_002d_002dlisting"></a> +<h3 class="section">2.8 Configuring listing output: <samp>--listing</samp></h3> + +<p>The listing feature of the assembler can be enabled via the command-line switch +‘<samp>-a</samp>’ (see <a href="#a">a</a>). This feature combines the input source file(s) with a +hex dump of the corresponding locations in the output object file, and displays +them as a listing file. The format of this listing can be controlled by +directives inside the assembler source (i.e., <code>.list</code> (see <a href="#List">List</a>), +<code>.title</code> (see <a href="#Title">Title</a>), <code>.sbttl</code> (see <a href="#Sbttl">Sbttl</a>), +<code>.psize</code> (see <a href="#Psize">Psize</a>), and +<code>.eject</code> (see <a href="#Eject">Eject</a>) and also by the following switches: +</p> +<dl compact="compact"> +<dt><code>--listing-lhs-width=‘<samp>number</samp>’</code></dt> +<dd><a name="index-_002d_002dlisting_002dlhs_002dwidth"></a> +<a name="index-Width-of-first-line-disassembly-output"></a> +<p>Sets the maximum width, in words, of the first line of the hex byte dump. This +dump appears on the left hand side of the listing output. +</p> +</dd> +<dt><code>--listing-lhs-width2=‘<samp>number</samp>’</code></dt> +<dd><a name="index-_002d_002dlisting_002dlhs_002dwidth2"></a> +<a name="index-Width-of-continuation-lines-of-disassembly-output"></a> +<p>Sets the maximum width, in words, of any further lines of the hex byte dump for +a given input source line. If this value is not specified, it defaults to being +the same as the value specified for ‘<samp>--listing-lhs-width</samp>’. If neither +switch is used the default is to one. +</p> +</dd> +<dt><code>--listing-rhs-width=‘<samp>number</samp>’</code></dt> +<dd><a name="index-_002d_002dlisting_002drhs_002dwidth"></a> +<a name="index-Width-of-source-line-output"></a> +<p>Sets the maximum width, in characters, of the source line that is displayed +alongside the hex dump. The default value for this parameter is 100. The +source line is displayed on the right hand side of the listing output. +</p> +</dd> +<dt><code>--listing-cont-lines=‘<samp>number</samp>’</code></dt> +<dd><a name="index-_002d_002dlisting_002dcont_002dlines"></a> +<a name="index-Maximum-number-of-continuation-lines"></a> +<p>Sets the maximum number of continuation lines of hex dump that will be +displayed for a given single line of source input. The default value is 4. +</p></dd> +</dl> + +<hr> +<a name="M"></a> +<div class="header"> +<p> +Next: <a href="#MD" accesskey="n" rel="next">MD</a>, Previous: <a href="#listing" accesskey="p" rel="previous">listing</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assemble-in-MRI-Compatibility-Mode_003a-_002dM"></a> +<h3 class="section">2.9 Assemble in MRI Compatibility Mode: <samp>-M</samp></h3> + +<a name="index-_002dM"></a> +<a name="index-MRI-compatibility-mode"></a> +<p>The <samp>-M</samp> or <samp>--mri</samp> option selects MRI compatibility mode. This +changes the syntax and pseudo-op handling of <code>as</code> to make it +compatible with the <code>ASM68K</code> assembler from Microtec Research. +The exact nature of the +MRI syntax will not be documented here; see the MRI manuals for more +information. Note in particular that the handling of macros and macro +arguments is somewhat different. The purpose of this option is to permit +assembling existing MRI assembler code using <code>as</code>. +</p> +<p>The MRI compatibility is not complete. Certain operations of the MRI assembler +depend upon its object file format, and can not be supported using other object +file formats. Supporting these would require enhancing each object file format +individually. These are: +</p> +<ul> +<li> global symbols in common section + +<p>The m68k MRI assembler supports common sections which are merged by the linker. +Other object file formats do not support this. <code>as</code> handles +common sections by treating them as a single common symbol. It permits local +symbols to be defined within a common section, but it can not support global +symbols, since it has no way to describe them. +</p> +</li><li> complex relocations + +<p>The MRI assemblers support relocations against a negated section address, and +relocations which combine the start addresses of two or more sections. These +are not support by other object file formats. +</p> +</li><li> <code>END</code> pseudo-op specifying start address + +<p>The MRI <code>END</code> pseudo-op permits the specification of a start address. +This is not supported by other object file formats. The start address may +instead be specified using the <samp>-e</samp> option to the linker, or in a linker +script. +</p> +</li><li> <code>IDNT</code>, <code>.ident</code> and <code>NAME</code> pseudo-ops + +<p>The MRI <code>IDNT</code>, <code>.ident</code> and <code>NAME</code> pseudo-ops assign a module +name to the output file. This is not supported by other object file formats. +</p> +</li><li> <code>ORG</code> pseudo-op + +<p>The m68k MRI <code>ORG</code> pseudo-op begins an absolute section at a given +address. This differs from the usual <code>as</code> <code>.org</code> pseudo-op, +which changes the location within the current section. Absolute sections are +not supported by other object file formats. The address of a section may be +assigned within a linker script. +</p></li></ul> + +<p>There are some other features of the MRI assembler which are not supported by +<code>as</code>, typically either because they are difficult or because they +seem of little consequence. Some of these may be supported in future releases. +</p> +<ul> +<li> EBCDIC strings + +<p>EBCDIC strings are not supported. +</p> +</li><li> packed binary coded decimal + +<p>Packed binary coded decimal is not supported. This means that the <code>DC.P</code> +and <code>DCB.P</code> pseudo-ops are not supported. +</p> +</li><li> <code>FEQU</code> pseudo-op + +<p>The m68k <code>FEQU</code> pseudo-op is not supported. +</p> +</li><li> <code>NOOBJ</code> pseudo-op + +<p>The m68k <code>NOOBJ</code> pseudo-op is not supported. +</p> +</li><li> <code>OPT</code> branch control options + +<p>The m68k <code>OPT</code> branch control options—<code>B</code>, <code>BRS</code>, <code>BRB</code>, +<code>BRL</code>, and <code>BRW</code>—are ignored. <code>as</code> automatically +relaxes all branches, whether forward or backward, to an appropriate size, so +these options serve no purpose. +</p> +</li><li> <code>OPT</code> list control options + +<p>The following m68k <code>OPT</code> list control options are ignored: <code>C</code>, +<code>CEX</code>, <code>CL</code>, <code>CRE</code>, <code>E</code>, <code>G</code>, <code>I</code>, <code>M</code>, +<code>MEX</code>, <code>MC</code>, <code>MD</code>, <code>X</code>. +</p> +</li><li> other <code>OPT</code> options + +<p>The following m68k <code>OPT</code> options are ignored: <code>NEST</code>, <code>O</code>, +<code>OLD</code>, <code>OP</code>, <code>P</code>, <code>PCO</code>, <code>PCR</code>, <code>PCS</code>, <code>R</code>. +</p> +</li><li> <code>OPT</code> <code>D</code> option is default + +<p>The m68k <code>OPT</code> <code>D</code> option is the default, unlike the MRI assembler. +<code>OPT NOD</code> may be used to turn it off. +</p> +</li><li> <code>XREF</code> pseudo-op. + +<p>The m68k <code>XREF</code> pseudo-op is ignored. +</p> +</li></ul> + +<hr> +<a name="MD"></a> +<div class="header"> +<p> +Next: <a href="#no_002dpad_002dsections" accesskey="n" rel="next">no-pad-sections</a>, Previous: <a href="#M" accesskey="p" rel="previous">M</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Dependency-Tracking_003a-_002d_002dMD"></a> +<h3 class="section">2.10 Dependency Tracking: <samp>--MD</samp></h3> + +<a name="index-_002d_002dMD"></a> +<a name="index-dependency-tracking"></a> +<a name="index-make-rules"></a> + +<p><code>as</code> can generate a dependency file for the file it creates. This +file consists of a single rule suitable for <code>make</code> describing the +dependencies of the main source file. +</p> +<p>The rule is written to the file named in its argument. +</p> +<p>This feature is used in the automatic updating of makefiles. +</p> +<hr> +<a name="no_002dpad_002dsections"></a> +<div class="header"> +<p> +Next: <a href="#o" accesskey="n" rel="next">o</a>, Previous: <a href="#MD" accesskey="p" rel="previous">MD</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Output-Section-Padding"></a> +<h3 class="section">2.11 Output Section Padding</h3> +<a name="index-_002d_002dno_002dpad_002dsections"></a> +<a name="index-output-section-padding"></a> +<p>Normally the assembler will pad the end of each output section up to its +alignment boundary. But this can waste space, which can be significant on +memory constrained targets. So the <samp>--no-pad-sections</samp> option will +disable this behaviour. +</p> +<hr> +<a name="o"></a> +<div class="header"> +<p> +Next: <a href="#R" accesskey="n" rel="next">R</a>, Previous: <a href="#no_002dpad_002dsections" accesskey="p" rel="previous">no-pad-sections</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Name-the-Object-File_003a-_002do"></a> +<h3 class="section">2.12 Name the Object File: <samp>-o</samp></h3> + +<a name="index-_002do"></a> +<a name="index-naming-object-file"></a> +<a name="index-object-file-name"></a> +<p>There is always one object file output when you run <code>as</code>. By +default it has the name <samp>a.out</samp>. +You use this option (which takes exactly one filename) to give the +object file a different name. +</p> +<p>Whatever the object file is called, <code>as</code> overwrites any +existing file of the same name. +</p> +<hr> +<a name="R"></a> +<div class="header"> +<p> +Next: <a href="#statistics" accesskey="n" rel="next">statistics</a>, Previous: <a href="#o" accesskey="p" rel="previous">o</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Join-Data-and-Text-Sections_003a-_002dR"></a> +<h3 class="section">2.13 Join Data and Text Sections: <samp>-R</samp></h3> + +<a name="index-_002dR"></a> +<a name="index-data-and-text-sections_002c-joining"></a> +<a name="index-text-and-data-sections_002c-joining"></a> +<a name="index-joining-text-and-data-sections"></a> +<a name="index-merging-text-and-data-sections"></a> +<p><samp>-R</samp> tells <code>as</code> to write the object file as if all +data-section data lives in the text section. This is only done at +the very last moment: your binary data are the same, but data +section parts are relocated differently. The data section part of +your object file is zero bytes long because all its bytes are +appended to the text section. (See <a href="#Sections">Sections and Relocation</a>.) +</p> +<p>When you specify <samp>-R</samp> it would be possible to generate shorter +address displacements (because we do not have to cross between text and +data section). We refrain from doing this simply for compatibility with +older versions of <code>as</code>. In future, <samp>-R</samp> may work this way. +</p> +<p>When <code>as</code> is configured for COFF or ELF output, +this option is only useful if you use sections named ‘<samp>.text</samp>’ and +‘<samp>.data</samp>’. +</p> +<p><samp>-R</samp> is not supported for any of the HPPA targets. Using +<samp>-R</samp> generates a warning from <code>as</code>. +</p> +<hr> +<a name="statistics"></a> +<div class="header"> +<p> +Next: <a href="#traditional_002dformat" accesskey="n" rel="next">traditional-format</a>, Previous: <a href="#R" accesskey="p" rel="previous">R</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Display-Assembly-Statistics_003a-_002d_002dstatistics"></a> +<h3 class="section">2.14 Display Assembly Statistics: <samp>--statistics</samp></h3> + +<a name="index-_002d_002dstatistics"></a> +<a name="index-statistics_002c-about-assembly"></a> +<a name="index-time_002c-total-for-assembly"></a> +<a name="index-space-used_002c-maximum-for-assembly"></a> +<p>Use ‘<samp>--statistics</samp>’ to display two statistics about the resources used by +<code>as</code>: the maximum amount of space allocated during the assembly +(in bytes), and the total execution time taken for the assembly (in <small>CPU</small> +seconds). +</p> +<hr> +<a name="traditional_002dformat"></a> +<div class="header"> +<p> +Next: <a href="#v" accesskey="n" rel="next">v</a>, Previous: <a href="#statistics" accesskey="p" rel="previous">statistics</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Compatible-Output_003a-_002d_002dtraditional_002dformat"></a> +<h3 class="section">2.15 Compatible Output: <samp>--traditional-format</samp></h3> + +<a name="index-_002d_002dtraditional_002dformat"></a> +<p>For some targets, the output of <code>as</code> is different in some ways +from the output of some existing assembler. This switch requests +<code>as</code> to use the traditional format instead. +</p> +<p>For example, it disables the exception frame optimizations which +<code>as</code> normally does by default on <code>gcc</code> output. +</p> +<hr> +<a name="v"></a> +<div class="header"> +<p> +Next: <a href="#W" accesskey="n" rel="next">W</a>, Previous: <a href="#traditional_002dformat" accesskey="p" rel="previous">traditional-format</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Announce-Version_003a-_002dv"></a> +<h3 class="section">2.16 Announce Version: <samp>-v</samp></h3> + +<a name="index-_002dv"></a> +<a name="index-_002dversion"></a> +<a name="index-assembler-version"></a> +<a name="index-version-of-assembler"></a> +<p>You can find out what version of as is running by including the +option ‘<samp>-v</samp>’ (which you can also spell as ‘<samp>-version</samp>’) on the +command line. +</p> +<hr> +<a name="W"></a> +<div class="header"> +<p> +Next: <a href="#Z" accesskey="n" rel="next">Z</a>, Previous: <a href="#v" accesskey="p" rel="previous">v</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Control-Warnings_003a-_002dW_002c-_002d_002dwarn_002c-_002d_002dno_002dwarn_002c-_002d_002dfatal_002dwarnings"></a> +<h3 class="section">2.17 Control Warnings: <samp>-W</samp>, <samp>--warn</samp>, <samp>--no-warn</samp>, <samp>--fatal-warnings</samp></h3> + +<p><code>as</code> should never give a warning or error message when +assembling compiler output. But programs written by people often +cause <code>as</code> to give a warning that a particular assumption was +made. All such warnings are directed to the standard error file. +</p> +<a name="index-_002dW"></a> +<a name="index-_002d_002dno_002dwarn"></a> +<a name="index-suppressing-warnings"></a> +<a name="index-warnings_002c-suppressing"></a> +<p>If you use the <samp>-W</samp> and <samp>--no-warn</samp> options, no warnings are issued. +This only affects the warning messages: it does not change any particular of +how <code>as</code> assembles your file. Errors, which stop the assembly, +are still reported. +</p> +<a name="index-_002d_002dfatal_002dwarnings"></a> +<a name="index-errors_002c-caused-by-warnings"></a> +<a name="index-warnings_002c-causing-error"></a> +<p>If you use the <samp>--fatal-warnings</samp> option, <code>as</code> considers +files that generate warnings to be in error. +</p> +<a name="index-_002d_002dwarn"></a> +<a name="index-warnings_002c-switching-on"></a> +<p>You can switch these options off again by specifying <samp>--warn</samp>, which +causes warnings to be output as usual. +</p> +<hr> +<a name="Z"></a> +<div class="header"> +<p> +Previous: <a href="#W" accesskey="p" rel="previous">W</a>, Up: <a href="#Invoking" accesskey="u" rel="up">Invoking</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Generate-Object-File-in-Spite-of-Errors_003a-_002dZ"></a> +<h3 class="section">2.18 Generate Object File in Spite of Errors: <samp>-Z</samp></h3> +<a name="index-object-file_002c-after-errors"></a> +<a name="index-errors_002c-continuing-after"></a> +<p>After an error message, <code>as</code> normally produces no output. If for +some reason you are interested in object file output even after +<code>as</code> gives an error message on your program, use the ‘<samp>-Z</samp>’ +option. If there are any errors, <code>as</code> continues anyways, and +writes an object file after a final warning message of the form ‘<samp><var>n</var> +errors, <var>m</var> warnings, generating bad object file.</samp>’ +</p> +<hr> +<a name="Syntax"></a> +<div class="header"> +<p> +Next: <a href="#Sections" accesskey="n" rel="next">Sections</a>, Previous: <a href="#Invoking" accesskey="p" rel="previous">Invoking</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-1"></a> +<h2 class="chapter">3 Syntax</h2> + +<a name="index-machine_002dindependent-syntax"></a> +<a name="index-syntax_002c-machine_002dindependent"></a> +<p>This chapter describes the machine-independent syntax allowed in a +source file. <code>as</code> syntax is similar to what many other +assemblers use; it is inspired by the BSD 4.2 +assembler, except that <code>as</code> does not assemble Vax bit-fields. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Preprocessing" accesskey="1">Preprocessing</a>:</td><td> </td><td align="left" valign="top">Preprocessing +</td></tr> +<tr><td align="left" valign="top">• <a href="#Whitespace" accesskey="2">Whitespace</a>:</td><td> </td><td align="left" valign="top">Whitespace +</td></tr> +<tr><td align="left" valign="top">• <a href="#Comments" accesskey="3">Comments</a>:</td><td> </td><td align="left" valign="top">Comments +</td></tr> +<tr><td align="left" valign="top">• <a href="#Symbol-Intro" accesskey="4">Symbol Intro</a>:</td><td> </td><td align="left" valign="top">Symbols +</td></tr> +<tr><td align="left" valign="top">• <a href="#Statements" accesskey="5">Statements</a>:</td><td> </td><td align="left" valign="top">Statements +</td></tr> +<tr><td align="left" valign="top">• <a href="#Constants" accesskey="6">Constants</a>:</td><td> </td><td align="left" valign="top">Constants +</td></tr> +</table> + +<hr> +<a name="Preprocessing"></a> +<div class="header"> +<p> +Next: <a href="#Whitespace" accesskey="n" rel="next">Whitespace</a>, Up: <a href="#Syntax" accesskey="u" rel="up">Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Preprocessing-1"></a> +<h3 class="section">3.1 Preprocessing</h3> + +<a name="index-preprocessing"></a> +<p>The <code>as</code> internal preprocessor: +</p><ul> +<li> <a name="index-whitespace_002c-removed-by-preprocessor"></a> +adjusts and removes extra whitespace. It leaves one space or tab before +the keywords on a line, and turns any other whitespace on the line into +a single space. + +</li><li> <a name="index-comments_002c-removed-by-preprocessor"></a> +removes all comments, replacing them with a single space, or an +appropriate number of newlines. + +</li><li> <a name="index-constants_002c-converted-by-preprocessor"></a> +converts character constants into the appropriate numeric values. +</li></ul> + +<p>It does not do macro processing, include file handling, or +anything else you may get from your C compiler’s preprocessor. You can +do include file processing with the <code>.include</code> directive +(see <a href="#Include"><code>.include</code></a>). You can use the <small>GNU</small> C compiler driver +to get other “CPP” style preprocessing by giving the input file a +‘<samp>.S</samp>’ suffix. <a href="https://gcc.gnu.org/onlinedocs/gcc/Overall-Options.html#Overall-Options">See the ’Options Controlling the Kind of Output’ section of the GCC manual for +more details</a> +</p> +<p>Excess whitespace, comments, and character constants +cannot be used in the portions of the input text that are not +preprocessed. +</p> +<a name="index-turning-preprocessing-on-and-off"></a> +<a name="index-preprocessing_002c-turning-on-and-off"></a> +<a name="index-_0023NO_005fAPP"></a> +<a name="index-_0023APP"></a> +<p>If the first line of an input file is <code>#NO_APP</code> or if you use the +‘<samp>-f</samp>’ option, whitespace and comments are not removed from the input file. +Within an input file, you can ask for whitespace and comment removal in +specific portions of the file by putting a line that says <code>#APP</code> before the +text that may contain whitespace or comments, and putting a line that says +<code>#NO_APP</code> after this text. This feature is mainly intended to support +<code>asm</code> statements in compilers whose output is otherwise free of comments +and whitespace. +</p> +<hr> +<a name="Whitespace"></a> +<div class="header"> +<p> +Next: <a href="#Comments" accesskey="n" rel="next">Comments</a>, Previous: <a href="#Preprocessing" accesskey="p" rel="previous">Preprocessing</a>, Up: <a href="#Syntax" accesskey="u" rel="up">Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Whitespace-1"></a> +<h3 class="section">3.2 Whitespace</h3> + +<a name="index-whitespace"></a> +<p><em>Whitespace</em> is one or more blanks or tabs, in any order. +Whitespace is used to separate symbols, and to make programs neater for +people to read. Unless within character constants +(see <a href="#Characters">Character Constants</a>), any whitespace means the same +as exactly one space. +</p> +<hr> +<a name="Comments"></a> +<div class="header"> +<p> +Next: <a href="#Symbol-Intro" accesskey="n" rel="next">Symbol Intro</a>, Previous: <a href="#Whitespace" accesskey="p" rel="previous">Whitespace</a>, Up: <a href="#Syntax" accesskey="u" rel="up">Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Comments-1"></a> +<h3 class="section">3.3 Comments</h3> + +<a name="index-comments"></a> +<p>There are two ways of rendering comments to <code>as</code>. In both +cases the comment is equivalent to one space. +</p> +<p>Anything from ‘<samp>/*</samp>’ through the next ‘<samp>*/</samp>’ is a comment. +This means you may not nest these comments. +</p> +<div class="smallexample"> +<pre class="smallexample">/* + The only way to include a newline ('\n') in a comment + is to use this sort of comment. +*/ + +/* This sort of comment does not nest. */ +</pre></div> + +<a name="index-line-comment-character"></a> +<p>Anything from a <em>line comment</em> character up to the next newline is +considered a comment and is ignored. The line comment character is target +specific, and some targets support multiple comment characters. Some targets +also have line comment characters that only work if they are the first +character on a line. Some targets use a sequence of two characters to +introduce a line comment. Some targets can also change their line comment +characters depending upon command-line options that have been used. For more +details see the <em>Syntax</em> section in the documentation for individual +targets. +</p> +<p>If the line comment character is the hash sign (‘<samp>#</samp>’) then it still has the +special ability to enable and disable preprocessing (see <a href="#Preprocessing">Preprocessing</a>) and +to specify logical line numbers: +</p> +<a name="index-_0023"></a> +<a name="index-lines-starting-with-_0023"></a> +<a name="index-logical-line-numbers"></a> +<p>To be compatible with past assemblers, lines that begin with ‘<samp>#</samp>’ have a +special interpretation. Following the ‘<samp>#</samp>’ should be an absolute +expression (see <a href="#Expressions">Expressions</a>): the logical line number of the <em>next</em> +line. Then a string (see <a href="#Strings">Strings</a>) is allowed: if present it is a +new logical file name. The rest of the line, if any, should be whitespace. +</p> +<p>If the first non-whitespace characters on the line are not numeric, +the line is ignored. (Just like a comment.) +</p> +<div class="smallexample"> +<pre class="smallexample"> # This is an ordinary comment. +# 42-6 "new_file_name" # New logical file name + # This is logical line # 36. +</pre></div> +<p>This feature is deprecated, and may disappear from future versions +of <code>as</code>. +</p> +<hr> +<a name="Symbol-Intro"></a> +<div class="header"> +<p> +Next: <a href="#Statements" accesskey="n" rel="next">Statements</a>, Previous: <a href="#Comments" accesskey="p" rel="previous">Comments</a>, Up: <a href="#Syntax" accesskey="u" rel="up">Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbols-1"></a> +<h3 class="section">3.4 Symbols</h3> + +<a name="index-characters-used-in-symbols"></a> +<p>A <em>symbol</em> is one or more characters chosen from the set of all +letters (both upper and lower case), digits and the three characters +‘<samp>_.$</samp>’. +On most machines, you can also use <code>$</code> in symbol names; exceptions +are noted in <a href="#Machine-Dependencies">Machine Dependencies</a>. +No symbol may begin with a digit. Case is significant. +There is no length limit; all characters are significant. Multibyte characters +are supported, but note that the setting of the +<samp>--multibyte-handling</samp> option might prevent their use. Symbols +are delimited by characters not in that set, or by the beginning of a file +(since the source program must end with a newline, the end of a file is not a +possible symbol delimiter). See <a href="#Symbols">Symbols</a>. +</p> +<p>Symbol names may also be enclosed in double quote <code>"</code> characters. In such +cases any characters are allowed, except for the NUL character. If a double +quote character is to be included in the symbol name it must be preceded by a +backslash <code>\</code> character. +<a name="index-length-of-symbols"></a> +</p> +<hr> +<a name="Statements"></a> +<div class="header"> +<p> +Next: <a href="#Constants" accesskey="n" rel="next">Constants</a>, Previous: <a href="#Symbol-Intro" accesskey="p" rel="previous">Symbol Intro</a>, Up: <a href="#Syntax" accesskey="u" rel="up">Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Statements-1"></a> +<h3 class="section">3.5 Statements</h3> + +<a name="index-statements_002c-structure-of"></a> +<a name="index-line-separator-character"></a> +<a name="index-statement-separator-character"></a> + +<p>A <em>statement</em> ends at a newline character (‘<samp>\n</samp>’) or a +<em>line separator character</em>. The line separator character is target +specific and described in the <em>Syntax</em> section of each +target’s documentation. Not all targets support a line separator character. +The newline or line separator character is considered to be part of the +preceding statement. Newlines and separators within character constants are an +exception: they do not end statements. +</p> +<a name="index-newline_002c-required-at-file-end"></a> +<a name="index-EOF_002c-newline-must-precede"></a> +<p>It is an error to end any statement with end-of-file: the last +character of any input file should be a newline. +</p> +<p>An empty statement is allowed, and may include whitespace. It is ignored. +</p> +<a name="index-instructions-and-directives"></a> +<a name="index-directives-and-instructions"></a> +<p>A statement begins with zero or more labels, optionally followed by a +key symbol which determines what kind of statement it is. The key +symbol determines the syntax of the rest of the statement. If the +symbol begins with a dot ‘<samp>.</samp>’ then the statement is an assembler +directive: typically valid for any computer. If the symbol begins with +a letter the statement is an assembly language <em>instruction</em>: it +assembles into a machine language instruction. +Different versions of <code>as</code> for different computers +recognize different instructions. In fact, the same symbol may +represent a different instruction in a different computer’s assembly +language. +</p> +<a name="index-_003a-_0028label_0029"></a> +<a name="index-label-_0028_003a_0029"></a> +<p>A label is a symbol immediately followed by a colon (<code>:</code>). +Whitespace before a label or after a colon is permitted, but you may not +have whitespace between a label’s symbol and its colon. See <a href="#Labels">Labels</a>. +</p> +<p>For HPPA targets, labels need not be immediately followed by a colon, but +the definition of a label must begin in column zero. This also implies that +only one label may be defined on each line. +</p> +<div class="smallexample"> +<pre class="smallexample">label: .directive followed by something +another_label: # This is an empty statement. + instruction operand_1, operand_2, … +</pre></div> + +<hr> +<a name="Constants"></a> +<div class="header"> +<p> +Previous: <a href="#Statements" accesskey="p" rel="previous">Statements</a>, Up: <a href="#Syntax" accesskey="u" rel="up">Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Constants-1"></a> +<h3 class="section">3.6 Constants</h3> + +<a name="index-constants"></a> +<p>A constant is a number, written so that its value is known by +inspection, without knowing any context. Like this: +</p><div class="smallexample"> +<pre class="smallexample">.byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. +.ascii "Ring the bell\7" # A string constant. +.octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. +.float 0f-314159265358979323846264338327\ +95028841971.693993751E-40 # - pi, a flonum. +</pre></div> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Characters" accesskey="1">Characters</a>:</td><td> </td><td align="left" valign="top">Character Constants +</td></tr> +<tr><td align="left" valign="top">• <a href="#Numbers" accesskey="2">Numbers</a>:</td><td> </td><td align="left" valign="top">Number Constants +</td></tr> +</table> + +<hr> +<a name="Characters"></a> +<div class="header"> +<p> +Next: <a href="#Numbers" accesskey="n" rel="next">Numbers</a>, Up: <a href="#Constants" accesskey="u" rel="up">Constants</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Character-Constants"></a> +<h4 class="subsection">3.6.1 Character Constants</h4> + +<a name="index-character-constants"></a> +<a name="index-constants_002c-character"></a> +<p>There are two kinds of character constants. A <em>character</em> stands +for one character in one byte and its value may be used in +numeric expressions. String constants (properly called string +<em>literals</em>) are potentially many bytes and their values may not be +used in arithmetic expressions. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Strings" accesskey="1">Strings</a>:</td><td> </td><td align="left" valign="top">Strings +</td></tr> +<tr><td align="left" valign="top">• <a href="#Chars" accesskey="2">Chars</a>:</td><td> </td><td align="left" valign="top">Characters +</td></tr> +</table> + +<hr> +<a name="Strings"></a> +<div class="header"> +<p> +Next: <a href="#Chars" accesskey="n" rel="next">Chars</a>, Up: <a href="#Characters" accesskey="u" rel="up">Characters</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Strings-1"></a> +<h4 class="subsubsection">3.6.1.1 Strings</h4> + +<a name="index-string-constants"></a> +<a name="index-constants_002c-string"></a> +<p>A <em>string</em> is written between double-quotes. It may contain +double-quotes or null characters. The way to get special characters +into a string is to <em>escape</em> these characters: precede them with +a backslash ‘<samp>\</samp>’ character. For example ‘<samp>\\</samp>’ represents +one backslash: the first <code>\</code> is an escape which tells +<code>as</code> to interpret the second character literally as a backslash +(which prevents <code>as</code> from recognizing the second <code>\</code> as an +escape character). The complete list of escapes follows. +</p> +<a name="index-escape-codes_002c-character"></a> +<a name="index-character-escape-codes"></a> +<dl compact="compact"> +<dd><a name="index--_005cb-_0028backspace-character_0029"></a> +<a name="index-backspace-_0028_005cb_0029"></a> +</dd> +<dt><kbd>\b</kbd></dt> +<dd><p>Mnemonic for backspace; for ASCII this is octal code 010. +</p> +<a name="index--_005cf-_0028formfeed-character_0029"></a> +<a name="index-formfeed-_0028_005cf_0029"></a> +</dd> +<dt><kbd>backslash-f</kbd></dt> +<dd><p>Mnemonic for FormFeed; for ASCII this is octal code 014. +</p> +<a name="index--_005cn-_0028newline-character_0029"></a> +<a name="index-newline-_0028_005cn_0029"></a> +</dd> +<dt><kbd>\n</kbd></dt> +<dd><p>Mnemonic for newline; for ASCII this is octal code 012. +</p> +<a name="index--_005cr-_0028carriage-return-character_0029"></a> +<a name="index-carriage-return-_0028backslash_002dr_0029"></a> +</dd> +<dt><kbd>\r</kbd></dt> +<dd><p>Mnemonic for carriage-Return; for ASCII this is octal code 015. +</p> +<a name="index--_005ct-_0028tab_0029"></a> +<a name="index-tab-_0028_005ct_0029"></a> +</dd> +<dt><kbd>\t</kbd></dt> +<dd><p>Mnemonic for horizontal Tab; for ASCII this is octal code 011. +</p> +<a name="index--_005cddd-_0028octal-character-code_0029"></a> +<a name="index-octal-character-code-_0028_005cddd_0029"></a> +</dd> +<dt><kbd>\ <var>digit</var> <var>digit</var> <var>digit</var></kbd></dt> +<dd><p>An octal character code. The numeric code is 3 octal digits. +For compatibility with other Unix systems, 8 and 9 are accepted as digits: +for example, <code>\008</code> has the value 010, and <code>\009</code> the value 011. +</p> +<a name="index--_005cxd_002e_002e_002e-_0028hex-character-code_0029"></a> +<a name="index-hex-character-code-_0028_005cxd_002e_002e_002e_0029"></a> +</dd> +<dt><kbd>\<code>x</code> <var>hex-digits...</var></kbd></dt> +<dd><p>A hex character code. All trailing hex digits are combined. Either upper or +lower case <code>x</code> works. +</p> +<a name="index--_005c_005c-_0028_005c-character_0029"></a> +<a name="index-backslash-_0028_005c_005c_0029"></a> +</dd> +<dt><kbd>\\</kbd></dt> +<dd><p>Represents one ‘<samp>\</samp>’ character. +</p> +<a name="index--_005c_0022-_0028doublequote-character_0029"></a> +<a name="index-doublequote-_0028_005c_0022_0029"></a> +</dd> +<dt><kbd>\"</kbd></dt> +<dd><p>Represents one ‘<samp>"</samp>’ character. Needed in strings to represent +this character, because an unescaped ‘<samp>"</samp>’ would end the string. +</p> +</dd> +<dt><kbd>\ <var>anything-else</var></kbd></dt> +<dd><p>Any other character when escaped by <kbd>\</kbd> gives a warning, but +assembles as if the ‘<samp>\</samp>’ was not present. The idea is that if +you used an escape sequence you clearly didn’t want the literal +interpretation of the following character. However <code>as</code> has no +other interpretation, so <code>as</code> knows it is giving you the wrong +code and warns you of the fact. +</p></dd> +</dl> + +<p>Which characters are escapable, and what those escapes represent, +varies widely among assemblers. The current set is what we think +the BSD 4.2 assembler recognizes, and is a subset of what most C +compilers recognize. If you are in doubt, do not use an escape +sequence. +</p> +<hr> +<a name="Chars"></a> +<div class="header"> +<p> +Previous: <a href="#Strings" accesskey="p" rel="previous">Strings</a>, Up: <a href="#Characters" accesskey="u" rel="up">Characters</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Characters-1"></a> +<h4 class="subsubsection">3.6.1.2 Characters</h4> + +<a name="index-single-character-constant"></a> +<a name="index-character_002c-single"></a> +<a name="index-constant_002c-single-character"></a> +<p>A single character may be written as a single quote immediately followed by +that character. Some backslash escapes apply to characters, <code>\b</code>, +<code>\f</code>, <code>\n</code>, <code>\r</code>, <code>\t</code>, and <code>\"</code> with the same meaning +as for strings, plus <code>\'</code> for a single quote. So if you want to write the +character backslash, you must write <kbd>'\\</kbd> where the first <code>\</code> escapes +the second <code>\</code>. As you can see, the quote is an acute accent, not a grave +accent. A newline +immediately following an acute accent is taken as a literal character +and does not count as the end of a statement. The value of a character +constant in a numeric expression is the machine’s byte-wide code for +that character. <code>as</code> assumes your character code is ASCII: +<kbd>'A</kbd> means 65, <kbd>'B</kbd> means 66, and so on. +</p> +<hr> +<a name="Numbers"></a> +<div class="header"> +<p> +Previous: <a href="#Characters" accesskey="p" rel="previous">Characters</a>, Up: <a href="#Constants" accesskey="u" rel="up">Constants</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Number-Constants"></a> +<h4 class="subsection">3.6.2 Number Constants</h4> + +<a name="index-constants_002c-number"></a> +<a name="index-number-constants"></a> +<p><code>as</code> distinguishes three kinds of numbers according to how they +are stored in the target machine. <em>Integers</em> are numbers that +would fit into an <code>int</code> in the C language. <em>Bignums</em> are +integers, but they are stored in more than 32 bits. <em>Flonums</em> +are floating point numbers, described below. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Integers" accesskey="1">Integers</a>:</td><td> </td><td align="left" valign="top">Integers +</td></tr> +<tr><td align="left" valign="top">• <a href="#Bignums" accesskey="2">Bignums</a>:</td><td> </td><td align="left" valign="top">Bignums +</td></tr> +<tr><td align="left" valign="top">• <a href="#Flonums" accesskey="3">Flonums</a>:</td><td> </td><td align="left" valign="top">Flonums +</td></tr> +</table> + +<hr> +<a name="Integers"></a> +<div class="header"> +<p> +Next: <a href="#Bignums" accesskey="n" rel="next">Bignums</a>, Up: <a href="#Numbers" accesskey="u" rel="up">Numbers</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Integers-1"></a> +<h4 class="subsubsection">3.6.2.1 Integers</h4> +<a name="index-integers"></a> +<a name="index-constants_002c-integer"></a> + +<a name="index-binary-integers"></a> +<a name="index-integers_002c-binary"></a> +<p>A binary integer is ‘<samp>0b</samp>’ or ‘<samp>0B</samp>’ followed by zero or more of +the binary digits ‘<samp>01</samp>’. +</p> +<a name="index-octal-integers"></a> +<a name="index-integers_002c-octal"></a> +<p>An octal integer is ‘<samp>0</samp>’ followed by zero or more of the octal +digits (‘<samp>01234567</samp>’). +</p> +<a name="index-decimal-integers"></a> +<a name="index-integers_002c-decimal"></a> +<p>A decimal integer starts with a non-zero digit followed by zero or +more digits (‘<samp>0123456789</samp>’). +</p> +<a name="index-hexadecimal-integers"></a> +<a name="index-integers_002c-hexadecimal"></a> +<p>A hexadecimal integer is ‘<samp>0x</samp>’ or ‘<samp>0X</samp>’ followed by one or +more hexadecimal digits chosen from ‘<samp>0123456789abcdefABCDEF</samp>’. +</p> +<p>Integers have the usual values. To denote a negative integer, use +the prefix operator ‘<samp>-</samp>’ discussed under expressions +(see <a href="#Prefix-Ops">Prefix Operators</a>). +</p> +<hr> +<a name="Bignums"></a> +<div class="header"> +<p> +Next: <a href="#Flonums" accesskey="n" rel="next">Flonums</a>, Previous: <a href="#Integers" accesskey="p" rel="previous">Integers</a>, Up: <a href="#Numbers" accesskey="u" rel="up">Numbers</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Bignums-1"></a> +<h4 class="subsubsection">3.6.2.2 Bignums</h4> + +<a name="index-bignums"></a> +<a name="index-constants_002c-bignum"></a> +<p>A <em>bignum</em> has the same syntax and semantics as an integer +except that the number (or its negative) takes more than 32 bits to +represent in binary. The distinction is made because in some places +integers are permitted while bignums are not. +</p> +<hr> +<a name="Flonums"></a> +<div class="header"> +<p> +Previous: <a href="#Bignums" accesskey="p" rel="previous">Bignums</a>, Up: <a href="#Numbers" accesskey="u" rel="up">Numbers</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Flonums-1"></a> +<h4 class="subsubsection">3.6.2.3 Flonums</h4> +<a name="index-flonums"></a> +<a name="index-floating-point-numbers"></a> +<a name="index-constants_002c-floating-point"></a> + +<a name="index-precision_002c-floating-point"></a> +<p>A <em>flonum</em> represents a floating point number. The translation is +indirect: a decimal floating point number from the text is converted by +<code>as</code> to a generic binary floating point number of more than +sufficient precision. This generic floating point number is converted +to a particular computer’s floating point format (or formats) by a +portion of <code>as</code> specialized to that computer. +</p> +<p>A flonum is written by writing (in order) +</p><ul> +<li> The digit ‘<samp>0</samp>’. +(‘<samp>0</samp>’ is optional on the HPPA.) + +</li><li> A letter, to tell <code>as</code> the rest of the number is a flonum. +<kbd>e</kbd> is recommended. Case is not important. + +<p>On the H8/300 and Renesas / SuperH SH architectures, the letter must be +one of the letters ‘<samp>DFPRSX</samp>’ (in upper or lower case). +</p> +<p>On the ARC, the letter must be one of the letters ‘<samp>DFRS</samp>’ +(in upper or lower case). +</p> +<p>On the HPPA architecture, the letter must be ‘<samp>E</samp>’ (upper case only). +</p> +</li><li> An optional sign: either ‘<samp>+</samp>’ or ‘<samp>-</samp>’. + +</li><li> An optional <em>integer part</em>: zero or more decimal digits. + +</li><li> An optional <em>fractional part</em>: ‘<samp>.</samp>’ followed by zero +or more decimal digits. + +</li><li> An optional exponent, consisting of: + +<ul> +<li> An ‘<samp>E</samp>’ or ‘<samp>e</samp>’. +</li><li> Optional sign: either ‘<samp>+</samp>’ or ‘<samp>-</samp>’. +</li><li> One or more decimal digits. +</li></ul> + +</li></ul> + +<p>At least one of the integer part or the fractional part must be +present. The floating point number has the usual base-10 value. +</p> +<p><code>as</code> does all processing using integers. Flonums are computed +independently of any floating point hardware in the computer running +<code>as</code>. +</p> +<hr> +<a name="Sections"></a> +<div class="header"> +<p> +Next: <a href="#Symbols" accesskey="n" rel="next">Symbols</a>, Previous: <a href="#Syntax" accesskey="p" rel="previous">Syntax</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Sections-and-Relocation"></a> +<h2 class="chapter">4 Sections and Relocation</h2> +<a name="index-sections"></a> +<a name="index-relocation"></a> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Secs-Background" accesskey="1">Secs Background</a>:</td><td> </td><td align="left" valign="top">Background +</td></tr> +<tr><td align="left" valign="top">• <a href="#Ld-Sections" accesskey="2">Ld Sections</a>:</td><td> </td><td align="left" valign="top">Linker Sections +</td></tr> +<tr><td align="left" valign="top">• <a href="#As-Sections" accesskey="3">As Sections</a>:</td><td> </td><td align="left" valign="top">Assembler Internal Sections +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sub_002dSections" accesskey="4">Sub-Sections</a>:</td><td> </td><td align="left" valign="top">Sub-Sections +</td></tr> +<tr><td align="left" valign="top">• <a href="#bss" accesskey="5">bss</a>:</td><td> </td><td align="left" valign="top">bss Section +</td></tr> +</table> + +<hr> +<a name="Secs-Background"></a> +<div class="header"> +<p> +Next: <a href="#Ld-Sections" accesskey="n" rel="next">Ld Sections</a>, Up: <a href="#Sections" accesskey="u" rel="up">Sections</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Background"></a> +<h3 class="section">4.1 Background</h3> + +<p>Roughly, a section is a range of addresses, with no gaps; all data +“in” those addresses is treated the same for some particular purpose. +For example there may be a “read only” section. +</p> +<a name="index-linker_002c-and-assembler"></a> +<a name="index-assembler_002c-and-linker"></a> +<p>The linker <code>ld</code> reads many object files (partial programs) and +combines their contents to form a runnable program. When <code>as</code> +emits an object file, the partial program is assumed to start at address 0. +<code>ld</code> assigns the final addresses for the partial program, so that +different partial programs do not overlap. This is actually an +oversimplification, but it suffices to explain how <code>as</code> uses +sections. +</p> +<p><code>ld</code> moves blocks of bytes of your program to their run-time +addresses. These blocks slide to their run-time addresses as rigid +units; their length does not change and neither does the order of bytes +within them. Such a rigid unit is called a <em>section</em>. Assigning +run-time addresses to sections is called <em>relocation</em>. It includes +the task of adjusting mentions of object-file addresses so they refer to +the proper run-time addresses. +For the H8/300, and for the Renesas / SuperH SH, +<code>as</code> pads sections if needed to +ensure they end on a word (sixteen bit) boundary. +</p> +<a name="index-standard-assembler-sections"></a> +<p>An object file written by <code>as</code> has at least three sections, any +of which may be empty. These are named <em>text</em>, <em>data</em> and +<em>bss</em> sections. +</p> +<p>When it generates COFF or ELF output, +<code>as</code> can also generate whatever other named sections you specify +using the ‘<samp>.section</samp>’ directive (see <a href="#Section"><code>.section</code></a>). +If you do not use any directives that place output in the ‘<samp>.text</samp>’ +or ‘<samp>.data</samp>’ sections, these sections still exist, but are empty. +</p> +<p>When <code>as</code> generates SOM or ELF output for the HPPA, +<code>as</code> can also generate whatever other named sections you +specify using the ‘<samp>.space</samp>’ and ‘<samp>.subspace</samp>’ directives. See +<cite>HP9000 Series 800 Assembly Language Reference Manual</cite> +(HP 92432-90001) for details on the ‘<samp>.space</samp>’ and ‘<samp>.subspace</samp>’ +assembler directives. +</p> +<p>Additionally, <code>as</code> uses different names for the standard +text, data, and bss sections when generating SOM output. Program text +is placed into the ‘<samp>$CODE$</samp>’ section, data into ‘<samp>$DATA$</samp>’, and +BSS into ‘<samp>$BSS$</samp>’. +</p> +<p>Within the object file, the text section starts at address <code>0</code>, the +data section follows, and the bss section follows the data section. +</p> +<p>When generating either SOM or ELF output files on the HPPA, the text +section starts at address <code>0</code>, the data section at address +<code>0x4000000</code>, and the bss section follows the data section. +</p> +<p>To let <code>ld</code> know which data changes when the sections are +relocated, and how to change that data, <code>as</code> also writes to the +object file details of the relocation needed. To perform relocation +<code>ld</code> must know, each time an address in the object +file is mentioned: +</p><ul> +<li> Where in the object file is the beginning of this reference to +an address? +</li><li> How long (in bytes) is this reference? +</li><li> Which section does the address refer to? What is the numeric value of +<div class="display"> +<pre class="display">(<var>address</var>) - (<var>start-address of section</var>)? +</pre></div> +</li><li> Is the reference to an address “Program-Counter relative”? +</li></ul> + +<a name="index-addresses_002c-format-of"></a> +<a name="index-section_002drelative-addressing"></a> +<p>In fact, every address <code>as</code> ever uses is expressed as +</p><div class="display"> +<pre class="display">(<var>section</var>) + (<var>offset into section</var>) +</pre></div> +<p>Further, most expressions <code>as</code> computes have this section-relative +nature. +(For some object formats, such as SOM for the HPPA, some expressions are +symbol-relative instead.) +</p> +<p>In this manual we use the notation {<var>secname</var> <var>N</var>} to mean “offset +<var>N</var> into section <var>secname</var>.” +</p> +<p>Apart from text, data and bss sections you need to know about the +<em>absolute</em> section. When <code>ld</code> mixes partial programs, +addresses in the absolute section remain unchanged. For example, address +<code>{absolute 0}</code> is “relocated” to run-time address 0 by +<code>ld</code>. Although the linker never arranges two partial programs’ +data sections with overlapping addresses after linking, <em>by definition</em> +their absolute sections must overlap. Address <code>{absolute 239}</code> in one +part of a program is always the same address when the program is running as +address <code>{absolute 239}</code> in any other part of the program. +</p> +<p>The idea of sections is extended to the <em>undefined</em> section. Any +address whose section is unknown at assembly time is by definition +rendered {undefined <var>U</var>}—where <var>U</var> is filled in later. +Since numbers are always defined, the only way to generate an undefined +address is to mention an undefined symbol. A reference to a named +common block would be such a symbol: its value is unknown at assembly +time so it has section <em>undefined</em>. +</p> +<p>By analogy the word <em>section</em> is used to describe groups of sections in +the linked program. <code>ld</code> puts all partial programs’ text +sections in contiguous addresses in the linked program. It is +customary to refer to the <em>text section</em> of a program, meaning all +the addresses of all partial programs’ text sections. Likewise for +data and bss sections. +</p> +<p>Some sections are manipulated by <code>ld</code>; others are invented for +use of <code>as</code> and have no meaning except during assembly. +</p> +<hr> +<a name="Ld-Sections"></a> +<div class="header"> +<p> +Next: <a href="#As-Sections" accesskey="n" rel="next">As Sections</a>, Previous: <a href="#Secs-Background" accesskey="p" rel="previous">Secs Background</a>, Up: <a href="#Sections" accesskey="u" rel="up">Sections</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Linker-Sections"></a> +<h3 class="section">4.2 Linker Sections</h3> +<p><code>ld</code> deals with just four kinds of sections, summarized below. +</p> +<dl compact="compact"> +<dd> +<a name="index-named-sections"></a> +<a name="index-sections_002c-named"></a> +</dd> +<dt><strong>named sections</strong></dt> +<dd><a name="index-text-section"></a> +<a name="index-data-section"></a> +</dd> +<dt><strong>text section</strong></dt> +<dt><strong>data section</strong></dt> +<dd><p>These sections hold your program. <code>as</code> and <code>ld</code> treat them as +separate but equal sections. Anything you can say of one section is +true of another. +When the program is running, however, it is +customary for the text section to be unalterable. The +text section is often shared among processes: it contains +instructions, constants and the like. The data section of a running +program is usually alterable: for example, C variables would be stored +in the data section. +</p> +<a name="index-bss-section"></a> +</dd> +<dt><strong>bss section</strong></dt> +<dd><p>This section contains zeroed bytes when your program begins running. It +is used to hold uninitialized variables or common storage. The length of +each partial program’s bss section is important, but because it starts +out containing zeroed bytes there is no need to store explicit zero +bytes in the object file. The bss section was invented to eliminate +those explicit zeros from object files. +</p> +<a name="index-absolute-section"></a> +</dd> +<dt><strong>absolute section</strong></dt> +<dd><p>Address 0 of this section is always “relocated” to runtime address 0. +This is useful if you want to refer to an address that <code>ld</code> must +not change when relocating. In this sense we speak of absolute +addresses being “unrelocatable”: they do not change during relocation. +</p> +<a name="index-undefined-section"></a> +</dd> +<dt><strong>undefined section</strong></dt> +<dd><p>This “section” is a catch-all for address references to objects not in +the preceding sections. +</p></dd> +</dl> + +<a name="index-relocation-example"></a> +<p>An idealized example of three relocatable sections follows. +The example uses the traditional section names ‘<samp>.text</samp>’ and ‘<samp>.data</samp>’. +Memory addresses are on the horizontal axis. +</p> +<div class="smallexample"> +<pre class="smallexample"> +-----+----+--+ +partial program # 1: |ttttt|dddd|00| + +-----+----+--+ + + text data bss + seg. seg. seg. + + +---+---+---+ +partial program # 2: |TTT|DDD|000| + +---+---+---+ + + +--+---+-----+--+----+---+-----+~~ +linked program: | |TTT|ttttt| |dddd|DDD|00000| + +--+---+-----+--+----+---+-----+~~ + + addresses: 0 … +</pre></div> + +<hr> +<a name="As-Sections"></a> +<div class="header"> +<p> +Next: <a href="#Sub_002dSections" accesskey="n" rel="next">Sub-Sections</a>, Previous: <a href="#Ld-Sections" accesskey="p" rel="previous">Ld Sections</a>, Up: <a href="#Sections" accesskey="u" rel="up">Sections</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Internal-Sections"></a> +<h3 class="section">4.3 Assembler Internal Sections</h3> + +<a name="index-internal-assembler-sections"></a> +<a name="index-sections-in-messages_002c-internal"></a> +<p>These sections are meant only for the internal use of <code>as</code>. They +have no meaning at run-time. You do not really need to know about these +sections for most purposes; but they can be mentioned in <code>as</code> +warning messages, so it might be helpful to have an idea of their +meanings to <code>as</code>. These sections are used to permit the +value of every expression in your assembly language program to be a +section-relative address. +</p> +<dl compact="compact"> +<dd><a name="index-assembler-internal-logic-error"></a> +</dd> +<dt><b>ASSEMBLER-INTERNAL-LOGIC-ERROR!</b></dt> +<dd><p>An internal assembler logic error has been found. This means there is a +bug in the assembler. +</p> +<a name="index-expr-_0028internal-section_0029"></a> +</dd> +<dt><b>expr section</b></dt> +<dd><p>The assembler stores complex expressions internally as combinations of +symbols. When it needs to represent an expression as a symbol, it puts +it in the expr section. +</p></dd> +</dl> + +<hr> +<a name="Sub_002dSections"></a> +<div class="header"> +<p> +Next: <a href="#bss" accesskey="n" rel="next">bss</a>, Previous: <a href="#As-Sections" accesskey="p" rel="previous">As Sections</a>, Up: <a href="#Sections" accesskey="u" rel="up">Sections</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Sub_002dSections-1"></a> +<h3 class="section">4.4 Sub-Sections</h3> + +<a name="index-numbered-subsections"></a> +<a name="index-grouping-data"></a> +<p>Assembled bytes +conventionally +fall into two sections: text and data. +You may have separate groups of +data in named sections +that you want to end up near to each other in the object file, even though they +are not contiguous in the assembler source. <code>as</code> allows you to +use <em>subsections</em> for this purpose. Within each section, there can be +numbered subsections with values from 0 to 8192. Objects assembled into the +same subsection go into the object file together with other objects in the same +subsection. For example, a compiler might want to store constants in the text +section, but might not want to have them interspersed with the program being +assembled. In this case, the compiler could issue a ‘<samp>.text 0</samp>’ before each +section of code being output, and a ‘<samp>.text 1</samp>’ before each group of +constants being output. +</p> +<p>Subsections are optional. If you do not use subsections, everything +goes in subsection number zero. +</p> +<p>Each subsection is zero-padded up to a multiple of four bytes. +(Subsections may be padded a different amount on different flavors +of <code>as</code>.) +</p> +<p>Subsections appear in your object file in numeric order, lowest numbered +to highest. (All this to be compatible with other people’s assemblers.) +The object file contains no representation of subsections; <code>ld</code> and +other programs that manipulate object files see no trace of them. +They just see all your text subsections as a text section, and all your +data subsections as a data section. +</p> +<p>To specify which subsection you want subsequent statements assembled +into, use a numeric argument to specify it, in a ‘<samp>.text +<var>expression</var></samp>’ or a ‘<samp>.data <var>expression</var></samp>’ statement. +When generating COFF output, you +can also use an extra subsection +argument with arbitrary named sections: ‘<samp>.section <var>name</var>, +<var>expression</var></samp>’. +When generating ELF output, you +can also use the <code>.subsection</code> directive (see <a href="#SubSection">SubSection</a>) +to specify a subsection: ‘<samp>.subsection <var>expression</var></samp>’. +<var>Expression</var> should be an absolute expression +(see <a href="#Expressions">Expressions</a>). If you just say ‘<samp>.text</samp>’ then ‘<samp>.text 0</samp>’ +is assumed. Likewise ‘<samp>.data</samp>’ means ‘<samp>.data 0</samp>’. Assembly +begins in <code>text 0</code>. For instance: +</p><div class="smallexample"> +<pre class="smallexample">.text 0 # The default subsection is text 0 anyway. +.ascii "This lives in the first text subsection. *" +.text 1 +.ascii "But this lives in the second text subsection." +.data 0 +.ascii "This lives in the data section," +.ascii "in the first data subsection." +.text 0 +.ascii "This lives in the first text section," +.ascii "immediately following the asterisk (*)." +</pre></div> + +<p>Each section has a <em>location counter</em> incremented by one for every byte +assembled into that section. Because subsections are merely a convenience +restricted to <code>as</code> there is no concept of a subsection location +counter. There is no way to directly manipulate a location counter—but the +<code>.align</code> directive changes it, and any label definition captures its +current value. The location counter of the section where statements are being +assembled is said to be the <em>active</em> location counter. +</p> +<hr> +<a name="bss"></a> +<div class="header"> +<p> +Previous: <a href="#Sub_002dSections" accesskey="p" rel="previous">Sub-Sections</a>, Up: <a href="#Sections" accesskey="u" rel="up">Sections</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="bss-Section"></a> +<h3 class="section">4.5 bss Section</h3> + +<a name="index-bss-section-1"></a> +<a name="index-common-variable-storage"></a> +<p>The bss section is used for local common variable storage. +You may allocate address space in the bss section, but you may +not dictate data to load into it before your program executes. When +your program starts running, all the contents of the bss +section are zeroed bytes. +</p> +<p>The <code>.lcomm</code> pseudo-op defines a symbol in the bss section; see +<a href="#Lcomm"><code>.lcomm</code></a>. +</p> +<p>The <code>.comm</code> pseudo-op may be used to declare a common symbol, which is +another form of uninitialized symbol; see <a href="#Comm"><code>.comm</code></a>. +</p> +<p>When assembling for a target which supports multiple sections, such as ELF or +COFF, you may switch into the <code>.bss</code> section and define symbols as usual; +see <a href="#Section"><code>.section</code></a>. You may only assemble zero values into the +section. Typically the section will only contain symbol definitions and +<code>.skip</code> directives (see <a href="#Skip"><code>.skip</code></a>). +</p> +<hr> +<a name="Symbols"></a> +<div class="header"> +<p> +Next: <a href="#Expressions" accesskey="n" rel="next">Expressions</a>, Previous: <a href="#Sections" accesskey="p" rel="previous">Sections</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbols-2"></a> +<h2 class="chapter">5 Symbols</h2> + +<a name="index-symbols"></a> +<p>Symbols are a central concept: the programmer uses symbols to name +things, the linker uses symbols to link, and the debugger uses symbols +to debug. +</p> +<blockquote> +<a name="index-debuggers_002c-and-symbol-order"></a> +<p><em>Warning:</em> <code>as</code> does not place symbols in the object file in +the same order they were declared. This may break some debuggers. +</p></blockquote> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Labels" accesskey="1">Labels</a>:</td><td> </td><td align="left" valign="top">Labels +</td></tr> +<tr><td align="left" valign="top">• <a href="#Setting-Symbols" accesskey="2">Setting Symbols</a>:</td><td> </td><td align="left" valign="top">Giving Symbols Other Values +</td></tr> +<tr><td align="left" valign="top">• <a href="#Symbol-Names" accesskey="3">Symbol Names</a>:</td><td> </td><td align="left" valign="top">Symbol Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#Dot" accesskey="4">Dot</a>:</td><td> </td><td align="left" valign="top">The Special Dot Symbol +</td></tr> +<tr><td align="left" valign="top">• <a href="#Symbol-Attributes" accesskey="5">Symbol Attributes</a>:</td><td> </td><td align="left" valign="top">Symbol Attributes +</td></tr> +</table> + +<hr> +<a name="Labels"></a> +<div class="header"> +<p> +Next: <a href="#Setting-Symbols" accesskey="n" rel="next">Setting Symbols</a>, Up: <a href="#Symbols" accesskey="u" rel="up">Symbols</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Labels-1"></a> +<h3 class="section">5.1 Labels</h3> + +<a name="index-labels"></a> +<p>A <em>label</em> is written as a symbol immediately followed by a colon +‘<samp>:</samp>’. The symbol then represents the current value of the +active location counter, and is, for example, a suitable instruction +operand. You are warned if you use the same symbol to represent two +different locations: the first definition overrides any other +definitions. +</p> +<p>On the HPPA, the usual form for a label need not be immediately followed by a +colon, but instead must start in column zero. Only one label may be defined on +a single line. To work around this, the HPPA version of <code>as</code> also +provides a special directive <code>.label</code> for defining labels more flexibly. +</p> +<hr> +<a name="Setting-Symbols"></a> +<div class="header"> +<p> +Next: <a href="#Symbol-Names" accesskey="n" rel="next">Symbol Names</a>, Previous: <a href="#Labels" accesskey="p" rel="previous">Labels</a>, Up: <a href="#Symbols" accesskey="u" rel="up">Symbols</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Giving-Symbols-Other-Values"></a> +<h3 class="section">5.2 Giving Symbols Other Values</h3> + +<a name="index-assigning-values-to-symbols"></a> +<a name="index-symbol-values_002c-assigning"></a> +<p>A symbol can be given an arbitrary value by writing a symbol, followed +by an equals sign ‘<samp>=</samp>’, followed by an expression +(see <a href="#Expressions">Expressions</a>). This is equivalent to using the <code>.set</code> +directive. See <a href="#Set"><code>.set</code></a>. In the same way, using a double +equals sign ‘<samp>=</samp>’‘<samp>=</samp>’ here represents an equivalent of the +<code>.eqv</code> directive. See <a href="#Eqv"><code>.eqv</code></a>. +</p> +<p>Blackfin does not support symbol assignment with ‘<samp>=</samp>’. +</p> +<hr> +<a name="Symbol-Names"></a> +<div class="header"> +<p> +Next: <a href="#Dot" accesskey="n" rel="next">Dot</a>, Previous: <a href="#Setting-Symbols" accesskey="p" rel="previous">Setting Symbols</a>, Up: <a href="#Symbols" accesskey="u" rel="up">Symbols</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbol-Names-1"></a> +<h3 class="section">5.3 Symbol Names</h3> + +<a name="index-symbol-names"></a> +<a name="index-names_002c-symbol"></a> +<p>Symbol names begin with a letter or with one of ‘<samp>._</samp>’. On most +machines, you can also use <code>$</code> in symbol names; exceptions are +noted in <a href="#Machine-Dependencies">Machine Dependencies</a>. That character may be followed by any +string of digits, letters, dollar signs (unless otherwise noted for a +particular target machine), and underscores. These restrictions do not +apply when quoting symbol names by ‘<samp>"</samp>’, which is permitted for most +targets. Escaping characters in quoted symbol names with ‘<samp>\</samp>’ generally +extends only to ‘<samp>\</samp>’ itself and ‘<samp>"</samp>’, at the time of writing. +</p> +<p>Case of letters is significant: <code>foo</code> is a different symbol name +than <code>Foo</code>. +</p> +<p>Symbol names do not start with a digit. An exception to this rule is made for +Local Labels. See below. +</p> +<p>Multibyte characters are supported, but note that the setting of the +<samp>multibyte-handling</samp> option might prevent their use. +To generate a symbol name containing +multibyte characters enclose it within double quotes and use escape codes. cf +See <a href="#Strings">Strings</a>. Generating a multibyte symbol name from a label is not +currently supported. +</p> +<p>Since multibyte symbol names are unusual, and could possibly be used +maliciously, <code>as</code> provides a command line option +(<samp>--multibyte-handling=warn-sym-only</samp>) which can be used to generate a +warning message whenever a symbol name containing multibyte characters is defined. +</p> +<p>Each symbol has exactly one name. Each name in an assembly language program +refers to exactly one symbol. You may use that symbol name any number of times +in a program. +</p> +<a name="Local-Symbol-Names"></a> +<h4 class="subheading">Local Symbol Names</h4> + +<a name="index-local-symbol-names"></a> +<a name="index-symbol-names_002c-local"></a> +<p>A local symbol is any symbol beginning with certain local label prefixes. +By default, the local label prefix is ‘<samp>.L</samp>’ for ELF systems or +‘<samp>L</samp>’ for traditional a.out systems, but each target may have its own +set of local label prefixes. +On the HPPA local symbols begin with ‘<samp>L$</samp>’. +</p> +<p>Local symbols are defined and used within the assembler, but they are +normally not saved in object files. Thus, they are not visible when debugging. +You may use the ‘<samp>-L</samp>’ option (see <a href="#L">Include Local Symbols</a>) +to retain the local symbols in the object files. +</p> +<a name="Local-Labels-1"></a> +<h4 class="subheading">Local Labels</h4> + +<a name="index-local-labels"></a> +<a name="index-temporary-symbol-names"></a> +<a name="index-symbol-names_002c-temporary"></a> +<p>Local labels are different from local symbols. Local labels help compilers and +programmers use names temporarily. They create symbols which are guaranteed to +be unique over the entire scope of the input source code and which can be +referred to by a simple notation. To define a local label, write a label of +the form ‘<samp><b>N</b>:</samp>’ (where <b>N</b> represents any non-negative integer). +To refer to the most recent previous definition of that label write +‘<samp><b>N</b>b</samp>’, using the same number as when you defined the label. To refer +to the next definition of a local label, write ‘<samp><b>N</b>f</samp>’. The ‘<samp>b</samp>’ +stands for “backwards” and the ‘<samp>f</samp>’ stands for “forwards”. +</p> +<p>There is no restriction on how you can use these labels, and you can reuse them +too. So that it is possible to repeatedly define the same local label (using +the same number ‘<samp><b>N</b></samp>’), although you can only refer to the most recently +defined local label of that number (for a backwards reference) or the next +definition of a specific local label for a forward reference. It is also worth +noting that the first 10 local labels (‘<samp><b>0:</b></samp>’…‘<samp><b>9:</b></samp>’) are +implemented in a slightly more efficient manner than the others. +</p> +<p>Here is an example: +</p> +<div class="smallexample"> +<pre class="smallexample">1: branch 1f +2: branch 1b +1: branch 2f +2: branch 1b +</pre></div> + +<p>Which is the equivalent of: +</p> +<div class="smallexample"> +<pre class="smallexample">label_1: branch label_3 +label_2: branch label_1 +label_3: branch label_4 +label_4: branch label_3 +</pre></div> + +<p>Local label names are only a notational device. They are immediately +transformed into more conventional symbol names before the assembler uses them. +The symbol names are stored in the symbol table, appear in error messages, and +are optionally emitted to the object file. The names are constructed using +these parts: +</p> +<dl compact="compact"> +<dt><code><em>local label prefix</em></code></dt> +<dd><p>All local symbols begin with the system-specific local label prefix. +Normally both <code>as</code> and <code>ld</code> forget symbols +that start with the local label prefix. These labels are +used for symbols you are never intended to see. If you use the +‘<samp>-L</samp>’ option then <code>as</code> retains these symbols in the +object file. If you also instruct <code>ld</code> to retain these symbols, +you may use them in debugging. +</p> +</dd> +<dt><code><var>number</var></code></dt> +<dd><p>This is the number that was used in the local label definition. So if the +label is written ‘<samp>55:</samp>’ then the number is ‘<samp>55</samp>’. +</p> +</dd> +<dt><code><kbd>C-B</kbd></code></dt> +<dd><p>This unusual character is included so you do not accidentally invent a symbol +of the same name. The character has ASCII value of ‘<samp>\002</samp>’ (control-B). +</p> +</dd> +<dt><code><em>ordinal number</em></code></dt> +<dd><p>This is a serial number to keep the labels distinct. The first definition of +‘<samp>0:</samp>’ gets the number ‘<samp>1</samp>’. The 15th definition of ‘<samp>0:</samp>’ gets the +number ‘<samp>15</samp>’, and so on. Likewise the first definition of ‘<samp>1:</samp>’ gets +the number ‘<samp>1</samp>’ and its 15th definition gets ‘<samp>15</samp>’ as well. +</p></dd> +</dl> + +<p>So for example, the first <code>1:</code> may be named <code>.L1<kbd>C-B</kbd>1</code>, and +the 44th <code>3:</code> may be named <code>.L3<kbd>C-B</kbd>44</code>. +</p> +<a name="Dollar-Local-Labels"></a> +<h4 class="subheading">Dollar Local Labels</h4> +<a name="index-dollar-local-symbols"></a> + +<p>On some targets <code>as</code> also supports an even more local form of +local labels called dollar labels. These labels go out of scope (i.e., they +become undefined) as soon as a non-local label is defined. Thus they remain +valid for only a small region of the input source code. Normal local labels, +by contrast, remain in scope for the entire file, or until they are redefined +by another occurrence of the same local label. +</p> +<p>Dollar labels are defined in exactly the same way as ordinary local labels, +except that they have a dollar sign suffix to their numeric value, e.g., +‘<samp><b>55$:</b></samp>’. +</p> +<p>They can also be distinguished from ordinary local labels by their transformed +names which use ASCII character ‘<samp>\001</samp>’ (control-A) as the magic character +to distinguish them from ordinary labels. For example, the fifth definition of +‘<samp>6$</samp>’ may be named ‘<samp>.L6<kbd>C-A</kbd>5</samp>’. +</p> +<hr> +<a name="Dot"></a> +<div class="header"> +<p> +Next: <a href="#Symbol-Attributes" accesskey="n" rel="next">Symbol Attributes</a>, Previous: <a href="#Symbol-Names" accesskey="p" rel="previous">Symbol Names</a>, Up: <a href="#Symbols" accesskey="u" rel="up">Symbols</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="The-Special-Dot-Symbol"></a> +<h3 class="section">5.4 The Special Dot Symbol</h3> + +<a name="index-dot-_0028symbol_0029"></a> +<a name="index-_002e-_0028symbol_0029"></a> +<a name="index-current-address"></a> +<a name="index-location-counter"></a> +<p>The special symbol ‘<samp>.</samp>’ refers to the current address that +<code>as</code> is assembling into. Thus, the expression ‘<samp>melvin: +.long .</samp>’ defines <code>melvin</code> to contain its own address. +Assigning a value to <code>.</code> is treated the same as a <code>.org</code> +directive. +Thus, the expression ‘<samp>.=.+4</samp>’ is the same as saying +‘<samp>.space 4</samp>’. +</p> +<hr> +<a name="Symbol-Attributes"></a> +<div class="header"> +<p> +Previous: <a href="#Dot" accesskey="p" rel="previous">Dot</a>, Up: <a href="#Symbols" accesskey="u" rel="up">Symbols</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbol-Attributes-1"></a> +<h3 class="section">5.5 Symbol Attributes</h3> + +<a name="index-symbol-attributes"></a> +<a name="index-attributes_002c-symbol"></a> +<p>Every symbol has, as well as its name, the attributes “Value” and +“Type”. Depending on output format, symbols can also have auxiliary +attributes. +</p> +<p>If you use a symbol without defining it, <code>as</code> assumes zero for +all these attributes, and probably won’t warn you. This makes the +symbol an externally defined symbol, which is generally what you +would want. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Symbol-Value" accesskey="1">Symbol Value</a>:</td><td> </td><td align="left" valign="top">Value +</td></tr> +<tr><td align="left" valign="top">• <a href="#Symbol-Type" accesskey="2">Symbol Type</a>:</td><td> </td><td align="left" valign="top">Type +</td></tr> +<tr><td align="left" valign="top">• <a href="#a_002eout-Symbols" accesskey="3">a.out Symbols</a>:</td><td> </td><td align="left" valign="top">Symbol Attributes: <code>a.out</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#COFF-Symbols" accesskey="4">COFF Symbols</a>:</td><td> </td><td align="left" valign="top">Symbol Attributes for COFF +</td></tr> +<tr><td align="left" valign="top">• <a href="#SOM-Symbols" accesskey="5">SOM Symbols</a>:</td><td> </td><td align="left" valign="top">Symbol Attributes for SOM +</td></tr> +</table> + +<hr> +<a name="Symbol-Value"></a> +<div class="header"> +<p> +Next: <a href="#Symbol-Type" accesskey="n" rel="next">Symbol Type</a>, Up: <a href="#Symbol-Attributes" accesskey="u" rel="up">Symbol Attributes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Value"></a> +<h4 class="subsection">5.5.1 Value</h4> + +<a name="index-value-of-a-symbol"></a> +<a name="index-symbol-value"></a> +<p>The value of a symbol is (usually) 32 bits. For a symbol which labels a +location in the text, data, bss or absolute sections the value is the +number of addresses from the start of that section to the label. +Naturally for text, data and bss sections the value of a symbol changes +as <code>ld</code> changes section base addresses during linking. Absolute +symbols’ values do not change during linking: that is why they are +called absolute. +</p> +<p>The value of an undefined symbol is treated in a special way. If it is +0 then the symbol is not defined in this assembler source file, and +<code>ld</code> tries to determine its value from other files linked into the +same program. You make this kind of symbol simply by mentioning a symbol +name without defining it. A non-zero value represents a <code>.comm</code> +common declaration. The value is how much common storage to reserve, in +bytes (addresses). The symbol refers to the first address of the +allocated storage. +</p> +<hr> +<a name="Symbol-Type"></a> +<div class="header"> +<p> +Next: <a href="#a_002eout-Symbols" accesskey="n" rel="next">a.out Symbols</a>, Previous: <a href="#Symbol-Value" accesskey="p" rel="previous">Symbol Value</a>, Up: <a href="#Symbol-Attributes" accesskey="u" rel="up">Symbol Attributes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Type-1"></a> +<h4 class="subsection">5.5.2 Type</h4> + +<a name="index-type-of-a-symbol"></a> +<a name="index-symbol-type"></a> +<p>The type attribute of a symbol contains relocation (section) +information, any flag settings indicating that a symbol is external, and +(optionally), other information for linkers and debuggers. The exact +format depends on the object-code output format in use. +</p> +<hr> +<a name="a_002eout-Symbols"></a> +<div class="header"> +<p> +Next: <a href="#COFF-Symbols" accesskey="n" rel="next">COFF Symbols</a>, Previous: <a href="#Symbol-Type" accesskey="p" rel="previous">Symbol Type</a>, Up: <a href="#Symbol-Attributes" accesskey="u" rel="up">Symbol Attributes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbol-Attributes_003a-a_002eout"></a> +<h4 class="subsection">5.5.3 Symbol Attributes: <code>a.out</code></h4> + +<a name="index-a_002eout-symbol-attributes"></a> +<a name="index-symbol-attributes_002c-a_002eout"></a> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Symbol-Desc" accesskey="1">Symbol Desc</a>:</td><td> </td><td align="left" valign="top">Descriptor +</td></tr> +<tr><td align="left" valign="top">• <a href="#Symbol-Other" accesskey="2">Symbol Other</a>:</td><td> </td><td align="left" valign="top">Other +</td></tr> +</table> + +<hr> +<a name="Symbol-Desc"></a> +<div class="header"> +<p> +Next: <a href="#Symbol-Other" accesskey="n" rel="next">Symbol Other</a>, Up: <a href="#a_002eout-Symbols" accesskey="u" rel="up">a.out Symbols</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Descriptor"></a> +<h4 class="subsubsection">5.5.3.1 Descriptor</h4> + +<a name="index-descriptor_002c-of-a_002eout-symbol"></a> +<p>This is an arbitrary 16-bit value. You may establish a symbol’s +descriptor value by using a <code>.desc</code> statement +(see <a href="#Desc"><code>.desc</code></a>). A descriptor value means nothing to +<code>as</code>. +</p> +<hr> +<a name="Symbol-Other"></a> +<div class="header"> +<p> +Previous: <a href="#Symbol-Desc" accesskey="p" rel="previous">Symbol Desc</a>, Up: <a href="#a_002eout-Symbols" accesskey="u" rel="up">a.out Symbols</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Other"></a> +<h4 class="subsubsection">5.5.3.2 Other</h4> + +<a name="index-other-attribute_002c-of-a_002eout-symbol"></a> +<p>This is an arbitrary 8-bit value. It means nothing to <code>as</code>. +</p> +<hr> +<a name="COFF-Symbols"></a> +<div class="header"> +<p> +Next: <a href="#SOM-Symbols" accesskey="n" rel="next">SOM Symbols</a>, Previous: <a href="#a_002eout-Symbols" accesskey="p" rel="previous">a.out Symbols</a>, Up: <a href="#Symbol-Attributes" accesskey="u" rel="up">Symbol Attributes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbol-Attributes-for-COFF"></a> +<h4 class="subsection">5.5.4 Symbol Attributes for COFF</h4> + +<a name="index-COFF-symbol-attributes"></a> +<a name="index-symbol-attributes_002c-COFF"></a> + +<p>The COFF format supports a multitude of auxiliary symbol attributes; +like the primary symbol attributes, they are set between <code>.def</code> and +<code>.endef</code> directives. +</p> +<a name="Primary-Attributes"></a> +<h4 class="subsubsection">5.5.4.1 Primary Attributes</h4> + +<a name="index-primary-attributes_002c-COFF-symbols"></a> +<p>The symbol name is set with <code>.def</code>; the value and type, +respectively, with <code>.val</code> and <code>.type</code>. +</p> +<a name="Auxiliary-Attributes"></a> +<h4 class="subsubsection">5.5.4.2 Auxiliary Attributes</h4> + +<a name="index-auxiliary-attributes_002c-COFF-symbols"></a> +<p>The <code>as</code> directives <code>.dim</code>, <code>.line</code>, <code>.scl</code>, +<code>.size</code>, <code>.tag</code>, and <code>.weak</code> can generate auxiliary symbol +table information for COFF. +</p> +<hr> +<a name="SOM-Symbols"></a> +<div class="header"> +<p> +Previous: <a href="#COFF-Symbols" accesskey="p" rel="previous">COFF Symbols</a>, Up: <a href="#Symbol-Attributes" accesskey="u" rel="up">Symbol Attributes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbol-Attributes-for-SOM"></a> +<h4 class="subsection">5.5.5 Symbol Attributes for SOM</h4> + +<a name="index-SOM-symbol-attributes"></a> +<a name="index-symbol-attributes_002c-SOM"></a> + +<p>The SOM format for the HPPA supports a multitude of symbol attributes set with +the <code>.EXPORT</code> and <code>.IMPORT</code> directives. +</p> +<p>The attributes are described in <cite>HP9000 Series 800 Assembly +Language Reference Manual</cite> (HP 92432-90001) under the <code>IMPORT</code> and +<code>EXPORT</code> assembler directive documentation. +</p> +<hr> +<a name="Expressions"></a> +<div class="header"> +<p> +Next: <a href="#Pseudo-Ops" accesskey="n" rel="next">Pseudo Ops</a>, Previous: <a href="#Symbols" accesskey="p" rel="previous">Symbols</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Expressions-1"></a> +<h2 class="chapter">6 Expressions</h2> + +<a name="index-expressions"></a> +<a name="index-addresses"></a> +<a name="index-numeric-values"></a> +<p>An <em>expression</em> specifies an address or numeric value. +Whitespace may precede and/or follow an expression. +</p> +<p>The result of an expression must be an absolute number, or else an offset into +a particular section. If an expression is not absolute, and there is not +enough information when <code>as</code> sees the expression to know its +section, a second pass over the source program might be necessary to interpret +the expression—but the second pass is currently not implemented. +<code>as</code> aborts with an error message in this situation. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Empty-Exprs" accesskey="1">Empty Exprs</a>:</td><td> </td><td align="left" valign="top">Empty Expressions +</td></tr> +<tr><td align="left" valign="top">• <a href="#Integer-Exprs" accesskey="2">Integer Exprs</a>:</td><td> </td><td align="left" valign="top">Integer Expressions +</td></tr> +</table> + +<hr> +<a name="Empty-Exprs"></a> +<div class="header"> +<p> +Next: <a href="#Integer-Exprs" accesskey="n" rel="next">Integer Exprs</a>, Up: <a href="#Expressions" accesskey="u" rel="up">Expressions</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Empty-Expressions"></a> +<h3 class="section">6.1 Empty Expressions</h3> + +<a name="index-empty-expressions"></a> +<a name="index-expressions_002c-empty"></a> +<p>An empty expression has no value: it is just whitespace or null. +Wherever an absolute expression is required, you may omit the +expression, and <code>as</code> assumes a value of (absolute) 0. This +is compatible with other assemblers. +</p> +<hr> +<a name="Integer-Exprs"></a> +<div class="header"> +<p> +Previous: <a href="#Empty-Exprs" accesskey="p" rel="previous">Empty Exprs</a>, Up: <a href="#Expressions" accesskey="u" rel="up">Expressions</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Integer-Expressions"></a> +<h3 class="section">6.2 Integer Expressions</h3> + +<a name="index-integer-expressions"></a> +<a name="index-expressions_002c-integer"></a> +<p>An <em>integer expression</em> is one or more <em>arguments</em> delimited +by <em>operators</em>. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Arguments" accesskey="1">Arguments</a>:</td><td> </td><td align="left" valign="top">Arguments +</td></tr> +<tr><td align="left" valign="top">• <a href="#Operators" accesskey="2">Operators</a>:</td><td> </td><td align="left" valign="top">Operators +</td></tr> +<tr><td align="left" valign="top">• <a href="#Prefix-Ops" accesskey="3">Prefix Ops</a>:</td><td> </td><td align="left" valign="top">Prefix Operators +</td></tr> +<tr><td align="left" valign="top">• <a href="#Infix-Ops" accesskey="4">Infix Ops</a>:</td><td> </td><td align="left" valign="top">Infix Operators +</td></tr> +</table> + +<hr> +<a name="Arguments"></a> +<div class="header"> +<p> +Next: <a href="#Operators" accesskey="n" rel="next">Operators</a>, Up: <a href="#Integer-Exprs" accesskey="u" rel="up">Integer Exprs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Arguments-1"></a> +<h4 class="subsection">6.2.1 Arguments</h4> + +<a name="index-expression-arguments"></a> +<a name="index-arguments-in-expressions"></a> +<a name="index-operands-in-expressions"></a> +<a name="index-arithmetic-operands"></a> +<p><em>Arguments</em> are symbols, numbers or subexpressions. In other +contexts arguments are sometimes called “arithmetic operands”. In +this manual, to avoid confusing them with the “instruction operands” of +the machine language, we use the term “argument” to refer to parts of +expressions only, reserving the word “operand” to refer only to machine +instruction operands. +</p> +<p>Symbols are evaluated to yield {<var>section</var> <var>NNN</var>} where +<var>section</var> is one of text, data, bss, absolute, +or undefined. <var>NNN</var> is a signed, 2’s complement 32 bit +integer. +</p> +<p>Numbers are usually integers. +</p> +<p>A number can be a flonum or bignum. In this case, you are warned +that only the low order 32 bits are used, and <code>as</code> pretends +these 32 bits are an integer. You may write integer-manipulating +instructions that act on exotic constants, compatible with other +assemblers. +</p> +<a name="index-subexpressions"></a> +<p>Subexpressions are a left parenthesis ‘<samp>(</samp>’ followed by an integer +expression, followed by a right parenthesis ‘<samp>)</samp>’; or a prefix +operator followed by an argument. +</p> +<hr> +<a name="Operators"></a> +<div class="header"> +<p> +Next: <a href="#Prefix-Ops" accesskey="n" rel="next">Prefix Ops</a>, Previous: <a href="#Arguments" accesskey="p" rel="previous">Arguments</a>, Up: <a href="#Integer-Exprs" accesskey="u" rel="up">Integer Exprs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Operators-1"></a> +<h4 class="subsection">6.2.2 Operators</h4> + +<a name="index-operators_002c-in-expressions"></a> +<a name="index-arithmetic-functions"></a> +<a name="index-functions_002c-in-expressions"></a> +<p><em>Operators</em> are arithmetic functions, like <code>+</code> or <code>%</code>. Prefix +operators are followed by an argument. Infix operators appear +between their arguments. Operators may be preceded and/or followed by +whitespace. +</p> +<hr> +<a name="Prefix-Ops"></a> +<div class="header"> +<p> +Next: <a href="#Infix-Ops" accesskey="n" rel="next">Infix Ops</a>, Previous: <a href="#Operators" accesskey="p" rel="previous">Operators</a>, Up: <a href="#Integer-Exprs" accesskey="u" rel="up">Integer Exprs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Prefix-Operator"></a> +<h4 class="subsection">6.2.3 Prefix Operator</h4> + +<a name="index-prefix-operators"></a> +<p><code>as</code> has the following <em>prefix operators</em>. They each take +one argument, which must be absolute. +</p> + +<dl compact="compact"> +<dt><code>-</code></dt> +<dd><p><em>Negation</em>. Two’s complement negation. +</p></dd> +<dt><code>~</code></dt> +<dd><p><em>Complementation</em>. Bitwise not. +</p></dd> +</dl> + + +<hr> +<a name="Infix-Ops"></a> +<div class="header"> +<p> +Previous: <a href="#Prefix-Ops" accesskey="p" rel="previous">Prefix Ops</a>, Up: <a href="#Integer-Exprs" accesskey="u" rel="up">Integer Exprs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Infix-Operators"></a> +<h4 class="subsection">6.2.4 Infix Operators</h4> + +<a name="index-infix-operators"></a> +<a name="index-operators_002c-permitted-arguments"></a> +<p><em>Infix operators</em> take two arguments, one on either side. Operators +have precedence, but operations with equal precedence are performed left +to right. Apart from <code>+</code> or <samp>-</samp>, both arguments must be +absolute, and the result is absolute. +</p> +<ol> +<li><a name="index-operator-precedence"></a> +<a name="index-precedence-of-operators"></a> + +</li><li> Highest Precedence + +<dl compact="compact"> +<dt><code>*</code></dt> +<dd><p><em>Multiplication</em>. +</p> +</dd> +<dt><code>/</code></dt> +<dd><p><em>Division</em>. Truncation is the same as the C operator ‘<samp>/</samp>’ +</p> +</dd> +<dt><code>%</code></dt> +<dd><p><em>Remainder</em>. +</p> +</dd> +<dt><code><<</code></dt> +<dd><p><em>Shift Left</em>. Same as the C operator ‘<samp><<</samp>’. +</p> +</dd> +<dt><code>>></code></dt> +<dd><p><em>Shift Right</em>. Same as the C operator ‘<samp>>></samp>’. +</p></dd> +</dl> + +</li><li> Intermediate precedence + +<dl compact="compact"> +<dt><code>|</code></dt> +<dd> +<p><em>Bitwise Inclusive Or</em>. +</p> +</dd> +<dt><code>&</code></dt> +<dd><p><em>Bitwise And</em>. +</p> +</dd> +<dt><code>^</code></dt> +<dd><p><em>Bitwise Exclusive Or</em>. +</p> +</dd> +<dt><code>!</code></dt> +<dd><p><em>Bitwise Or Not</em>. +</p></dd> +</dl> + +</li><li> Low Precedence + +<dl compact="compact"> +<dd><a name="index-addition_002c-permitted-arguments"></a> +<a name="index-plus_002c-permitted-arguments"></a> +<a name="index-arguments-for-addition"></a> +</dd> +<dt><code>+</code></dt> +<dd><p><em>Addition</em>. If either argument is absolute, the result has the section of +the other argument. You may not add together arguments from different +sections. +</p> +<a name="index-subtraction_002c-permitted-arguments"></a> +<a name="index-minus_002c-permitted-arguments"></a> +<a name="index-arguments-for-subtraction"></a> +</dd> +<dt><code>-</code></dt> +<dd><p><em>Subtraction</em>. If the right argument is absolute, the +result has the section of the left argument. +If both arguments are in the same section, the result is absolute. +You may not subtract arguments from different sections. +</p> +<a name="index-comparison-expressions"></a> +<a name="index-expressions_002c-comparison"></a> +</dd> +<dt><code>==</code></dt> +<dd><p><em>Is Equal To</em> +</p></dd> +<dt><code><></code></dt> +<dt><code>!=</code></dt> +<dd><p><em>Is Not Equal To</em> +</p></dd> +<dt><code><</code></dt> +<dd><p><em>Is Less Than</em> +</p></dd> +<dt><code>></code></dt> +<dd><p><em>Is Greater Than</em> +</p></dd> +<dt><code>>=</code></dt> +<dd><p><em>Is Greater Than Or Equal To</em> +</p></dd> +<dt><code><=</code></dt> +<dd><p><em>Is Less Than Or Equal To</em> +</p> +<p>The comparison operators can be used as infix operators. A true result has a +value of -1 whereas a false result has a value of 0. Note, these operators +perform signed comparisons. +</p></dd> +</dl> + +</li><li> Lowest Precedence + +<dl compact="compact"> +<dt><code>&&</code></dt> +<dd><p><em>Logical And</em>. +</p> +</dd> +<dt><code>||</code></dt> +<dd><p><em>Logical Or</em>. +</p> +<p>These two logical operations can be used to combine the results of sub +expressions. Note, unlike the comparison operators a true result returns a +value of 1 but a false result does still return 0. Also note that the logical +or operator has a slightly lower precedence than logical and. +</p> +</dd> +</dl> +</li></ol> + +<p>In short, it’s only meaningful to add or subtract the <em>offsets</em> in an +address; you can only have a defined section in one of the two arguments. +</p> +<hr> +<a name="Pseudo-Ops"></a> +<div class="header"> +<p> +Next: <a href="#Object-Attributes" accesskey="n" rel="next">Object Attributes</a>, Previous: <a href="#Expressions" accesskey="p" rel="previous">Expressions</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives"></a> +<h2 class="chapter">7 Assembler Directives</h2> + +<a name="index-directives_002c-machine-independent"></a> +<a name="index-pseudo_002dops_002c-machine-independent"></a> +<a name="index-machine-independent-directives"></a> +<p>All assembler directives have names that begin with a period (‘<samp>.</samp>’). +The names are case insensitive for most targets, and usually written +in lower case. +</p> +<p>This chapter discusses directives that are available regardless of the +target machine configuration for the <small>GNU</small> assembler. +Some machine configurations provide additional directives. +See <a href="#Machine-Dependencies">Machine Dependencies</a>. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Abort" accesskey="1">Abort</a>:</td><td> </td><td align="left" valign="top"><code>.abort</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#ABORT-_0028COFF_0029" accesskey="2">ABORT (COFF)</a>:</td><td> </td><td align="left" valign="top"><code>.ABORT</code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Align" accesskey="3">Align</a>:</td><td> </td><td align="left" valign="top"><code>.align [<var>abs-expr</var>[, <var>abs-expr</var>[, <var>abs-expr</var>]]]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Altmacro" accesskey="4">Altmacro</a>:</td><td> </td><td align="left" valign="top"><code>.altmacro</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Ascii" accesskey="5">Ascii</a>:</td><td> </td><td align="left" valign="top"><code>.ascii "<var>string</var>"</code>… +</td></tr> +<tr><td align="left" valign="top">• <a href="#Asciz" accesskey="6">Asciz</a>:</td><td> </td><td align="left" valign="top"><code>.asciz "<var>string</var>"</code>… +</td></tr> +<tr><td align="left" valign="top">• <a href="#Attach_005fto_005fgroup" accesskey="7">Attach_to_group</a>:</td><td> </td><td align="left" valign="top"><code>.attach_to_group <var>name</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Balign" accesskey="8">Balign</a>:</td><td> </td><td align="left" valign="top"><code>.balign [<var>abs-expr</var>[, <var>abs-expr</var>]]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Bss" accesskey="9">Bss</a>:</td><td> </td><td align="left" valign="top"><code>.bss <var>subsection</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Bundle-directives">Bundle directives</a>:</td><td> </td><td align="left" valign="top"><code>.bundle_align_mode <var>abs-expr</var></code>, etc +</td></tr> +<tr><td align="left" valign="top">• <a href="#Byte">Byte</a>:</td><td> </td><td align="left" valign="top"><code>.byte <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#CFI-directives">CFI directives</a>:</td><td> </td><td align="left" valign="top"><code>.cfi_startproc [simple]</code>, <code>.cfi_endproc</code>, etc. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Comm">Comm</a>:</td><td> </td><td align="left" valign="top"><code>.comm <var>symbol</var> , <var>length</var> </code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Data">Data</a>:</td><td> </td><td align="left" valign="top"><code>.data <var>subsection</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Dc">Dc</a>:</td><td> </td><td align="left" valign="top"><code>.dc[<var>size</var>] <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Dcb">Dcb</a>:</td><td> </td><td align="left" valign="top"><code>.dcb[<var>size</var>] <var>number</var> [,<var>fill</var>]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Ds">Ds</a>:</td><td> </td><td align="left" valign="top"><code>.ds[<var>size</var>] <var>number</var> [,<var>fill</var>]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Def">Def</a>:</td><td> </td><td align="left" valign="top"><code>.def <var>name</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Desc">Desc</a>:</td><td> </td><td align="left" valign="top"><code>.desc <var>symbol</var>, <var>abs-expression</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Dim">Dim</a>:</td><td> </td><td align="left" valign="top"><code>.dim</code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Double">Double</a>:</td><td> </td><td align="left" valign="top"><code>.double <var>flonums</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Eject">Eject</a>:</td><td> </td><td align="left" valign="top"><code>.eject</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Else">Else</a>:</td><td> </td><td align="left" valign="top"><code>.else</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Elseif">Elseif</a>:</td><td> </td><td align="left" valign="top"><code>.elseif</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#End">End</a>:</td><td> </td><td align="left" valign="top"><code>.end</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Endef">Endef</a>:</td><td> </td><td align="left" valign="top"><code>.endef</code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Endfunc">Endfunc</a>:</td><td> </td><td align="left" valign="top"><code>.endfunc</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Endif">Endif</a>:</td><td> </td><td align="left" valign="top"><code>.endif</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Equ">Equ</a>:</td><td> </td><td align="left" valign="top"><code>.equ <var>symbol</var>, <var>expression</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Equiv">Equiv</a>:</td><td> </td><td align="left" valign="top"><code>.equiv <var>symbol</var>, <var>expression</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Eqv">Eqv</a>:</td><td> </td><td align="left" valign="top"><code>.eqv <var>symbol</var>, <var>expression</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Err">Err</a>:</td><td> </td><td align="left" valign="top"><code>.err</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Error">Error</a>:</td><td> </td><td align="left" valign="top"><code>.error <var>string</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Exitm">Exitm</a>:</td><td> </td><td align="left" valign="top"><code>.exitm</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Extern">Extern</a>:</td><td> </td><td align="left" valign="top"><code>.extern</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Fail">Fail</a>:</td><td> </td><td align="left" valign="top"><code>.fail</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#File">File</a>:</td><td> </td><td align="left" valign="top"><code>.file</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Fill">Fill</a>:</td><td> </td><td align="left" valign="top"><code>.fill <var>repeat</var> , <var>size</var> , <var>value</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Float">Float</a>:</td><td> </td><td align="left" valign="top"><code>.float <var>flonums</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Func">Func</a>:</td><td> </td><td align="left" valign="top"><code>.func</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Global">Global</a>:</td><td> </td><td align="left" valign="top"><code>.global <var>symbol</var></code>, <code>.globl <var>symbol</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Gnu_005fattribute">Gnu_attribute</a>:</td><td> </td><td align="left" valign="top"><code>.gnu_attribute <var>tag</var>,<var>value</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Hidden">Hidden</a>:</td><td> </td><td align="left" valign="top"><code>.hidden <var>names</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#hword">hword</a>:</td><td> </td><td align="left" valign="top"><code>.hword <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Ident">Ident</a>:</td><td> </td><td align="left" valign="top"><code>.ident</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#If">If</a>:</td><td> </td><td align="left" valign="top"><code>.if <var>absolute expression</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Incbin">Incbin</a>:</td><td> </td><td align="left" valign="top"><code>.incbin "<var>file</var>"[,<var>skip</var>[,<var>count</var>]]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Include">Include</a>:</td><td> </td><td align="left" valign="top"><code>.include "<var>file</var>"</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Int">Int</a>:</td><td> </td><td align="left" valign="top"><code>.int <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Internal">Internal</a>:</td><td> </td><td align="left" valign="top"><code>.internal <var>names</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Irp">Irp</a>:</td><td> </td><td align="left" valign="top"><code>.irp <var>symbol</var>,<var>values</var></code>… +</td></tr> +<tr><td align="left" valign="top">• <a href="#Irpc">Irpc</a>:</td><td> </td><td align="left" valign="top"><code>.irpc <var>symbol</var>,<var>values</var></code>… +</td></tr> +<tr><td align="left" valign="top">• <a href="#Lcomm">Lcomm</a>:</td><td> </td><td align="left" valign="top"><code>.lcomm <var>symbol</var> , <var>length</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Lflags">Lflags</a>:</td><td> </td><td align="left" valign="top"><code>.lflags</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Line">Line</a>:</td><td> </td><td align="left" valign="top"><code>.line <var>line-number</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Linkonce">Linkonce</a>:</td><td> </td><td align="left" valign="top"><code>.linkonce [<var>type</var>]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#List">List</a>:</td><td> </td><td align="left" valign="top"><code>.list</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Ln">Ln</a>:</td><td> </td><td align="left" valign="top"><code>.ln <var>line-number</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Loc">Loc</a>:</td><td> </td><td align="left" valign="top"><code>.loc <var>fileno</var> <var>lineno</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Loc_005fmark_005flabels">Loc_mark_labels</a>:</td><td> </td><td align="left" valign="top"><code>.loc_mark_labels <var>enable</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Local">Local</a>:</td><td> </td><td align="left" valign="top"><code>.local <var>names</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Long">Long</a>:</td><td> </td><td align="left" valign="top"><code>.long <var>expressions</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Macro">Macro</a>:</td><td> </td><td align="left" valign="top"><code>.macro <var>name</var> <var>args</var></code>… +</td></tr> +<tr><td align="left" valign="top">• <a href="#MRI">MRI</a>:</td><td> </td><td align="left" valign="top"><code>.mri <var>val</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Noaltmacro">Noaltmacro</a>:</td><td> </td><td align="left" valign="top"><code>.noaltmacro</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Nolist">Nolist</a>:</td><td> </td><td align="left" valign="top"><code>.nolist</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Nop">Nop</a>:</td><td> </td><td align="left" valign="top"><code>.nop</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Nops">Nops</a>:</td><td> </td><td align="left" valign="top"><code>.nops <var>size</var>[, <var>control</var>]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Octa">Octa</a>:</td><td> </td><td align="left" valign="top"><code>.octa <var>bignums</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Offset">Offset</a>:</td><td> </td><td align="left" valign="top"><code>.offset <var>loc</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Org">Org</a>:</td><td> </td><td align="left" valign="top"><code>.org <var>new-lc</var>, <var>fill</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#P2align">P2align</a>:</td><td> </td><td align="left" valign="top"><code>.p2align [<var>abs-expr</var>[, <var>abs-expr</var>[, <var>abs-expr</var>]]]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#PopSection">PopSection</a>:</td><td> </td><td align="left" valign="top"><code>.popsection</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Previous">Previous</a>:</td><td> </td><td align="left" valign="top"><code>.previous</code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Print">Print</a>:</td><td> </td><td align="left" valign="top"><code>.print <var>string</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Protected">Protected</a>:</td><td> </td><td align="left" valign="top"><code>.protected <var>names</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Psize">Psize</a>:</td><td> </td><td align="left" valign="top"><code>.psize <var>lines</var>, <var>columns</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Purgem">Purgem</a>:</td><td> </td><td align="left" valign="top"><code>.purgem <var>name</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#PushSection">PushSection</a>:</td><td> </td><td align="left" valign="top"><code>.pushsection <var>name</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Quad">Quad</a>:</td><td> </td><td align="left" valign="top"><code>.quad <var>bignums</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Reloc">Reloc</a>:</td><td> </td><td align="left" valign="top"><code>.reloc <var>offset</var>, <var>reloc_name</var>[, <var>expression</var>]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Rept">Rept</a>:</td><td> </td><td align="left" valign="top"><code>.rept <var>count</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sbttl">Sbttl</a>:</td><td> </td><td align="left" valign="top"><code>.sbttl "<var>subheading</var>"</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Scl">Scl</a>:</td><td> </td><td align="left" valign="top"><code>.scl <var>class</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Section">Section</a>:</td><td> </td><td align="left" valign="top"><code>.section <var>name</var>[, <var>flags</var>]</code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Set">Set</a>:</td><td> </td><td align="left" valign="top"><code>.set <var>symbol</var>, <var>expression</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Short">Short</a>:</td><td> </td><td align="left" valign="top"><code>.short <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Single">Single</a>:</td><td> </td><td align="left" valign="top"><code>.single <var>flonums</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Size">Size</a>:</td><td> </td><td align="left" valign="top"><code>.size [<var>name</var> , <var>expression</var>]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Skip">Skip</a>:</td><td> </td><td align="left" valign="top"><code>.skip <var>size</var> [,<var>fill</var>]</code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Sleb128">Sleb128</a>:</td><td> </td><td align="left" valign="top"><code>.sleb128 <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Space">Space</a>:</td><td> </td><td align="left" valign="top"><code>.space <var>size</var> [,<var>fill</var>]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Stab">Stab</a>:</td><td> </td><td align="left" valign="top"><code>.stabd, .stabn, .stabs</code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#String">String</a>:</td><td> </td><td align="left" valign="top"><code>.string "<var>str</var>"</code>, <code>.string8 "<var>str</var>"</code>, <code>.string16 "<var>str</var>"</code>, <code>.string32 "<var>str</var>"</code>, <code>.string64 "<var>str</var>"</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Struct">Struct</a>:</td><td> </td><td align="left" valign="top"><code>.struct <var>expression</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#SubSection">SubSection</a>:</td><td> </td><td align="left" valign="top"><code>.subsection</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Symver">Symver</a>:</td><td> </td><td align="left" valign="top"><code>.symver <var>name</var>,<var>name2@nodename</var>[,<var>visibility</var>]</code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Tag">Tag</a>:</td><td> </td><td align="left" valign="top"><code>.tag <var>structname</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Text">Text</a>:</td><td> </td><td align="left" valign="top"><code>.text <var>subsection</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Title">Title</a>:</td><td> </td><td align="left" valign="top"><code>.title "<var>heading</var>"</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Tls_005fcommon">Tls_common</a>:</td><td> </td><td align="left" valign="top"><code>.tls_common <var>symbol</var>, <var>length</var>[, <var>alignment</var>]</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Type">Type</a>:</td><td> </td><td align="left" valign="top"><code>.type <<var>int</var> | <var>name</var> , <var>type description</var>></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Uleb128">Uleb128</a>:</td><td> </td><td align="left" valign="top"><code>.uleb128 <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Val">Val</a>:</td><td> </td><td align="left" valign="top"><code>.val <var>addr</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Version">Version</a>:</td><td> </td><td align="left" valign="top"><code>.version "<var>string</var>"</code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#VTableEntry">VTableEntry</a>:</td><td> </td><td align="left" valign="top"><code>.vtable_entry <var>table</var>, <var>offset</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#VTableInherit">VTableInherit</a>:</td><td> </td><td align="left" valign="top"><code>.vtable_inherit <var>child</var>, <var>parent</var></code> +</td></tr> +<tr><th colspan="3" align="left" valign="top"><pre class="menu-comment"> +</pre></th></tr><tr><td align="left" valign="top">• <a href="#Warning">Warning</a>:</td><td> </td><td align="left" valign="top"><code>.warning <var>string</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Weak">Weak</a>:</td><td> </td><td align="left" valign="top"><code>.weak <var>names</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Weakref">Weakref</a>:</td><td> </td><td align="left" valign="top"><code>.weakref <var>alias</var>, <var>symbol</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Word">Word</a>:</td><td> </td><td align="left" valign="top"><code>.word <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Zero">Zero</a>:</td><td> </td><td align="left" valign="top"><code>.zero <var>size</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#g_t2byte">2byte</a>:</td><td> </td><td align="left" valign="top"><code>.2byte <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#g_t4byte">4byte</a>:</td><td> </td><td align="left" valign="top"><code>.4byte <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#g_t8byte">8byte</a>:</td><td> </td><td align="left" valign="top"><code>.8byte <var>expressions</var></code> +</td></tr> +<tr><td align="left" valign="top">• <a href="#Deprecated">Deprecated</a>:</td><td> </td><td align="left" valign="top">Deprecated Directives +</td></tr> +</table> + +<hr> +<a name="Abort"></a> +<div class="header"> +<p> +Next: <a href="#ABORT-_0028COFF_0029" accesskey="n" rel="next">ABORT (COFF)</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eabort"></a> +<h3 class="section">7.1 <code>.abort</code></h3> + +<a name="index-abort-directive"></a> +<a name="index-stopping-the-assembly"></a> +<p>This directive stops the assembly immediately. It is for +compatibility with other assemblers. The original idea was that the +assembly language source would be piped into the assembler. If the sender +of the source quit, it could use this directive tells <code>as</code> to +quit also. One day <code>.abort</code> will not be supported. +</p> +<hr> +<a name="ABORT-_0028COFF_0029"></a> +<div class="header"> +<p> +Next: <a href="#Align" accesskey="n" rel="next">Align</a>, Previous: <a href="#Abort" accesskey="p" rel="previous">Abort</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eABORT-_0028COFF_0029"></a> +<h3 class="section">7.2 <code>.ABORT</code> (COFF)</h3> + +<a name="index-ABORT-directive"></a> +<p>When producing COFF output, <code>as</code> accepts this directive as a +synonym for ‘<samp>.abort</samp>’. +</p> + +<hr> +<a name="Align"></a> +<div class="header"> +<p> +Next: <a href="#Altmacro" accesskey="n" rel="next">Altmacro</a>, Previous: <a href="#ABORT-_0028COFF_0029" accesskey="p" rel="previous">ABORT (COFF)</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ealign-_005babs_002dexpr_005b_002c-abs_002dexpr_005b_002c-abs_002dexpr_005d_005d_005d"></a> +<h3 class="section">7.3 <code>.align [<var>abs-expr</var>[, <var>abs-expr</var>[, <var>abs-expr</var>]]]</code></h3> + +<a name="index-padding-the-location-counter"></a> +<a name="index-align-directive"></a> +<p>Pad the location counter (in the current subsection) to a particular storage +boundary. The first expression (which must be absolute) is the alignment +required, as described below. If this expression is omitted then a default +value of 0 is used, effectively disabling alignment requirements. +</p> +<p>The second expression (also absolute) gives the fill value to be stored in the +padding bytes. It (and the comma) may be omitted. If it is omitted, the +padding bytes are normally zero. However, on most systems, if the section is +marked as containing code and the fill value is omitted, the space is filled +with no-op instructions. +</p> +<p>The third expression is also absolute, and is also optional. If it is present, +it is the maximum number of bytes that should be skipped by this alignment +directive. If doing the alignment would require skipping more bytes than the +specified maximum, then the alignment is not done at all. You can omit the +fill value (the second argument) entirely by simply using two commas after the +required alignment; this can be useful if you want the alignment to be filled +with no-op instructions when appropriate. +</p> +<p>The way the required alignment is specified varies from system to system. +For the arc, hppa, i386 using ELF, iq2000, m68k, or1k, +s390, sparc, tic4x and xtensa, the first expression is the +alignment request in bytes. For example ‘<samp>.align 8</samp>’ advances +the location counter until it is a multiple of 8. If the location counter +is already a multiple of 8, no change is needed. For the tic54x, the +first expression is the alignment request in words. +</p> +<p>For other systems, including ppc, i386 using a.out format, arm and +strongarm, it is the +number of low-order zero bits the location counter must have after +advancement. For example ‘<samp>.align 3</samp>’ advances the location +counter until it is a multiple of 8. If the location counter is already a +multiple of 8, no change is needed. +</p> +<p>This inconsistency is due to the different behaviors of the various +native assemblers for these systems which GAS must emulate. +GAS also provides <code>.balign</code> and <code>.p2align</code> directives, +described later, which have a consistent behavior across all +architectures (but are specific to GAS). +</p> +<hr> +<a name="Altmacro"></a> +<div class="header"> +<p> +Next: <a href="#Ascii" accesskey="n" rel="next">Ascii</a>, Previous: <a href="#Align" accesskey="p" rel="previous">Align</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ealtmacro"></a> +<h3 class="section">7.4 <code>.altmacro</code></h3> +<p>Enable alternate macro mode, enabling: +</p> +<dl compact="compact"> +<dt><code>LOCAL <var>name</var> [ , … ]</code> +<a name="index-LOCAL-name-_005b-_002c-_2026-_005d"></a> +</dt> +<dd><p>One additional directive, <code>LOCAL</code>, is available. It is used to +generate a string replacement for each of the <var>name</var> arguments, and +replace any instances of <var>name</var> in each macro expansion. The +replacement string is unique in the assembly, and different for each +separate macro expansion. <code>LOCAL</code> allows you to write macros that +define symbols, without fear of conflict between separate macro expansions. +</p> +</dd> +<dt><code>String delimiters</code> +<a name="index-String-delimiters"></a> +</dt> +<dd><p>You can write strings delimited in these other ways besides +<code>"<var>string</var>"</code>: +</p> +<dl compact="compact"> +<dt><code>'<var>string</var>'</code></dt> +<dd><p>You can delimit strings with single-quote characters. +</p> +</dd> +<dt><code><<var>string</var>></code></dt> +<dd><p>You can delimit strings with matching angle brackets. +</p></dd> +</dl> + +</dd> +<dt><code>single-character string escape</code> +<a name="index-single_002dcharacter-string-escape"></a> +</dt> +<dd><p>To include any single character literally in a string (even if the +character would otherwise have some special meaning), you can prefix the +character with ‘<samp>!</samp>’ (an exclamation mark). For example, you can +write ‘<samp><4.3 !> 5.4!!></samp>’ to get the literal text ‘<samp>4.3 > 5.4!</samp>’. +</p> +</dd> +<dt><code>Expression results as strings</code> +<a name="index-Expression-results-as-strings"></a> +</dt> +<dd><p>You can write ‘<samp>%<var>expr</var></samp>’ to evaluate the expression <var>expr</var> +and use the result as a string. +</p></dd> +</dl> + +<hr> +<a name="Ascii"></a> +<div class="header"> +<p> +Next: <a href="#Asciz" accesskey="n" rel="next">Asciz</a>, Previous: <a href="#Altmacro" accesskey="p" rel="previous">Altmacro</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eascii-_0022string_0022_2026"></a> +<h3 class="section">7.5 <code>.ascii "<var>string</var>"</code>…</h3> + +<a name="index-ascii-directive"></a> +<a name="index-string-literals"></a> +<p><code>.ascii</code> expects zero or more string literals (see <a href="#Strings">Strings</a>) +separated by commas. It assembles each string (with no automatic +trailing zero byte) into consecutive addresses. +</p> +<hr> +<a name="Asciz"></a> +<div class="header"> +<p> +Next: <a href="#Attach_005fto_005fgroup" accesskey="n" rel="next">Attach_to_group</a>, Previous: <a href="#Ascii" accesskey="p" rel="previous">Ascii</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002easciz-_0022string_0022_2026"></a> +<h3 class="section">7.6 <code>.asciz "<var>string</var>"</code>…</h3> + +<a name="index-asciz-directive"></a> +<a name="index-zero_002dterminated-strings"></a> +<a name="index-null_002dterminated-strings"></a> +<p><code>.asciz</code> is just like <code>.ascii</code>, but each string is followed by +a zero byte. The “z” in ‘<samp>.asciz</samp>’ stands for “zero”. Note that +multiple string arguments not separated by commas will be concatenated +together and only one final zero byte will be stored. +</p> +<hr> +<a name="Attach_005fto_005fgroup"></a> +<div class="header"> +<p> +Next: <a href="#Balign" accesskey="n" rel="next">Balign</a>, Previous: <a href="#Asciz" accesskey="p" rel="previous">Asciz</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eattach_005fto_005fgroup-name"></a> +<h3 class="section">7.7 <code>.attach_to_group <var>name</var></code></h3> +<p>Attaches the current section to the named group. This is like declaring +the section with the <code>G</code> attribute, but can be done after the section +has been created. Note if the group section does not exist at the point that +this directive is used then it will be created. +</p> +<hr> +<a name="Balign"></a> +<div class="header"> +<p> +Next: <a href="#Bss" accesskey="n" rel="next">Bss</a>, Previous: <a href="#Attach_005fto_005fgroup" accesskey="p" rel="previous">Attach_to_group</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ebalign_005bwl_005d-_005babs_002dexpr_005b_002c-abs_002dexpr_005b_002c-abs_002dexpr_005d_005d_005d"></a> +<h3 class="section">7.8 <code>.balign[wl] [<var>abs-expr</var>[, <var>abs-expr</var>[, <var>abs-expr</var>]]]</code></h3> + +<a name="index-padding-the-location-counter-given-number-of-bytes"></a> +<a name="index-balign-directive"></a> +<p>Pad the location counter (in the current subsection) to a particular +storage boundary. The first expression (which must be absolute) is the +alignment request in bytes. For example ‘<samp>.balign 8</samp>’ advances +the location counter until it is a multiple of 8. If the location counter +is already a multiple of 8, no change is needed. If the expression is omitted +then a default value of 0 is used, effectively disabling alignment requirements. +</p> +<p>The second expression (also absolute) gives the fill value to be stored in the +padding bytes. It (and the comma) may be omitted. If it is omitted, the +padding bytes are normally zero. However, on most systems, if the section is +marked as containing code and the fill value is omitted, the space is filled +with no-op instructions. +</p> +<p>The third expression is also absolute, and is also optional. If it is present, +it is the maximum number of bytes that should be skipped by this alignment +directive. If doing the alignment would require skipping more bytes than the +specified maximum, then the alignment is not done at all. You can omit the +fill value (the second argument) entirely by simply using two commas after the +required alignment; this can be useful if you want the alignment to be filled +with no-op instructions when appropriate. +</p> +<a name="index-balignw-directive"></a> +<a name="index-balignl-directive"></a> +<p>The <code>.balignw</code> and <code>.balignl</code> directives are variants of the +<code>.balign</code> directive. The <code>.balignw</code> directive treats the fill +pattern as a two byte word value. The <code>.balignl</code> directives treats the +fill pattern as a four byte longword value. For example, <code>.balignw +4,0x368d</code> will align to a multiple of 4. If it skips two bytes, they will be +filled in with the value 0x368d (the exact placement of the bytes depends upon +the endianness of the processor). If it skips 1 or 3 bytes, the fill value is +undefined. +</p> +<hr> +<a name="Bss"></a> +<div class="header"> +<p> +Next: <a href="#Bundle-directives" accesskey="n" rel="next">Bundle directives</a>, Previous: <a href="#Balign" accesskey="p" rel="previous">Balign</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ebss-subsection"></a> +<h3 class="section">7.9 <code>.bss <var>subsection</var></code></h3> +<a name="index-bss-directive"></a> + +<p><code>.bss</code> tells <code>as</code> to assemble the following statements +onto the end of the bss section. +For ELF based targets an optional <var>subsection</var> expression (which must +evaluate to a positive integer) can be provided. In this case the statements +are appended to the end of the indicated bss subsection. +</p> +<hr> +<a name="Bundle-directives"></a> +<div class="header"> +<p> +Next: <a href="#Byte" accesskey="n" rel="next">Byte</a>, Previous: <a href="#Bss" accesskey="p" rel="previous">Bss</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Bundle-directives-1"></a> +<h3 class="section">7.10 Bundle directives</h3> +<a name="g_t_002ebundle_005falign_005fmode-abs_002dexpr"></a> +<h4 class="subsection">7.10.1 <code>.bundle_align_mode <var>abs-expr</var></code></h4> +<a name="index-bundle_005falign_005fmode-directive"></a> +<a name="index-bundle"></a> +<a name="index-instruction-bundle"></a> +<a name="index-aligned-instruction-bundle"></a> +<p><code>.bundle_align_mode</code> enables or disables <em>aligned instruction +bundle</em> mode. In this mode, sequences of adjacent instructions are grouped +into fixed-sized <em>bundles</em>. If the argument is zero, this mode is +disabled (which is the default state). If the argument it not zero, it +gives the size of an instruction bundle as a power of two (as for the +<code>.p2align</code> directive, see <a href="#P2align">P2align</a>). +</p> +<p>For some targets, it’s an ABI requirement that no instruction may span a +certain aligned boundary. A <em>bundle</em> is simply a sequence of +instructions that starts on an aligned boundary. For example, if +<var>abs-expr</var> is <code>5</code> then the bundle size is 32, so each aligned +chunk of 32 bytes is a bundle. When aligned instruction bundle mode is in +effect, no single instruction may span a boundary between bundles. If an +instruction would start too close to the end of a bundle for the length of +that particular instruction to fit within the bundle, then the space at the +end of that bundle is filled with no-op instructions so the instruction +starts in the next bundle. As a corollary, it’s an error if any single +instruction’s encoding is longer than the bundle size. +</p> +<a name="g_t_002ebundle_005flock-and-_002ebundle_005funlock"></a> +<h4 class="subsection">7.10.2 <code>.bundle_lock</code> and <code>.bundle_unlock</code></h4> +<a name="index-bundle_005flock-directive"></a> +<a name="index-bundle_005funlock-directive"></a> +<p>The <code>.bundle_lock</code> and directive <code>.bundle_unlock</code> directives +allow explicit control over instruction bundle padding. These directives +are only valid when <code>.bundle_align_mode</code> has been used to enable +aligned instruction bundle mode. It’s an error if they appear when +<code>.bundle_align_mode</code> has not been used at all, or when the last +directive was <code><span class="nolinebreak">.bundle_align_mode</span> 0</code><!-- /@w -->. +</p> +<a name="index-bundle_002dlocked"></a> +<p>For some targets, it’s an ABI requirement that certain instructions may +appear only as part of specified permissible sequences of multiple +instructions, all within the same bundle. A pair of <code>.bundle_lock</code> +and <code>.bundle_unlock</code> directives define a <em>bundle-locked</em> +instruction sequence. For purposes of aligned instruction bundle mode, a +sequence starting with <code>.bundle_lock</code> and ending with +<code>.bundle_unlock</code> is treated as a single instruction. That is, the +entire sequence must fit into a single bundle and may not span a bundle +boundary. If necessary, no-op instructions will be inserted before the +first instruction of the sequence so that the whole sequence starts on an +aligned bundle boundary. It’s an error if the sequence is longer than the +bundle size. +</p> +<p>For convenience when using <code>.bundle_lock</code> and <code>.bundle_unlock</code> +inside assembler macros (see <a href="#Macro">Macro</a>), bundle-locked sequences may be +nested. That is, a second <code>.bundle_lock</code> directive before the next +<code>.bundle_unlock</code> directive has no effect except that it must be +matched by another closing <code>.bundle_unlock</code> so that there is the +same number of <code>.bundle_lock</code> and <code>.bundle_unlock</code> directives. +</p> +<hr> +<a name="Byte"></a> +<div class="header"> +<p> +Next: <a href="#CFI-directives" accesskey="n" rel="next">CFI directives</a>, Previous: <a href="#Bundle-directives" accesskey="p" rel="previous">Bundle directives</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ebyte-expressions"></a> +<h3 class="section">7.11 <code>.byte <var>expressions</var></code></h3> + +<a name="index-byte-directive"></a> +<a name="index-integers_002c-one-byte"></a> +<p><code>.byte</code> expects zero or more expressions, separated by commas. +Each expression is assembled into the next byte. +</p> +<p>Note - this directive is not intended for encoding instructions, and it will +not trigger effects like DWARF line number generation. Instead some targets +support special directives for encoding arbitrary binary sequences as +instructions such as <code>.insn</code> or <code>.inst</code>. +</p> +<hr> +<a name="CFI-directives"></a> +<div class="header"> +<p> +Next: <a href="#Comm" accesskey="n" rel="next">Comm</a>, Previous: <a href="#Byte" accesskey="p" rel="previous">Byte</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="CFI-directives-1"></a> +<h3 class="section">7.12 CFI directives</h3> +<a name="g_t_002ecfi_005fsections-section_005flist"></a> +<h4 class="subsection">7.12.1 <code>.cfi_sections <var>section_list</var></code></h4> +<a name="index-cfi_005fsections-directive"></a> +<p><code>.cfi_sections</code> may be used to specify whether CFI directives +should emit <code>.eh_frame</code> section, <code>.debug_frame</code> section and/or +<code>.sframe</code> section. If <var>section_list</var> contains <code>.eh_frame</code>, +<code>.eh_frame</code> is emitted, if <var>section_list</var> contains +<code>.debug_frame</code>, <code>.debug_frame</code> is emitted, and finally, if +<var>section_list</var> contains <code>.sframe</code>, <code>.sframe</code> is emitted. +To emit multiple sections, specify them together in a list. For example, to +emit both <code>.eh_frame</code> and <code>.debug_frame</code>, use +<code>.eh_frame, .debug_frame</code>. The default if this directive is not used +is <code>.cfi_sections .eh_frame</code>. +</p> +<p>On targets that support compact unwinding tables these can be generated +by specifying <code>.eh_frame_entry</code> instead of <code>.eh_frame</code>. +</p> +<p>Some targets may support an additional name, such as <code>.c6xabi.exidx</code> +which is used by the target. +</p> +<p>The <code>.cfi_sections</code> directive can be repeated, with the same or different +arguments, provided that CFI generation has not yet started. Once CFI +generation has started however the section list is fixed and any attempts to +redefine it will result in an error. +</p> +<a name="g_t_002ecfi_005fstartproc-_005bsimple_005d"></a> +<h4 class="subsection">7.12.2 <code>.cfi_startproc [simple]</code></h4> +<a name="index-cfi_005fstartproc-directive"></a> +<p><code>.cfi_startproc</code> is used at the beginning of each function that +should have an entry in <code>.eh_frame</code>. It initializes some internal +data structures. Don’t forget to close the function by +<code>.cfi_endproc</code>. +</p> +<p>Unless <code>.cfi_startproc</code> is used along with parameter <code>simple</code> +it also emits some architecture dependent initial CFI instructions. +</p> +<a name="g_t_002ecfi_005fendproc"></a> +<h4 class="subsection">7.12.3 <code>.cfi_endproc</code></h4> +<a name="index-cfi_005fendproc-directive"></a> +<p><code>.cfi_endproc</code> is used at the end of a function where it closes its +unwind entry previously opened by +<code>.cfi_startproc</code>, and emits it to <code>.eh_frame</code>. +</p> +<a name="g_t_002ecfi_005fpersonality-encoding-_005b_002c-exp_005d"></a> +<h4 class="subsection">7.12.4 <code>.cfi_personality <var>encoding</var> [, <var>exp</var>]</code></h4> +<a name="index-cfi_005fpersonality-directive"></a> +<p><code>.cfi_personality</code> defines personality routine and its encoding. +<var>encoding</var> must be a constant determining how the personality +should be encoded. If it is 255 (<code>DW_EH_PE_omit</code>), second +argument is not present, otherwise second argument should be +a constant or a symbol name. When using indirect encodings, +the symbol provided should be the location where personality +can be loaded from, not the personality routine itself. +The default after <code>.cfi_startproc</code> is <code>.cfi_personality 0xff</code>, +no personality routine. +</p> +<a name="g_t_002ecfi_005fpersonality_005fid-id"></a> +<h4 class="subsection">7.12.5 <code>.cfi_personality_id <var>id</var></code></h4> +<a name="index-cfi_005fpersonality_005fid-directive"></a> +<p><code>cfi_personality_id</code> defines a personality routine by its index as +defined in a compact unwinding format. +Only valid when generating compact EH frames (i.e. +with <code>.cfi_sections eh_frame_entry</code>. +</p> +<a name="g_t_002ecfi_005ffde_005fdata-_005bopcode1-_005b_002c-_2026_005d_005d"></a> +<h4 class="subsection">7.12.6 <code>.cfi_fde_data [<var>opcode1</var> [, …]]</code></h4> +<a name="index-cfi_005ffde_005fdata-directive"></a> +<p><code>cfi_fde_data</code> is used to describe the compact unwind opcodes to be +used for the current function. These are emitted inline in the +<code>.eh_frame_entry</code> section if small enough and there is no LSDA, or +in the <code>.gnu.extab</code> section otherwise. +Only valid when generating compact EH frames (i.e. +with <code>.cfi_sections eh_frame_entry</code>. +</p> +<a name="g_t_002ecfi_005flsda-encoding-_005b_002c-exp_005d"></a> +<h4 class="subsection">7.12.7 <code>.cfi_lsda <var>encoding</var> [, <var>exp</var>]</code></h4> +<p><code>.cfi_lsda</code> defines LSDA and its encoding. +<var>encoding</var> must be a constant determining how the LSDA +should be encoded. If it is 255 (<code>DW_EH_PE_omit</code>), the second +argument is not present, otherwise the second argument should be a constant +or a symbol name. The default after <code>.cfi_startproc</code> is <code>.cfi_lsda 0xff</code>, +meaning that no LSDA is present. +</p> +<a name="g_t_002ecfi_005finline_005flsda-_005balign_005d"></a> +<h4 class="subsection">7.12.8 <code>.cfi_inline_lsda</code> [<var>align</var>]</h4> +<p><code>.cfi_inline_lsda</code> marks the start of a LSDA data section and +switches to the corresponding <code>.gnu.extab</code> section. +Must be preceded by a CFI block containing a <code>.cfi_lsda</code> directive. +Only valid when generating compact EH frames (i.e. +with <code>.cfi_sections eh_frame_entry</code>. +</p> +<p>The table header and unwinding opcodes will be generated at this point, +so that they are immediately followed by the LSDA data. The symbol +referenced by the <code>.cfi_lsda</code> directive should still be defined +in case a fallback FDE based encoding is used. The LSDA data is terminated +by a section directive. +</p> +<p>The optional <var>align</var> argument specifies the alignment required. +The alignment is specified as a power of two, as with the +<code>.p2align</code> directive. +</p> +<a name="g_t_002ecfi_005fdef_005fcfa-register_002c-offset"></a> +<h4 class="subsection">7.12.9 <code>.cfi_def_cfa <var>register</var>, <var>offset</var></code></h4> +<p><code>.cfi_def_cfa</code> defines a rule for computing CFA as: <i>take +address from <var>register</var> and add <var>offset</var> to it</i>. +</p> +<a name="g_t_002ecfi_005fdef_005fcfa_005fregister-register"></a> +<h4 class="subsection">7.12.10 <code>.cfi_def_cfa_register <var>register</var></code></h4> +<p><code>.cfi_def_cfa_register</code> modifies a rule for computing CFA. From +now on <var>register</var> will be used instead of the old one. Offset +remains the same. +</p> +<a name="g_t_002ecfi_005fdef_005fcfa_005foffset-offset"></a> +<h4 class="subsection">7.12.11 <code>.cfi_def_cfa_offset <var>offset</var></code></h4> +<p><code>.cfi_def_cfa_offset</code> modifies a rule for computing CFA. Register +remains the same, but <var>offset</var> is new. Note that it is the +absolute offset that will be added to a defined register to compute +CFA address. +</p> +<a name="g_t_002ecfi_005fadjust_005fcfa_005foffset-offset"></a> +<h4 class="subsection">7.12.12 <code>.cfi_adjust_cfa_offset <var>offset</var></code></h4> +<p>Same as <code>.cfi_def_cfa_offset</code> but <var>offset</var> is a relative +value that is added/subtracted from the previous offset. +</p> +<a name="g_t_002ecfi_005foffset-register_002c-offset"></a> +<h4 class="subsection">7.12.13 <code>.cfi_offset <var>register</var>, <var>offset</var></code></h4> +<p>Previous value of <var>register</var> is saved at offset <var>offset</var> from +CFA. +</p> +<a name="g_t_002ecfi_005fval_005foffset-register_002c-offset"></a> +<h4 class="subsection">7.12.14 <code>.cfi_val_offset <var>register</var>, <var>offset</var></code></h4> +<p>Previous value of <var>register</var> is CFA + <var>offset</var>. +</p> +<a name="g_t_002ecfi_005frel_005foffset-register_002c-offset"></a> +<h4 class="subsection">7.12.15 <code>.cfi_rel_offset <var>register</var>, <var>offset</var></code></h4> +<p>Previous value of <var>register</var> is saved at offset <var>offset</var> from +the current CFA register. This is transformed to <code>.cfi_offset</code> +using the known displacement of the CFA register from the CFA. +This is often easier to use, because the number will match the +code it’s annotating. +</p> +<a name="g_t_002ecfi_005fregister-register1_002c-register2"></a> +<h4 class="subsection">7.12.16 <code>.cfi_register <var>register1</var>, <var>register2</var></code></h4> +<p>Previous value of <var>register1</var> is saved in register <var>register2</var>. +</p> +<a name="g_t_002ecfi_005frestore-register"></a> +<h4 class="subsection">7.12.17 <code>.cfi_restore <var>register</var></code></h4> +<p><code>.cfi_restore</code> says that the rule for <var>register</var> is now the +same as it was at the beginning of the function, after all initial +instruction added by <code>.cfi_startproc</code> were executed. +</p> +<a name="g_t_002ecfi_005fundefined-register"></a> +<h4 class="subsection">7.12.18 <code>.cfi_undefined <var>register</var></code></h4> +<p>From now on the previous value of <var>register</var> can’t be restored anymore. +</p> +<a name="g_t_002ecfi_005fsame_005fvalue-register"></a> +<h4 class="subsection">7.12.19 <code>.cfi_same_value <var>register</var></code></h4> +<p>Current value of <var>register</var> is the same like in the previous frame, +i.e. no restoration needed. +</p> +<a name="g_t_002ecfi_005fremember_005fstate-and-_002ecfi_005frestore_005fstate"></a> +<h4 class="subsection">7.12.20 <code>.cfi_remember_state</code> and <code>.cfi_restore_state</code></h4> +<p><code>.cfi_remember_state</code> pushes the set of rules for every register onto an +implicit stack, while <code>.cfi_restore_state</code> pops them off the stack and +places them in the current row. This is useful for situations where you have +multiple <code>.cfi_*</code> directives that need to be undone due to the control +flow of the program. For example, we could have something like this (assuming +the CFA is the value of <code>rbp</code>): +</p> +<div class="smallexample"> +<pre class="smallexample"> je label + popq %rbx + .cfi_restore %rbx + popq %r12 + .cfi_restore %r12 + popq %rbp + .cfi_restore %rbp + .cfi_def_cfa %rsp, 8 + ret +label: + /* Do something else */ +</pre></div> + +<p>Here, we want the <code>.cfi</code> directives to affect only the rows corresponding +to the instructions before <code>label</code>. This means we’d have to add multiple +<code>.cfi</code> directives after <code>label</code> to recreate the original save +locations of the registers, as well as setting the CFA back to the value of +<code>rbp</code>. This would be clumsy, and result in a larger binary size. Instead, +we can write: +</p> +<div class="smallexample"> +<pre class="smallexample"> je label + popq %rbx + .cfi_remember_state + .cfi_restore %rbx + popq %r12 + .cfi_restore %r12 + popq %rbp + .cfi_restore %rbp + .cfi_def_cfa %rsp, 8 + ret +label: + .cfi_restore_state + /* Do something else */ +</pre></div> + +<p>That way, the rules for the instructions after <code>label</code> will be the same +as before the first <code>.cfi_restore</code> without having to use multiple +<code>.cfi</code> directives. +</p> +<a name="g_t_002ecfi_005freturn_005fcolumn-register"></a> +<h4 class="subsection">7.12.21 <code>.cfi_return_column <var>register</var></code></h4> +<p>Change return column <var>register</var>, i.e. the return address is either +directly in <var>register</var> or can be accessed by rules for <var>register</var>. +</p> +<a name="g_t_002ecfi_005fsignal_005fframe"></a> +<h4 class="subsection">7.12.22 <code>.cfi_signal_frame</code></h4> +<p>Mark current function as signal trampoline. +</p> +<a name="g_t_002ecfi_005fwindow_005fsave"></a> +<h4 class="subsection">7.12.23 <code>.cfi_window_save</code></h4> +<p>SPARC register window has been saved. +</p> +<a name="g_t_002ecfi_005fescape-expression_005b_002c-_2026_005d"></a> +<h4 class="subsection">7.12.24 <code>.cfi_escape</code> <var>expression</var>[, …]</h4> +<p>Allows the user to add arbitrary bytes to the unwind info. One +might use this to add OS-specific CFI opcodes, or generic CFI +opcodes that GAS does not yet support. +</p> +<a name="g_t_002ecfi_005fval_005fencoded_005faddr-register_002c-encoding_002c-label"></a> +<h4 class="subsection">7.12.25 <code>.cfi_val_encoded_addr <var>register</var>, <var>encoding</var>, <var>label</var></code></h4> +<p>The current value of <var>register</var> is <var>label</var>. The value of <var>label</var> +will be encoded in the output file according to <var>encoding</var>; see the +description of <code>.cfi_personality</code> for details on this encoding. +</p> +<p>The usefulness of equating a register to a fixed label is probably +limited to the return address register. Here, it can be useful to +mark a code segment that has only one return address which is reached +by a direct branch and no copy of the return address exists in memory +or another register. +</p> +<hr> +<a name="Comm"></a> +<div class="header"> +<p> +Next: <a href="#Data" accesskey="n" rel="next">Data</a>, Previous: <a href="#CFI-directives" accesskey="p" rel="previous">CFI directives</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ecomm-symbol-_002c-length-"></a> +<h3 class="section">7.13 <code>.comm <var>symbol</var> , <var>length</var> </code></h3> + +<a name="index-comm-directive"></a> +<a name="index-symbol_002c-common"></a> +<p><code>.comm</code> declares a common symbol named <var>symbol</var>. When linking, a +common symbol in one object file may be merged with a defined or common symbol +of the same name in another object file. If <code>ld</code> does not see a +definition for the symbol–just one or more common symbols–then it will +allocate <var>length</var> bytes of uninitialized memory. <var>length</var> must be an +absolute expression. If <code>ld</code> sees multiple common symbols with +the same name, and they do not all have the same size, it will allocate space +using the largest size. +</p> +<p>When using ELF or (as a GNU extension) PE, the <code>.comm</code> directive takes +an optional third argument. This is the desired alignment of the symbol, +specified for ELF as a byte boundary (for example, an alignment of 16 means +that the least significant 4 bits of the address should be zero), and for PE +as a power of two (for example, an alignment of 5 means aligned to a 32-byte +boundary). The alignment must be an absolute expression, and it must be a +power of two. If <code>ld</code> allocates uninitialized memory for the +common symbol, it will use the alignment when placing the symbol. If no +alignment is specified, <code>as</code> will set the alignment to the +largest power of two less than or equal to the size of the symbol, up to a +maximum of 16 on ELF, or the default section alignment of 4 on PE<a name="DOCF1" href="#FOOT1"><sup>1</sup></a>. +</p> +<p>The syntax for <code>.comm</code> differs slightly on the HPPA. The syntax is +‘<samp><var>symbol</var> .comm, <var>length</var></samp>’; <var>symbol</var> is optional. +</p> +<hr> +<a name="Data"></a> +<div class="header"> +<p> +Next: <a href="#Dc" accesskey="n" rel="next">Dc</a>, Previous: <a href="#Comm" accesskey="p" rel="previous">Comm</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002edata-subsection"></a> +<h3 class="section">7.14 <code>.data <var>subsection</var></code></h3> +<a name="index-data-directive"></a> + +<p><code>.data</code> tells <code>as</code> to assemble the following statements onto the +end of the data subsection numbered <var>subsection</var> (which is an +absolute expression). If <var>subsection</var> is omitted, it defaults +to zero. +</p> +<hr> +<a name="Dc"></a> +<div class="header"> +<p> +Next: <a href="#Dcb" accesskey="n" rel="next">Dcb</a>, Previous: <a href="#Data" accesskey="p" rel="previous">Data</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002edc_005bsize_005d-expressions"></a> +<h3 class="section">7.15 <code>.dc[<var>size</var>] <var>expressions</var></code></h3> +<a name="index-dc-directive"></a> + +<p>The <code>.dc</code> directive expects zero or more <var>expressions</var> separated by +commas. These expressions are evaluated and their values inserted into the +current section. The size of the emitted value depends upon the suffix to the +<code>.dc</code> directive: +</p> +<dl compact="compact"> +<dt><code>‘<samp>.a</samp>’</code></dt> +<dd><p>Emits N-bit values, where N is the size of an address on the target system. +</p></dd> +<dt><code>‘<samp>.b</samp>’</code></dt> +<dd><p>Emits 8-bit values. +</p></dd> +<dt><code>‘<samp>.d</samp>’</code></dt> +<dd><p>Emits double precision floating-point values. +</p></dd> +<dt><code>‘<samp>.l</samp>’</code></dt> +<dd><p>Emits 32-bit values. +</p></dd> +<dt><code>‘<samp>.s</samp>’</code></dt> +<dd><p>Emits single precision floating-point values. +</p></dd> +<dt><code>‘<samp>.w</samp>’</code></dt> +<dd><p>Emits 16-bit values. +Note - this is true even on targets where the <code>.word</code> directive would emit +32-bit values. +</p></dd> +<dt><code>‘<samp>.x</samp>’</code></dt> +<dd><p>Emits long double precision floating-point values. +</p></dd> +</dl> + +<p>If no suffix is used then ‘<samp>.w</samp>’ is assumed. +</p> +<p>The byte ordering is target dependent, as is the size and format of floating +point values. +</p> +<p>Note - these directives are not intended for encoding instructions, and they +will not trigger effects like DWARF line number generation. Instead some +targets support special directives for encoding arbitrary binary sequences as +instructions such as <code>.insn</code> or <code>.inst</code>. +</p> +<hr> +<a name="Dcb"></a> +<div class="header"> +<p> +Next: <a href="#Ds" accesskey="n" rel="next">Ds</a>, Previous: <a href="#Dc" accesskey="p" rel="previous">Dc</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002edcb_005bsize_005d-number-_005b_002cfill_005d"></a> +<h3 class="section">7.16 <code>.dcb[<var>size</var>] <var>number</var> [,<var>fill</var>]</code></h3> +<a name="index-dcb-directive"></a> +<p>This directive emits <var>number</var> copies of <var>fill</var>, each of <var>size</var> +bytes. Both <var>number</var> and <var>fill</var> are absolute expressions. If the +comma and <var>fill</var> are omitted, <var>fill</var> is assumed to be zero. The +<var>size</var> suffix, if present, must be one of: +</p> +<dl compact="compact"> +<dt><code>‘<samp>.b</samp>’</code></dt> +<dd><p>Emits single byte values. +</p></dd> +<dt><code>‘<samp>.d</samp>’</code></dt> +<dd><p>Emits double-precision floating point values. +</p></dd> +<dt><code>‘<samp>.l</samp>’</code></dt> +<dd><p>Emits 4-byte values. +</p></dd> +<dt><code>‘<samp>.s</samp>’</code></dt> +<dd><p>Emits single-precision floating point values. +</p></dd> +<dt><code>‘<samp>.w</samp>’</code></dt> +<dd><p>Emits 2-byte values. +</p></dd> +<dt><code>‘<samp>.x</samp>’</code></dt> +<dd><p>Emits long double-precision floating point values. +</p></dd> +</dl> + +<p>If the <var>size</var> suffix is omitted then ‘<samp>.w</samp>’ is assumed. +</p> +<p>The byte ordering is target dependent, as is the size and format of floating +point values. +</p> +<hr> +<a name="Ds"></a> +<div class="header"> +<p> +Next: <a href="#Def" accesskey="n" rel="next">Def</a>, Previous: <a href="#Dcb" accesskey="p" rel="previous">Dcb</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eds_005bsize_005d-number-_005b_002cfill_005d"></a> +<h3 class="section">7.17 <code>.ds[<var>size</var>] <var>number</var> [,<var>fill</var>]</code></h3> +<a name="index-ds-directive"></a> +<p>This directive emits <var>number</var> copies of <var>fill</var>, each of <var>size</var> +bytes. Both <var>number</var> and <var>fill</var> are absolute expressions. If the +comma and <var>fill</var> are omitted, <var>fill</var> is assumed to be zero. The +<var>size</var> suffix, if present, must be one of: +</p> +<dl compact="compact"> +<dt><code>‘<samp>.b</samp>’</code></dt> +<dd><p>Emits single byte values. +</p></dd> +<dt><code>‘<samp>.d</samp>’</code></dt> +<dd><p>Emits 8-byte values. +</p></dd> +<dt><code>‘<samp>.l</samp>’</code></dt> +<dd><p>Emits 4-byte values. +</p></dd> +<dt><code>‘<samp>.p</samp>’</code></dt> +<dd><p>Emits values with size matching packed-decimal floating-point ones. +</p></dd> +<dt><code>‘<samp>.s</samp>’</code></dt> +<dd><p>Emits 4-byte values. +</p></dd> +<dt><code>‘<samp>.w</samp>’</code></dt> +<dd><p>Emits 2-byte values. +</p></dd> +<dt><code>‘<samp>.x</samp>’</code></dt> +<dd><p>Emits values with size matching long double precision floating-point ones. +</p></dd> +</dl> + +<p>Note - unlike the <code>.dcb</code> directive the ‘<samp>.d</samp>’, ‘<samp>.s</samp>’ and ‘<samp>.x</samp>’ +suffixes do not indicate that floating-point values are to be inserted. +</p> +<p>If the <var>size</var> suffix is omitted then ‘<samp>.w</samp>’ is assumed. +</p> +<p>The byte ordering is target dependent. +</p> +<hr> +<a name="Def"></a> +<div class="header"> +<p> +Next: <a href="#Desc" accesskey="n" rel="next">Desc</a>, Previous: <a href="#Ds" accesskey="p" rel="previous">Ds</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002edef-name"></a> +<h3 class="section">7.18 <code>.def <var>name</var></code></h3> + +<a name="index-def-directive"></a> +<a name="index-COFF-symbols_002c-debugging"></a> +<a name="index-debugging-COFF-symbols"></a> +<p>Begin defining debugging information for a symbol <var>name</var>; the +definition extends until the <code>.endef</code> directive is encountered. +</p> +<hr> +<a name="Desc"></a> +<div class="header"> +<p> +Next: <a href="#Dim" accesskey="n" rel="next">Dim</a>, Previous: <a href="#Def" accesskey="p" rel="previous">Def</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002edesc-symbol_002c-abs_002dexpression"></a> +<h3 class="section">7.19 <code>.desc <var>symbol</var>, <var>abs-expression</var></code></h3> + +<a name="index-desc-directive"></a> +<a name="index-COFF-symbol-descriptor"></a> +<a name="index-symbol-descriptor_002c-COFF"></a> +<p>This directive sets the descriptor of the symbol (see <a href="#Symbol-Attributes">Symbol Attributes</a>) +to the low 16 bits of an absolute expression. +</p> +<p>The ‘<samp>.desc</samp>’ directive is not available when <code>as</code> is +configured for COFF output; it is only for <code>a.out</code> or <code>b.out</code> +object format. For the sake of compatibility, <code>as</code> accepts +it, but produces no output, when configured for COFF. +</p> +<hr> +<a name="Dim"></a> +<div class="header"> +<p> +Next: <a href="#Double" accesskey="n" rel="next">Double</a>, Previous: <a href="#Desc" accesskey="p" rel="previous">Desc</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002edim"></a> +<h3 class="section">7.20 <code>.dim</code></h3> + +<a name="index-dim-directive"></a> +<a name="index-COFF-auxiliary-symbol-information"></a> +<a name="index-auxiliary-symbol-information_002c-COFF"></a> +<p>This directive is generated by compilers to include auxiliary debugging +information in the symbol table. It is only permitted inside +<code>.def</code>/<code>.endef</code> pairs. +</p> +<hr> +<a name="Double"></a> +<div class="header"> +<p> +Next: <a href="#Eject" accesskey="n" rel="next">Eject</a>, Previous: <a href="#Dim" accesskey="p" rel="previous">Dim</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002edouble-flonums"></a> +<h3 class="section">7.21 <code>.double <var>flonums</var></code></h3> + +<a name="index-double-directive"></a> +<a name="index-floating-point-numbers-_0028double_0029"></a> +<p><code>.double</code> expects zero or more flonums, separated by commas. It +assembles floating point numbers. +The exact kind of floating point numbers emitted depends on how +<code>as</code> is configured. See <a href="#Machine-Dependencies">Machine Dependencies</a>. +</p> +<hr> +<a name="Eject"></a> +<div class="header"> +<p> +Next: <a href="#Else" accesskey="n" rel="next">Else</a>, Previous: <a href="#Double" accesskey="p" rel="previous">Double</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eeject"></a> +<h3 class="section">7.22 <code>.eject</code></h3> + +<a name="index-eject-directive"></a> +<a name="index-new-page_002c-in-listings"></a> +<a name="index-page_002c-in-listings"></a> +<a name="index-listing-control_003a-new-page"></a> +<p>Force a page break at this point, when generating assembly listings. +</p> +<hr> +<a name="Else"></a> +<div class="header"> +<p> +Next: <a href="#Elseif" accesskey="n" rel="next">Elseif</a>, Previous: <a href="#Eject" accesskey="p" rel="previous">Eject</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eelse"></a> +<h3 class="section">7.23 <code>.else</code></h3> + +<a name="index-else-directive"></a> +<p><code>.else</code> is part of the <code>as</code> support for conditional +assembly; see <a href="#If"><code>.if</code></a>. It marks the beginning of a section +of code to be assembled if the condition for the preceding <code>.if</code> +was false. +</p> +<hr> +<a name="Elseif"></a> +<div class="header"> +<p> +Next: <a href="#End" accesskey="n" rel="next">End</a>, Previous: <a href="#Else" accesskey="p" rel="previous">Else</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eelseif"></a> +<h3 class="section">7.24 <code>.elseif</code></h3> + +<a name="index-elseif-directive"></a> +<p><code>.elseif</code> is part of the <code>as</code> support for conditional +assembly; see <a href="#If"><code>.if</code></a>. It is shorthand for beginning a new +<code>.if</code> block that would otherwise fill the entire <code>.else</code> section. +</p> +<hr> +<a name="End"></a> +<div class="header"> +<p> +Next: <a href="#Endef" accesskey="n" rel="next">Endef</a>, Previous: <a href="#Elseif" accesskey="p" rel="previous">Elseif</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eend"></a> +<h3 class="section">7.25 <code>.end</code></h3> + +<a name="index-end-directive"></a> +<p><code>.end</code> marks the end of the assembly file. <code>as</code> does not +process anything in the file past the <code>.end</code> directive. +</p> +<hr> +<a name="Endef"></a> +<div class="header"> +<p> +Next: <a href="#Endfunc" accesskey="n" rel="next">Endfunc</a>, Previous: <a href="#End" accesskey="p" rel="previous">End</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eendef"></a> +<h3 class="section">7.26 <code>.endef</code></h3> + +<a name="index-endef-directive"></a> +<p>This directive flags the end of a symbol definition begun with +<code>.def</code>. +</p> +<hr> +<a name="Endfunc"></a> +<div class="header"> +<p> +Next: <a href="#Endif" accesskey="n" rel="next">Endif</a>, Previous: <a href="#Endef" accesskey="p" rel="previous">Endef</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eendfunc"></a> +<h3 class="section">7.27 <code>.endfunc</code></h3> +<a name="index-endfunc-directive"></a> +<p><code>.endfunc</code> marks the end of a function specified with <code>.func</code>. +</p> +<hr> +<a name="Endif"></a> +<div class="header"> +<p> +Next: <a href="#Equ" accesskey="n" rel="next">Equ</a>, Previous: <a href="#Endfunc" accesskey="p" rel="previous">Endfunc</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eendif"></a> +<h3 class="section">7.28 <code>.endif</code></h3> + +<a name="index-endif-directive"></a> +<p><code>.endif</code> is part of the <code>as</code> support for conditional assembly; +it marks the end of a block of code that is only assembled +conditionally. See <a href="#If"><code>.if</code></a>. +</p> +<hr> +<a name="Equ"></a> +<div class="header"> +<p> +Next: <a href="#Equiv" accesskey="n" rel="next">Equiv</a>, Previous: <a href="#Endif" accesskey="p" rel="previous">Endif</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eequ-symbol_002c-expression"></a> +<h3 class="section">7.29 <code>.equ <var>symbol</var>, <var>expression</var></code></h3> + +<a name="index-equ-directive"></a> +<a name="index-assigning-values-to-symbols-1"></a> +<a name="index-symbols_002c-assigning-values-to"></a> +<p>This directive sets the value of <var>symbol</var> to <var>expression</var>. +It is synonymous with ‘<samp>.set</samp>’; see <a href="#Set"><code>.set</code></a>. +</p> +<p>The syntax for <code>equ</code> on the HPPA is +‘<samp><var>symbol</var> .equ <var>expression</var></samp>’. +</p> +<p>The syntax for <code>equ</code> on the Z80 is +‘<samp><var>symbol</var> equ <var>expression</var></samp>’. +On the Z80 it is an error if <var>symbol</var> is already defined, +but the symbol is not protected from later redefinition. +Compare <a href="#Equiv">Equiv</a>. +</p> +<hr> +<a name="Equiv"></a> +<div class="header"> +<p> +Next: <a href="#Eqv" accesskey="n" rel="next">Eqv</a>, Previous: <a href="#Equ" accesskey="p" rel="previous">Equ</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eequiv-symbol_002c-expression"></a> +<h3 class="section">7.30 <code>.equiv <var>symbol</var>, <var>expression</var></code></h3> +<a name="index-equiv-directive"></a> +<p>The <code>.equiv</code> directive is like <code>.equ</code> and <code>.set</code>, except that +the assembler will signal an error if <var>symbol</var> is already defined. Note a +symbol which has been referenced but not actually defined is considered to be +undefined. +</p> +<p>Except for the contents of the error message, this is roughly equivalent to +</p><div class="smallexample"> +<pre class="smallexample">.ifdef SYM +.err +.endif +.equ SYM,VAL +</pre></div> +<p>plus it protects the symbol from later redefinition. +</p> +<hr> +<a name="Eqv"></a> +<div class="header"> +<p> +Next: <a href="#Err" accesskey="n" rel="next">Err</a>, Previous: <a href="#Equiv" accesskey="p" rel="previous">Equiv</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eeqv-symbol_002c-expression"></a> +<h3 class="section">7.31 <code>.eqv <var>symbol</var>, <var>expression</var></code></h3> +<a name="index-eqv-directive"></a> +<p>The <code>.eqv</code> directive is like <code>.equiv</code>, but no attempt is made to +evaluate the expression or any part of it immediately. Instead each time +the resulting symbol is used in an expression, a snapshot of its current +value is taken. +</p> +<hr> +<a name="Err"></a> +<div class="header"> +<p> +Next: <a href="#Error" accesskey="n" rel="next">Error</a>, Previous: <a href="#Eqv" accesskey="p" rel="previous">Eqv</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eerr"></a> +<h3 class="section">7.32 <code>.err</code></h3> +<a name="index-err-directive"></a> +<p>If <code>as</code> assembles a <code>.err</code> directive, it will print an error +message and, unless the <samp>-Z</samp> option was used, it will not generate an +object file. This can be used to signal an error in conditionally compiled code. +</p> +<hr> +<a name="Error"></a> +<div class="header"> +<p> +Next: <a href="#Exitm" accesskey="n" rel="next">Exitm</a>, Previous: <a href="#Err" accesskey="p" rel="previous">Err</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eerror-_0022string_0022"></a> +<h3 class="section">7.33 <code>.error "<var>string</var>"</code></h3> +<a name="index-error-directive"></a> + +<p>Similarly to <code>.err</code>, this directive emits an error, but you can specify a +string that will be emitted as the error message. If you don’t specify the +message, it defaults to <code>".error directive invoked in source file"</code>. +See <a href="#Errors">Error and Warning Messages</a>. +</p> +<div class="smallexample"> +<pre class="smallexample"> .error "This code has not been assembled and tested." +</pre></div> + +<hr> +<a name="Exitm"></a> +<div class="header"> +<p> +Next: <a href="#Extern" accesskey="n" rel="next">Extern</a>, Previous: <a href="#Error" accesskey="p" rel="previous">Error</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eexitm"></a> +<h3 class="section">7.34 <code>.exitm</code></h3> +<p>Exit early from the current macro definition. See <a href="#Macro">Macro</a>. +</p> +<hr> +<a name="Extern"></a> +<div class="header"> +<p> +Next: <a href="#Fail" accesskey="n" rel="next">Fail</a>, Previous: <a href="#Exitm" accesskey="p" rel="previous">Exitm</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eextern"></a> +<h3 class="section">7.35 <code>.extern</code></h3> + +<a name="index-extern-directive"></a> +<p><code>.extern</code> is accepted in the source program—for compatibility +with other assemblers—but it is ignored. <code>as</code> treats +all undefined symbols as external. +</p> +<hr> +<a name="Fail"></a> +<div class="header"> +<p> +Next: <a href="#File" accesskey="n" rel="next">File</a>, Previous: <a href="#Extern" accesskey="p" rel="previous">Extern</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002efail-expression"></a> +<h3 class="section">7.36 <code>.fail <var>expression</var></code></h3> + +<a name="index-fail-directive"></a> +<p>Generates an error or a warning. If the value of the <var>expression</var> is 500 +or more, <code>as</code> will print a warning message. If the value is less +than 500, <code>as</code> will print an error message. The message will +include the value of <var>expression</var>. This can occasionally be useful inside +complex nested macros or conditional assembly. +</p> +<hr> +<a name="File"></a> +<div class="header"> +<p> +Next: <a href="#Fill" accesskey="n" rel="next">Fill</a>, Previous: <a href="#Fail" accesskey="p" rel="previous">Fail</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002efile"></a> +<h3 class="section">7.37 <code>.file</code></h3> +<a name="index-file-directive"></a> + +<p>There are two different versions of the <code>.file</code> directive. Targets +that support DWARF2 line number information use the DWARF2 version of +<code>.file</code>. Other targets use the default version. +</p> +<a name="Default-Version"></a> +<h4 class="subheading">Default Version</h4> + +<a name="index-logical-file-name"></a> +<a name="index-file-name_002c-logical"></a> +<p>This version of the <code>.file</code> directive tells <code>as</code> that we +are about to start a new logical file. The syntax is: +</p> +<div class="smallexample"> +<pre class="smallexample">.file <var>string</var> +</pre></div> + +<p><var>string</var> is the new file name. In general, the filename is +recognized whether or not it is surrounded by quotes ‘<samp>"</samp>’; but if you wish +to specify an empty file name, you must give the quotes–<code>""</code>. This +statement may go away in future: it is only recognized to be compatible with +old <code>as</code> programs. +</p> +<a name="DWARF2-Version"></a> +<h4 class="subheading">DWARF2 Version</h4> + +<p>When emitting DWARF2 line number information, <code>.file</code> assigns filenames +to the <code>.debug_line</code> file name table. The syntax is: +</p> +<div class="smallexample"> +<pre class="smallexample">.file <var>fileno</var> <var>filename</var> +</pre></div> + +<p>The <var>fileno</var> operand should be a unique positive integer to use as the +index of the entry in the table. The <var>filename</var> operand is a C string +literal enclosed in double quotes. The <var>filename</var> can include directory +elements. If it does, then the directory will be added to the directory table +and the basename will be added to the file table. +</p> +<p>The detail of filename indices is exposed to the user because the filename +table is shared with the <code>.debug_info</code> section of the DWARF2 debugging +information, and thus the user must know the exact indices that table +entries will have. +</p> +<p>If DWARF5 support has been enabled via the <samp>-gdwarf-5</samp> option then +an extended version of <code>.file</code> is also allowed: +</p> +<div class="smallexample"> +<pre class="smallexample">.file <var>fileno</var> [<var>dirname</var>] <var>filename</var> [md5 <var>value</var>] +</pre></div> + +<p>With this version a separate directory name is allowed, although if this is +used then <var>filename</var> should not contain any directory component, except +for <var>fileno</var> equal to 0: in this case, <var>dirname</var> is expected to be +the current directory and <var>filename</var> the currently processed file, and +the latter need not be located in the former. In addtion an MD5 hash value +of the contents of <var>filename</var> can be provided. This will be stored in +the the file table as well, and can be used by tools reading the debug +information to verify that the contents of the source file match the +contents of the compiled file. +</p> +<hr> +<a name="Fill"></a> +<div class="header"> +<p> +Next: <a href="#Float" accesskey="n" rel="next">Float</a>, Previous: <a href="#File" accesskey="p" rel="previous">File</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002efill-repeat-_002c-size-_002c-value"></a> +<h3 class="section">7.38 <code>.fill <var>repeat</var> , <var>size</var> , <var>value</var></code></h3> + +<a name="index-fill-directive"></a> +<a name="index-writing-patterns-in-memory"></a> +<a name="index-patterns_002c-writing-in-memory"></a> +<p><var>repeat</var>, <var>size</var> and <var>value</var> are absolute expressions. +This emits <var>repeat</var> copies of <var>size</var> bytes. <var>Repeat</var> +may be zero or more. <var>Size</var> may be zero or more, but if it is +more than 8, then it is deemed to have the value 8, compatible with +other people’s assemblers. The contents of each <var>repeat</var> bytes +is taken from an 8-byte number. The highest order 4 bytes are +zero. The lowest order 4 bytes are <var>value</var> rendered in the +byte-order of an integer on the computer <code>as</code> is assembling for. +Each <var>size</var> bytes in a repetition is taken from the lowest order +<var>size</var> bytes of this number. Again, this bizarre behavior is +compatible with other people’s assemblers. +</p> +<p><var>size</var> and <var>value</var> are optional. +If the second comma and <var>value</var> are absent, <var>value</var> is +assumed zero. If the first comma and following tokens are absent, +<var>size</var> is assumed to be 1. +</p> +<hr> +<a name="Float"></a> +<div class="header"> +<p> +Next: <a href="#Func" accesskey="n" rel="next">Func</a>, Previous: <a href="#Fill" accesskey="p" rel="previous">Fill</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002efloat-flonums"></a> +<h3 class="section">7.39 <code>.float <var>flonums</var></code></h3> + +<a name="index-floating-point-numbers-_0028single_0029"></a> +<a name="index-float-directive"></a> +<p>This directive assembles zero or more flonums, separated by commas. It +has the same effect as <code>.single</code>. +The exact kind of floating point numbers emitted depends on how +<code>as</code> is configured. +See <a href="#Machine-Dependencies">Machine Dependencies</a>. +</p> +<hr> +<a name="Func"></a> +<div class="header"> +<p> +Next: <a href="#Global" accesskey="n" rel="next">Global</a>, Previous: <a href="#Float" accesskey="p" rel="previous">Float</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002efunc-name_005b_002clabel_005d"></a> +<h3 class="section">7.40 <code>.func <var>name</var>[,<var>label</var>]</code></h3> +<a name="index-func-directive"></a> +<p><code>.func</code> emits debugging information to denote function <var>name</var>, and +is ignored unless the file is assembled with debugging enabled. +Only ‘<samp>--gstabs[+]</samp>’ is currently supported. +<var>label</var> is the entry point of the function and if omitted <var>name</var> +prepended with the ‘<samp>leading char</samp>’ is used. +‘<samp>leading char</samp>’ is usually <code>_</code> or nothing, depending on the target. +All functions are currently defined to have <code>void</code> return type. +The function must be terminated with <code>.endfunc</code>. +</p> +<hr> +<a name="Global"></a> +<div class="header"> +<p> +Next: <a href="#Gnu_005fattribute" accesskey="n" rel="next">Gnu_attribute</a>, Previous: <a href="#Func" accesskey="p" rel="previous">Func</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eglobal-symbol_002c-_002eglobl-symbol"></a> +<h3 class="section">7.41 <code>.global <var>symbol</var></code>, <code>.globl <var>symbol</var></code></h3> + +<a name="index-global-directive"></a> +<a name="index-symbol_002c-making-visible-to-linker"></a> +<p><code>.global</code> makes the symbol visible to <code>ld</code>. If you define +<var>symbol</var> in your partial program, its value is made available to +other partial programs that are linked with it. Otherwise, +<var>symbol</var> takes its attributes from a symbol of the same name +from another file linked into the same program. +</p> +<p>Both spellings (‘<samp>.globl</samp>’ and ‘<samp>.global</samp>’) are accepted, for +compatibility with other assemblers. +</p> +<p>On the HPPA, <code>.global</code> is not always enough to make it accessible to other +partial programs. You may need the HPPA-only <code>.EXPORT</code> directive as well. +See <a href="#HPPA-Directives">HPPA Assembler Directives</a>. +</p> +<hr> +<a name="Gnu_005fattribute"></a> +<div class="header"> +<p> +Next: <a href="#Hidden" accesskey="n" rel="next">Hidden</a>, Previous: <a href="#Global" accesskey="p" rel="previous">Global</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002egnu_005fattribute-tag_002cvalue"></a> +<h3 class="section">7.42 <code>.gnu_attribute <var>tag</var>,<var>value</var></code></h3> +<p>Record a <small>GNU</small> object attribute for this file. See <a href="#Object-Attributes">Object Attributes</a>. +</p> +<hr> +<a name="Hidden"></a> +<div class="header"> +<p> +Next: <a href="#hword" accesskey="n" rel="next">hword</a>, Previous: <a href="#Gnu_005fattribute" accesskey="p" rel="previous">Gnu_attribute</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ehidden-names"></a> +<h3 class="section">7.43 <code>.hidden <var>names</var></code></h3> + +<a name="index-hidden-directive"></a> +<a name="index-visibility"></a> +<p>This is one of the ELF visibility directives. The other two are +<code>.internal</code> (see <a href="#Internal"><code>.internal</code></a>) and +<code>.protected</code> (see <a href="#Protected"><code>.protected</code></a>). +</p> +<p>This directive overrides the named symbols default visibility (which is set by +their binding: local, global or weak). The directive sets the visibility to +<code>hidden</code> which means that the symbols are not visible to other components. +Such symbols are always considered to be <code>protected</code> as well. +</p> +<hr> +<a name="hword"></a> +<div class="header"> +<p> +Next: <a href="#Ident" accesskey="n" rel="next">Ident</a>, Previous: <a href="#Hidden" accesskey="p" rel="previous">Hidden</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ehword-expressions"></a> +<h3 class="section">7.44 <code>.hword <var>expressions</var></code></h3> + +<a name="index-hword-directive"></a> +<a name="index-integers_002c-16_002dbit"></a> +<a name="index-numbers_002c-16_002dbit"></a> +<a name="index-sixteen-bit-integers"></a> +<p>This expects zero or more <var>expressions</var>, and emits +a 16 bit number for each. +</p> +<p>This directive is a synonym for ‘<samp>.short</samp>’; depending on the target +architecture, it may also be a synonym for ‘<samp>.word</samp>’. +</p> +<hr> +<a name="Ident"></a> +<div class="header"> +<p> +Next: <a href="#If" accesskey="n" rel="next">If</a>, Previous: <a href="#hword" accesskey="p" rel="previous">hword</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eident"></a> +<h3 class="section">7.45 <code>.ident</code></h3> + +<a name="index-ident-directive"></a> + +<p>This directive is used by some assemblers to place tags in object files. The +behavior of this directive varies depending on the target. When using the +a.out object file format, <code>as</code> simply accepts the directive for +source-file compatibility with existing assemblers, but does not emit anything +for it. When using COFF, comments are emitted to the <code>.comment</code> or +<code>.rdata</code> section, depending on the target. When using ELF, comments are +emitted to the <code>.comment</code> section. +</p> +<hr> +<a name="If"></a> +<div class="header"> +<p> +Next: <a href="#Incbin" accesskey="n" rel="next">Incbin</a>, Previous: <a href="#Ident" accesskey="p" rel="previous">Ident</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eif-absolute-expression"></a> +<h3 class="section">7.46 <code>.if <var>absolute expression</var></code></h3> + +<a name="index-conditional-assembly"></a> +<a name="index-if-directive"></a> +<p><code>.if</code> marks the beginning of a section of code which is only +considered part of the source program being assembled if the argument +(which must be an <var>absolute expression</var>) is non-zero. The end of +the conditional section of code must be marked by <code>.endif</code> +(see <a href="#Endif"><code>.endif</code></a>); optionally, you may include code for the +alternative condition, flagged by <code>.else</code> (see <a href="#Else"><code>.else</code></a>). +If you have several conditions to check, <code>.elseif</code> may be used to avoid +nesting blocks if/else within each subsequent <code>.else</code> block. +</p> +<p>The following variants of <code>.if</code> are also supported: +</p><dl compact="compact"> +<dd><a name="index-ifdef-directive"></a> +</dd> +<dt><code>.ifdef <var>symbol</var></code></dt> +<dd><p>Assembles the following section of code if the specified <var>symbol</var> +has been defined. Note a symbol which has been referenced but not yet defined +is considered to be undefined. +</p> +<a name="index-ifb-directive"></a> +</dd> +<dt><code>.ifb <var>text</var></code></dt> +<dd><p>Assembles the following section of code if the operand is blank (empty). +</p> +<a name="index-ifc-directive"></a> +</dd> +<dt><code>.ifc <var>string1</var>,<var>string2</var></code></dt> +<dd><p>Assembles the following section of code if the two strings are the same. The +strings may be optionally quoted with single quotes. If they are not quoted, +the first string stops at the first comma, and the second string stops at the +end of the line. Strings which contain whitespace should be quoted. The +string comparison is case sensitive. +</p> +<a name="index-ifeq-directive"></a> +</dd> +<dt><code>.ifeq <var>absolute expression</var></code></dt> +<dd><p>Assembles the following section of code if the argument is zero. +</p> +<a name="index-ifeqs-directive"></a> +</dd> +<dt><code>.ifeqs <var>string1</var>,<var>string2</var></code></dt> +<dd><p>Another form of <code>.ifc</code>. The strings must be quoted using double quotes. +</p> +<a name="index-ifge-directive"></a> +</dd> +<dt><code>.ifge <var>absolute expression</var></code></dt> +<dd><p>Assembles the following section of code if the argument is greater than or +equal to zero. +</p> +<a name="index-ifgt-directive"></a> +</dd> +<dt><code>.ifgt <var>absolute expression</var></code></dt> +<dd><p>Assembles the following section of code if the argument is greater than zero. +</p> +<a name="index-ifle-directive"></a> +</dd> +<dt><code>.ifle <var>absolute expression</var></code></dt> +<dd><p>Assembles the following section of code if the argument is less than or equal +to zero. +</p> +<a name="index-iflt-directive"></a> +</dd> +<dt><code>.iflt <var>absolute expression</var></code></dt> +<dd><p>Assembles the following section of code if the argument is less than zero. +</p> +<a name="index-ifnb-directive"></a> +</dd> +<dt><code>.ifnb <var>text</var></code></dt> +<dd><p>Like <code>.ifb</code>, but the sense of the test is reversed: this assembles the +following section of code if the operand is non-blank (non-empty). +</p> +<a name="index-ifnc-directive"></a> +</dd> +<dt><code>.ifnc <var>string1</var>,<var>string2</var>.</code></dt> +<dd><p>Like <code>.ifc</code>, but the sense of the test is reversed: this assembles the +following section of code if the two strings are not the same. +</p> +<a name="index-ifndef-directive"></a> +<a name="index-ifnotdef-directive"></a> +</dd> +<dt><code>.ifndef <var>symbol</var></code></dt> +<dt><code>.ifnotdef <var>symbol</var></code></dt> +<dd><p>Assembles the following section of code if the specified <var>symbol</var> +has not been defined. Both spelling variants are equivalent. Note a symbol +which has been referenced but not yet defined is considered to be undefined. +</p> +<a name="index-ifne-directive"></a> +</dd> +<dt><code>.ifne <var>absolute expression</var></code></dt> +<dd><p>Assembles the following section of code if the argument is not equal to zero +(in other words, this is equivalent to <code>.if</code>). +</p> +<a name="index-ifnes-directive"></a> +</dd> +<dt><code>.ifnes <var>string1</var>,<var>string2</var></code></dt> +<dd><p>Like <code>.ifeqs</code>, but the sense of the test is reversed: this assembles the +following section of code if the two strings are not the same. +</p></dd> +</dl> + +<hr> +<a name="Incbin"></a> +<div class="header"> +<p> +Next: <a href="#Include" accesskey="n" rel="next">Include</a>, Previous: <a href="#If" accesskey="p" rel="previous">If</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eincbin-_0022file_0022_005b_002cskip_005b_002ccount_005d_005d"></a> +<h3 class="section">7.47 <code>.incbin "<var>file</var>"[,<var>skip</var>[,<var>count</var>]]</code></h3> + +<a name="index-incbin-directive"></a> +<a name="index-binary-files_002c-including"></a> +<p>The <code>incbin</code> directive includes <var>file</var> verbatim at the current +location. You can control the search paths used with the ‘<samp>-I</samp>’ command-line +option (see <a href="#Invoking">Command-Line Options</a>). Quotation marks are required +around <var>file</var>. +</p> +<p>The <var>skip</var> argument skips a number of bytes from the start of the +<var>file</var>. The <var>count</var> argument indicates the maximum number of bytes to +read. Note that the data is not aligned in any way, so it is the user’s +responsibility to make sure that proper alignment is provided both before and +after the <code>incbin</code> directive. +</p> +<hr> +<a name="Include"></a> +<div class="header"> +<p> +Next: <a href="#Int" accesskey="n" rel="next">Int</a>, Previous: <a href="#Incbin" accesskey="p" rel="previous">Incbin</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002einclude-_0022file_0022"></a> +<h3 class="section">7.48 <code>.include "<var>file</var>"</code></h3> + +<a name="index-include-directive"></a> +<a name="index-supporting-files_002c-including"></a> +<a name="index-files_002c-including"></a> +<p>This directive provides a way to include supporting files at specified +points in your source program. The code from <var>file</var> is assembled as +if it followed the point of the <code>.include</code>; when the end of the +included file is reached, assembly of the original file continues. You +can control the search paths used with the ‘<samp>-I</samp>’ command-line option +(see <a href="#Invoking">Command-Line Options</a>). Quotation marks are required +around <var>file</var>. +</p> +<hr> +<a name="Int"></a> +<div class="header"> +<p> +Next: <a href="#Internal" accesskey="n" rel="next">Internal</a>, Previous: <a href="#Include" accesskey="p" rel="previous">Include</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eint-expressions"></a> +<h3 class="section">7.49 <code>.int <var>expressions</var></code></h3> + +<a name="index-int-directive"></a> +<a name="index-integers_002c-32_002dbit"></a> +<p>Expect zero or more <var>expressions</var>, of any section, separated by commas. +For each expression, emit a number that, at run time, is the value of that +expression. The byte order and bit size of the number depends on what kind +of target the assembly is for. +</p> + +<p>Note - this directive is not intended for encoding instructions, and it will +not trigger effects like DWARF line number generation. Instead some targets +support special directives for encoding arbitrary binary sequences as +instructions such as eg <code>.insn</code> or <code>.inst</code>. +</p> +<hr> +<a name="Internal"></a> +<div class="header"> +<p> +Next: <a href="#Irp" accesskey="n" rel="next">Irp</a>, Previous: <a href="#Int" accesskey="p" rel="previous">Int</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002einternal-names"></a> +<h3 class="section">7.50 <code>.internal <var>names</var></code></h3> + +<a name="index-internal-directive"></a> +<a name="index-visibility-1"></a> +<p>This is one of the ELF visibility directives. The other two are +<code>.hidden</code> (see <a href="#Hidden"><code>.hidden</code></a>) and +<code>.protected</code> (see <a href="#Protected"><code>.protected</code></a>). +</p> +<p>This directive overrides the named symbols default visibility (which is set by +their binding: local, global or weak). The directive sets the visibility to +<code>internal</code> which means that the symbols are considered to be <code>hidden</code> +(i.e., not visible to other components), and that some extra, processor specific +processing must also be performed upon the symbols as well. +</p> +<hr> +<a name="Irp"></a> +<div class="header"> +<p> +Next: <a href="#Irpc" accesskey="n" rel="next">Irpc</a>, Previous: <a href="#Internal" accesskey="p" rel="previous">Internal</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eirp-symbol_002cvalues_2026"></a> +<h3 class="section">7.51 <code>.irp <var>symbol</var>,<var>values</var></code>…</h3> + +<a name="index-irp-directive"></a> +<p>Evaluate a sequence of statements assigning different values to <var>symbol</var>. +The sequence of statements starts at the <code>.irp</code> directive, and is +terminated by an <code>.endr</code> directive. For each <var>value</var>, <var>symbol</var> is +set to <var>value</var>, and the sequence of statements is assembled. If no +<var>value</var> is listed, the sequence of statements is assembled once, with +<var>symbol</var> set to the null string. To refer to <var>symbol</var> within the +sequence of statements, use <var>\symbol</var>. +</p> +<p>For example, assembling +</p> +<div class="example"> +<pre class="example"> .irp param,1,2,3 + move d\param,sp@- + .endr +</pre></div> + +<p>is equivalent to assembling +</p> +<div class="example"> +<pre class="example"> move d1,sp@- + move d2,sp@- + move d3,sp@- +</pre></div> + +<p>For some caveats with the spelling of <var>symbol</var>, see also <a href="#Macro">Macro</a>. +</p> +<hr> +<a name="Irpc"></a> +<div class="header"> +<p> +Next: <a href="#Lcomm" accesskey="n" rel="next">Lcomm</a>, Previous: <a href="#Irp" accesskey="p" rel="previous">Irp</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eirpc-symbol_002cvalues_2026"></a> +<h3 class="section">7.52 <code>.irpc <var>symbol</var>,<var>values</var></code>…</h3> + +<a name="index-irpc-directive"></a> +<p>Evaluate a sequence of statements assigning different values to <var>symbol</var>. +The sequence of statements starts at the <code>.irpc</code> directive, and is +terminated by an <code>.endr</code> directive. For each character in <var>value</var>, +<var>symbol</var> is set to the character, and the sequence of statements is +assembled. If no <var>value</var> is listed, the sequence of statements is +assembled once, with <var>symbol</var> set to the null string. To refer to +<var>symbol</var> within the sequence of statements, use <var>\symbol</var>. +</p> +<p>For example, assembling +</p> +<div class="example"> +<pre class="example"> .irpc param,123 + move d\param,sp@- + .endr +</pre></div> + +<p>is equivalent to assembling +</p> +<div class="example"> +<pre class="example"> move d1,sp@- + move d2,sp@- + move d3,sp@- +</pre></div> + +<p>For some caveats with the spelling of <var>symbol</var>, see also the discussion +at See <a href="#Macro">Macro</a>. +</p> +<hr> +<a name="Lcomm"></a> +<div class="header"> +<p> +Next: <a href="#Lflags" accesskey="n" rel="next">Lflags</a>, Previous: <a href="#Irpc" accesskey="p" rel="previous">Irpc</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002elcomm-symbol-_002c-length"></a> +<h3 class="section">7.53 <code>.lcomm <var>symbol</var> , <var>length</var></code></h3> + +<a name="index-lcomm-directive"></a> +<a name="index-local-common-symbols"></a> +<a name="index-symbols_002c-local-common"></a> +<p>Reserve <var>length</var> (an absolute expression) bytes for a local common +denoted by <var>symbol</var>. The section and value of <var>symbol</var> are +those of the new local common. The addresses are allocated in the bss +section, so that at run-time the bytes start off zeroed. <var>Symbol</var> +is not declared global (see <a href="#Global"><code>.global</code></a>), so is normally +not visible to <code>ld</code>. +</p> +<p>Some targets permit a third argument to be used with <code>.lcomm</code>. This +argument specifies the desired alignment of the symbol in the bss section. +</p> +<p>The syntax for <code>.lcomm</code> differs slightly on the HPPA. The syntax is +‘<samp><var>symbol</var> .lcomm, <var>length</var></samp>’; <var>symbol</var> is optional. +</p> +<hr> +<a name="Lflags"></a> +<div class="header"> +<p> +Next: <a href="#Line" accesskey="n" rel="next">Line</a>, Previous: <a href="#Lcomm" accesskey="p" rel="previous">Lcomm</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002elflags"></a> +<h3 class="section">7.54 <code>.lflags</code></h3> + +<a name="index-lflags-directive-_0028ignored_0029"></a> +<p><code>as</code> accepts this directive, for compatibility with other +assemblers, but ignores it. +</p> +<hr> +<a name="Line"></a> +<div class="header"> +<p> +Next: <a href="#Linkonce" accesskey="n" rel="next">Linkonce</a>, Previous: <a href="#Lflags" accesskey="p" rel="previous">Lflags</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eline-line_002dnumber"></a> +<h3 class="section">7.55 <code>.line <var>line-number</var></code></h3> + +<a name="index-line-directive"></a> +<a name="index-logical-line-number"></a> +<p>Change the logical line number. <var>line-number</var> must be an absolute +expression. The next line has that logical line number. Therefore any other +statements on the current line (after a statement separator character) are +reported as on logical line number <var>line-number</var> - 1. One day +<code>as</code> will no longer support this directive: it is recognized only +for compatibility with existing assembler programs. +</p> +<p>Even though this is a directive associated with the <code>a.out</code> or +<code>b.out</code> object-code formats, <code>as</code> still recognizes it +when producing COFF output, and treats ‘<samp>.line</samp>’ as though it +were the COFF ‘<samp>.ln</samp>’ <em>if</em> it is found outside a +<code>.def</code>/<code>.endef</code> pair. +</p> +<p>Inside a <code>.def</code>, ‘<samp>.line</samp>’ is, instead, one of the directives +used by compilers to generate auxiliary symbol information for +debugging. +</p> +<hr> +<a name="Linkonce"></a> +<div class="header"> +<p> +Next: <a href="#List" accesskey="n" rel="next">List</a>, Previous: <a href="#Line" accesskey="p" rel="previous">Line</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002elinkonce-_005btype_005d"></a> +<h3 class="section">7.56 <code>.linkonce [<var>type</var>]</code></h3> +<a name="index-COMDAT"></a> +<a name="index-linkonce-directive"></a> +<a name="index-common-sections"></a> +<p>Mark the current section so that the linker only includes a single copy of it. +This may be used to include the same section in several different object files, +but ensure that the linker will only include it once in the final output file. +The <code>.linkonce</code> pseudo-op must be used for each instance of the section. +Duplicate sections are detected based on the section name, so it should be +unique. +</p> +<p>This directive is only supported by a few object file formats; as of this +writing, the only object file format which supports it is the Portable +Executable format used on Windows NT. +</p> +<p>The <var>type</var> argument is optional. If specified, it must be one of the +following strings. For example: +</p><div class="smallexample"> +<pre class="smallexample">.linkonce same_size +</pre></div> +<p>Not all types may be supported on all object file formats. +</p> +<dl compact="compact"> +<dt><code>discard</code></dt> +<dd><p>Silently discard duplicate sections. This is the default. +</p> +</dd> +<dt><code>one_only</code></dt> +<dd><p>Warn if there are duplicate sections, but still keep only one copy. +</p> +</dd> +<dt><code>same_size</code></dt> +<dd><p>Warn if any of the duplicates have different sizes. +</p> +</dd> +<dt><code>same_contents</code></dt> +<dd><p>Warn if any of the duplicates do not have exactly the same contents. +</p></dd> +</dl> + +<hr> +<a name="List"></a> +<div class="header"> +<p> +Next: <a href="#Ln" accesskey="n" rel="next">Ln</a>, Previous: <a href="#Linkonce" accesskey="p" rel="previous">Linkonce</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002elist"></a> +<h3 class="section">7.57 <code>.list</code></h3> + +<a name="index-list-directive"></a> +<a name="index-listing-control_002c-turning-on"></a> +<p>Control (in conjunction with the <code>.nolist</code> directive) whether or +not assembly listings are generated. These two directives maintain an +internal counter (which is zero initially). <code>.list</code> increments the +counter, and <code>.nolist</code> decrements it. Assembly listings are +generated whenever the counter is greater than zero. +</p> +<p>By default, listings are disabled. When you enable them (with the +‘<samp>-a</samp>’ command-line option; see <a href="#Invoking">Command-Line Options</a>), +the initial value of the listing counter is one. +</p> +<hr> +<a name="Ln"></a> +<div class="header"> +<p> +Next: <a href="#Loc" accesskey="n" rel="next">Loc</a>, Previous: <a href="#List" accesskey="p" rel="previous">List</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eln-line_002dnumber"></a> +<h3 class="section">7.58 <code>.ln <var>line-number</var></code></h3> + +<a name="index-ln-directive"></a> +<p>‘<samp>.ln</samp>’ is a synonym for ‘<samp>.line</samp>’. +</p> +<hr> +<a name="Loc"></a> +<div class="header"> +<p> +Next: <a href="#Loc_005fmark_005flabels" accesskey="n" rel="next">Loc_mark_labels</a>, Previous: <a href="#Ln" accesskey="p" rel="previous">Ln</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eloc-fileno-lineno-_005bcolumn_005d-_005boptions_005d"></a> +<h3 class="section">7.59 <code>.loc <var>fileno</var> <var>lineno</var> [<var>column</var>] [<var>options</var>]</code></h3> +<a name="index-loc-directive"></a> +<p>When emitting DWARF2 line number information, +the <code>.loc</code> directive will add a row to the <code>.debug_line</code> line +number matrix corresponding to the immediately following assembly +instruction. The <var>fileno</var>, <var>lineno</var>, and optional <var>column</var> +arguments will be applied to the <code>.debug_line</code> state machine before +the row is added. It is an error for the input assembly file to generate +a non-empty <code>.debug_line</code> and also use <code>loc</code> directives. +</p> +<p>The <var>options</var> are a sequence of the following tokens in any order: +</p> +<dl compact="compact"> +<dt><code>basic_block</code></dt> +<dd><p>This option will set the <code>basic_block</code> register in the +<code>.debug_line</code> state machine to <code>true</code>. +</p> +</dd> +<dt><code>prologue_end</code></dt> +<dd><p>This option will set the <code>prologue_end</code> register in the +<code>.debug_line</code> state machine to <code>true</code>. +</p> +</dd> +<dt><code>epilogue_begin</code></dt> +<dd><p>This option will set the <code>epilogue_begin</code> register in the +<code>.debug_line</code> state machine to <code>true</code>. +</p> +</dd> +<dt><code>is_stmt <var>value</var></code></dt> +<dd><p>This option will set the <code>is_stmt</code> register in the +<code>.debug_line</code> state machine to <code>value</code>, which must be +either 0 or 1. +</p> +</dd> +<dt><code>isa <var>value</var></code></dt> +<dd><p>This directive will set the <code>isa</code> register in the <code>.debug_line</code> +state machine to <var>value</var>, which must be an unsigned integer. +</p> +</dd> +<dt><code>discriminator <var>value</var></code></dt> +<dd><p>This directive will set the <code>discriminator</code> register in the <code>.debug_line</code> +state machine to <var>value</var>, which must be an unsigned integer. +</p> +</dd> +<dt><code>view <var>value</var></code></dt> +<dd><p>This option causes a row to be added to <code>.debug_line</code> in reference to the +current address (which might not be the same as that of the following assembly +instruction), and to associate <var>value</var> with the <code>view</code> register in the +<code>.debug_line</code> state machine. If <var>value</var> is a label, both the +<code>view</code> register and the label are set to the number of prior <code>.loc</code> +directives at the same program location. If <var>value</var> is the literal +<code>0</code>, the <code>view</code> register is set to zero, and the assembler asserts +that there aren’t any prior <code>.loc</code> directives at the same program +location. If <var>value</var> is the literal <code>-0</code>, the assembler arrange for +the <code>view</code> register to be reset in this row, even if there are prior +<code>.loc</code> directives at the same program location. +</p> +</dd> +</dl> + +<hr> +<a name="Loc_005fmark_005flabels"></a> +<div class="header"> +<p> +Next: <a href="#Local" accesskey="n" rel="next">Local</a>, Previous: <a href="#Loc" accesskey="p" rel="previous">Loc</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eloc_005fmark_005flabels-enable"></a> +<h3 class="section">7.60 <code>.loc_mark_labels <var>enable</var></code></h3> +<a name="index-loc_005fmark_005flabels-directive"></a> +<p>When emitting DWARF2 line number information, +the <code>.loc_mark_labels</code> directive makes the assembler emit an entry +to the <code>.debug_line</code> line number matrix with the <code>basic_block</code> +register in the state machine set whenever a code label is seen. +The <var>enable</var> argument should be either 1 or 0, to enable or disable +this function respectively. +</p> +<hr> +<a name="Local"></a> +<div class="header"> +<p> +Next: <a href="#Long" accesskey="n" rel="next">Long</a>, Previous: <a href="#Loc_005fmark_005flabels" accesskey="p" rel="previous">Loc_mark_labels</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002elocal-names"></a> +<h3 class="section">7.61 <code>.local <var>names</var></code></h3> + +<a name="index-local-directive"></a> +<p>This directive, which is available for ELF targets, marks each symbol in +the comma-separated list of <code>names</code> as a local symbol so that it +will not be externally visible. If the symbols do not already exist, +they will be created. +</p> +<p>For targets where the <code>.lcomm</code> directive (see <a href="#Lcomm">Lcomm</a>) does not +accept an alignment argument, which is the case for most ELF targets, +the <code>.local</code> directive can be used in combination with <code>.comm</code> +(see <a href="#Comm">Comm</a>) to define aligned local common data. +</p> +<hr> +<a name="Long"></a> +<div class="header"> +<p> +Next: <a href="#Macro" accesskey="n" rel="next">Macro</a>, Previous: <a href="#Local" accesskey="p" rel="previous">Local</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002elong-expressions"></a> +<h3 class="section">7.62 <code>.long <var>expressions</var></code></h3> + +<a name="index-long-directive"></a> +<p><code>.long</code> is the same as ‘<samp>.int</samp>’. See <a href="#Int"><code>.int</code></a>. +</p> + +<hr> +<a name="Macro"></a> +<div class="header"> +<p> +Next: <a href="#MRI" accesskey="n" rel="next">MRI</a>, Previous: <a href="#Long" accesskey="p" rel="previous">Long</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002emacro"></a> +<h3 class="section">7.63 <code>.macro</code></h3> + +<a name="index-macros"></a> +<p>The commands <code>.macro</code> and <code>.endm</code> allow you to define macros that +generate assembly output. For example, this definition specifies a macro +<code>sum</code> that puts a sequence of numbers into memory: +</p> +<div class="example"> +<pre class="example"> .macro sum from=0, to=5 + .long \from + .if \to-\from + sum "(\from+1)",\to + .endif + .endm +</pre></div> + +<p>With that definition, ‘<samp>SUM 0,5</samp>’ is equivalent to this assembly input: +</p> +<div class="example"> +<pre class="example"> .long 0 + .long 1 + .long 2 + .long 3 + .long 4 + .long 5 +</pre></div> + +<dl compact="compact"> +<dt><code>.macro <var>macname</var></code> +<a name="index-_002emacro-macname"></a> +</dt> +<dt><code>.macro <var>macname</var> <var>macargs</var> …</code> +<a name="index-_002emacro-macname-macargs-_2026"></a> +</dt> +<dd><a name="index-macro-directive"></a> +<p>Begin the definition of a macro called <var>macname</var>. If your macro +definition requires arguments, specify their names after the macro name, +separated by commas or spaces. You can qualify the macro argument to +indicate whether all invocations must specify a non-blank value (through +‘<samp>:<code>req</code></samp>’), or whether it takes all of the remaining arguments +(through ‘<samp>:<code>vararg</code></samp>’). You can supply a default value for any +macro argument by following the name with ‘<samp>=<var>deflt</var></samp>’. You +cannot define two macros with the same <var>macname</var> unless it has been +subject to the <code>.purgem</code> directive (see <a href="#Purgem">Purgem</a>) between the two +definitions. For example, these are all valid <code>.macro</code> statements: +</p> +<dl compact="compact"> +<dt><code>.macro comm</code></dt> +<dd><p>Begin the definition of a macro called <code>comm</code>, which takes no +arguments. +</p> +</dd> +<dt><code>.macro plus1 p, p1</code></dt> +<dt><code>.macro plus1 p p1</code></dt> +<dd><p>Either statement begins the definition of a macro called <code>plus1</code>, +which takes two arguments; within the macro definition, write +‘<samp>\p</samp>’ or ‘<samp>\p1</samp>’ to evaluate the arguments. +</p> +</dd> +<dt><code>.macro reserve_str p1=0 p2</code></dt> +<dd><p>Begin the definition of a macro called <code>reserve_str</code>, with two +arguments. The first argument has a default value, but not the second. +After the definition is complete, you can call the macro either as +‘<samp>reserve_str <var>a</var>,<var>b</var></samp>’ (with ‘<samp>\p1</samp>’ evaluating to +<var>a</var> and ‘<samp>\p2</samp>’ evaluating to <var>b</var>), or as ‘<samp>reserve_str +,<var>b</var></samp>’ (with ‘<samp>\p1</samp>’ evaluating as the default, in this case +‘<samp>0</samp>’, and ‘<samp>\p2</samp>’ evaluating to <var>b</var>). +</p> +</dd> +<dt><code>.macro m p1:req, p2=0, p3:vararg</code></dt> +<dd><p>Begin the definition of a macro called <code>m</code>, with at least three +arguments. The first argument must always have a value specified, but +not the second, which instead has a default value. The third formal +will get assigned all remaining arguments specified at invocation time. +</p> +<p>When you call a macro, you can specify the argument values either by +position, or by keyword. For example, ‘<samp>sum 9,17</samp>’ is equivalent to +‘<samp>sum to=17, from=9</samp>’. +</p> +</dd> +</dl> + +<p>Note that since each of the <var>macargs</var> can be an identifier exactly +as any other one permitted by the target architecture, there may be +occasional problems if the target hand-crafts special meanings to certain +characters when they occur in a special position. For example, if the colon +(<code>:</code>) is generally permitted to be part of a symbol name, but the +architecture specific code special-cases it when occurring as the final +character of a symbol (to denote a label), then the macro parameter +replacement code will have no way of knowing that and consider the whole +construct (including the colon) an identifier, and check only this +identifier for being the subject to parameter substitution. So for example +this macro definition: +</p> +<div class="example"> +<pre class="example"> .macro label l +\l: + .endm +</pre></div> + +<p>might not work as expected. Invoking ‘<samp>label foo</samp>’ might not create a label +called ‘<samp>foo</samp>’ but instead just insert the text ‘<samp>\l:</samp>’ into the +assembler source, probably generating an error about an unrecognised +identifier. +</p> +<p>Similarly problems might occur with the period character (‘<samp>.</samp>’) +which is often allowed inside opcode names (and hence identifier names). So +for example constructing a macro to build an opcode from a base name and a +length specifier like this: +</p> +<div class="example"> +<pre class="example"> .macro opcode base length + \base.\length + .endm +</pre></div> + +<p>and invoking it as ‘<samp>opcode store l</samp>’ will not create a ‘<samp>store.l</samp>’ +instruction but instead generate some kind of error as the assembler tries to +interpret the text ‘<samp>\base.\length</samp>’. +</p> +<p>There are several possible ways around this problem: +</p> +<dl compact="compact"> +<dt><code>Insert white space</code></dt> +<dd><p>If it is possible to use white space characters then this is the simplest +solution. eg: +</p> +<div class="example"> +<pre class="example"> .macro label l +\l : + .endm +</pre></div> + +</dd> +<dt><code>Use ‘<samp>\()</samp>’</code></dt> +<dd><p>The string ‘<samp>\()</samp>’ can be used to separate the end of a macro argument from +the following text. eg: +</p> +<div class="example"> +<pre class="example"> .macro opcode base length + \base\().\length + .endm +</pre></div> + +</dd> +<dt><code>Use the alternate macro syntax mode</code></dt> +<dd><p>In the alternative macro syntax mode the ampersand character (‘<samp>&</samp>’) can be +used as a separator. eg: +</p> +<div class="example"> +<pre class="example"> .altmacro + .macro label l +l&: + .endm +</pre></div> +</dd> +</dl> + +<p>Note: this problem of correctly identifying string parameters to pseudo ops +also applies to the identifiers used in <code>.irp</code> (see <a href="#Irp">Irp</a>) +and <code>.irpc</code> (see <a href="#Irpc">Irpc</a>) as well. +</p> +<p>Another issue can occur with the actual arguments passed during macro +invocation: Multiple arguments can be separated by blanks or commas. To have +arguments actually contain blanks or commas (or potentially other non-alpha- +numeric characters), individual arguments will need to be enclosed in either +parentheses <code>()</code>, square brackets <code>[]</code>, or double quote <code>"</code> +characters. The latter may be the only viable option in certain situations, +as only double quotes are actually stripped while establishing arguments. It +may be important to be aware of two escaping models used when processing such +quoted argument strings: For one two adjacent double quotes represent a single +double quote in the resulting argument, going along the lines of the stripping +of the enclosing quotes. But then double quotes can also be escaped by a +backslash <code>\</code>, but this backslash will not be retained in the resulting +actual argument as then seen / used while expanding the macro. +</p> +<p>As a consequence to the first of these escaping mechanisms two string literals +intended to be representing separate macro arguments need to be separated by +white space (or, better yet, by a comma). To state it differently, such +adjacent string literals - even if separated only by a blank - will not be +concatenated when determining macro arguments, even if they’re only separated +by white space. This is unlike certain other pseudo ops, e.g. <code>.ascii</code>. +</p> +</dd> +<dt><code>.endm</code> +<a name="index-_002eendm"></a> +</dt> +<dd><a name="index-endm-directive"></a> +<p>Mark the end of a macro definition. +</p> +</dd> +<dt><code>.exitm</code> +<a name="index-_002eexitm"></a> +</dt> +<dd><a name="index-exitm-directive"></a> +<p>Exit early from the current macro definition. +</p> +<a name="index-number-of-macros-executed"></a> +<a name="index-macros_002c-count-executed"></a> +</dd> +<dt><code>\@</code> +<a name="index-_005c_0040"></a> +</dt> +<dd><p><code>as</code> maintains a counter of how many macros it has +executed in this pseudo-variable; you can copy that number to your +output with ‘<samp>\@</samp>’, but <em>only within a macro definition</em>. +</p> +</dd> +<dt><code>LOCAL <var>name</var> [ , … ]</code> +<a name="index-LOCAL-name-_005b-_002c-_2026-_005d-1"></a> +</dt> +<dd><p><em>Warning: <code>LOCAL</code> is only available if you select “alternate +macro syntax” with ‘<samp>--alternate</samp>’ or <code>.altmacro</code>.</em> +See <a href="#Altmacro"><code>.altmacro</code></a>. +</p></dd> +</dl> + +<hr> +<a name="MRI"></a> +<div class="header"> +<p> +Next: <a href="#Noaltmacro" accesskey="n" rel="next">Noaltmacro</a>, Previous: <a href="#Macro" accesskey="p" rel="previous">Macro</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002emri-val"></a> +<h3 class="section">7.64 <code>.mri <var>val</var></code></h3> + +<a name="index-mri-directive"></a> +<a name="index-MRI-mode_002c-temporarily"></a> +<p>If <var>val</var> is non-zero, this tells <code>as</code> to enter MRI mode. If +<var>val</var> is zero, this tells <code>as</code> to exit MRI mode. This change +affects code assembled until the next <code>.mri</code> directive, or until the end +of the file. See <a href="#M">MRI mode</a>. +</p> +<hr> +<a name="Noaltmacro"></a> +<div class="header"> +<p> +Next: <a href="#Nolist" accesskey="n" rel="next">Nolist</a>, Previous: <a href="#MRI" accesskey="p" rel="previous">MRI</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002enoaltmacro"></a> +<h3 class="section">7.65 <code>.noaltmacro</code></h3> +<p>Disable alternate macro mode. See <a href="#Altmacro">Altmacro</a>. +</p> +<hr> +<a name="Nolist"></a> +<div class="header"> +<p> +Next: <a href="#Nop" accesskey="n" rel="next">Nop</a>, Previous: <a href="#Noaltmacro" accesskey="p" rel="previous">Noaltmacro</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002enolist"></a> +<h3 class="section">7.66 <code>.nolist</code></h3> + +<a name="index-nolist-directive"></a> +<a name="index-listing-control_002c-turning-off"></a> +<p>Control (in conjunction with the <code>.list</code> directive) whether or +not assembly listings are generated. These two directives maintain an +internal counter (which is zero initially). <code>.list</code> increments the +counter, and <code>.nolist</code> decrements it. Assembly listings are +generated whenever the counter is greater than zero. +</p> +<hr> +<a name="Nop"></a> +<div class="header"> +<p> +Next: <a href="#Nops" accesskey="n" rel="next">Nops</a>, Previous: <a href="#Nolist" accesskey="p" rel="previous">Nolist</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002enop-_005bsize_005d"></a> +<h3 class="section">7.67 <code>.nop [<var>size</var>]</code></h3> + +<a name="index-nop-directive"></a> +<a name="index-filling-memory-with-no_002dop-instructions"></a> +<p>This directive emits no-op instructions. It is provided on all architectures, +allowing the creation of architecture neutral tests involving actual code. The +size of the generated instruction is target specific, but if the optional +<var>size</var> argument is given and resolves to an absolute positive value at that +point in assembly (no forward expressions allowed) then the fewest no-op +instructions are emitted that equal or exceed a total <var>size</var> in bytes. +<code>.nop</code> does affect the generation of DWARF debug line information. +Some targets do not support using <code>.nop</code> with <var>size</var>. +</p> +<hr> +<a name="Nops"></a> +<div class="header"> +<p> +Next: <a href="#Octa" accesskey="n" rel="next">Octa</a>, Previous: <a href="#Nop" accesskey="p" rel="previous">Nop</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002enops-size_005b_002c-control_005d"></a> +<h3 class="section">7.68 <code>.nops <var>size</var>[, <var>control</var>]</code></h3> + +<a name="index-nops-directive"></a> +<a name="index-filling-memory-with-no_002dop-instructions-1"></a> +<p>This directive emits no-op instructions. It is specific to the Intel 80386 and +AMD x86-64 targets. It takes a <var>size</var> argument and generates <var>size</var> +bytes of no-op instructions. <var>size</var> must be absolute and positive. These +bytes do not affect the generation of DWARF debug line information. +</p> +<p>The optional <var>control</var> argument specifies a size limit for a single no-op +instruction. If not provided then a value of 0 is assumed. The valid values +of <var>control</var> are between 0 and 4 in 16-bit mode, between 0 and 7 when +tuning for older processors in 32-bit mode, between 0 and 11 in 64-bit mode or +when tuning for newer processors in 32-bit mode. When 0 is used, the no-op +instruction size limit is set to the maximum supported size. +</p> +<hr> +<a name="Octa"></a> +<div class="header"> +<p> +Next: <a href="#Offset" accesskey="n" rel="next">Offset</a>, Previous: <a href="#Nops" accesskey="p" rel="previous">Nops</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eocta-bignums"></a> +<h3 class="section">7.69 <code>.octa <var>bignums</var></code></h3> + +<a name="index-octa-directive"></a> +<a name="index-integer_002c-16_002dbyte"></a> +<a name="index-sixteen-byte-integer"></a> +<p>This directive expects zero or more bignums, separated by commas. For each +bignum, it emits a 16-byte integer. +</p> +<p>The term “octa” comes from contexts in which a “word” is two bytes; +hence <em>octa</em>-word for 16 bytes. +</p> +<hr> +<a name="Offset"></a> +<div class="header"> +<p> +Next: <a href="#Org" accesskey="n" rel="next">Org</a>, Previous: <a href="#Octa" accesskey="p" rel="previous">Octa</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eoffset-loc"></a> +<h3 class="section">7.70 <code>.offset <var>loc</var></code></h3> + +<a name="index-offset-directive"></a> +<p>Set the location counter to <var>loc</var> in the absolute section. <var>loc</var> must +be an absolute expression. This directive may be useful for defining +symbols with absolute values. Do not confuse it with the <code>.org</code> +directive. +</p> +<hr> +<a name="Org"></a> +<div class="header"> +<p> +Next: <a href="#P2align" accesskey="n" rel="next">P2align</a>, Previous: <a href="#Offset" accesskey="p" rel="previous">Offset</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eorg-new_002dlc-_002c-fill"></a> +<h3 class="section">7.71 <code>.org <var>new-lc</var> , <var>fill</var></code></h3> + +<a name="index-org-directive"></a> +<a name="index-location-counter_002c-advancing"></a> +<a name="index-advancing-location-counter"></a> +<a name="index-current-address_002c-advancing"></a> +<p>Advance the location counter of the current section to +<var>new-lc</var>. <var>new-lc</var> is either an absolute expression or an +expression with the same section as the current subsection. That is, +you can’t use <code>.org</code> to cross sections: if <var>new-lc</var> has the +wrong section, the <code>.org</code> directive is ignored. To be compatible +with former assemblers, if the section of <var>new-lc</var> is absolute, +<code>as</code> issues a warning, then pretends the section of <var>new-lc</var> +is the same as the current subsection. +</p> +<p><code>.org</code> may only increase the location counter, or leave it +unchanged; you cannot use <code>.org</code> to move the location counter +backwards. +</p> +<p>Because <code>as</code> tries to assemble programs in one pass, <var>new-lc</var> +may not be undefined. If you really detest this restriction we eagerly await +a chance to share your improved assembler. +</p> +<p>Beware that the origin is relative to the start of the section, not +to the start of the subsection. This is compatible with other +people’s assemblers. +</p> +<p>When the location counter (of the current subsection) is advanced, the +intervening bytes are filled with <var>fill</var> which should be an +absolute expression. If the comma and <var>fill</var> are omitted, +<var>fill</var> defaults to zero. +</p> +<hr> +<a name="P2align"></a> +<div class="header"> +<p> +Next: <a href="#PopSection" accesskey="n" rel="next">PopSection</a>, Previous: <a href="#Org" accesskey="p" rel="previous">Org</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ep2align_005bwl_005d-_005babs_002dexpr_005b_002c-abs_002dexpr_005b_002c-abs_002dexpr_005d_005d_005d"></a> +<h3 class="section">7.72 <code>.p2align[wl] [<var>abs-expr</var>[, <var>abs-expr</var>[, <var>abs-expr</var>]]]</code></h3> + +<a name="index-padding-the-location-counter-given-a-power-of-two"></a> +<a name="index-p2align-directive"></a> +<p>Pad the location counter (in the current subsection) to a particular +storage boundary. The first expression (which must be absolute) is the +number of low-order zero bits the location counter must have after +advancement. For example ‘<samp>.p2align 3</samp>’ advances the location +counter until it is a multiple of 8. If the location counter is already a +multiple of 8, no change is needed. If the expression is omitted then a +default value of 0 is used, effectively disabling alignment requirements. +</p> +<p>The second expression (also absolute) gives the fill value to be stored in the +padding bytes. It (and the comma) may be omitted. If it is omitted, the +padding bytes are normally zero. However, on most systems, if the section is +marked as containing code and the fill value is omitted, the space is filled +with no-op instructions. +</p> +<p>The third expression is also absolute, and is also optional. If it is present, +it is the maximum number of bytes that should be skipped by this alignment +directive. If doing the alignment would require skipping more bytes than the +specified maximum, then the alignment is not done at all. You can omit the +fill value (the second argument) entirely by simply using two commas after the +required alignment; this can be useful if you want the alignment to be filled +with no-op instructions when appropriate. +</p> +<a name="index-p2alignw-directive"></a> +<a name="index-p2alignl-directive"></a> +<p>The <code>.p2alignw</code> and <code>.p2alignl</code> directives are variants of the +<code>.p2align</code> directive. The <code>.p2alignw</code> directive treats the fill +pattern as a two byte word value. The <code>.p2alignl</code> directives treats the +fill pattern as a four byte longword value. For example, <code>.p2alignw +2,0x368d</code> will align to a multiple of 4. If it skips two bytes, they will be +filled in with the value 0x368d (the exact placement of the bytes depends upon +the endianness of the processor). If it skips 1 or 3 bytes, the fill value is +undefined. +</p> +<hr> +<a name="PopSection"></a> +<div class="header"> +<p> +Next: <a href="#Previous" accesskey="n" rel="next">Previous</a>, Previous: <a href="#P2align" accesskey="p" rel="previous">P2align</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002epopsection"></a> +<h3 class="section">7.73 <code>.popsection</code></h3> + +<a name="index-popsection-directive"></a> +<a name="index-Section-Stack"></a> +<p>This is one of the ELF section stack manipulation directives. The others are +<code>.section</code> (see <a href="#Section">Section</a>), <code>.subsection</code> (see <a href="#SubSection">SubSection</a>), +<code>.pushsection</code> (see <a href="#PushSection">PushSection</a>), and <code>.previous</code> +(see <a href="#Previous">Previous</a>). +</p> +<p>This directive replaces the current section (and subsection) with the top +section (and subsection) on the section stack. This section is popped off the +stack. +</p> +<hr> +<a name="Previous"></a> +<div class="header"> +<p> +Next: <a href="#Print" accesskey="n" rel="next">Print</a>, Previous: <a href="#PopSection" accesskey="p" rel="previous">PopSection</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eprevious"></a> +<h3 class="section">7.74 <code>.previous</code></h3> + +<a name="index-previous-directive"></a> +<a name="index-Section-Stack-1"></a> +<p>This is one of the ELF section stack manipulation directives. The others are +<code>.section</code> (see <a href="#Section">Section</a>), <code>.subsection</code> (see <a href="#SubSection">SubSection</a>), +<code>.pushsection</code> (see <a href="#PushSection">PushSection</a>), and <code>.popsection</code> +(see <a href="#PopSection">PopSection</a>). +</p> +<p>This directive swaps the current section (and subsection) with most recently +referenced section/subsection pair prior to this one. Multiple +<code>.previous</code> directives in a row will flip between two sections (and their +subsections). For example: +</p> +<div class="smallexample"> +<pre class="smallexample">.section A + .subsection 1 + .word 0x1234 + .subsection 2 + .word 0x5678 +.previous + .word 0x9abc +</pre></div> + +<p>Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into subsection 2 of +section A. Whilst: +</p> +<div class="smallexample"> +<pre class="smallexample">.section A +.subsection 1 + # Now in section A subsection 1 + .word 0x1234 +.section B +.subsection 0 + # Now in section B subsection 0 + .word 0x5678 +.subsection 1 + # Now in section B subsection 1 + .word 0x9abc +.previous + # Now in section B subsection 0 + .word 0xdef0 +</pre></div> + +<p>Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 0 of +section B and 0x9abc into subsection 1 of section B. +</p> +<p>In terms of the section stack, this directive swaps the current section with +the top section on the section stack. +</p> +<hr> +<a name="Print"></a> +<div class="header"> +<p> +Next: <a href="#Protected" accesskey="n" rel="next">Protected</a>, Previous: <a href="#Previous" accesskey="p" rel="previous">Previous</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eprint-string"></a> +<h3 class="section">7.75 <code>.print <var>string</var></code></h3> + +<a name="index-print-directive"></a> +<p><code>as</code> will print <var>string</var> on the standard output during +assembly. You must put <var>string</var> in double quotes. +</p> +<hr> +<a name="Protected"></a> +<div class="header"> +<p> +Next: <a href="#Psize" accesskey="n" rel="next">Psize</a>, Previous: <a href="#Print" accesskey="p" rel="previous">Print</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eprotected-names"></a> +<h3 class="section">7.76 <code>.protected <var>names</var></code></h3> + +<a name="index-protected-directive"></a> +<a name="index-visibility-2"></a> +<p>This is one of the ELF visibility directives. The other two are +<code>.hidden</code> (see <a href="#Hidden">Hidden</a>) and <code>.internal</code> (see <a href="#Internal">Internal</a>). +</p> +<p>This directive overrides the named symbols default visibility (which is set by +their binding: local, global or weak). The directive sets the visibility to +<code>protected</code> which means that any references to the symbols from within the +components that defines them must be resolved to the definition in that +component, even if a definition in another component would normally preempt +this. +</p> +<hr> +<a name="Psize"></a> +<div class="header"> +<p> +Next: <a href="#Purgem" accesskey="n" rel="next">Purgem</a>, Previous: <a href="#Protected" accesskey="p" rel="previous">Protected</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002epsize-lines-_002c-columns"></a> +<h3 class="section">7.77 <code>.psize <var>lines</var> , <var>columns</var></code></h3> + +<a name="index-psize-directive"></a> +<a name="index-listing-control_003a-paper-size"></a> +<a name="index-paper-size_002c-for-listings"></a> +<p>Use this directive to declare the number of lines—and, optionally, the +number of columns—to use for each page, when generating listings. +</p> +<p>If you do not use <code>.psize</code>, listings use a default line-count +of 60. You may omit the comma and <var>columns</var> specification; the +default width is 200 columns. +</p> +<p><code>as</code> generates formfeeds whenever the specified number of +lines is exceeded (or whenever you explicitly request one, using +<code>.eject</code>). +</p> +<p>If you specify <var>lines</var> as <code>0</code>, no formfeeds are generated save +those explicitly specified with <code>.eject</code>. +</p> +<hr> +<a name="Purgem"></a> +<div class="header"> +<p> +Next: <a href="#PushSection" accesskey="n" rel="next">PushSection</a>, Previous: <a href="#Psize" accesskey="p" rel="previous">Psize</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002epurgem-name"></a> +<h3 class="section">7.78 <code>.purgem <var>name</var></code></h3> + +<a name="index-purgem-directive"></a> +<p>Undefine the macro <var>name</var>, so that later uses of the string will not be +expanded. See <a href="#Macro">Macro</a>. +</p> +<hr> +<a name="PushSection"></a> +<div class="header"> +<p> +Next: <a href="#Quad" accesskey="n" rel="next">Quad</a>, Previous: <a href="#Purgem" accesskey="p" rel="previous">Purgem</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002epushsection-name-_005b_002c-subsection_005d-_005b_002c-_0022flags_0022_005b_002c-_0040type_005b_002carguments_005d_005d_005d"></a> +<h3 class="section">7.79 <code>.pushsection <var>name</var> [, <var>subsection</var>] [, "<var>flags</var>"[, @<var>type</var>[,<var>arguments</var>]]]</code></h3> + +<a name="index-pushsection-directive"></a> +<a name="index-Section-Stack-2"></a> +<p>This is one of the ELF section stack manipulation directives. The others are +<code>.section</code> (see <a href="#Section">Section</a>), <code>.subsection</code> (see <a href="#SubSection">SubSection</a>), +<code>.popsection</code> (see <a href="#PopSection">PopSection</a>), and <code>.previous</code> +(see <a href="#Previous">Previous</a>). +</p> +<p>This directive pushes the current section (and subsection) onto the +top of the section stack, and then replaces the current section and +subsection with <code>name</code> and <code>subsection</code>. The optional +<code>flags</code>, <code>type</code> and <code>arguments</code> are treated the same +as in the <code>.section</code> (see <a href="#Section">Section</a>) directive. +</p> +<hr> +<a name="Quad"></a> +<div class="header"> +<p> +Next: <a href="#Reloc" accesskey="n" rel="next">Reloc</a>, Previous: <a href="#PushSection" accesskey="p" rel="previous">PushSection</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002equad-expressions"></a> +<h3 class="section">7.80 <code>.quad <var>expressions</var></code></h3> + +<a name="index-quad-directive"></a> +<p>For 64-bit architectures, or more generally with any GAS configured to support +64-bit target virtual addresses, this is like ‘<samp>.int</samp>’, but emitting 64-bit +quantities. Otherwise <code>.quad</code> expects zero or more bignums, separated by +commas. For each item, it emits an 8-byte integer. If a bignum won’t fit in +8 bytes, a warning message is printed and just the lowest order 8 bytes of the +bignum are taken. +<a name="index-eight_002dbyte-integer"></a> +<a name="index-integer_002c-8_002dbyte"></a> +</p> +<p>The term “quad” comes from contexts in which a “word” is two bytes; +hence <em>quad</em>-word for 8 bytes. +</p> +<p>Note - this directive is not intended for encoding instructions, and it will +not trigger effects like DWARF line number generation. Instead some targets +support special directives for encoding arbitrary binary sequences as +instructions such as <code>.insn</code> or <code>.inst</code>. +</p> +<hr> +<a name="Reloc"></a> +<div class="header"> +<p> +Next: <a href="#Rept" accesskey="n" rel="next">Rept</a>, Previous: <a href="#Quad" accesskey="p" rel="previous">Quad</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ereloc-offset_002c-reloc_005fname_005b_002c-expression_005d"></a> +<h3 class="section">7.81 <code>.reloc <var>offset</var>, <var>reloc_name</var>[, <var>expression</var>]</code></h3> + +<a name="index-reloc-directive"></a> +<p>Generate a relocation at <var>offset</var> of type <var>reloc_name</var> with value +<var>expression</var>. If <var>offset</var> is a number, the relocation is generated in +the current section. If <var>offset</var> is an expression that resolves to a +symbol plus offset, the relocation is generated in the given symbol’s section. +<var>expression</var>, if present, must resolve to a symbol plus addend or to an +absolute value, but note that not all targets support an addend. e.g. ELF REL +targets such as i386 store an addend in the section contents rather than in the +relocation. This low level interface does not support addends stored in the +section. +</p> +<hr> +<a name="Rept"></a> +<div class="header"> +<p> +Next: <a href="#Sbttl" accesskey="n" rel="next">Sbttl</a>, Previous: <a href="#Reloc" accesskey="p" rel="previous">Reloc</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002erept-count"></a> +<h3 class="section">7.82 <code>.rept <var>count</var></code></h3> + +<a name="index-rept-directive"></a> +<p>Repeat the sequence of lines between the <code>.rept</code> directive and the next +<code>.endr</code> directive <var>count</var> times. +</p> +<p>For example, assembling +</p> +<div class="example"> +<pre class="example"> .rept 3 + .long 0 + .endr +</pre></div> + +<p>is equivalent to assembling +</p> +<div class="example"> +<pre class="example"> .long 0 + .long 0 + .long 0 +</pre></div> + +<p>A count of zero is allowed, but nothing is generated. Negative counts are not +allowed and if encountered will be treated as if they were zero. +</p> +<hr> +<a name="Sbttl"></a> +<div class="header"> +<p> +Next: <a href="#Scl" accesskey="n" rel="next">Scl</a>, Previous: <a href="#Rept" accesskey="p" rel="previous">Rept</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002esbttl-_0022subheading_0022"></a> +<h3 class="section">7.83 <code>.sbttl "<var>subheading</var>"</code></h3> + +<a name="index-sbttl-directive"></a> +<a name="index-subtitles-for-listings"></a> +<a name="index-listing-control_003a-subtitle"></a> +<p>Use <var>subheading</var> as the title (third line, immediately after the +title line) when generating assembly listings. +</p> +<p>This directive affects subsequent pages, as well as the current page if +it appears within ten lines of the top of a page. +</p> +<hr> +<a name="Scl"></a> +<div class="header"> +<p> +Next: <a href="#Section" accesskey="n" rel="next">Section</a>, Previous: <a href="#Sbttl" accesskey="p" rel="previous">Sbttl</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002escl-class"></a> +<h3 class="section">7.84 <code>.scl <var>class</var></code></h3> + +<a name="index-scl-directive"></a> +<a name="index-symbol-storage-class-_0028COFF_0029"></a> +<a name="index-COFF-symbol-storage-class"></a> +<p>Set the storage-class value for a symbol. This directive may only be +used inside a <code>.def</code>/<code>.endef</code> pair. Storage class may flag +whether a symbol is static or external, or it may record further +symbolic debugging information. +</p> +<hr> +<a name="Section"></a> +<div class="header"> +<p> +Next: <a href="#Set" accesskey="n" rel="next">Set</a>, Previous: <a href="#Scl" accesskey="p" rel="previous">Scl</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002esection-name"></a> +<h3 class="section">7.85 <code>.section <var>name</var></code></h3> + +<a name="index-named-section"></a> +<p>Use the <code>.section</code> directive to assemble the following code into a section +named <var>name</var>. +</p> +<p>This directive is only supported for targets that actually support arbitrarily +named sections; on <code>a.out</code> targets, for example, it is not accepted, even +with a standard <code>a.out</code> section name. +</p> +<a name="COFF-Version"></a> +<h4 class="subheading">COFF Version</h4> + +<a name="index-section-directive-_0028COFF-version_0029"></a> +<p>For COFF targets, the <code>.section</code> directive is used in one of the following +ways: +</p> +<div class="smallexample"> +<pre class="smallexample">.section <var>name</var>[, "<var>flags</var>"] +.section <var>name</var>[, <var>subsection</var>] +</pre></div> + +<p>If the optional argument is quoted, it is taken as flags to use for the +section. Each flag is a single character. The following flags are recognized: +</p> +<dl compact="compact"> +<dt><code>b</code></dt> +<dd><p>bss section (uninitialized data) +</p></dd> +<dt><code>n</code></dt> +<dd><p>section is not loaded +</p></dd> +<dt><code>w</code></dt> +<dd><p>writable section +</p></dd> +<dt><code>d</code></dt> +<dd><p>data section +</p></dd> +<dt><code>e</code></dt> +<dd><p>exclude section from linking +</p></dd> +<dt><code>r</code></dt> +<dd><p>read-only section +</p></dd> +<dt><code>x</code></dt> +<dd><p>executable section +</p></dd> +<dt><code>s</code></dt> +<dd><p>shared section (meaningful for PE targets) +</p></dd> +<dt><code>a</code></dt> +<dd><p>ignored. (For compatibility with the ELF version) +</p></dd> +<dt><code>y</code></dt> +<dd><p>section is not readable (meaningful for PE targets) +</p></dd> +<dt><code>0-9</code></dt> +<dd><p>single-digit power-of-two section alignment (GNU extension) +</p></dd> +</dl> + +<p>If no flags are specified, the default flags depend upon the section name. If +the section name is not recognized, the default will be for the section to be +loaded and writable. Note the <code>n</code> and <code>w</code> flags remove attributes +from the section, rather than adding them, so if they are used on their own it +will be as if no flags had been specified at all. +</p> +<p>If the optional argument to the <code>.section</code> directive is not quoted, it is +taken as a subsection number (see <a href="#Sub_002dSections">Sub-Sections</a>). +</p> +<a name="ELF-Version"></a> +<h4 class="subheading">ELF Version</h4> + +<a name="index-Section-Stack-3"></a> +<p>This is one of the ELF section stack manipulation directives. The others are +<code>.subsection</code> (see <a href="#SubSection">SubSection</a>), <code>.pushsection</code> +(see <a href="#PushSection">PushSection</a>), <code>.popsection</code> (see <a href="#PopSection">PopSection</a>), and +<code>.previous</code> (see <a href="#Previous">Previous</a>). +</p> +<a name="index-section-directive-_0028ELF-version_0029"></a> +<p>For ELF targets, the <code>.section</code> directive is used like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.section <var>name</var> [, "<var>flags</var>"[, @<var>type</var>[,<var>flag_specific_arguments</var>]]] +</pre></div> + +<a name="Section-Name-Substitutions"></a><a name="index-_002d_002dsectname_002dsubst"></a> +<a name="index-section-name-substitution"></a> +<p>If the ‘<samp>--sectname-subst</samp>’ command-line option is provided, the <var>name</var> +argument may contain a substitution sequence. Only <code>%S</code> is supported +at the moment, and substitutes the current section name. For example: +</p> +<div class="smallexample"> +<pre class="smallexample">.macro exception_code +.section %S.exception +[exception code here] +.previous +.endm + +.text +[code] +exception_code +[...] + +.section .init +[init code] +exception_code +[...] +</pre></div> + +<p>The two <code>exception_code</code> invocations above would create the +<code>.text.exception</code> and <code>.init.exception</code> sections respectively. +This is useful e.g. to discriminate between ancillary sections that are +tied to setup code to be discarded after use from ancillary sections that +need to stay resident without having to define multiple <code>exception_code</code> +macros just for that purpose. +</p> +<p>The optional <var>flags</var> argument is a quoted string which may contain any +combination of the following characters: +</p> +<dl compact="compact"> +<dt><code>a</code></dt> +<dd><p>section is allocatable +</p></dd> +<dt><code>d</code></dt> +<dd><p>section is a GNU_MBIND section +</p></dd> +<dt><code>e</code></dt> +<dd><p>section is excluded from executable and shared library. +</p></dd> +<dt><code>o</code></dt> +<dd><p>section references a symbol defined in another section (the linked-to +section) in the same file. +</p></dd> +<dt><code>w</code></dt> +<dd><p>section is writable +</p></dd> +<dt><code>x</code></dt> +<dd><p>section is executable +</p></dd> +<dt><code>M</code></dt> +<dd><p>section is mergeable +</p></dd> +<dt><code>S</code></dt> +<dd><p>section contains zero terminated strings +</p></dd> +<dt><code>G</code></dt> +<dd><p>section is a member of a section group +</p></dd> +<dt><code>T</code></dt> +<dd><p>section is used for thread-local-storage +</p></dd> +<dt><code>?</code></dt> +<dd><p>section is a member of the previously-current section’s group, if any +</p></dd> +<dt><code>R</code></dt> +<dd><p>retained section (apply SHF_GNU_RETAIN to prevent linker garbage +collection, GNU ELF extension) +</p></dd> +<dt><code><code><number></code></code></dt> +<dd><p>a numeric value indicating the bits to be set in the ELF section header’s flags +field. Note - if one or more of the alphabetic characters described above is +also included in the flags field, their bit values will be ORed into the +resulting value. +</p></dd> +<dt><code><code><target specific></code></code></dt> +<dd><p>some targets extend this list with their own flag characters +</p></dd> +</dl> + +<p>Note - once a section’s flags have been set they cannot be changed. There are +a few exceptions to this rule however. Processor and application specific +flags can be added to an already defined section. The <code>.interp</code>, +<code>.strtab</code> and <code>.symtab</code> sections can have the allocate flag +(<code>a</code>) set after they are initially defined, and the <code>.note-GNU-stack</code> +section may have the executable (<code>x</code>) flag added. Also note that the +<code>.attach_to_group</code> directive can be used to add a section to a group even +if the section was not originally declared to be part of that group. +</p> +<p>The optional <var>type</var> argument may contain one of the following constants: +</p> +<dl compact="compact"> +<dt><code>@progbits</code></dt> +<dd><p>section contains data +</p></dd> +<dt><code>@nobits</code></dt> +<dd><p>section does not contain data (i.e., section only occupies space) +</p></dd> +<dt><code>@note</code></dt> +<dd><p>section contains data which is used by things other than the program +</p></dd> +<dt><code>@init_array</code></dt> +<dd><p>section contains an array of pointers to init functions +</p></dd> +<dt><code>@fini_array</code></dt> +<dd><p>section contains an array of pointers to finish functions +</p></dd> +<dt><code>@preinit_array</code></dt> +<dd><p>section contains an array of pointers to pre-init functions +</p></dd> +<dt><code>@<code><number></code></code></dt> +<dd><p>a numeric value to be set as the ELF section header’s type field. +</p></dd> +<dt><code>@<code><target specific></code></code></dt> +<dd><p>some targets extend this list with their own types +</p></dd> +</dl> + +<p>Many targets only support the first three section types. The type may be +enclosed in double quotes if necessary. +</p> +<p>Note on targets where the <code>@</code> character is the start of a comment (eg +ARM) then another character is used instead. For example the ARM port uses the +<code>%</code> character. +</p> +<p>Note - some sections, eg <code>.text</code> and <code>.data</code> are considered to be +special and have fixed types. Any attempt to declare them with a different +type will generate an error from the assembler. +</p> +<p>If <var>flags</var> contains the <code>M</code> symbol then the <var>type</var> argument must +be specified as well as an extra argument—<var>entsize</var>—like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.section <var>name</var> , "<var>flags</var>"M, @<var>type</var>, <var>entsize</var> +</pre></div> + +<p>Sections with the <code>M</code> flag but not <code>S</code> flag must contain fixed size +constants, each <var>entsize</var> octets long. Sections with both <code>M</code> and +<code>S</code> must contain zero terminated strings where each character is +<var>entsize</var> bytes long. The linker may remove duplicates within sections with +the same name, same entity size and same flags. <var>entsize</var> must be an +absolute expression. For sections with both <code>M</code> and <code>S</code>, a string +which is a suffix of a larger string is considered a duplicate. Thus +<code>"def"</code> will be merged with <code>"abcdef"</code>; A reference to the first +<code>"def"</code> will be changed to a reference to <code>"abcdef"+3</code>. +</p> +<p>If <var>flags</var> contains the <code>o</code> flag, then the <var>type</var> argument +must be present along with an additional field like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.section <var>name</var>,"<var>flags</var>"o,@<var>type</var>,<var>SymbolName</var>|<var>SectionIndex</var> +</pre></div> + +<p>The <var>SymbolName</var> field specifies the symbol name which the section +references. Alternatively a numeric <var>SectionIndex</var> can be provided. This +is not generally a good idea as section indicies are rarely known at assembly +time, but the facility is provided for testing purposes. An index of zero is +allowed. It indicates that the linked-to section has already been discarded. +</p> +<p>Note: If both the <var>M</var> and <var>o</var> flags are present, then the fields +for the Merge flag should come first, like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.section <var>name</var>,"<var>flags</var>"Mo,@<var>type</var>,<var>entsize</var>,<var>SymbolName</var> +</pre></div> + +<p>If <var>flags</var> contains the <code>G</code> symbol then the <var>type</var> argument must +be present along with an additional field like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.section <var>name</var> , "<var>flags</var>"G, @<var>type</var>, <var>GroupName</var>[, <var>linkage</var>] +</pre></div> + +<p>The <var>GroupName</var> field specifies the name of the section group to which this +particular section belongs. The optional linkage field can contain: +</p> +<dl compact="compact"> +<dt><code>comdat</code></dt> +<dd><p>indicates that only one copy of this section should be retained +</p></dd> +<dt><code>.gnu.linkonce</code></dt> +<dd><p>an alias for comdat +</p></dd> +</dl> + +<p>Note: if both the <var>M</var> and <var>G</var> flags are present then the fields for +the Merge flag should come first, like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.section <var>name</var> , "<var>flags</var>"MG, @<var>type</var>, <var>entsize</var>, <var>GroupName</var>[, <var>linkage</var>] +</pre></div> + +<p>If both <code>o</code> flag and <code>G</code> flag are present, then the +<var>SymbolName</var> field for <code>o</code> comes first, like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.section <var>name</var>,"<var>flags</var>"oG,@<var>type</var>,<var>SymbolName</var>,<var>GroupName</var>[,<var>linkage</var>] +</pre></div> + +<p>If <var>flags</var> contains the <code>?</code> symbol then it may not also contain the +<code>G</code> symbol and the <var>GroupName</var> or <var>linkage</var> fields should not be +present. Instead, <code>?</code> says to consider the section that’s current before +this directive. If that section used <code>G</code>, then the new section will use +<code>G</code> with those same <var>GroupName</var> and <var>linkage</var> fields implicitly. +If not, then the <code>?</code> symbol has no effect. +</p> +<p>The optional <var>unique,<code><number></code></var> argument must come last. It +assigns <var><code><number></code></var> as a unique section ID to distinguish +different sections with the same section name like these: +</p> +<div class="smallexample"> +<pre class="smallexample">.section <var>name</var>,"<var>flags</var>",@<var>type</var>,<var>unique,<code><number></code></var> +.section <var>name</var>,"<var>flags</var>"G,@<var>type</var>,<var>GroupName</var>,[<var>linkage</var>],<var>unique,<code><number></code></var> +.section <var>name</var>,"<var>flags</var>"MG,@<var>type</var>,<var>entsize</var>,<var>GroupName</var>[,<var>linkage</var>],<var>unique,<code><number></code></var> +</pre></div> + +<p>The valid values of <var><code><number></code></var> are between 0 and 4294967295. +</p> +<p>If no flags are specified, the default flags depend upon the section name. If +the section name is not recognized, the default will be for the section to have +none of the above flags: it will not be allocated in memory, nor writable, nor +executable. The section will contain data. +</p> +<p>For SPARC ELF targets, the assembler supports another type of <code>.section</code> +directive for compatibility with the Solaris assembler: +</p> +<div class="smallexample"> +<pre class="smallexample">.section "<var>name</var>"[, <var>flags</var>...] +</pre></div> + +<p>Note that the section name is quoted. There may be a sequence of comma +separated flags: +</p> +<dl compact="compact"> +<dt><code>#alloc</code></dt> +<dd><p>section is allocatable +</p></dd> +<dt><code>#write</code></dt> +<dd><p>section is writable +</p></dd> +<dt><code>#execinstr</code></dt> +<dd><p>section is executable +</p></dd> +<dt><code>#exclude</code></dt> +<dd><p>section is excluded from executable and shared library. +</p></dd> +<dt><code>#tls</code></dt> +<dd><p>section is used for thread local storage +</p></dd> +</dl> + +<p>This directive replaces the current section and subsection. See the +contents of the gas testsuite directory <code>gas/testsuite/gas/elf</code> for +some examples of how this directive and the other section stack directives +work. +</p> +<hr> +<a name="Set"></a> +<div class="header"> +<p> +Next: <a href="#Short" accesskey="n" rel="next">Short</a>, Previous: <a href="#Section" accesskey="p" rel="previous">Section</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eset-symbol_002c-expression"></a> +<h3 class="section">7.86 <code>.set <var>symbol</var>, <var>expression</var></code></h3> + +<a name="index-set-directive"></a> +<a name="index-symbol-value_002c-setting"></a> +<p>Set the value of <var>symbol</var> to <var>expression</var>. This +changes <var>symbol</var>’s value and type to conform to +<var>expression</var>. If <var>symbol</var> was flagged as external, it remains +flagged (see <a href="#Symbol-Attributes">Symbol Attributes</a>). +</p> +<p>You may <code>.set</code> a symbol many times in the same assembly provided that the +values given to the symbol are constants. Values that are based on expressions +involving other symbols are allowed, but some targets may restrict this to only +being done once per assembly. This is because those targets do not set the +addresses of symbols at assembly time, but rather delay the assignment until a +final link is performed. This allows the linker a chance to change the code in +the files, changing the location of, and the relative distance between, various +different symbols. +</p> +<p>If you <code>.set</code> a global symbol, the value stored in the object +file is the last value stored into it. +</p> +<p>On Z80 <code>set</code> is a real instruction, use <code>.set</code> or +‘<samp><var>symbol</var> defl <var>expression</var></samp>’ instead. +</p> +<hr> +<a name="Short"></a> +<div class="header"> +<p> +Next: <a href="#Single" accesskey="n" rel="next">Single</a>, Previous: <a href="#Set" accesskey="p" rel="previous">Set</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eshort-expressions"></a> +<h3 class="section">7.87 <code>.short <var>expressions</var></code></h3> + +<a name="index-short-directive"></a> +<p><code>.short</code> is normally the same as ‘<samp>.word</samp>’. +See <a href="#Word"><code>.word</code></a>. +</p> +<p>In some configurations, however, <code>.short</code> and <code>.word</code> generate +numbers of different lengths. See <a href="#Machine-Dependencies">Machine Dependencies</a>. +</p> +<p>Note - this directive is not intended for encoding instructions, and it will +not trigger effects like DWARF line number generation. Instead some targets +support special directives for encoding arbitrary binary sequences as +instructions such as <code>.insn</code> or <code>.inst</code>. +</p> +<hr> +<a name="Single"></a> +<div class="header"> +<p> +Next: <a href="#Size" accesskey="n" rel="next">Size</a>, Previous: <a href="#Short" accesskey="p" rel="previous">Short</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002esingle-flonums"></a> +<h3 class="section">7.88 <code>.single <var>flonums</var></code></h3> + +<a name="index-single-directive"></a> +<a name="index-floating-point-numbers-_0028single_0029-1"></a> +<p>This directive assembles zero or more flonums, separated by commas. It +has the same effect as <code>.float</code>. +The exact kind of floating point numbers emitted depends on how +<code>as</code> is configured. See <a href="#Machine-Dependencies">Machine Dependencies</a>. +</p> +<hr> +<a name="Size"></a> +<div class="header"> +<p> +Next: <a href="#Skip" accesskey="n" rel="next">Skip</a>, Previous: <a href="#Single" accesskey="p" rel="previous">Single</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002esize"></a> +<h3 class="section">7.89 <code>.size</code></h3> + +<p>This directive is used to set the size associated with a symbol. +</p> +<a name="COFF-Version-1"></a> +<h4 class="subheading">COFF Version</h4> + +<a name="index-size-directive-_0028COFF-version_0029"></a> +<p>For COFF targets, the <code>.size</code> directive is only permitted inside +<code>.def</code>/<code>.endef</code> pairs. It is used like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.size <var>expression</var> +</pre></div> + + +<a name="ELF-Version-1"></a> +<h4 class="subheading">ELF Version</h4> + +<a name="index-size-directive-_0028ELF-version_0029"></a> +<p>For ELF targets, the <code>.size</code> directive is used like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.size <var>name</var> , <var>expression</var> +</pre></div> + +<p>This directive sets the size associated with a symbol <var>name</var>. +The size in bytes is computed from <var>expression</var> which can make use of label +arithmetic. This directive is typically used to set the size of function +symbols. +</p> +<hr> +<a name="Skip"></a> +<div class="header"> +<p> +Next: <a href="#Sleb128" accesskey="n" rel="next">Sleb128</a>, Previous: <a href="#Size" accesskey="p" rel="previous">Size</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eskip-size-_005b_002cfill_005d"></a> +<h3 class="section">7.90 <code>.skip <var>size</var> [,<var>fill</var>]</code></h3> + +<a name="index-skip-directive"></a> +<a name="index-filling-memory"></a> +<p>This directive emits <var>size</var> bytes, each of value <var>fill</var>. Both +<var>size</var> and <var>fill</var> are absolute expressions. If the comma and +<var>fill</var> are omitted, <var>fill</var> is assumed to be zero. This is the same as +‘<samp>.space</samp>’. +</p> +<hr> +<a name="Sleb128"></a> +<div class="header"> +<p> +Next: <a href="#Space" accesskey="n" rel="next">Space</a>, Previous: <a href="#Skip" accesskey="p" rel="previous">Skip</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002esleb128-expressions"></a> +<h3 class="section">7.91 <code>.sleb128 <var>expressions</var></code></h3> + +<a name="index-sleb128-directive"></a> +<p><var>sleb128</var> stands for “signed little endian base 128.” This is a +compact, variable length representation of numbers used by the DWARF +symbolic debugging format. See <a href="#Uleb128"><code>.uleb128</code></a>. +</p> +<hr> +<a name="Space"></a> +<div class="header"> +<p> +Next: <a href="#Stab" accesskey="n" rel="next">Stab</a>, Previous: <a href="#Sleb128" accesskey="p" rel="previous">Sleb128</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002espace-size-_005b_002cfill_005d"></a> +<h3 class="section">7.92 <code>.space <var>size</var> [,<var>fill</var>]</code></h3> + +<a name="index-space-directive"></a> +<a name="index-filling-memory-1"></a> +<p>This directive emits <var>size</var> bytes, each of value <var>fill</var>. Both +<var>size</var> and <var>fill</var> are absolute expressions. If the comma +and <var>fill</var> are omitted, <var>fill</var> is assumed to be zero. This is the same +as ‘<samp>.skip</samp>’. +</p> +<blockquote> +<p><em>Warning:</em> <code>.space</code> has a completely different meaning for HPPA +targets; use <code>.block</code> as a substitute. See <cite>HP9000 Series 800 +Assembly Language Reference Manual</cite> (HP 92432-90001) for the meaning of the +<code>.space</code> directive. See <a href="#HPPA-Directives">HPPA Assembler Directives</a>, +for a summary. +</p></blockquote> + +<hr> +<a name="Stab"></a> +<div class="header"> +<p> +Next: <a href="#String" accesskey="n" rel="next">String</a>, Previous: <a href="#Space" accesskey="p" rel="previous">Space</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002estabd_002c-_002estabn_002c-_002estabs"></a> +<h3 class="section">7.93 <code>.stabd, .stabn, .stabs</code></h3> + +<a name="index-symbolic-debuggers_002c-information-for"></a> +<a name="index-stabx-directives"></a> +<p>There are three directives that begin ‘<samp>.stab</samp>’. +All emit symbols (see <a href="#Symbols">Symbols</a>), for use by symbolic debuggers. +The symbols are not entered in the <code>as</code> hash table: they +cannot be referenced elsewhere in the source file. +Up to five fields are required: +</p> +<dl compact="compact"> +<dt><var>string</var></dt> +<dd><p>This is the symbol’s name. It may contain any character except +‘<samp>\000</samp>’, so is more general than ordinary symbol names. Some +debuggers used to code arbitrarily complex structures into symbol names +using this field. +</p> +</dd> +<dt><var>type</var></dt> +<dd><p>An absolute expression. The symbol’s type is set to the low 8 bits of +this expression. Any bit pattern is permitted, but <code>ld</code> +and debuggers choke on silly bit patterns. +</p> +</dd> +<dt><var>other</var></dt> +<dd><p>An absolute expression. The symbol’s “other” attribute is set to the +low 8 bits of this expression. +</p> +</dd> +<dt><var>desc</var></dt> +<dd><p>An absolute expression. The symbol’s descriptor is set to the low 16 +bits of this expression. +</p> +</dd> +<dt><var>value</var></dt> +<dd><p>An absolute expression which becomes the symbol’s value. +</p></dd> +</dl> + +<p>If a warning is detected while reading a <code>.stabd</code>, <code>.stabn</code>, +or <code>.stabs</code> statement, the symbol has probably already been created; +you get a half-formed symbol in your object file. This is +compatible with earlier assemblers! +</p> +<dl compact="compact"> +<dd><a name="index-stabd-directive"></a> +</dd> +<dt><code>.stabd <var>type</var> , <var>other</var> , <var>desc</var></code></dt> +<dd> +<p>The “name” of the symbol generated is not even an empty string. +It is a null pointer, for compatibility. Older assemblers used a +null pointer so they didn’t waste space in object files with empty +strings. +</p> +<p>The symbol’s value is set to the location counter, +relocatably. When your program is linked, the value of this symbol +is the address of the location counter when the <code>.stabd</code> was +assembled. +</p> +<a name="index-stabn-directive"></a> +</dd> +<dt><code>.stabn <var>type</var> , <var>other</var> , <var>desc</var> , <var>value</var></code></dt> +<dd><p>The name of the symbol is set to the empty string <code>""</code>. +</p> +<a name="index-stabs-directive"></a> +</dd> +<dt><code>.stabs <var>string</var> , <var>type</var> , <var>other</var> , <var>desc</var> , <var>value</var></code></dt> +<dd><p>All five fields are specified. +</p></dd> +</dl> + +<hr> +<a name="String"></a> +<div class="header"> +<p> +Next: <a href="#Struct" accesskey="n" rel="next">Struct</a>, Previous: <a href="#Stab" accesskey="p" rel="previous">Stab</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002estring-_0022str_0022_002c-_002estring8-_0022str_0022_002c-_002estring16"></a> +<h3 class="section">7.94 <code>.string</code> "<var>str</var>", <code>.string8</code> "<var>str</var>", <code>.string16</code></h3> +<p>"<var>str</var>", <code>.string32</code> "<var>str</var>", <code>.string64</code> "<var>str</var>" +</p> +<a name="index-string_002c-copying-to-object-file"></a> +<a name="index-string8_002c-copying-to-object-file"></a> +<a name="index-string16_002c-copying-to-object-file"></a> +<a name="index-string32_002c-copying-to-object-file"></a> +<a name="index-string64_002c-copying-to-object-file"></a> +<a name="index-string-directive"></a> +<a name="index-string8-directive"></a> +<a name="index-string16-directive"></a> +<a name="index-string32-directive"></a> +<a name="index-string64-directive"></a> + +<p>Copy the characters in <var>str</var> to the object file. You may specify more than +one string to copy, separated by commas. Unless otherwise specified for a +particular machine, the assembler marks the end of each string with a 0 byte. +You can use any of the escape sequences described in <a href="#Strings">Strings</a>. +</p> +<p>The variants <code>string16</code>, <code>string32</code> and <code>string64</code> differ from +the <code>string</code> pseudo opcode in that each 8-bit character from <var>str</var> is +copied and expanded to 16, 32 or 64 bits respectively. The expanded characters +are stored in target endianness byte order. +</p> +<p>Example: +</p><div class="smallexample"> +<pre class="smallexample"> .string32 "BYE" +expands to: + .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ + .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */ +</pre></div> + + +<hr> +<a name="Struct"></a> +<div class="header"> +<p> +Next: <a href="#SubSection" accesskey="n" rel="next">SubSection</a>, Previous: <a href="#String" accesskey="p" rel="previous">String</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002estruct-expression"></a> +<h3 class="section">7.95 <code>.struct <var>expression</var></code></h3> + +<a name="index-struct-directive"></a> +<p>Switch to the absolute section, and set the section offset to <var>expression</var>, +which must be an absolute expression. You might use this as follows: +</p><div class="smallexample"> +<pre class="smallexample"> .struct 0 +field1: + .struct field1 + 4 +field2: + .struct field2 + 4 +field3: +</pre></div> +<p>This would define the symbol <code>field1</code> to have the value 0, the symbol +<code>field2</code> to have the value 4, and the symbol <code>field3</code> to have the +value 8. Assembly would be left in the absolute section, and you would need to +use a <code>.section</code> directive of some sort to change to some other section +before further assembly. +</p> +<hr> +<a name="SubSection"></a> +<div class="header"> +<p> +Next: <a href="#Symver" accesskey="n" rel="next">Symver</a>, Previous: <a href="#Struct" accesskey="p" rel="previous">Struct</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002esubsection-name"></a> +<h3 class="section">7.96 <code>.subsection <var>name</var></code></h3> + +<a name="index-subsection-directive"></a> +<a name="index-Section-Stack-4"></a> +<p>This is one of the ELF section stack manipulation directives. The others are +<code>.section</code> (see <a href="#Section">Section</a>), <code>.pushsection</code> (see <a href="#PushSection">PushSection</a>), +<code>.popsection</code> (see <a href="#PopSection">PopSection</a>), and <code>.previous</code> +(see <a href="#Previous">Previous</a>). +</p> +<p>This directive replaces the current subsection with <code>name</code>. The current +section is not changed. The replaced subsection is put onto the section stack +in place of the then current top of stack subsection. +</p> +<hr> +<a name="Symver"></a> +<div class="header"> +<p> +Next: <a href="#Tag" accesskey="n" rel="next">Tag</a>, Previous: <a href="#SubSection" accesskey="p" rel="previous">SubSection</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002esymver"></a> +<h3 class="section">7.97 <code>.symver</code></h3> +<a name="index-symver-directive"></a> +<a name="index-symbol-versioning"></a> +<a name="index-versions-of-symbols"></a> +<p>Use the <code>.symver</code> directive to bind symbols to specific version nodes +within a source file. This is only supported on ELF platforms, and is +typically used when assembling files to be linked into a shared library. +There are cases where it may make sense to use this in objects to be bound +into an application itself so as to override a versioned symbol from a +shared library. +</p> +<p>For ELF targets, the <code>.symver</code> directive can be used like this: +</p><div class="smallexample"> +<pre class="smallexample">.symver <var>name</var>, <var>name2@nodename</var>[ ,<var>visibility</var>] +</pre></div> +<p>If the original symbol <var>name</var> is defined within the file +being assembled, the <code>.symver</code> directive effectively creates a symbol +alias with the name <var>name2@nodename</var>, and in fact the main reason that we +just don’t try and create a regular alias is that the <var>@</var> character isn’t +permitted in symbol names. The <var>name2</var> part of the name is the actual name +of the symbol by which it will be externally referenced. The name <var>name</var> +itself is merely a name of convenience that is used so that it is possible to +have definitions for multiple versions of a function within a single source +file, and so that the compiler can unambiguously know which version of a +function is being mentioned. The <var>nodename</var> portion of the alias should be +the name of a node specified in the version script supplied to the linker when +building a shared library. If you are attempting to override a versioned +symbol from a shared library, then <var>nodename</var> should correspond to the +nodename of the symbol you are trying to override. The optional argument +<var>visibility</var> updates the visibility of the original symbol. The valid +visibilities are <code>local</code>, <code>hidden</code>, and <code>remove</code>. The +<code>local</code> visibility makes the original symbol a local symbol +(see <a href="#Local">Local</a>). The <code>hidden</code> visibility sets the visibility of the +original symbol to <code>hidden</code> (see <a href="#Hidden">Hidden</a>). The <code>remove</code> +visibility removes the original symbol from the symbol table. If visibility +isn’t specified, the original symbol is unchanged. +</p> +<p>If the symbol <var>name</var> is not defined within the file being assembled, all +references to <var>name</var> will be changed to <var>name2@nodename</var>. If no +reference to <var>name</var> is made, <var>name2@nodename</var> will be removed from the +symbol table. +</p> +<p>Another usage of the <code>.symver</code> directive is: +</p><div class="smallexample"> +<pre class="smallexample">.symver <var>name</var>, <var>name2@@nodename</var> +</pre></div> +<p>In this case, the symbol <var>name</var> must exist and be defined within +the file being assembled. It is similar to <var>name2@nodename</var>. The +difference is <var>name2@@nodename</var> will also be used to resolve +references to <var>name2</var> by the linker. +</p> +<p>The third usage of the <code>.symver</code> directive is: +</p><div class="smallexample"> +<pre class="smallexample">.symver <var>name</var>, <var>name2@@@nodename</var> +</pre></div> +<p>When <var>name</var> is not defined within the +file being assembled, it is treated as <var>name2@nodename</var>. When +<var>name</var> is defined within the file being assembled, the symbol +name, <var>name</var>, will be changed to <var>name2@@nodename</var>. +</p> +<hr> +<a name="Tag"></a> +<div class="header"> +<p> +Next: <a href="#Text" accesskey="n" rel="next">Text</a>, Previous: <a href="#Symver" accesskey="p" rel="previous">Symver</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002etag-structname"></a> +<h3 class="section">7.98 <code>.tag <var>structname</var></code></h3> + +<a name="index-COFF-structure-debugging"></a> +<a name="index-structure-debugging_002c-COFF"></a> +<a name="index-tag-directive"></a> +<p>This directive is generated by compilers to include auxiliary debugging +information in the symbol table. It is only permitted inside +<code>.def</code>/<code>.endef</code> pairs. Tags are used to link structure +definitions in the symbol table with instances of those structures. +</p> +<hr> +<a name="Text"></a> +<div class="header"> +<p> +Next: <a href="#Title" accesskey="n" rel="next">Title</a>, Previous: <a href="#Tag" accesskey="p" rel="previous">Tag</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002etext-subsection"></a> +<h3 class="section">7.99 <code>.text <var>subsection</var></code></h3> + +<a name="index-text-directive"></a> +<p>Tells <code>as</code> to assemble the following statements onto the end of +the text subsection numbered <var>subsection</var>, which is an absolute +expression. If <var>subsection</var> is omitted, subsection number zero +is used. +</p> +<hr> +<a name="Title"></a> +<div class="header"> +<p> +Next: <a href="#Tls_005fcommon" accesskey="n" rel="next">Tls_common</a>, Previous: <a href="#Text" accesskey="p" rel="previous">Text</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002etitle-_0022heading_0022"></a> +<h3 class="section">7.100 <code>.title "<var>heading</var>"</code></h3> + +<a name="index-title-directive"></a> +<a name="index-listing-control_003a-title-line"></a> +<p>Use <var>heading</var> as the title (second line, immediately after the +source file name and pagenumber) when generating assembly listings. +</p> +<p>This directive affects subsequent pages, as well as the current page if +it appears within ten lines of the top of a page. +</p> +<hr> +<a name="Tls_005fcommon"></a> +<div class="header"> +<p> +Next: <a href="#Type" accesskey="n" rel="next">Type</a>, Previous: <a href="#Title" accesskey="p" rel="previous">Title</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002etls_005fcommon-symbol_002c-length_005b_002c-alignment_005d"></a> +<h3 class="section">7.101 <code>.tls_common <var>symbol</var>, <var>length</var>[, <var>alignment</var>]</code></h3> + +<a name="index-tls_005fcommon-directive"></a> +<p>This directive behaves in the same way as the <code>.comm</code> directive +(see <a href="#Comm">Comm</a>) except that <var>symbol</var> has type of STT_TLS instead of +STT_OBJECT. +</p> +<hr> +<a name="Type"></a> +<div class="header"> +<p> +Next: <a href="#Uleb128" accesskey="n" rel="next">Uleb128</a>, Previous: <a href="#Tls_005fcommon" accesskey="p" rel="previous">Tls_common</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002etype"></a> +<h3 class="section">7.102 <code>.type</code></h3> + +<p>This directive is used to set the type of a symbol. +</p> +<a name="COFF-Version-2"></a> +<h4 class="subheading">COFF Version</h4> + +<a name="index-COFF-symbol-type"></a> +<a name="index-symbol-type_002c-COFF"></a> +<a name="index-type-directive-_0028COFF-version_0029"></a> +<p>For COFF targets, this directive is permitted only within +<code>.def</code>/<code>.endef</code> pairs. It is used like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.type <var>int</var> +</pre></div> + +<p>This records the integer <var>int</var> as the type attribute of a symbol table +entry. +</p> + +<a name="ELF-Version-2"></a> +<h4 class="subheading">ELF Version</h4> + +<a name="index-ELF-symbol-type"></a> +<a name="index-symbol-type_002c-ELF"></a> +<a name="index-type-directive-_0028ELF-version_0029"></a> +<p>For ELF targets, the <code>.type</code> directive is used like this: +</p> +<div class="smallexample"> +<pre class="smallexample">.type <var>name</var> , <var>type description</var> +</pre></div> + +<p>This sets the type of symbol <var>name</var> to be either a +function symbol or an object symbol. There are five different syntaxes +supported for the <var>type description</var> field, in order to provide +compatibility with various other assemblers. +</p> +<p>Because some of the characters used in these syntaxes (such as ‘<samp>@</samp>’ and +‘<samp>#</samp>’) are comment characters for some architectures, some of the syntaxes +below do not work on all architectures. The first variant will be accepted by +the GNU assembler on all architectures so that variant should be used for +maximum portability, if you do not need to assemble your code with other +assemblers. +</p> +<p>The syntaxes supported are: +</p> +<div class="smallexample"> +<pre class="smallexample"> .type <name> STT_<TYPE_IN_UPPER_CASE> + .type <name>,#<type> + .type <name>,@<type> + .type <name>,%<type> + .type <name>,"<type>" +</pre></div> + +<p>The types supported are: +</p> +<dl compact="compact"> +<dt><code>STT_FUNC</code></dt> +<dt><code>function</code></dt> +<dd><p>Mark the symbol as being a function name. +</p> +</dd> +<dt><code>STT_GNU_IFUNC</code></dt> +<dt><code>gnu_indirect_function</code></dt> +<dd><p>Mark the symbol as an indirect function when evaluated during reloc +processing. (This is only supported on assemblers targeting GNU systems). +</p> +</dd> +<dt><code>STT_OBJECT</code></dt> +<dt><code>object</code></dt> +<dd><p>Mark the symbol as being a data object. +</p> +</dd> +<dt><code>STT_TLS</code></dt> +<dt><code>tls_object</code></dt> +<dd><p>Mark the symbol as being a thread-local data object. +</p> +</dd> +<dt><code>STT_COMMON</code></dt> +<dt><code>common</code></dt> +<dd><p>Mark the symbol as being a common data object. +</p> +</dd> +<dt><code>STT_NOTYPE</code></dt> +<dt><code>notype</code></dt> +<dd><p>Does not mark the symbol in any way. It is supported just for completeness. +</p> +</dd> +<dt><code>gnu_unique_object</code></dt> +<dd><p>Marks the symbol as being a globally unique data object. The dynamic linker +will make sure that in the entire process there is just one symbol with this +name and type in use. (This is only supported on assemblers targeting GNU +systems). +</p> +</dd> +</dl> + +<p>Changing between incompatible types other than from/to STT_NOTYPE will +result in a diagnostic. An intermediate change to STT_NOTYPE will silence +this. +</p> +<p>Note: Some targets support extra types in addition to those listed above. +</p> + +<hr> +<a name="Uleb128"></a> +<div class="header"> +<p> +Next: <a href="#Val" accesskey="n" rel="next">Val</a>, Previous: <a href="#Type" accesskey="p" rel="previous">Type</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002euleb128-expressions"></a> +<h3 class="section">7.103 <code>.uleb128 <var>expressions</var></code></h3> + +<a name="index-uleb128-directive"></a> +<p><var>uleb128</var> stands for “unsigned little endian base 128.” This is a +compact, variable length representation of numbers used by the DWARF +symbolic debugging format. See <a href="#Sleb128"><code>.sleb128</code></a>. +</p> +<hr> +<a name="Val"></a> +<div class="header"> +<p> +Next: <a href="#Version" accesskey="n" rel="next">Version</a>, Previous: <a href="#Uleb128" accesskey="p" rel="previous">Uleb128</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eval-addr"></a> +<h3 class="section">7.104 <code>.val <var>addr</var></code></h3> + +<a name="index-val-directive"></a> +<a name="index-COFF-value-attribute"></a> +<a name="index-value-attribute_002c-COFF"></a> +<p>This directive, permitted only within <code>.def</code>/<code>.endef</code> pairs, +records the address <var>addr</var> as the value attribute of a symbol table +entry. +</p> +<hr> +<a name="Version"></a> +<div class="header"> +<p> +Next: <a href="#VTableEntry" accesskey="n" rel="next">VTableEntry</a>, Previous: <a href="#Val" accesskey="p" rel="previous">Val</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eversion-_0022string_0022"></a> +<h3 class="section">7.105 <code>.version "<var>string</var>"</code></h3> + +<a name="index-version-directive"></a> +<p>This directive creates a <code>.note</code> section and places into it an ELF +formatted note of type NT_VERSION. The note’s name is set to <code>string</code>. +</p> +<hr> +<a name="VTableEntry"></a> +<div class="header"> +<p> +Next: <a href="#VTableInherit" accesskey="n" rel="next">VTableInherit</a>, Previous: <a href="#Version" accesskey="p" rel="previous">Version</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002evtable_005fentry-table_002c-offset"></a> +<h3 class="section">7.106 <code>.vtable_entry <var>table</var>, <var>offset</var></code></h3> + +<a name="index-vtable_005fentry-directive"></a> +<p>This directive finds or creates a symbol <code>table</code> and creates a +<code>VTABLE_ENTRY</code> relocation for it with an addend of <code>offset</code>. +</p> +<hr> +<a name="VTableInherit"></a> +<div class="header"> +<p> +Next: <a href="#Warning" accesskey="n" rel="next">Warning</a>, Previous: <a href="#VTableEntry" accesskey="p" rel="previous">VTableEntry</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002evtable_005finherit-child_002c-parent"></a> +<h3 class="section">7.107 <code>.vtable_inherit <var>child</var>, <var>parent</var></code></h3> + +<a name="index-vtable_005finherit-directive"></a> +<p>This directive finds the symbol <code>child</code> and finds or creates the symbol +<code>parent</code> and then creates a <code>VTABLE_INHERIT</code> relocation for the +parent whose addend is the value of the child symbol. As a special case the +parent name of <code>0</code> is treated as referring to the <code>*ABS*</code> section. +</p> +<hr> +<a name="Warning"></a> +<div class="header"> +<p> +Next: <a href="#Weak" accesskey="n" rel="next">Weak</a>, Previous: <a href="#VTableInherit" accesskey="p" rel="previous">VTableInherit</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ewarning-_0022string_0022"></a> +<h3 class="section">7.108 <code>.warning "<var>string</var>"</code></h3> +<a name="index-warning-directive"></a> +<p>Similar to the directive <code>.error</code> +(see <a href="#Error"><code>.error "<var>string</var>"</code></a>), but just emits a warning. +</p> +<hr> +<a name="Weak"></a> +<div class="header"> +<p> +Next: <a href="#Weakref" accesskey="n" rel="next">Weakref</a>, Previous: <a href="#Warning" accesskey="p" rel="previous">Warning</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eweak-names"></a> +<h3 class="section">7.109 <code>.weak <var>names</var></code></h3> + +<a name="index-weak-directive"></a> +<p>This directive sets the weak attribute on the comma separated list of symbol +<code>names</code>. If the symbols do not already exist, they will be created. +</p> +<p>On COFF targets other than PE, weak symbols are a GNU extension. This +directive sets the weak attribute on the comma separated list of symbol +<code>names</code>. If the symbols do not already exist, they will be created. +</p> +<p>On the PE target, weak symbols are supported natively as weak aliases. +When a weak symbol is created that is not an alias, GAS creates an +alternate symbol to hold the default value. +</p> +<hr> +<a name="Weakref"></a> +<div class="header"> +<p> +Next: <a href="#Word" accesskey="n" rel="next">Word</a>, Previous: <a href="#Weak" accesskey="p" rel="previous">Weak</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eweakref-alias_002c-target"></a> +<h3 class="section">7.110 <code>.weakref <var>alias</var>, <var>target</var></code></h3> + +<a name="index-weakref-directive"></a> +<p>This directive creates an alias to the target symbol that enables the symbol to +be referenced with weak-symbol semantics, but without actually making it weak. +If direct references or definitions of the symbol are present, then the symbol +will not be weak, but if all references to it are through weak references, the +symbol will be marked as weak in the symbol table. +</p> +<p>The effect is equivalent to moving all references to the alias to a separate +assembly source file, renaming the alias to the symbol in it, declaring the +symbol as weak there, and running a reloadable link to merge the object files +resulting from the assembly of the new source file and the old source file that +had the references to the alias removed. +</p> +<p>The alias itself never makes to the symbol table, and is entirely handled +within the assembler. +</p> +<hr> +<a name="Word"></a> +<div class="header"> +<p> +Next: <a href="#Zero" accesskey="n" rel="next">Zero</a>, Previous: <a href="#Weakref" accesskey="p" rel="previous">Weakref</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002eword-expressions"></a> +<h3 class="section">7.111 <code>.word <var>expressions</var></code></h3> + +<a name="index-word-directive"></a> +<p>This directive expects zero or more <var>expressions</var>, of any section, +separated by commas. +</p> +<p>The size of the number emitted, and its byte order, +depend on what target computer the assembly is for. +</p> +<a name="index-difference-tables-altered"></a> +<a name="index-altered-difference-tables"></a> +<blockquote> +<p><em>Warning: Special Treatment to support Compilers</em> +</p></blockquote> + +<p>Machines with a 32-bit address space, but that do less than 32-bit +addressing, require the following special treatment. If the machine of +interest to you does 32-bit addressing (or doesn’t require it; +see <a href="#Machine-Dependencies">Machine Dependencies</a>), you can ignore this issue. +</p> +<p>In order to assemble compiler output into something that works, +<code>as</code> occasionally does strange things to ‘<samp>.word</samp>’ directives. +Directives of the form ‘<samp>.word sym1-sym2</samp>’ are often emitted by +compilers as part of jump tables. Therefore, when <code>as</code> assembles a +directive of the form ‘<samp>.word sym1-sym2</samp>’, and the difference between +<code>sym1</code> and <code>sym2</code> does not fit in 16 bits, <code>as</code> +creates a <em>secondary jump table</em>, immediately before the next label. +This secondary jump table is preceded by a short-jump to the +first byte after the secondary table. This short-jump prevents the flow +of control from accidentally falling into the new table. Inside the +table is a long-jump to <code>sym2</code>. The original ‘<samp>.word</samp>’ +contains <code>sym1</code> minus the address of the long-jump to +<code>sym2</code>. +</p> +<p>If there were several occurrences of ‘<samp>.word sym1-sym2</samp>’ before the +secondary jump table, all of them are adjusted. If there was a +‘<samp>.word sym3-sym4</samp>’, that also did not fit in sixteen bits, a +long-jump to <code>sym4</code> is included in the secondary jump table, +and the <code>.word</code> directives are adjusted to contain <code>sym3</code> +minus the address of the long-jump to <code>sym4</code>; and so on, for as many +entries in the original jump table as necessary. +</p> + +<hr> +<a name="Zero"></a> +<div class="header"> +<p> +Next: <a href="#g_t2byte" accesskey="n" rel="next">2byte</a>, Previous: <a href="#Word" accesskey="p" rel="previous">Word</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002ezero-size"></a> +<h3 class="section">7.112 <code>.zero <var>size</var></code></h3> + +<a name="index-zero-directive"></a> +<a name="index-filling-memory-with-zero-bytes"></a> +<p>This directive emits <var>size</var> 0-valued bytes. <var>size</var> must be an absolute +expression. This directive is actually an alias for the ‘<samp>.skip</samp>’ directive +so it can take an optional second argument of the value to store in the bytes +instead of zero. Using ‘<samp>.zero</samp>’ in this way would be confusing however. +</p> +<hr> +<a name="g_t2byte"></a> +<div class="header"> +<p> +Next: <a href="#g_t4byte" accesskey="n" rel="next">4byte</a>, Previous: <a href="#Zero" accesskey="p" rel="previous">Zero</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002e2byte-expression-_005b_002c-expression_005d_002a"></a> +<h3 class="section">7.113 <code>.2byte <var>expression</var> [, <var>expression</var>]*</code></h3> +<a name="index-2byte-directive"></a> +<a name="index-two_002dbyte-integer"></a> +<a name="index-integer_002c-2_002dbyte"></a> + +<p>This directive expects zero or more expressions, separated by commas. If there +are no expressions then the directive does nothing. Otherwise each expression +is evaluated in turn and placed in the next two bytes of the current output +section, using the endian model of the target. If an expression will not fit +in two bytes, a warning message is displayed and the least significant two +bytes of the expression’s value are used. If an expression cannot be evaluated +at assembly time then relocations will be generated in order to compute the +value at link time. +</p> +<p>This directive does not apply any alignment before or after inserting the +values. As a result of this, if relocations are generated, they may be +different from those used for inserting values with a guaranteed alignment. +</p> +<hr> +<a name="g_t4byte"></a> +<div class="header"> +<p> +Next: <a href="#g_t8byte" accesskey="n" rel="next">8byte</a>, Previous: <a href="#g_t2byte" accesskey="p" rel="previous">2byte</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002e4byte-expression-_005b_002c-expression_005d_002a"></a> +<h3 class="section">7.114 <code>.4byte <var>expression</var> [, <var>expression</var>]*</code></h3> +<a name="index-4byte-directive"></a> +<a name="index-four_002dbyte-integer"></a> +<a name="index-integer_002c-4_002dbyte"></a> + +<p>Like the <samp>.2byte</samp> directive, except that it inserts unaligned, four byte +long values into the output. +</p> +<hr> +<a name="g_t8byte"></a> +<div class="header"> +<p> +Next: <a href="#Deprecated" accesskey="n" rel="next">Deprecated</a>, Previous: <a href="#g_t4byte" accesskey="p" rel="previous">4byte</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_002e8byte-expression-_005b_002c-expression_005d_002a"></a> +<h3 class="section">7.115 <code>.8byte <var>expression</var> [, <var>expression</var>]*</code></h3> +<a name="index-8byte-directive"></a> +<a name="index-eight_002dbyte-integer-1"></a> +<a name="index-integer_002c-8_002dbyte-1"></a> + +<p>For 64-bit architectures, or more generally with any GAS configured to support +64-bit target virtual addresses, this is like the <samp>.2byte</samp> directive, +except that it inserts unaligned, eight byte long values into the output. +Otherwise, like <a href="#Quad"><code>.quad <var>expressions</var></code></a>, it expects zero or +more bignums, separated by commas. +</p> +<hr> +<a name="Deprecated"></a> +<div class="header"> +<p> +Previous: <a href="#g_t8byte" accesskey="p" rel="previous">8byte</a>, Up: <a href="#Pseudo-Ops" accesskey="u" rel="up">Pseudo Ops</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Deprecated-Directives"></a> +<h3 class="section">7.116 Deprecated Directives</h3> + +<a name="index-deprecated-directives"></a> +<a name="index-obsolescent-directives"></a> +<p>One day these directives won’t work. +They are included for compatibility with older assemblers. +</p><dl compact="compact"> +<dt><tt>.abort</tt></dt> +<dt><tt>.line</tt></dt> +</dl> + +<hr> +<a name="Object-Attributes"></a> +<div class="header"> +<p> +Next: <a href="#Machine-Dependencies" accesskey="n" rel="next">Machine Dependencies</a>, Previous: <a href="#Pseudo-Ops" accesskey="p" rel="previous">Pseudo Ops</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Object-Attributes-1"></a> +<h2 class="chapter">8 Object Attributes</h2> +<a name="index-object-attributes"></a> + +<p><code>as</code> assembles source files written for a specific architecture +into object files for that architecture. But not all object files are alike. +Many architectures support incompatible variations. For instance, floating +point arguments might be passed in floating point registers if the object file +requires hardware floating point support—or floating point arguments might be +passed in integer registers if the object file supports processors with no +hardware floating point unit. Or, if two objects are built for different +generations of the same architecture, the combination may require the +newer generation at run-time. +</p> +<p>This information is useful during and after linking. At link time, +<code>ld</code> can warn about incompatible object files. After link +time, tools like <code>gdb</code> can use it to process the linked file +correctly. +</p> +<p>Compatibility information is recorded as a series of object attributes. Each +attribute has a <em>vendor</em>, <em>tag</em>, and <em>value</em>. The vendor is a +string, and indicates who sets the meaning of the tag. The tag is an integer, +and indicates what property the attribute describes. The value may be a string +or an integer, and indicates how the property affects this object. Missing +attributes are the same as attributes with a zero value or empty string value. +</p> +<p>Object attributes were developed as part of the ABI for the ARM Architecture. +The file format is documented in <cite>ELF for the ARM Architecture</cite>. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#GNU-Object-Attributes" accesskey="1">GNU Object Attributes</a>:</td><td> </td><td align="left" valign="top"><small>GNU</small> Object Attributes +</td></tr> +<tr><td align="left" valign="top">• <a href="#Defining-New-Object-Attributes" accesskey="2">Defining New Object Attributes</a>:</td><td> </td><td align="left" valign="top">Defining New Object Attributes +</td></tr> +</table> + +<hr> +<a name="GNU-Object-Attributes"></a> +<div class="header"> +<p> +Next: <a href="#Defining-New-Object-Attributes" accesskey="n" rel="next">Defining New Object Attributes</a>, Up: <a href="#Object-Attributes" accesskey="u" rel="up">Object Attributes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="GNU-Object-Attributes-1"></a> +<h3 class="section">8.1 <small>GNU</small> Object Attributes</h3> + +<p>The <code>.gnu_attribute</code> directive records an object attribute +with vendor ‘<samp>gnu</samp>’. +</p> +<p>Except for ‘<samp>Tag_compatibility</samp>’, which has both an integer and a string for +its value, <small>GNU</small> attributes have a string value if the tag number is odd and +an integer value if the tag number is even. The second bit (<code><var>tag</var> & +2</code> is set for architecture-independent attributes and clear for +architecture-dependent ones. +</p> +<a name="Common-GNU-attributes"></a> +<h4 class="subsection">8.1.1 Common <small>GNU</small> attributes</h4> + +<p>These attributes are valid on all architectures. +</p> +<dl compact="compact"> +<dt><span class="roman">Tag_compatibility (32)</span></dt> +<dd><p>The compatibility attribute takes an integer flag value and a vendor name. If +the flag value is 0, the file is compatible with other toolchains. If it is 1, +then the file is only compatible with the named toolchain. If it is greater +than 1, the file can only be processed by other toolchains under some private +arrangement indicated by the flag value and the vendor name. +</p></dd> +</dl> + +<a name="M680x0-Attributes"></a> +<h4 class="subsection">8.1.2 M680x0 Attributes</h4> + +<dl compact="compact"> +<dt><span class="roman">Tag_GNU_M68K_ABI_FP (4)</span></dt> +<dd><p>The floating-point ABI used by this object file. The value will be: +</p> +<ul> +<li> 0 for files not affected by the floating-point ABI. +</li><li> 1 for files using double-precision hardware floating-point ABI. +</li><li> 2 for files using the software floating-point ABI. +</li></ul> +</dd> +</dl> + +<a name="MIPS-Attributes"></a> +<h4 class="subsection">8.1.3 MIPS Attributes</h4> + +<dl compact="compact"> +<dt><span class="roman">Tag_GNU_MIPS_ABI_FP (4)</span></dt> +<dd><p>The floating-point ABI used by this object file. The value will be: +</p> +<ul> +<li> 0 for files not affected by the floating-point ABI. +</li><li> 1 for files using the hardware floating-point ABI with a standard +double-precision FPU. +</li><li> 2 for files using the hardware floating-point ABI with a single-precision FPU. +</li><li> 3 for files using the software floating-point ABI. +</li><li> 4 for files using the deprecated hardware floating-point ABI which used 64-bit +floating-point registers, 32-bit general-purpose registers and increased the +number of callee-saved floating-point registers. +</li><li> 5 for files using the hardware floating-point ABI with a double-precision FPU +with either 32-bit or 64-bit floating-point registers and 32-bit +general-purpose registers. +</li><li> 6 for files using the hardware floating-point ABI with 64-bit floating-point +registers and 32-bit general-purpose registers. +</li><li> 7 for files using the hardware floating-point ABI with 64-bit floating-point +registers, 32-bit general-purpose registers and a rule that forbids the +direct use of odd-numbered single-precision floating-point registers. +</li></ul> + +</dd> +<dt><span class="roman">Tag_GNU_MIPS_ABI_MSA (8)</span></dt> +<dd><p>The MIPS SIMD Architecture (MSA) ABI used by this object file. The value +will be: +</p> +<ul> +<li> 0 for files not affected by the MSA ABI. +</li><li> 1 for files using the 128-bit MSA ABI. +</li></ul> + +</dd> +</dl> + +<a name="PowerPC-Attributes"></a> +<h4 class="subsection">8.1.4 PowerPC Attributes</h4> + +<dl compact="compact"> +<dt><span class="roman">Tag_GNU_Power_ABI_FP (4)</span></dt> +<dd><p>The floating-point ABI used by this object file. The value will be: +</p> +<ul> +<li> 0 for files not affected by the floating-point ABI. +</li><li> 1 for files using double-precision hardware floating-point ABI. +</li><li> 2 for files using the software floating-point ABI. +</li><li> 3 for files using single-precision hardware floating-point ABI. +</li></ul> + +</dd> +<dt><span class="roman">Tag_GNU_Power_ABI_Vector (8)</span></dt> +<dd><p>The vector ABI used by this object file. The value will be: +</p> +<ul> +<li> 0 for files not affected by the vector ABI. +</li><li> 1 for files using general purpose registers to pass vectors. +</li><li> 2 for files using AltiVec registers to pass vectors. +</li><li> 3 for files using SPE registers to pass vectors. +</li></ul> +</dd> +</dl> + +<a name="IBM-z-Systems-Attributes"></a> +<h4 class="subsection">8.1.5 IBM z Systems Attributes</h4> + +<dl compact="compact"> +<dt><span class="roman">Tag_GNU_S390_ABI_Vector (8)</span></dt> +<dd><p>The vector ABI used by this object file. The value will be: +</p> +<ul> +<li> 0 for files not affected by the vector ABI. +</li><li> 1 for files using software vector ABI. +</li><li> 2 for files using hardware vector ABI. +</li></ul> +</dd> +</dl> + +<a name="MSP430-Attributes"></a> +<h4 class="subsection">8.1.6 MSP430 Attributes</h4> + +<dl compact="compact"> +<dt><span class="roman">Tag_GNU_MSP430_Data_Region (4)</span></dt> +<dd><p>The data region used by this object file. The value will be: +</p> +<ul> +<li> 0 for files not using the large memory model. +</li><li> 1 for files which have been compiled with the condition that all +data is in the lower memory region, i.e. below address 0x10000. +</li><li> 2 for files which allow data to be placed in the full 20-bit memory range. +</li></ul> +</dd> +</dl> + +<hr> +<a name="Defining-New-Object-Attributes"></a> +<div class="header"> +<p> +Previous: <a href="#GNU-Object-Attributes" accesskey="p" rel="previous">GNU Object Attributes</a>, Up: <a href="#Object-Attributes" accesskey="u" rel="up">Object Attributes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Defining-New-Object-Attributes-1"></a> +<h3 class="section">8.2 Defining New Object Attributes</h3> + +<p>If you want to define a new <small>GNU</small> object attribute, here are the places you +will need to modify. New attributes should be discussed on the ‘<samp>binutils</samp>’ +mailing list. +</p> +<ul> +<li> This manual, which is the official register of attributes. +</li><li> The header for your architecture <samp>include/elf</samp>, to define the tag. +</li><li> The <samp>bfd</samp> support file for your architecture, to merge the attribute +and issue any appropriate link warnings. +</li><li> Test cases in <samp>ld/testsuite</samp> for merging and link warnings. +</li><li> <samp>binutils/readelf.c</samp> to display your attribute. +</li><li> GCC, if you want the compiler to mark the attribute automatically. +</li></ul> + + +<hr> +<a name="Machine-Dependencies"></a> +<div class="header"> +<p> +Next: <a href="#Reporting-Bugs" accesskey="n" rel="next">Reporting Bugs</a>, Previous: <a href="#Object-Attributes" accesskey="p" rel="previous">Object Attributes</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Machine-Dependent-Features"></a> +<h2 class="chapter">9 Machine Dependent Features</h2> + +<a name="index-machine-dependencies"></a> +<p>The machine instruction sets are (almost by definition) different on +each machine where <code>as</code> runs. Floating point representations +vary as well, and <code>as</code> often supports a few additional +directives or command-line options for compatibility with other +assemblers on a particular platform. Finally, some versions of +<code>as</code> support special pseudo-instructions for branch +optimization. +</p> +<p>This chapter discusses most of these differences, though it does not +include details on any machine’s instruction set. For details on that +subject, see the hardware manufacturer’s manual. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#AArch64_002dDependent" accesskey="1">AArch64-Dependent</a>:</td><td> </td><td align="left" valign="top">AArch64 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Alpha_002dDependent" accesskey="2">Alpha-Dependent</a>:</td><td> </td><td align="left" valign="top">Alpha Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARC_002dDependent" accesskey="3">ARC-Dependent</a>:</td><td> </td><td align="left" valign="top">ARC Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM_002dDependent" accesskey="4">ARM-Dependent</a>:</td><td> </td><td align="left" valign="top">ARM Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#AVR_002dDependent" accesskey="5">AVR-Dependent</a>:</td><td> </td><td align="left" valign="top">AVR Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Blackfin_002dDependent" accesskey="6">Blackfin-Dependent</a>:</td><td> </td><td align="left" valign="top">Blackfin Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#BPF_002dDependent" accesskey="7">BPF-Dependent</a>:</td><td> </td><td align="left" valign="top">BPF Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#CR16_002dDependent" accesskey="8">CR16-Dependent</a>:</td><td> </td><td align="left" valign="top">CR16 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#CRIS_002dDependent" accesskey="9">CRIS-Dependent</a>:</td><td> </td><td align="left" valign="top">CRIS Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#C_002dSKY_002dDependent">C-SKY-Dependent</a>:</td><td> </td><td align="left" valign="top">C-SKY Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#D10V_002dDependent">D10V-Dependent</a>:</td><td> </td><td align="left" valign="top">D10V Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#D30V_002dDependent">D30V-Dependent</a>:</td><td> </td><td align="left" valign="top">D30V Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Epiphany_002dDependent">Epiphany-Dependent</a>:</td><td> </td><td align="left" valign="top">EPIPHANY Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#H8_002f300_002dDependent">H8/300-Dependent</a>:</td><td> </td><td align="left" valign="top">Renesas H8/300 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#HPPA_002dDependent">HPPA-Dependent</a>:</td><td> </td><td align="left" valign="top">HPPA Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dDependent">i386-Dependent</a>:</td><td> </td><td align="left" valign="top">Intel 80386 and AMD x86-64 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#IA_002d64_002dDependent">IA-64-Dependent</a>:</td><td> </td><td align="left" valign="top">Intel IA-64 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#IP2K_002dDependent">IP2K-Dependent</a>:</td><td> </td><td align="left" valign="top">IP2K Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#LM32_002dDependent">LM32-Dependent</a>:</td><td> </td><td align="left" valign="top">LM32 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#M32C_002dDependent">M32C-Dependent</a>:</td><td> </td><td align="left" valign="top">M32C Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#M32R_002dDependent">M32R-Dependent</a>:</td><td> </td><td align="left" valign="top">M32R Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68K_002dDependent">M68K-Dependent</a>:</td><td> </td><td align="left" valign="top">M680x0 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68HC11_002dDependent">M68HC11-Dependent</a>:</td><td> </td><td align="left" valign="top">M68HC11 and 68HC12 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#S12Z_002dDependent">S12Z-Dependent</a>:</td><td> </td><td align="left" valign="top">S12Z Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Meta_002dDependent">Meta-Dependent </a>:</td><td> </td><td align="left" valign="top">Meta Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#MicroBlaze_002dDependent">MicroBlaze-Dependent</a>:</td><td> </td><td align="left" valign="top">MICROBLAZE Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS_002dDependent">MIPS-Dependent</a>:</td><td> </td><td align="left" valign="top">MIPS Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#MMIX_002dDependent">MMIX-Dependent</a>:</td><td> </td><td align="left" valign="top">MMIX Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#MSP430_002dDependent">MSP430-Dependent</a>:</td><td> </td><td align="left" valign="top">MSP430 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#NDS32_002dDependent">NDS32-Dependent</a>:</td><td> </td><td align="left" valign="top">Andes NDS32 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#NiosII_002dDependent">NiosII-Dependent</a>:</td><td> </td><td align="left" valign="top">Altera Nios II Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#NS32K_002dDependent">NS32K-Dependent</a>:</td><td> </td><td align="left" valign="top">NS32K Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#OpenRISC_002dDependent">OpenRISC-Dependent</a>:</td><td> </td><td align="left" valign="top">OpenRISC 1000 Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#PDP_002d11_002dDependent">PDP-11-Dependent</a>:</td><td> </td><td align="left" valign="top">PDP-11 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#PJ_002dDependent">PJ-Dependent</a>:</td><td> </td><td align="left" valign="top">picoJava Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#PPC_002dDependent">PPC-Dependent</a>:</td><td> </td><td align="left" valign="top">PowerPC Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#PRU_002dDependent">PRU-Dependent</a>:</td><td> </td><td align="left" valign="top">PRU Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#RISC_002dV_002dDependent">RISC-V-Dependent</a>:</td><td> </td><td align="left" valign="top">RISC-V Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#RL78_002dDependent">RL78-Dependent</a>:</td><td> </td><td align="left" valign="top">RL78 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#RX_002dDependent">RX-Dependent</a>:</td><td> </td><td align="left" valign="top">RX Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#S_002f390_002dDependent">S/390-Dependent</a>:</td><td> </td><td align="left" valign="top">IBM S/390 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#SCORE_002dDependent">SCORE-Dependent</a>:</td><td> </td><td align="left" valign="top">SCORE Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#SH_002dDependent">SH-Dependent</a>:</td><td> </td><td align="left" valign="top">Renesas / SuperH SH Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sparc_002dDependent">Sparc-Dependent</a>:</td><td> </td><td align="left" valign="top">SPARC Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dDependent">TIC54X-Dependent</a>:</td><td> </td><td align="left" valign="top">TI TMS320C54x Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC6X_002dDependent">TIC6X-Dependent </a>:</td><td> </td><td align="left" valign="top">TI TMS320C6x Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILE_002dGx_002dDependent">TILE-Gx-Dependent </a>:</td><td> </td><td align="left" valign="top">Tilera TILE-Gx Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILEPro_002dDependent">TILEPro-Dependent </a>:</td><td> </td><td align="left" valign="top">Tilera TILEPro Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#V850_002dDependent">V850-Dependent</a>:</td><td> </td><td align="left" valign="top">V850 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Vax_002dDependent">Vax-Dependent</a>:</td><td> </td><td align="left" valign="top">VAX Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Visium_002dDependent">Visium-Dependent</a>:</td><td> </td><td align="left" valign="top">Visium Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#WebAssembly_002dDependent">WebAssembly-Dependent</a>:</td><td> </td><td align="left" valign="top">WebAssembly Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#XGATE_002dDependent">XGATE-Dependent</a>:</td><td> </td><td align="left" valign="top">XGATE Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#XSTORMY16_002dDependent">XSTORMY16-Dependent</a>:</td><td> </td><td align="left" valign="top">XStormy16 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa_002dDependent">Xtensa-Dependent</a>:</td><td> </td><td align="left" valign="top">Xtensa Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z80_002dDependent">Z80-Dependent</a>:</td><td> </td><td align="left" valign="top">Z80 Dependent Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z8000_002dDependent">Z8000-Dependent</a>:</td><td> </td><td align="left" valign="top">Z8000 Dependent Features +</td></tr> +</table> + + + + +<hr> +<a name="AArch64_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Alpha_002dDependent" accesskey="n" rel="next">Alpha-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="AArch64-Dependent-Features"></a> +<h3 class="section">9.1 AArch64 Dependent Features</h3> + + +<a name="index-AArch64-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#AArch64-Options" accesskey="1">AArch64 Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#AArch64-Extensions" accesskey="2">AArch64 Extensions</a>:</td><td> </td><td align="left" valign="top">Extensions +</td></tr> +<tr><td align="left" valign="top">• <a href="#AArch64-Syntax" accesskey="3">AArch64 Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#AArch64-Floating-Point" accesskey="4">AArch64 Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#AArch64-Directives" accesskey="5">AArch64 Directives</a>:</td><td> </td><td align="left" valign="top">AArch64 Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#AArch64-Opcodes" accesskey="6">AArch64 Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +<tr><td align="left" valign="top">• <a href="#AArch64-Mapping-Symbols" accesskey="7">AArch64 Mapping Symbols</a>:</td><td> </td><td align="left" valign="top">Mapping Symbols +</td></tr> +</table> + +<hr> +<a name="AArch64-Options"></a> +<div class="header"> +<p> +Next: <a href="#AArch64-Extensions" accesskey="n" rel="next">AArch64 Extensions</a>, Up: <a href="#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options"></a> +<h4 class="subsection">9.1.1 Options</h4> +<a name="index-AArch64-options-_0028none_0029"></a> +<a name="index-options-for-AArch64-_0028none_0029"></a> + +<dl compact="compact"> +<dd> +<a name="index-_002dEB-command_002dline-option_002c-AArch64"></a> +</dd> +<dt><code>-EB</code></dt> +<dd><p>This option specifies that the output generated by the assembler should +be marked as being encoded for a big-endian processor. +</p> +<a name="index-_002dEL-command_002dline-option_002c-AArch64"></a> +</dd> +<dt><code>-EL</code></dt> +<dd><p>This option specifies that the output generated by the assembler should +be marked as being encoded for a little-endian processor. +</p> +<a name="index-_002dmabi_003d-command_002dline-option_002c-AArch64"></a> +</dd> +<dt><code>-mabi=<var>abi</var></code></dt> +<dd><p>Specify which ABI the source code uses. The recognized arguments +are: <code>ilp32</code> and <code>lp64</code>, which decides the generated object +file in ELF32 and ELF64 format respectively. The default is <code>lp64</code>. +</p> +<a name="index-_002dmcpu_003d-command_002dline-option_002c-AArch64"></a> +</dd> +<dt><code>-mcpu=<var>processor</var>[+<var>extension</var>…]</code></dt> +<dd><p>This option specifies the target processor. The assembler will issue an error +message if an attempt is made to assemble an instruction which will not execute +on the target processor. The following processor names are recognized: +<code>cortex-a34</code>, +<code>cortex-a35</code>, +<code>cortex-a53</code>, +<code>cortex-a55</code>, +<code>cortex-a57</code>, +<code>cortex-a65</code>, +<code>cortex-a65ae</code>, +<code>cortex-a72</code>, +<code>cortex-a73</code>, +<code>cortex-a75</code>, +<code>cortex-a76</code>, +<code>cortex-a76ae</code>, +<code>cortex-a77</code>, +<code>cortex-a78</code>, +<code>cortex-a78ae</code>, +<code>cortex-a78c</code>, +<code>cortex-a510</code>, +<code>cortex-a710</code>, +<code>ares</code>, +<code>exynos-m1</code>, +<code>falkor</code>, +<code>neoverse-n1</code>, +<code>neoverse-n2</code>, +<code>neoverse-e1</code>, +<code>neoverse-v1</code>, +<code>qdf24xx</code>, +<code>saphira</code>, +<code>thunderx</code>, +<code>vulcan</code>, +<code>xgene1</code> +<code>xgene2</code>, +<code>cortex-r82</code>, +<code>cortex-x1</code>, +and +<code>cortex-x2</code>. +The special name <code>all</code> may be used to allow the assembler to accept +instructions valid for any supported processor, including all optional +extensions. +</p> +<p>In addition to the basic instruction set, the assembler can be told to +accept, or restrict, various extension mnemonics that extend the +processor. See <a href="#AArch64-Extensions">AArch64 Extensions</a>. +</p> +<p>If some implementations of a particular processor can have an +extension, then then those extensions are automatically enabled. +Consequently, you will not normally have to specify any additional +extensions. +</p> +<a name="index-_002dmarch_003d-command_002dline-option_002c-AArch64"></a> +</dd> +<dt><code>-march=<var>architecture</var>[+<var>extension</var>…]</code></dt> +<dd><p>This option specifies the target architecture. The assembler will +issue an error message if an attempt is made to assemble an +instruction which will not execute on the target architecture. The +following architecture names are recognized: <code>armv8-a</code>, +<code>armv8.1-a</code>, <code>armv8.2-a</code>, <code>armv8.3-a</code>, <code>armv8.4-a</code> +<code>armv8.5-a</code>, <code>armv8.6-a</code>, <code>armv8.7-a</code>, <code>armv8.8-a</code>, +<code>armv8-r</code>, <code>armv9-a</code>, <code>armv9.1-a</code>, <code>armv9.2-a</code>, +and <code>armv9.3-a</code>. +</p> +<p>If both <samp>-mcpu</samp> and <samp>-march</samp> are specified, the +assembler will use the setting for <samp>-mcpu</samp>. If neither are +specified, the assembler will default to <samp>-mcpu=all</samp>. +</p> +<p>The architecture option can be extended with the same instruction set +extension options as the <samp>-mcpu</samp> option. Unlike +<samp>-mcpu</samp>, extensions are not always enabled by default, +See <a href="#AArch64-Extensions">AArch64 Extensions</a>. +</p> +<a name="index-_002dmverbose_002derror-command_002dline-option_002c-AArch64"></a> +</dd> +<dt><code>-mverbose-error</code></dt> +<dd><p>This option enables verbose error messages for AArch64 gas. This option +is enabled by default. +</p> +<a name="index-_002dmno_002dverbose_002derror-command_002dline-option_002c-AArch64"></a> +</dd> +<dt><code>-mno-verbose-error</code></dt> +<dd><p>This option disables verbose error messages in AArch64 gas. +</p> +</dd> +</dl> + +<hr> +<a name="AArch64-Extensions"></a> +<div class="header"> +<p> +Next: <a href="#AArch64-Syntax" accesskey="n" rel="next">AArch64 Syntax</a>, Previous: <a href="#AArch64-Options" accesskey="p" rel="previous">AArch64 Options</a>, Up: <a href="#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Architecture-Extensions"></a> +<h4 class="subsection">9.1.2 Architecture Extensions</h4> + +<p>The table below lists the permitted architecture extensions that are +supported by the assembler and the conditions under which they are +automatically enabled. +</p> +<p>Multiple extensions may be specified, separated by a <code>+</code>. +Extension mnemonics may also be removed from those the assembler +accepts. This is done by prepending <code>no</code> to the option that adds +the extension. Extensions that are removed must be listed after all +extensions that have been added. +</p> +<p>Enabling an extension that requires other extensions will +automatically cause those extensions to be enabled. Similarly, +disabling an extension that is required by other extensions will +automatically cause those extensions to be disabled. +</p> +<table> +<thead><tr><th width="12%">Extension</th><th width="17%">Minimum Architecture</th><th width="17%">Enabled by default</th><th width="54%">Description</th></tr></thead> +<tr><td width="12%"><code>aes</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable the AES cryptographic extensions. This implies <code>fp</code> and + <code>simd</code>.</td></tr> +<tr><td width="12%"><code>bf16</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.6-A or later</td><td width="54%">Enable BFloat16 extension.</td></tr> +<tr><td width="12%"><code>compnum</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.3-A or later</td><td width="54%">Enable the complex number SIMD extensions. This implies <code>fp16</code> and + <code>simd</code>.</td></tr> +<tr><td width="12%"><code>crc</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable CRC instructions.</td></tr> +<tr><td width="12%"><code>crypto</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable cryptographic extensions. This implies <code>fp</code>, <code>simd</code>, + <code>aes</code> and <code>sha2</code>.</td></tr> +<tr><td width="12%"><code>dotprod</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.4-A or later</td><td width="54%">Enable the Dot Product extension. This implies <code>simd</code>.</td></tr> +<tr><td width="12%"><code>f32mm</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable F32 Matrix Multiply extension. This implies <code>sve</code>.</td></tr> +<tr><td width="12%"><code>f64mm</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable F64 Matrix Multiply extension. This implies <code>sve</code>.</td></tr> +<tr><td width="12%"><code>flagm</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.4-A or later</td><td width="54%">Enable Flag Manipulation instructions.</td></tr> +<tr><td width="12%"><code>fp16fml</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.4-A or later</td><td width="54%">Enable ARMv8.2 16-bit floating-point multiplication variant support. This + implies <code>fp</code> and <code>fp16</code>.</td></tr> +<tr><td width="12%"><code>fp16</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.2-A or later</td><td width="54%">Enable ARMv8.2 16-bit floating-point support. This implies <code>fp</code>.</td></tr> +<tr><td width="12%"><code>fp</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8-A or later</td><td width="54%">Enable floating-point extensions.</td></tr> +<tr><td width="12%"><code>hbc</code></td><td width="17%"></td><td width="17%">Armv8.8-A or later</td><td width="54%">Enable Armv8.8-A hinted conditional branch instructions</td></tr> +<tr><td width="12%"><code>cssc</code></td><td width="17%"></td><td width="17%">Armv8.7-A or later</td><td width="54%">Enable Armv8.9-A Common Short Sequence Compression instructions.</td></tr> +<tr><td width="12%"><code>i8mm</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.6-A or later</td><td width="54%">Enable Int8 Matrix Multiply extension.</td></tr> +<tr><td width="12%"><code>lor</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable Limited Ordering Regions extensions.</td></tr> +<tr><td width="12%"><code>ls64</code></td><td width="17%">ARMv8.6-A</td><td width="17%">ARMv8.7-A or later</td><td width="54%">Enable 64 Byte Loads/Stores.</td></tr> +<tr><td width="12%"><code>lse</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable Large System extensions.</td></tr> +<tr><td width="12%"><code>memtag</code></td><td width="17%">ARMv8.5-A</td><td width="17%">No</td><td width="54%">Enable ARMv8.5-A Memory Tagging Extensions.</td></tr> +<tr><td width="12%"><code>mops</code></td><td width="17%"></td><td width="17%">Armv8.8-A or later</td><td width="54%">Enable Armv8.8-A memcpy and memset acceleration instructions</td></tr> +<tr><td width="12%"><code>pan</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable Privileged Access Never support.</td></tr> +<tr><td width="12%"><code>pauth</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable Pointer Authentication.</td></tr> +<tr><td width="12%"><code>predres</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.5-A or later</td><td width="54%">Enable the Execution and Data and Prediction instructions.</td></tr> +<tr><td width="12%"><code>profile</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable statistical profiling extensions.</td></tr> +<tr><td width="12%"><code>ras</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.2-A or later</td><td width="54%">Enable the Reliability, Availability and Serviceability extension.</td></tr> +<tr><td width="12%"><code>rcpc</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.3-A or later</td><td width="54%">Enable the weak release consistency extension.</td></tr> +<tr><td width="12%"><code>rdma</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable ARMv8.1 Advanced SIMD extensions. This implies <code>simd</code>.</td></tr> +<tr><td width="12%"><code>rng</code></td><td width="17%">ARMv8.5-A</td><td width="17%">No</td><td width="54%">Enable ARMv8.5-A random number instructions.</td></tr> +<tr><td width="12%"><code>sb</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.5-A or later</td><td width="54%">Enable the speculation barrier instruction sb.</td></tr> +<tr><td width="12%"><code>sha2</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable the SHA2 cryptographic extensions. This implies <code>fp</code> and + <code>simd</code>.</td></tr> +<tr><td width="12%"><code>sha3</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies + <code>fp</code>, <code>simd</code> and <code>sha2</code>.</td></tr> +<tr><td width="12%"><code>simd</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8-A or later</td><td width="54%">Enable Advanced SIMD extensions. This implies <code>fp</code>.</td></tr> +<tr><td width="12%"><code>sm4</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies + <code>fp</code> and <code>simd</code>.</td></tr> +<tr><td width="12%"><code>sme</code></td><td width="17%">Armv9-A</td><td width="17%">No</td><td width="54%">Enable SME Extension.</td></tr> +<tr><td width="12%"><code>sme-f64f64</code></td><td width="17%">Armv9-A</td><td width="17%">No</td><td width="54%">Enable SME F64F64 Extension.</td></tr> +<tr><td width="12%"><code>sme-i16i64</code></td><td width="17%">Armv9-A</td><td width="17%">No</td><td width="54%">Enable SME I16I64 Extension.</td></tr> +<tr><td width="12%"><code>sme2</code></td><td width="17%">Armv9-A</td><td width="17%">No</td><td width="54%">Enable SME2. This implies <code>sme</code>.</td></tr> +<tr><td width="12%"><code>ssbs</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.5-A or later</td><td width="54%">Enable Speculative Store Bypassing Safe state read and write.</td></tr> +<tr><td width="12%"><code>sve</code></td><td width="17%">ARMv8.2-A</td><td width="17%">Armv9-A or later</td><td width="54%">Enable the Scalable Vector Extensions. This implies <code>fp16</code>, + <code>simd</code> and <code>compnum</code>.</td></tr> +<tr><td width="12%"><code>sve2</code></td><td width="17%">ARMv8-A</td><td width="17%">Armv9-A or later</td><td width="54%">Enable the SVE2 Extension. This implies <code>sve</code>.</td></tr> +<tr><td width="12%"><code>sve2-aes</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable SVE2 AES Extension. This also enables the .Q->.B form of the + <code>pmullt</code> and <code>pmullb</code> instructions. This implies <code>aes</code> and + <code>sve2</code>.</td></tr> +<tr><td width="12%"><code>sve2-bitperm</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable SVE2 BITPERM Extension.</td></tr> +<tr><td width="12%"><code>sve2-sha3</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable SVE2 SHA3 Extension. This implies <code>sha3</code> and <code>sve2</code>.</td></tr> +<tr><td width="12%"><code>sve2-sm4</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable SVE2 SM4 Extension. This implies <code>sm4</code> and <code>sve2</code>.</td></tr> +<tr><td width="12%"><code>tme</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable Transactional Memory Extensions.</td></tr> +</table> + +<hr> +<a name="AArch64-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#AArch64-Floating-Point" accesskey="n" rel="next">AArch64 Floating Point</a>, Previous: <a href="#AArch64-Extensions" accesskey="p" rel="previous">AArch64 Extensions</a>, Up: <a href="#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-2"></a> +<h4 class="subsection">9.1.3 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#AArch64_002dChars" accesskey="1">AArch64-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#AArch64_002dRegs" accesskey="2">AArch64-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#AArch64_002dRelocations" accesskey="3">AArch64-Relocations</a>:</td><td> </td><td align="left" valign="top">Relocations +</td></tr> +</table> + +<hr> +<a name="AArch64_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#AArch64_002dRegs" accesskey="n" rel="next">AArch64-Regs</a>, Up: <a href="#AArch64-Syntax" accesskey="u" rel="up">AArch64 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters"></a> +<h4 class="subsubsection">9.1.3.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-AArch64"></a> +<a name="index-AArch64-line-comment-character"></a> +<p>The presence of a ‘<samp>//</samp>’ on a line indicates the start of a comment +that extends to the end of the current line. If a ‘<samp>#</samp>’ appears as +the first character of a line, the whole line is treated as a comment. +</p> +<a name="index-line-separator_002c-AArch64"></a> +<a name="index-statement-separator_002c-AArch64"></a> +<a name="index-AArch64-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used instead of a newline to separate +statements. +</p> +<a name="index-immediate-character_002c-AArch64"></a> +<a name="index-AArch64-immediate-character"></a> +<p>The ‘<samp>#</samp>’ can be optionally used to indicate immediate operands. +</p> +<hr> +<a name="AArch64_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#AArch64_002dRelocations" accesskey="n" rel="next">AArch64-Relocations</a>, Previous: <a href="#AArch64_002dChars" accesskey="p" rel="previous">AArch64-Chars</a>, Up: <a href="#AArch64-Syntax" accesskey="u" rel="up">AArch64 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names"></a> +<h4 class="subsubsection">9.1.3.2 Register Names</h4> + +<a name="index-AArch64-register-names"></a> +<a name="index-register-names_002c-AArch64"></a> +<p>Please refer to the section ‘<samp>4.4 Register Names</samp>’ of +‘<samp>ARMv8 Instruction Set Overview</samp>’, which is available at +<a href="http://infocenter.arm.com">http://infocenter.arm.com</a>. +</p> +<hr> +<a name="AArch64_002dRelocations"></a> +<div class="header"> +<p> +Previous: <a href="#AArch64_002dRegs" accesskey="p" rel="previous">AArch64-Regs</a>, Up: <a href="#AArch64-Syntax" accesskey="u" rel="up">AArch64 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Relocations"></a> +<h4 class="subsubsection">9.1.3.3 Relocations</h4> + +<a name="index-relocations_002c-AArch64"></a> +<a name="index-AArch64-relocations"></a> +<a name="index-MOVN_002c-MOVZ-and-MOVK-group-relocations_002c-AArch64"></a> +<p>Relocations for ‘<samp>MOVZ</samp>’ and ‘<samp>MOVK</samp>’ instructions can be generated +by prefixing the label with ‘<samp>#:abs_g2:</samp>’ etc. +For example to load the 48-bit absolute address of <var>foo</var> into x0: +</p> +<div class="smallexample"> +<pre class="smallexample"> movz x0, #:abs_g2:foo // bits 32-47, overflow check + movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check + movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check +</pre></div> + +<a name="index-ADRP_002c-ADD_002c-LDR_002fSTR-group-relocations_002c-AArch64"></a> +<p>Relocations for ‘<samp>ADRP</samp>’, and ‘<samp>ADD</samp>’, ‘<samp>LDR</samp>’ or ‘<samp>STR</samp>’ +instructions can be generated by prefixing the label with +‘<samp>:pg_hi21:</samp>’ and ‘<samp>#:lo12:</samp>’ respectively. +</p> +<p>For example to use 33-bit (+/-4GB) pc-relative addressing to +load the address of <var>foo</var> into x0: +</p> +<div class="smallexample"> +<pre class="smallexample"> adrp x0, :pg_hi21:foo + add x0, x0, #:lo12:foo +</pre></div> + +<p>Or to load the value of <var>foo</var> into x0: +</p> +<div class="smallexample"> +<pre class="smallexample"> adrp x0, :pg_hi21:foo + ldr x0, [x0, #:lo12:foo] +</pre></div> + +<p>Note that ‘<samp>:pg_hi21:</samp>’ is optional. +</p> +<div class="smallexample"> +<pre class="smallexample"> adrp x0, foo +</pre></div> + +<p>is equivalent to +</p> +<div class="smallexample"> +<pre class="smallexample"> adrp x0, :pg_hi21:foo +</pre></div> + +<hr> +<a name="AArch64-Floating-Point"></a> +<div class="header"> +<p> +Next: <a href="#AArch64-Directives" accesskey="n" rel="next">AArch64 Directives</a>, Previous: <a href="#AArch64-Syntax" accesskey="p" rel="previous">AArch64 Syntax</a>, Up: <a href="#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point"></a> +<h4 class="subsection">9.1.4 Floating Point</h4> + +<a name="index-floating-point_002c-AArch64-_0028IEEE_0029"></a> +<a name="index-AArch64-floating-point-_0028IEEE_0029"></a> +<p>The AArch64 architecture uses <small>IEEE</small> floating-point numbers. +</p> +<hr> +<a name="AArch64-Directives"></a> +<div class="header"> +<p> +Next: <a href="#AArch64-Opcodes" accesskey="n" rel="next">AArch64 Opcodes</a>, Previous: <a href="#AArch64-Floating-Point" accesskey="p" rel="previous">AArch64 Floating Point</a>, Up: <a href="#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="AArch64-Machine-Directives"></a> +<h4 class="subsection">9.1.5 AArch64 Machine Directives</h4> + +<a name="index-machine-directives_002c-AArch64"></a> +<a name="index-AArch64-machine-directives"></a> +<dl compact="compact"> +<dd> + +<a name="index-_002earch-directive_002c-AArch64"></a> +</dd> +<dt><code>.arch <var>name</var></code></dt> +<dd><p>Select the target architecture. Valid values for <var>name</var> are the same as +for the <samp>-march</samp> command-line option. +</p> +<p>Specifying <code>.arch</code> clears any previously selected architecture +extensions. +</p> +<a name="index-_002earch_005fextension-directive_002c-AArch64"></a> +</dd> +<dt><code>.arch_extension <var>name</var></code></dt> +<dd><p>Add or remove an architecture extension to the target architecture. Valid +values for <var>name</var> are the same as those accepted as architectural +extensions by the <samp>-mcpu</samp> command-line option. +</p> +<p><code>.arch_extension</code> may be used multiple times to add or remove extensions +incrementally to the architecture being compiled for. +</p> + +<a name="index-_002ebss-directive_002c-AArch64"></a> +</dd> +<dt><code>.bss</code></dt> +<dd><p>This directive switches to the <code>.bss</code> section. +</p> + +<a name="index-_002ecpu-directive_002c-AArch64"></a> +</dd> +<dt><code>.cpu <var>name</var></code></dt> +<dd><p>Set the target processor. Valid values for <var>name</var> are the same as +those accepted by the <samp>-mcpu=</samp> command-line option. +</p> + +<a name="index-_002edword-directive_002c-AArch64"></a> +</dd> +<dt><code>.dword <var>expressions</var></code></dt> +<dd><p>The <code>.dword</code> directive produces 64 bit values. +</p> + +<a name="index-_002eeven-directive_002c-AArch64"></a> +</dd> +<dt><code>.even</code></dt> +<dd><p>The <code>.even</code> directive aligns the output on the next even byte +boundary. +</p> + +<a name="index-_002efloat16-directive_002c-AArch64"></a> +</dd> +<dt><code>.float16 <var>value [,...,value_n]</var></code></dt> +<dd><p>Place the half precision floating point representation of one or more +floating-point values into the current section. +The format used to encode the floating point values is always the +IEEE 754-2008 half precision floating point format. +</p> + +<a name="index-_002einst-directive_002c-AArch64"></a> +</dd> +<dt><code>.inst <var>expressions</var></code></dt> +<dd><p>Inserts the expressions into the output as if they were instructions, +rather than data. +</p> + +<a name="index-_002eltorg-directive_002c-AArch64"></a> +</dd> +<dt><code>.ltorg</code></dt> +<dd><p>This directive causes the current contents of the literal pool to be +dumped into the current section (which is assumed to be the .text +section) at the current location (aligned to a word boundary). +GAS maintains a separate literal pool for each section and each +sub-section. The <code>.ltorg</code> directive will only affect the literal +pool of the current section and sub-section. At the end of assembly +all remaining, un-empty literal pools will automatically be dumped. +</p> +<p>Note - older versions of GAS would dump the current literal +pool any time a section change occurred. This is no longer done, since +it prevents accurate control of the placement of literal pools. +</p> + + + +<a name="index-_002epool-directive_002c-AArch64"></a> +</dd> +<dt><code>.pool</code></dt> +<dd><p>This is a synonym for .ltorg. +</p> + +<a name="index-_002ereq-directive_002c-AArch64"></a> +</dd> +<dt><code><var>name</var> .req <var>register name</var></code></dt> +<dd><p>This creates an alias for <var>register name</var> called <var>name</var>. For +example: +</p> +<div class="smallexample"> +<pre class="smallexample"> foo .req w0 +</pre></div> + +<p>ip0, ip1, lr and fp are automatically defined to +alias to X16, X17, X30 and X29 respectively. +</p> + + +<a name="index-_002etlsdescadd-directive_002c-AArch64"></a> +</dd> +<dt><code><code>.tlsdescadd</code></code></dt> +<dd><p>Emits a TLSDESC_ADD reloc on the next instruction. +</p> +<a name="index-_002etlsdesccall-directive_002c-AArch64"></a> +</dd> +<dt><code><code>.tlsdesccall</code></code></dt> +<dd><p>Emits a TLSDESC_CALL reloc on the next instruction. +</p> +<a name="index-_002etlsdescldr-directive_002c-AArch64"></a> +</dd> +<dt><code><code>.tlsdescldr</code></code></dt> +<dd><p>Emits a TLSDESC_LDR reloc on the next instruction. +</p> + +<a name="index-_002eunreq-directive_002c-AArch64"></a> +</dd> +<dt><code>.unreq <var>alias-name</var></code></dt> +<dd><p>This undefines a register alias which was previously defined using the +<code>req</code> directive. For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> foo .req w0 + .unreq foo +</pre></div> + +<p>An error occurs if the name is undefined. Note - this pseudo op can +be used to delete builtin in register name aliases (eg ’w0’). This +should only be done if it is really necessary. +</p> + +<a name="index-_002evariant_005fpcs-directive_002c-AArch64"></a> +</dd> +<dt><code>.variant_pcs <var>symbol</var></code></dt> +<dd><p>This directive marks <var>symbol</var> referencing a function that may +follow a variant procedure call standard with different register +usage convention from the base procedure call standard. +</p> + +<a name="index-_002exword-directive_002c-AArch64"></a> +</dd> +<dt><code>.xword <var>expressions</var></code></dt> +<dd><p>The <code>.xword</code> directive produces 64 bit values. This is the same +as the <code>.dword</code> directive. +</p> + +<a name="index-_002ecfi_005fb_005fkey_005fframe-directive_002c-AArch64"></a> +</dd> +<dt><code><code>.cfi_b_key_frame</code></code></dt> +<dd><p>The <code>.cfi_b_key_frame</code> directive inserts a ’B’ character into the CIE +corresponding to the current frame’s FDE, meaning that its return address has +been signed with the B-key. If two frames are signed with differing keys then +they will not share the same CIE. This information is intended to be used by +the stack unwinder in order to properly authenticate return addresses. +</p> +</dd> +</dl> + +<hr> +<a name="AArch64-Opcodes"></a> +<div class="header"> +<p> +Next: <a href="#AArch64-Mapping-Symbols" accesskey="n" rel="next">AArch64 Mapping Symbols</a>, Previous: <a href="#AArch64-Directives" accesskey="p" rel="previous">AArch64 Directives</a>, Up: <a href="#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes"></a> +<h4 class="subsection">9.1.6 Opcodes</h4> + +<a name="index-AArch64-opcodes"></a> +<a name="index-opcodes-for-AArch64"></a> +<p>GAS implements all the standard AArch64 opcodes. It also +implements several pseudo opcodes, including several synthetic load +instructions. +</p> +<dl compact="compact"> +<dd> +<a name="index-LDR-reg_002c_003d_003cexpr_003e-pseudo-op_002c-AArch64"></a> +</dd> +<dt><code>LDR =</code></dt> +<dd><div class="smallexample"> +<pre class="smallexample"> ldr <register> , =<expression> +</pre></div> + +<p>The constant expression will be placed into the nearest literal pool (if it not +already there) and a PC-relative LDR instruction will be generated. +</p> +</dd> +</dl> + +<p>For more information on the AArch64 instruction set and assembly language +notation, see ‘<samp>ARMv8 Instruction Set Overview</samp>’ available at +<a href="http://infocenter.arm.com">http://infocenter.arm.com</a>. +</p> + +<hr> +<a name="AArch64-Mapping-Symbols"></a> +<div class="header"> +<p> +Previous: <a href="#AArch64-Opcodes" accesskey="p" rel="previous">AArch64 Opcodes</a>, Up: <a href="#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Mapping-Symbols"></a> +<h4 class="subsection">9.1.7 Mapping Symbols</h4> + +<p>The AArch64 ELF specification requires that special symbols be inserted +into object files to mark certain features: +</p> +<dl compact="compact"> +<dd> +<a name="index-_0024x"></a> +</dd> +<dt><code>$x</code></dt> +<dd><p>At the start of a region of code containing AArch64 instructions. +</p> +<a name="index-_0024d"></a> +</dd> +<dt><code>$d</code></dt> +<dd><p>At the start of a region of data. +</p> +</dd> +</dl> + + +<hr> +<a name="Alpha_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#ARC_002dDependent" accesskey="n" rel="next">ARC-Dependent</a>, Previous: <a href="#AArch64_002dDependent" accesskey="p" rel="previous">AArch64-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Alpha-Dependent-Features"></a> +<h3 class="section">9.2 Alpha Dependent Features</h3> + + +<a name="index-Alpha-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Alpha-Notes" accesskey="1">Alpha Notes</a>:</td><td> </td><td align="left" valign="top">Notes +</td></tr> +<tr><td align="left" valign="top">• <a href="#Alpha-Options" accesskey="2">Alpha Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#Alpha-Syntax" accesskey="3">Alpha Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#Alpha-Floating-Point" accesskey="4">Alpha Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#Alpha-Directives" accesskey="5">Alpha Directives</a>:</td><td> </td><td align="left" valign="top">Alpha Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#Alpha-Opcodes" accesskey="6">Alpha Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="Alpha-Notes"></a> +<div class="header"> +<p> +Next: <a href="#Alpha-Options" accesskey="n" rel="next">Alpha Options</a>, Up: <a href="#Alpha_002dDependent" accesskey="u" rel="up">Alpha-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Notes"></a> +<h4 class="subsection">9.2.1 Notes</h4> +<a name="index-Alpha-notes"></a> +<a name="index-notes-for-Alpha"></a> + +<p>The documentation here is primarily for the ELF object format. +<code>as</code> also supports the ECOFF and EVAX formats, but +features specific to these formats are not yet documented. +</p> +<hr> +<a name="Alpha-Options"></a> +<div class="header"> +<p> +Next: <a href="#Alpha-Syntax" accesskey="n" rel="next">Alpha Syntax</a>, Previous: <a href="#Alpha-Notes" accesskey="p" rel="previous">Alpha Notes</a>, Up: <a href="#Alpha_002dDependent" accesskey="u" rel="up">Alpha-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-1"></a> +<h4 class="subsection">9.2.2 Options</h4> +<a name="index-Alpha-options"></a> +<a name="index-options-for-Alpha"></a> + +<dl compact="compact"> +<dd><a name="index-_002dmcpu-command_002dline-option_002c-Alpha"></a> +</dd> +<dt><code>-m<var>cpu</var></code></dt> +<dd><p>This option specifies the target processor. If an attempt is made to +assemble an instruction which will not execute on the target processor, +the assembler may either expand the instruction as a macro or issue an +error message. This option is equivalent to the <code>.arch</code> directive. +</p> +<p>The following processor names are recognized: +<code>21064</code>, +<code>21064a</code>, +<code>21066</code>, +<code>21068</code>, +<code>21164</code>, +<code>21164a</code>, +<code>21164pc</code>, +<code>21264</code>, +<code>21264a</code>, +<code>21264b</code>, +<code>ev4</code>, +<code>ev5</code>, +<code>lca45</code>, +<code>ev5</code>, +<code>ev56</code>, +<code>pca56</code>, +<code>ev6</code>, +<code>ev67</code>, +<code>ev68</code>. +The special name <code>all</code> may be used to allow the assembler to accept +instructions valid for any Alpha processor. +</p> +<p>In order to support existing practice in OSF/1 with respect to <code>.arch</code>, +and existing practice within <code>MILO</code> (the Linux ARC bootloader), the +numbered processor names (e.g. 21064) enable the processor-specific PALcode +instructions, while the “electro-vlasic” names (e.g. <code>ev4</code>) do not. +</p> +<a name="index-_002dmdebug-command_002dline-option_002c-Alpha"></a> +<a name="index-_002dno_002dmdebug-command_002dline-option_002c-Alpha"></a> +</dd> +<dt><code>-mdebug</code></dt> +<dt><code>-no-mdebug</code></dt> +<dd><p>Enables or disables the generation of <code>.mdebug</code> encapsulation for +stabs directives and procedure descriptors. The default is to automatically +enable <code>.mdebug</code> when the first stabs directive is seen. +</p> +<a name="index-_002drelax-command_002dline-option_002c-Alpha"></a> +</dd> +<dt><code>-relax</code></dt> +<dd><p>This option forces all relocations to be put into the object file, instead +of saving space and resolving some relocations at assembly time. Note that +this option does not propagate all symbol arithmetic into the object file, +because not all symbol arithmetic can be represented. However, the option +can still be useful in specific applications. +</p> +<a name="index-_002dreplace-command_002dline-option_002c-Alpha"></a> +<a name="index-_002dnoreplace-command_002dline-option_002c-Alpha"></a> +</dd> +<dt><code>-replace</code></dt> +<dt><code>-noreplace</code></dt> +<dd><p>Enables or disables the optimization of procedure calls, both at assemblage +and at link time. These options are only available for VMS targets and +<code>-replace</code> is the default. See section 1.4.1 of the OpenVMS Linker +Utility Manual. +</p> +<a name="index-_002dg-command_002dline-option_002c-Alpha"></a> +</dd> +<dt><code>-g</code></dt> +<dd><p>This option is used when the compiler generates debug information. When +<code>gcc</code> is using <code>mips-tfile</code> to generate debug +information for ECOFF, local labels must be passed through to the object +file. Otherwise this option has no effect. +</p> +<a name="index-_002dG-command_002dline-option_002c-Alpha"></a> +</dd> +<dt><code>-G<var>size</var></code></dt> +<dd><p>A local common symbol larger than <var>size</var> is placed in <code>.bss</code>, +while smaller symbols are placed in <code>.sbss</code>. +</p> +<a name="index-_002dF-command_002dline-option_002c-Alpha"></a> +<a name="index-_002d32addr-command_002dline-option_002c-Alpha"></a> +</dd> +<dt><code>-F</code></dt> +<dt><code>-32addr</code></dt> +<dd><p>These options are ignored for backward compatibility. +</p></dd> +</dl> + +<a name="index-Alpha-Syntax"></a> +<hr> +<a name="Alpha-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#Alpha-Floating-Point" accesskey="n" rel="next">Alpha Floating Point</a>, Previous: <a href="#Alpha-Options" accesskey="p" rel="previous">Alpha Options</a>, Up: <a href="#Alpha_002dDependent" accesskey="u" rel="up">Alpha-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-3"></a> +<h4 class="subsection">9.2.3 Syntax</h4> +<p>The assembler syntax closely follow the Alpha Reference Manual; +assembler directives and general syntax closely follow the OSF/1 and +OpenVMS syntax, with a few differences for ELF. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Alpha_002dChars" accesskey="1">Alpha-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#Alpha_002dRegs" accesskey="2">Alpha-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#Alpha_002dRelocs" accesskey="3">Alpha-Relocs</a>:</td><td> </td><td align="left" valign="top">Relocations +</td></tr> +</table> + +<hr> +<a name="Alpha_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#Alpha_002dRegs" accesskey="n" rel="next">Alpha-Regs</a>, Up: <a href="#Alpha-Syntax" accesskey="u" rel="up">Alpha Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-1"></a> +<h4 class="subsubsection">9.2.3.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-Alpha"></a> +<a name="index-Alpha-line-comment-character"></a> +<p>‘<samp>#</samp>’ is the line comment character. Note that if ‘<samp>#</samp>’ is the +first character on a line then it can also be a logical line number +directive (see <a href="#Comments">Comments</a>) or a preprocessor control +command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-Alpha"></a> +<a name="index-statement-separator_002c-Alpha"></a> +<a name="index-Alpha-line-separator"></a> +<p>‘<samp>;</samp>’ can be used instead of a newline to separate statements. +</p> +<hr> +<a name="Alpha_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#Alpha_002dRelocs" accesskey="n" rel="next">Alpha-Relocs</a>, Previous: <a href="#Alpha_002dChars" accesskey="p" rel="previous">Alpha-Chars</a>, Up: <a href="#Alpha-Syntax" accesskey="u" rel="up">Alpha Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-1"></a> +<h4 class="subsubsection">9.2.3.2 Register Names</h4> +<a name="index-Alpha-registers"></a> +<a name="index-register-names_002c-Alpha"></a> + +<p>The 32 integer registers are referred to as ‘<samp>$<var>n</var></samp>’ or +‘<samp>$r<var>n</var></samp>’. In addition, registers 15, 28, 29, and 30 may +be referred to by the symbols ‘<samp>$fp</samp>’, ‘<samp>$at</samp>’, ‘<samp>$gp</samp>’, +and ‘<samp>$sp</samp>’ respectively. +</p> +<p>The 32 floating-point registers are referred to as ‘<samp>$f<var>n</var></samp>’. +</p> +<hr> +<a name="Alpha_002dRelocs"></a> +<div class="header"> +<p> +Previous: <a href="#Alpha_002dRegs" accesskey="p" rel="previous">Alpha-Regs</a>, Up: <a href="#Alpha-Syntax" accesskey="u" rel="up">Alpha Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Relocations-1"></a> +<h4 class="subsubsection">9.2.3.3 Relocations</h4> +<a name="index-Alpha-relocations"></a> +<a name="index-relocations_002c-Alpha"></a> + +<p>Some of these relocations are available for ECOFF, but mostly +only for ELF. They are modeled after the relocation format +introduced in Digital Unix 4.0, but there are additions. +</p> +<p>The format is ‘<samp>!<var>tag</var></samp>’ or ‘<samp>!<var>tag</var>!<var>number</var></samp>’ +where <var>tag</var> is the name of the relocation. In some cases +<var>number</var> is used to relate specific instructions. +</p> +<p>The relocation is placed at the end of the instruction like so: +</p> +<div class="example"> +<pre class="example">ldah $0,a($29) !gprelhigh +lda $0,a($0) !gprellow +ldq $1,b($29) !literal!100 +ldl $2,0($1) !lituse_base!100 +</pre></div> + +<dl compact="compact"> +<dt><code>!literal</code></dt> +<dt><code>!literal!<var>N</var></code></dt> +<dd><p>Used with an <code>ldq</code> instruction to load the address of a symbol +from the GOT. +</p> +<p>A sequence number <var>N</var> is optional, and if present is used to pair +<code>lituse</code> relocations with this <code>literal</code> relocation. The +<code>lituse</code> relocations are used by the linker to optimize the code +based on the final location of the symbol. +</p> +<p>Note that these optimizations are dependent on the data flow of the +program. Therefore, if <em>any</em> <code>lituse</code> is paired with a +<code>literal</code> relocation, then <em>all</em> uses of the register set by +the <code>literal</code> instruction must also be marked with <code>lituse</code> +relocations. This is because the original <code>literal</code> instruction +may be deleted or transformed into another instruction. +</p> +<p>Also note that there may be a one-to-many relationship between +<code>literal</code> and <code>lituse</code>, but not a many-to-one. That is, if +there are two code paths that load up the same address and feed the +value to a single use, then the use may not use a <code>lituse</code> +relocation. +</p> +</dd> +<dt><code>!lituse_base!<var>N</var></code></dt> +<dd><p>Used with any memory format instruction (e.g. <code>ldl</code>) to indicate +that the literal is used for an address load. The offset field of the +instruction must be zero. During relaxation, the code may be altered +to use a gp-relative load. +</p> +</dd> +<dt><code>!lituse_jsr!<var>N</var></code></dt> +<dd><p>Used with a register branch format instruction (e.g. <code>jsr</code>) to +indicate that the literal is used for a call. During relaxation, the +code may be altered to use a direct branch (e.g. <code>bsr</code>). +</p> +</dd> +<dt><code>!lituse_jsrdirect!<var>N</var></code></dt> +<dd><p>Similar to <code>lituse_jsr</code>, but also that this call cannot be vectored +through a PLT entry. This is useful for functions with special calling +conventions which do not allow the normal call-clobbered registers to be +clobbered. +</p> +</dd> +<dt><code>!lituse_bytoff!<var>N</var></code></dt> +<dd><p>Used with a byte mask instruction (e.g. <code>extbl</code>) to indicate +that only the low 3 bits of the address are relevant. During relaxation, +the code may be altered to use an immediate instead of a register shift. +</p> +</dd> +<dt><code>!lituse_addr!<var>N</var></code></dt> +<dd><p>Used with any other instruction to indicate that the original address +is in fact used, and the original <code>ldq</code> instruction may not be +altered or deleted. This is useful in conjunction with <code>lituse_jsr</code> +to test whether a weak symbol is defined. +</p> +<div class="example"> +<pre class="example">ldq $27,foo($29) !literal!1 +beq $27,is_undef !lituse_addr!1 +jsr $26,($27),foo !lituse_jsr!1 +</pre></div> + +</dd> +<dt><code>!lituse_tlsgd!<var>N</var></code></dt> +<dd><p>Used with a register branch format instruction to indicate that the +literal is the call to <code>__tls_get_addr</code> used to compute the +address of the thread-local storage variable whose descriptor was +loaded with <code>!tlsgd!<var>N</var></code>. +</p> +</dd> +<dt><code>!lituse_tlsldm!<var>N</var></code></dt> +<dd><p>Used with a register branch format instruction to indicate that the +literal is the call to <code>__tls_get_addr</code> used to compute the +address of the base of the thread-local storage block for the current +module. The descriptor for the module must have been loaded with +<code>!tlsldm!<var>N</var></code>. +</p> +</dd> +<dt><code>!gpdisp!<var>N</var></code></dt> +<dd><p>Used with <code>ldah</code> and <code>lda</code> to load the GP from the current +address, a-la the <code>ldgp</code> macro. The source register for the +<code>ldah</code> instruction must contain the address of the <code>ldah</code> +instruction. There must be exactly one <code>lda</code> instruction paired +with the <code>ldah</code> instruction, though it may appear anywhere in +the instruction stream. The immediate operands must be zero. +</p> +<div class="example"> +<pre class="example">bsr $26,foo +ldah $29,0($26) !gpdisp!1 +lda $29,0($29) !gpdisp!1 +</pre></div> + +</dd> +<dt><code>!gprelhigh</code></dt> +<dd><p>Used with an <code>ldah</code> instruction to add the high 16 bits of a +32-bit displacement from the GP. +</p> +</dd> +<dt><code>!gprellow</code></dt> +<dd><p>Used with any memory format instruction to add the low 16 bits of a +32-bit displacement from the GP. +</p> +</dd> +<dt><code>!gprel</code></dt> +<dd><p>Used with any memory format instruction to add a 16-bit displacement +from the GP. +</p> +</dd> +<dt><code>!samegp</code></dt> +<dd><p>Used with any branch format instruction to skip the GP load at the +target address. The referenced symbol must have the same GP as the +source object file, and it must be declared to either not use <code>$27</code> +or perform a standard GP load in the first two instructions via the +<code>.prologue</code> directive. +</p> +</dd> +<dt><code>!tlsgd</code></dt> +<dt><code>!tlsgd!<var>N</var></code></dt> +<dd><p>Used with an <code>lda</code> instruction to load the address of a TLS +descriptor for a symbol in the GOT. +</p> +<p>The sequence number <var>N</var> is optional, and if present it used to +pair the descriptor load with both the <code>literal</code> loading the +address of the <code>__tls_get_addr</code> function and the <code>lituse_tlsgd</code> +marking the call to that function. +</p> +<p>For proper relaxation, both the <code>tlsgd</code>, <code>literal</code> and +<code>lituse</code> relocations must be in the same extended basic block. +That is, the relocation with the lowest address must be executed +first at runtime. +</p> +</dd> +<dt><code>!tlsldm</code></dt> +<dt><code>!tlsldm!<var>N</var></code></dt> +<dd><p>Used with an <code>lda</code> instruction to load the address of a TLS +descriptor for the current module in the GOT. +</p> +<p>Similar in other respects to <code>tlsgd</code>. +</p> +</dd> +<dt><code>!gotdtprel</code></dt> +<dd><p>Used with an <code>ldq</code> instruction to load the offset of the TLS +symbol within its module’s thread-local storage block. Also known +as the dynamic thread pointer offset or dtp-relative offset. +</p> +</dd> +<dt><code>!dtprelhi</code></dt> +<dt><code>!dtprello</code></dt> +<dt><code>!dtprel</code></dt> +<dd><p>Like <code>gprel</code> relocations except they compute dtp-relative offsets. +</p> +</dd> +<dt><code>!gottprel</code></dt> +<dd><p>Used with an <code>ldq</code> instruction to load the offset of the TLS +symbol from the thread pointer. Also known as the tp-relative offset. +</p> +</dd> +<dt><code>!tprelhi</code></dt> +<dt><code>!tprello</code></dt> +<dt><code>!tprel</code></dt> +<dd><p>Like <code>gprel</code> relocations except they compute tp-relative offsets. +</p></dd> +</dl> + +<hr> +<a name="Alpha-Floating-Point"></a> +<div class="header"> +<p> +Next: <a href="#Alpha-Directives" accesskey="n" rel="next">Alpha Directives</a>, Previous: <a href="#Alpha-Syntax" accesskey="p" rel="previous">Alpha Syntax</a>, Up: <a href="#Alpha_002dDependent" accesskey="u" rel="up">Alpha-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-1"></a> +<h4 class="subsection">9.2.4 Floating Point</h4> +<a name="index-floating-point_002c-Alpha-_0028IEEE_0029"></a> +<a name="index-Alpha-floating-point-_0028IEEE_0029"></a> +<p>The Alpha family uses both <small>IEEE</small> and VAX floating-point numbers. +</p> +<hr> +<a name="Alpha-Directives"></a> +<div class="header"> +<p> +Next: <a href="#Alpha-Opcodes" accesskey="n" rel="next">Alpha Opcodes</a>, Previous: <a href="#Alpha-Floating-Point" accesskey="p" rel="previous">Alpha Floating Point</a>, Up: <a href="#Alpha_002dDependent" accesskey="u" rel="up">Alpha-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Alpha-Assembler-Directives"></a> +<h4 class="subsection">9.2.5 Alpha Assembler Directives</h4> + +<p><code>as</code> for the Alpha supports many additional directives for +compatibility with the native assembler. This section describes them only +briefly. +</p> +<a name="index-Alpha_002donly-directives"></a> +<p>These are the additional directives in <code>as</code> for the Alpha: +</p> +<dl compact="compact"> +<dt><code>.arch <var>cpu</var></code></dt> +<dd><p>Specifies the target processor. This is equivalent to the +<samp>-m<var>cpu</var></samp> command-line option. See <a href="#Alpha-Options">Options</a>, +for a list of values for <var>cpu</var>. +</p> +</dd> +<dt><code>.ent <var>function</var>[, <var>n</var>]</code></dt> +<dd><p>Mark the beginning of <var>function</var>. An optional number may follow for +compatibility with the OSF/1 assembler, but is ignored. When generating +<code>.mdebug</code> information, this will create a procedure descriptor for +the function. In ELF, it will mark the symbol as a function a-la the +generic <code>.type</code> directive. +</p> +</dd> +<dt><code>.end <var>function</var></code></dt> +<dd><p>Mark the end of <var>function</var>. In ELF, it will set the size of the symbol +a-la the generic <code>.size</code> directive. +</p> +</dd> +<dt><code>.mask <var>mask</var>, <var>offset</var></code></dt> +<dd><p>Indicate which of the integer registers are saved in the current +function’s stack frame. <var>mask</var> is interpreted a bit mask in which +bit <var>n</var> set indicates that register <var>n</var> is saved. The registers +are saved in a block located <var>offset</var> bytes from the <em>canonical +frame address</em> (CFA) which is the value of the stack pointer on entry to +the function. The registers are saved sequentially, except that the +return address register (normally <code>$26</code>) is saved first. +</p> +<p>This and the other directives that describe the stack frame are +currently only used when generating <code>.mdebug</code> information. They +may in the future be used to generate DWARF2 <code>.debug_frame</code> unwind +information for hand written assembly. +</p> +</dd> +<dt><code>.fmask <var>mask</var>, <var>offset</var></code></dt> +<dd><p>Indicate which of the floating-point registers are saved in the current +stack frame. The <var>mask</var> and <var>offset</var> parameters are interpreted +as with <code>.mask</code>. +</p> +</dd> +<dt><code>.frame <var>framereg</var>, <var>frameoffset</var>, <var>retreg</var>[, <var>argoffset</var>]</code></dt> +<dd><p>Describes the shape of the stack frame. The frame pointer in use is +<var>framereg</var>; normally this is either <code>$fp</code> or <code>$sp</code>. The +frame pointer is <var>frameoffset</var> bytes below the CFA. The return +address is initially located in <var>retreg</var> until it is saved as +indicated in <code>.mask</code>. For compatibility with OSF/1 an optional +<var>argoffset</var> parameter is accepted and ignored. It is believed to +indicate the offset from the CFA to the saved argument registers. +</p> +</dd> +<dt><code>.prologue <var>n</var></code></dt> +<dd><p>Indicate that the stack frame is set up and all registers have been +spilled. The argument <var>n</var> indicates whether and how the function +uses the incoming <em>procedure vector</em> (the address of the called +function) in <code>$27</code>. 0 indicates that <code>$27</code> is not used; 1 +indicates that the first two instructions of the function use <code>$27</code> +to perform a load of the GP register; 2 indicates that <code>$27</code> is +used in some non-standard way and so the linker cannot elide the load of +the procedure vector during relaxation. +</p> +</dd> +<dt><code>.usepv <var>function</var>, <var>which</var></code></dt> +<dd><p>Used to indicate the use of the <code>$27</code> register, similar to +<code>.prologue</code>, but without the other semantics of needing to +be inside an open <code>.ent</code>/<code>.end</code> block. +</p> +<p>The <var>which</var> argument should be either <code>no</code>, indicating that +<code>$27</code> is not used, or <code>std</code>, indicating that the first two +instructions of the function perform a GP load. +</p> +<p>One might use this directive instead of <code>.prologue</code> if you are +also using dwarf2 CFI directives. +</p> +</dd> +<dt><code>.gprel32 <var>expression</var></code></dt> +<dd><p>Computes the difference between the address in <var>expression</var> and the +GP for the current object file, and stores it in 4 bytes. In addition +to being smaller than a full 8 byte address, this also does not require +a dynamic relocation when used in a shared library. +</p> +</dd> +<dt><code>.t_floating <var>expression</var></code></dt> +<dd><p>Stores <var>expression</var> as an <small>IEEE</small> double precision value. +</p> +</dd> +<dt><code>.s_floating <var>expression</var></code></dt> +<dd><p>Stores <var>expression</var> as an <small>IEEE</small> single precision value. +</p> +</dd> +<dt><code>.f_floating <var>expression</var></code></dt> +<dd><p>Stores <var>expression</var> as a VAX F format value. +</p> +</dd> +<dt><code>.g_floating <var>expression</var></code></dt> +<dd><p>Stores <var>expression</var> as a VAX G format value. +</p> +</dd> +<dt><code>.d_floating <var>expression</var></code></dt> +<dd><p>Stores <var>expression</var> as a VAX D format value. +</p> +</dd> +<dt><code>.set <var>feature</var></code></dt> +<dd><p>Enables or disables various assembler features. Using the positive +name of the feature enables while using ‘<samp>no<var>feature</var></samp>’ disables. +</p> +<dl compact="compact"> +<dt><code>at</code></dt> +<dd><p>Indicates that macro expansions may clobber the <em>assembler +temporary</em> (<code>$at</code> or <code>$28</code>) register. Some macros may not be +expanded without this and will generate an error message if <code>noat</code> +is in effect. When <code>at</code> is in effect, a warning will be generated +if <code>$at</code> is used by the programmer. +</p> +</dd> +<dt><code>macro</code></dt> +<dd><p>Enables the expansion of macro instructions. Note that variants of real +instructions, such as <code>br label</code> vs <code>br $31,label</code> are +considered alternate forms and not macros. +</p> +</dd> +<dt><code>move</code></dt> +<dt><code>reorder</code></dt> +<dt><code>volatile</code></dt> +<dd><p>These control whether and how the assembler may re-order instructions. +Accepted for compatibility with the OSF/1 assembler, but <code>as</code> +does not do instruction scheduling, so these features are ignored. +</p></dd> +</dl> +</dd> +</dl> + +<p>The following directives are recognized for compatibility with the OSF/1 +assembler but are ignored. +</p> +<div class="example"> +<pre class="example">.proc .aproc +.reguse .livereg +.option .aent +.ugen .eflag +.alias .noalias +</pre></div> + +<hr> +<a name="Alpha-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#Alpha-Directives" accesskey="p" rel="previous">Alpha Directives</a>, Up: <a href="#Alpha_002dDependent" accesskey="u" rel="up">Alpha-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-1"></a> +<h4 class="subsection">9.2.6 Opcodes</h4> +<p>For detailed information on the Alpha machine instruction set, see the +<a href="ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf">Alpha Architecture Handbook</a>. +</p> + +<hr> +<a name="ARC_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#ARM_002dDependent" accesskey="n" rel="next">ARM-Dependent</a>, Previous: <a href="#Alpha_002dDependent" accesskey="p" rel="previous">Alpha-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="ARC-Dependent-Features"></a> +<h3 class="section">9.3 ARC Dependent Features</h3> + + + +<a name="index-ARC-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#ARC-Options" accesskey="1">ARC Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARC-Syntax" accesskey="2">ARC Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARC-Directives" accesskey="3">ARC Directives</a>:</td><td> </td><td align="left" valign="top">ARC Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARC-Modifiers" accesskey="4">ARC Modifiers</a>:</td><td> </td><td align="left" valign="top">ARC Assembler Modifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARC-Symbols" accesskey="5">ARC Symbols</a>:</td><td> </td><td align="left" valign="top">ARC Pre-defined Symbols +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARC-Opcodes" accesskey="6">ARC Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="ARC-Options"></a> +<div class="header"> +<p> +Next: <a href="#ARC-Syntax" accesskey="n" rel="next">ARC Syntax</a>, Up: <a href="#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-2"></a> +<h4 class="subsection">9.3.1 Options</h4> +<a name="index-ARC-options"></a> +<a name="index-options-for-ARC"></a> + +<p>The following options control the type of CPU for which code is +assembled, and generic constraints on the code generated: +</p> +<dl compact="compact"> +<dt><code>-mcpu=<var>cpu</var></code></dt> +<dd><a name="index-_002dmcpu_003dcpu-command_002dline-option_002c-ARC"></a> +<p>Set architecture type and register usage for <var>cpu</var>. There are +also shortcut alias options available for backward compatibility and +convenience. Supported values for <var>cpu</var> are +</p> +<dl compact="compact"> +<dd><a name="index-mA6-command_002dline-option_002c-ARC"></a> +<a name="index-marc600-command_002dline-option_002c-ARC"></a> +</dd> +<dt><code>arc600</code></dt> +<dd><p>Assemble for ARC 600. Aliases: <code>-mA6</code>, <code>-mARC600</code>. +</p> +</dd> +<dt><code>arc600_norm</code></dt> +<dd><p>Assemble for ARC 600 with norm instructions. +</p> +</dd> +<dt><code>arc600_mul64</code></dt> +<dd><p>Assemble for ARC 600 with mul64 instructions. +</p> +</dd> +<dt><code>arc600_mul32x16</code></dt> +<dd><p>Assemble for ARC 600 with mul32x16 instructions. +</p> +</dd> +<dt><code>arc601</code></dt> +<dd><a name="index-mARC601-command_002dline-option_002c-ARC"></a> +<p>Assemble for ARC 601. Alias: <code>-mARC601</code>. +</p> +</dd> +<dt><code>arc601_norm</code></dt> +<dd><p>Assemble for ARC 601 with norm instructions. +</p> +</dd> +<dt><code>arc601_mul64</code></dt> +<dd><p>Assemble for ARC 601 with mul64 instructions. +</p> +</dd> +<dt><code>arc601_mul32x16</code></dt> +<dd><p>Assemble for ARC 601 with mul32x16 instructions. +</p> +</dd> +<dt><code>arc700</code></dt> +<dd><a name="index-mA7-command_002dline-option_002c-ARC"></a> +<a name="index-mARC700-command_002dline-option_002c-ARC"></a> +<p>Assemble for ARC 700. Aliases: <code>-mA7</code>, <code>-mARC700</code>. +</p> +</dd> +<dt><code>arcem</code></dt> +<dd><a name="index-mEM-command_002dline-option_002c-ARC"></a> +<p>Assemble for ARC EM. Aliases: <code>-mEM</code> +</p> +</dd> +<dt><code>em</code></dt> +<dd><p>Assemble for ARC EM, identical as arcem variant. +</p> +</dd> +<dt><code>em4</code></dt> +<dd><p>Assemble for ARC EM with code-density instructions. +</p> +</dd> +<dt><code>em4_dmips</code></dt> +<dd><p>Assemble for ARC EM with code-density instructions. +</p> +</dd> +<dt><code>em4_fpus</code></dt> +<dd><p>Assemble for ARC EM with code-density instructions. +</p> +</dd> +<dt><code>em4_fpuda</code></dt> +<dd><p>Assemble for ARC EM with code-density, and double-precision assist +instructions. +</p> +</dd> +<dt><code>quarkse_em</code></dt> +<dd><p>Assemble for QuarkSE-EM cpu. +</p> +</dd> +<dt><code>archs</code></dt> +<dd><a name="index-mHS-command_002dline-option_002c-ARC"></a> +<p>Assemble for ARC HS. Aliases: <code>-mHS</code>, <code>-mav2hs</code>. +</p> +</dd> +<dt><code>hs</code></dt> +<dd><p>Assemble for ARC HS. +</p> +</dd> +<dt><code>hs34</code></dt> +<dd><p>Assemble for ARC HS34. +</p> +</dd> +<dt><code>hs38</code></dt> +<dd><p>Assemble for ARC HS38. +</p> +</dd> +<dt><code>hs38_linux</code></dt> +<dd><p>Assemble for ARC HS38 with floating point support on. +</p> +</dd> +<dt><code>nps400</code></dt> +<dd><a name="index-mnps400-command_002dline-option_002c-ARC"></a> +<p>Assemble for ARC 700 with NPS-400 extended instructions. +</p> +</dd> +</dl> + +<p>Note: the <code>.cpu</code> directive (see <a href="#ARC-Directives">ARC Directives</a>) can +to be used to select a core variant from within assembly code. +</p> +<a name="index-_002dEB-command_002dline-option_002c-ARC"></a> +</dd> +<dt><code>-EB</code></dt> +<dd><p>This option specifies that the output generated by the assembler should +be marked as being encoded for a big-endian processor. +</p> +<a name="index-_002dEL-command_002dline-option_002c-ARC"></a> +</dd> +<dt><code>-EL</code></dt> +<dd><p>This option specifies that the output generated by the assembler should +be marked as being encoded for a little-endian processor - this is the +default. +</p> +<a name="index-_002dmcode_002ddensity-command_002dline-option_002c-ARC"></a> +</dd> +<dt><code>-mcode-density</code></dt> +<dd><p>This option turns on Code Density instructions. Only valid for ARC EM +processors. +</p> +<a name="index-_002dmrelax-command_002dline-option_002c-ARC"></a> +</dd> +<dt><code>-mrelax</code></dt> +<dd><p>Enable support for assembly-time relaxation. The assembler will +replace a longer version of an instruction with a shorter one, +whenever it is possible. +</p> +<a name="index-_002dmnps400-command_002dline-option_002c-ARC"></a> +</dd> +<dt><code>-mnps400</code></dt> +<dd><p>Enable support for NPS-400 extended instructions. +</p> +<a name="index-_002dmspfp-command_002dline-option_002c-ARC"></a> +</dd> +<dt><code>-mspfp</code></dt> +<dd><p>Enable support for single-precision floating point instructions. +</p> +<a name="index-_002dmdpfp-command_002dline-option_002c-ARC"></a> +</dd> +<dt><code>-mdpfp</code></dt> +<dd><p>Enable support for double-precision floating point instructions. +</p> +<a name="index-_002dmfpuda-command_002dline-option_002c-ARC"></a> +</dd> +<dt><code>-mfpuda</code></dt> +<dd><p>Enable support for double-precision assist floating point instructions. +Only valid for ARC EM processors. +</p> +</dd> +</dl> + +<hr> +<a name="ARC-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#ARC-Directives" accesskey="n" rel="next">ARC Directives</a>, Previous: <a href="#ARC-Options" accesskey="p" rel="previous">ARC Options</a>, Up: <a href="#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-4"></a> +<h4 class="subsection">9.3.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#ARC_002dChars" accesskey="1">ARC-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARC_002dRegs" accesskey="2">ARC-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +</table> + +<hr> +<a name="ARC_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#ARC_002dRegs" accesskey="n" rel="next">ARC-Regs</a>, Up: <a href="#ARC-Syntax" accesskey="u" rel="up">ARC Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-2"></a> +<h4 class="subsubsection">9.3.2.1 Special Characters</h4> + +<dl compact="compact"> +<dt><code>%</code></dt> +<dd><a name="index-register-name-prefix-character_002c-ARC"></a> +<a name="index-ARC-register-name-prefix-character"></a> +<p>A register name can optionally be prefixed by a ‘<samp>%</samp>’ character. So +register <code>%r0</code> is equivalent to <code>r0</code> in the assembly code. +</p> +</dd> +<dt><code>#</code></dt> +<dd><a name="index-line-comment-character_002c-ARC"></a> +<a name="index-ARC-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ character within a line (but not at the +start of a line) indicates the start of a comment that extends to the +end of the current line. +</p> +<p><em>Note:</em> if a line starts with a ‘<samp>#</samp>’ character then it can +also be a logical line number directive (see <a href="#Comments">Comments</a>) or a +preprocessor control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +</dd> +<dt><code>@</code></dt> +<dd><a name="index-symbol-prefix-character_002c-ARC"></a> +<a name="index-ARC-symbol-prefix-character"></a> +<p>Prefixing an operand with an ‘<samp>@</samp>’ specifies that the operand is a +symbol and not a register. This is how the assembler disambiguates +the use of an ARC register name as a symbol. So the instruction +</p><div class="example"> +<pre class="example">mov r0, @r0 +</pre></div> +<p>moves the address of symbol <code>r0</code> into register <code>r0</code>. +</p> +</dd> +<dt><code>`</code></dt> +<dd><a name="index-line-separator_002c-ARC"></a> +<a name="index-statement-separator_002c-ARC"></a> +<a name="index-ARC-line-separator"></a> +<p>The ‘<samp>`</samp>’ (backtick) character is used to separate statements on a +single line. +</p> +<a name="index-line"></a> +</dd> +<dt><code>-</code></dt> +<dd><a name="index-C-preprocessor-macro-separator_002c-ARC"></a> +<a name="index-ARC-C-preprocessor-macro-separator"></a> +<p>Used as a separator to obtain a sequence of commands from a C +preprocessor macro. +</p> +</dd> +</dl> + +<hr> +<a name="ARC_002dRegs"></a> +<div class="header"> +<p> +Previous: <a href="#ARC_002dChars" accesskey="p" rel="previous">ARC-Chars</a>, Up: <a href="#ARC-Syntax" accesskey="u" rel="up">ARC Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-2"></a> +<h4 class="subsubsection">9.3.2.2 Register Names</h4> + +<a name="index-ARC-register-names"></a> +<a name="index-register-names_002c-ARC"></a> +<p>The ARC assembler uses the following register names for its core +registers: +</p> +<dl compact="compact"> +<dt><code>r0-r31</code></dt> +<dd><a name="index-core-general-registers_002c-ARC"></a> +<a name="index-ARC-core-general-registers"></a> +<p>The core general registers. Registers <code>r26</code> through <code>r31</code> +have special functions, and are usually referred to by those synonyms. +</p> +</dd> +<dt><code>gp</code></dt> +<dd><a name="index-global-pointer_002c-ARC"></a> +<a name="index-ARC-global-pointer"></a> +<p>The global pointer and a synonym for <code>r26</code>. +</p> +</dd> +<dt><code>fp</code></dt> +<dd><a name="index-frame-pointer_002c-ARC"></a> +<a name="index-ARC-frame-pointer"></a> +<p>The frame pointer and a synonym for <code>r27</code>. +</p> +</dd> +<dt><code>sp</code></dt> +<dd><a name="index-stack-pointer_002c-ARC"></a> +<a name="index-ARC-stack-pointer"></a> +<p>The stack pointer and a synonym for <code>r28</code>. +</p> +</dd> +<dt><code>ilink1</code></dt> +<dd><a name="index-level-1-interrupt-link-register_002c-ARC"></a> +<a name="index-ARC-level-1-interrupt-link-register"></a> +<p>For ARC 600 and ARC 700, the level 1 interrupt link register and a +synonym for <code>r29</code>. Not supported for ARCv2. +</p> +</dd> +<dt><code>ilink</code></dt> +<dd><a name="index-interrupt-link-register_002c-ARC"></a> +<a name="index-ARC-interrupt-link-register"></a> +<p>For ARCv2, the interrupt link register and a synonym for <code>r29</code>. +Not supported for ARC 600 and ARC 700. +</p> +</dd> +<dt><code>ilink2</code></dt> +<dd><a name="index-level-2-interrupt-link-register_002c-ARC"></a> +<a name="index-ARC-level-2-interrupt-link-register"></a> +<p>For ARC 600 and ARC 700, the level 2 interrupt link register and a +synonym for <code>r30</code>. Not supported for ARC v2. +</p> +</dd> +<dt><code>blink</code></dt> +<dd><a name="index-link-register_002c-ARC"></a> +<a name="index-ARC-link-register"></a> +<p>The link register and a synonym for <code>r31</code>. +</p> +</dd> +<dt><code>r32-r59</code></dt> +<dd><a name="index-extension-core-registers_002c-ARC"></a> +<a name="index-ARC-extension-core-registers"></a> +<p>The extension core registers. +</p> +</dd> +<dt><code>lp_count</code></dt> +<dd><a name="index-loop-counter_002c-ARC"></a> +<a name="index-ARC-loop-counter"></a> +<p>The loop count register. +</p> +</dd> +<dt><code>pcl</code></dt> +<dd><a name="index-word-aligned-program-counter_002c-ARC"></a> +<a name="index-ARC-word-aligned-program-counter"></a> +<p>The word aligned program counter. +</p> +</dd> +</dl> + +<p>In addition the ARC processor has a large number of <em>auxiliary +registers</em>. The precise set depends on the extensions being +supported, but the following baseline set are always defined: +</p> +<dl compact="compact"> +<dt><code>identity</code></dt> +<dd><a name="index-Processor-Identification-register_002c-ARC"></a> +<a name="index-ARC-Processor-Identification-register"></a> +<p>Processor Identification register. Auxiliary register address 0x4. +</p> +</dd> +<dt><code>pc</code></dt> +<dd><a name="index-Program-Counter_002c-ARC"></a> +<a name="index-ARC-Program-Counter"></a> +<p>Program Counter. Auxiliary register address 0x6. +</p> +</dd> +<dt><code>status32</code></dt> +<dd><a name="index-Status-register_002c-ARC"></a> +<a name="index-ARC-Status-register"></a> +<p>Status register. Auxiliary register address 0x0a. +</p> +</dd> +<dt><code>bta</code></dt> +<dd><a name="index-Branch-Target-Address_002c-ARC"></a> +<a name="index-ARC-Branch-Target-Address"></a> +<p>Branch Target Address. Auxiliary register address 0x412. +</p> +</dd> +<dt><code>ecr</code></dt> +<dd><a name="index-Exception-Cause-Register_002c-ARC"></a> +<a name="index-ARC-Exception-Cause-Register"></a> +<p>Exception Cause Register. Auxiliary register address 0x403. +</p> +</dd> +<dt><code>int_vector_base</code></dt> +<dd><a name="index-Interrupt-Vector-Base-address_002c-ARC"></a> +<a name="index-ARC-Interrupt-Vector-Base-address"></a> +<p>Interrupt Vector Base address. Auxiliary register address 0x25. +</p> +</dd> +<dt><code>status32_p0</code></dt> +<dd><a name="index-Stored-STATUS32-register-on-entry-to-level-P0-interrupts_002c-ARC"></a> +<a name="index-ARC-Stored-STATUS32-register-on-entry-to-level-P0-interrupts"></a> +<p>Stored STATUS32 register on entry to level P0 interrupts. Auxiliary +register address 0xb. +</p> +</dd> +<dt><code>aux_user_sp</code></dt> +<dd><a name="index-Saved-User-Stack-Pointer_002c-ARC"></a> +<a name="index-ARC-Saved-User-Stack-Pointer"></a> +<p>Saved User Stack Pointer. Auxiliary register address 0xd. +</p> +</dd> +<dt><code>eret</code></dt> +<dd><a name="index-Exception-Return-Address_002c-ARC"></a> +<a name="index-ARC-Exception-Return-Address"></a> +<p>Exception Return Address. Auxiliary register address 0x400. +</p> +</dd> +<dt><code>erbta</code></dt> +<dd><a name="index-BTA-saved-on-exception-entry_002c-ARC"></a> +<a name="index-ARC-BTA-saved-on-exception-entry"></a> +<p>BTA saved on exception entry. Auxiliary register address 0x401. +</p> +</dd> +<dt><code>erstatus</code></dt> +<dd><a name="index-STATUS32-saved-on-exception_002c-ARC"></a> +<a name="index-ARC-STATUS32-saved-on-exception"></a> +<p>STATUS32 saved on exception. Auxiliary register address 0x402. +</p> +</dd> +<dt><code>bcr_ver</code></dt> +<dd><a name="index-Build-Configuration-Registers-Version_002c-ARC"></a> +<a name="index-ARC-Build-Configuration-Registers-Version"></a> +<p>Build Configuration Registers Version. Auxiliary register address 0x60. +</p> +</dd> +<dt><code>bta_link_build</code></dt> +<dd><a name="index-Build-configuration-for_003a-BTA-Registers_002c-ARC"></a> +<a name="index-ARC-Build-configuration-for_003a-BTA-Registers"></a> +<p>Build configuration for: BTA Registers. Auxiliary register address 0x63. +</p> +</dd> +<dt><code>vecbase_ac_build</code></dt> +<dd><a name="index-Build-configuration-for_003a-Interrupts_002c-ARC"></a> +<a name="index-ARC-Build-configuration-for_003a-Interrupts"></a> +<p>Build configuration for: Interrupts. Auxiliary register address 0x68. +</p> +</dd> +<dt><code>rf_build</code></dt> +<dd><a name="index-Build-configuration-for_003a-Core-Registers_002c-ARC"></a> +<a name="index-ARC-Build-configuration-for_003a-Core-Registers"></a> +<p>Build configuration for: Core Registers. Auxiliary register address 0x6e. +</p> +</dd> +<dt><code>dccm_build</code></dt> +<dd><a name="index-DCCM-RAM-Configuration-Register_002c-ARC"></a> +<a name="index-ARC-DCCM-RAM-Configuration-Register"></a> +<p>DCCM RAM Configuration Register. Auxiliary register address 0xc1. +</p> +</dd> +</dl> + +<p>Additional auxiliary register names are defined according to the +processor architecture version and extensions selected by the options. +</p> +<hr> +<a name="ARC-Directives"></a> +<div class="header"> +<p> +Next: <a href="#ARC-Modifiers" accesskey="n" rel="next">ARC Modifiers</a>, Previous: <a href="#ARC-Syntax" accesskey="p" rel="previous">ARC Syntax</a>, Up: <a href="#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="ARC-Machine-Directives"></a> +<h4 class="subsection">9.3.3 ARC Machine Directives</h4> + +<a name="index-machine-directives_002c-ARC"></a> +<a name="index-ARC-machine-directives"></a> +<p>The ARC version of <code>as</code> supports the following additional +machine directives: +</p> +<dl compact="compact"> +<dd> +<a name="index-lcomm-directive-1"></a> +</dd> +<dt><code>.lcomm <var>symbol</var>, <var>length</var>[, <var>alignment</var>]</code></dt> +<dd><p>Reserve <var>length</var> (an absolute expression) bytes for a local common +denoted by <var>symbol</var>. The section and value of <var>symbol</var> are +those of the new local common. The addresses are allocated in the bss +section, so that at run-time the bytes start off zeroed. Since +<var>symbol</var> is not declared global, it is normally not visible to +<code>ld</code>. The optional third parameter, <var>alignment</var>, +specifies the desired alignment of the symbol in the bss section, +specified as a byte boundary (for example, an alignment of 16 means +that the least significant 4 bits of the address should be zero). The +alignment must be an absolute expression, and it must be a power of +two. If no alignment is specified, as will set the alignment to the +largest power of two less than or equal to the size of the symbol, up +to a maximum of 16. +</p> +<a name="index-lcommon-directive_002c-ARC"></a> +</dd> +<dt><code>.lcommon <var>symbol</var>, <var>length</var>[, <var>alignment</var>]</code></dt> +<dd><p>The same as <code>lcomm</code> directive. +</p> +<a name="index-cpu-directive_002c-ARC"></a> +</dd> +<dt><code>.cpu <var>cpu</var></code></dt> +<dd><p>The <code>.cpu</code> directive must be followed by the desired core +version. Permitted values for CPU are: +</p><dl compact="compact"> +<dt><code>ARC600</code></dt> +<dd><p>Assemble for the ARC600 instruction set. +</p> +</dd> +<dt><code>arc600_norm</code></dt> +<dd><p>Assemble for ARC 600 with norm instructions. +</p> +</dd> +<dt><code>arc600_mul64</code></dt> +<dd><p>Assemble for ARC 600 with mul64 instructions. +</p> +</dd> +<dt><code>arc600_mul32x16</code></dt> +<dd><p>Assemble for ARC 600 with mul32x16 instructions. +</p> +</dd> +<dt><code>arc601</code></dt> +<dd><p>Assemble for ARC 601 instruction set. +</p> +</dd> +<dt><code>arc601_norm</code></dt> +<dd><p>Assemble for ARC 601 with norm instructions. +</p> +</dd> +<dt><code>arc601_mul64</code></dt> +<dd><p>Assemble for ARC 601 with mul64 instructions. +</p> +</dd> +<dt><code>arc601_mul32x16</code></dt> +<dd><p>Assemble for ARC 601 with mul32x16 instructions. +</p> +</dd> +<dt><code>ARC700</code></dt> +<dd><p>Assemble for the ARC700 instruction set. +</p> +</dd> +<dt><code>NPS400</code></dt> +<dd><p>Assemble for the NPS400 instruction set. +</p> +</dd> +<dt><code>EM</code></dt> +<dd><p>Assemble for the ARC EM instruction set. +</p> +</dd> +<dt><code>arcem</code></dt> +<dd><p>Assemble for ARC EM instruction set +</p> +</dd> +<dt><code>em4</code></dt> +<dd><p>Assemble for ARC EM with code-density instructions. +</p> +</dd> +<dt><code>em4_dmips</code></dt> +<dd><p>Assemble for ARC EM with code-density instructions. +</p> +</dd> +<dt><code>em4_fpus</code></dt> +<dd><p>Assemble for ARC EM with code-density instructions. +</p> +</dd> +<dt><code>em4_fpuda</code></dt> +<dd><p>Assemble for ARC EM with code-density, and double-precision assist +instructions. +</p> +</dd> +<dt><code>quarkse_em</code></dt> +<dd><p>Assemble for QuarkSE-EM instruction set. +</p> +</dd> +<dt><code>HS</code></dt> +<dd><p>Assemble for the ARC HS instruction set. +</p> +</dd> +<dt><code>archs</code></dt> +<dd><p>Assemble for ARC HS instruction set. +</p> +</dd> +<dt><code>hs</code></dt> +<dd><p>Assemble for ARC HS instruction set. +</p> +</dd> +<dt><code>hs34</code></dt> +<dd><p>Assemble for ARC HS34 instruction set. +</p> +</dd> +<dt><code>hs38</code></dt> +<dd><p>Assemble for ARC HS38 instruction set. +</p> +</dd> +<dt><code>hs38_linux</code></dt> +<dd><p>Assemble for ARC HS38 with floating point support on. +</p> +</dd> +</dl> + +<p>Note: the <code>.cpu</code> directive overrides the command-line option +<code>-mcpu=<var>cpu</var></code>; a warning is emitted when the version is not +consistent between the two. +</p> +</dd> +<dt><code>.extAuxRegister <var>name</var>, <var>addr</var>, <var>mode</var></code></dt> +<dd><a name="index-extAuxRegister-directive_002c-ARC"></a> +<p>Auxiliary registers can be defined in the assembler source code by +using this directive. The first parameter, <var>name</var>, is the name of the +new auxiliary register. The second parameter, <var>addr</var>, is +address the of the auxiliary register. The third parameter, +<var>mode</var>, specifies whether the register is readable and/or writable +and is one of: +</p><dl compact="compact"> +<dt><code>r</code></dt> +<dd><p>Read only; +</p> +</dd> +<dt><code>w</code></dt> +<dd><p>Write only; +</p> +</dd> +<dt><code>r|w</code></dt> +<dd><p>Read and write. +</p> +</dd> +</dl> + +<p>For example: +</p><div class="example"> +<pre class="example"> .extAuxRegister mulhi, 0x12, w +</pre></div> +<p>specifies a write only extension auxiliary register, <var>mulhi</var> at +address 0x12. +</p> +</dd> +<dt><code>.extCondCode <var>suffix</var>, <var>val</var></code></dt> +<dd><a name="index-extCondCode-directive_002c-ARC"></a> +<p>ARC supports extensible condition codes. This directive defines a new +condition code, to be known by the suffix, <var>suffix</var> and will +depend on the value, <var>val</var> in the condition code. +</p> +<p>For example: +</p><div class="example"> +<pre class="example"> .extCondCode is_busy,0x14 + add.is_busy r1,r2,r3 +</pre></div> +<p>will only execute the <code>add</code> instruction if the condition code +value is 0x14. +</p> +</dd> +<dt><code>.extCoreRegister <var>name</var>, <var>regnum</var>, <var>mode</var>, <var>shortcut</var></code></dt> +<dd><a name="index-extCoreRegister-directive_002c-ARC"></a> +<p>Specifies an extension core register named <var>name</var> as a synonym for +the register numbered <var>regnum</var>. The register number must be +between 32 and 59. The third argument, <var>mode</var>, indicates whether +the register is readable and/or writable and is one of: +</p><dl compact="compact"> +<dt><code>r</code></dt> +<dd><p>Read only; +</p> +</dd> +<dt><code>w</code></dt> +<dd><p>Write only; +</p> +</dd> +<dt><code>r|w</code></dt> +<dd><p>Read and write. +</p> +</dd> +</dl> + +<p>The final parameter, <var>shortcut</var> indicates whether the register has +a short cut in the pipeline. The valid values are: +</p><dl compact="compact"> +<dt><code>can_shortcut</code></dt> +<dd><p>The register has a short cut in the pipeline; +</p> +</dd> +<dt><code>cannot_shortcut</code></dt> +<dd><p>The register does not have a short cut in the pipeline. +</p></dd> +</dl> + +<p>For example: +</p><div class="example"> +<pre class="example"> .extCoreRegister mlo, 57, r , can_shortcut +</pre></div> +<p>defines a read only extension core register, <code>mlo</code>, which is +register 57, and can short cut the pipeline. +</p> +</dd> +<dt><code>.extInstruction <var>name</var>, <var>opcode</var>, <var>subopcode</var>, <var>suffixclass</var>, <var>syntaxclass</var></code></dt> +<dd><a name="index-extInstruction-directive_002c-ARC"></a> +<p>ARC allows the user to specify extension instructions. These +extension instructions are not macros; the assembler creates encodings +for use of these instructions according to the specification by the +user. +</p> +<p>The first argument, <var>name</var>, gives the name of the instruction. +</p> +<p>The second argument, <var>opcode</var>, is the opcode to be used (bits 31:27 +in the encoding). +</p> +<p>The third argument, <var>subopcode</var>, is the sub-opcode to be used, but +the correct value also depends on the fifth argument, +<var>syntaxclass</var> +</p> +<p>The fourth argument, <var>suffixclass</var>, determines the kinds of +suffixes to be allowed. Valid values are: +</p><dl compact="compact"> +<dt><code>SUFFIX_NONE</code></dt> +<dd><p>No suffixes are permitted; +</p> +</dd> +<dt><code>SUFFIX_COND</code></dt> +<dd><p>Conditional suffixes are permitted; +</p> +</dd> +<dt><code>SUFFIX_FLAG</code></dt> +<dd><p>Flag setting suffixes are permitted. +</p> +</dd> +<dt><code>SUFFIX_COND|SUFFIX_FLAG</code></dt> +<dd><p>Both conditional and flag setting suffices are permitted. +</p> +</dd> +</dl> + +<p>The fifth and final argument, <var>syntaxclass</var>, determines the syntax +class for the instruction. It can have the following values: +</p><dl compact="compact"> +<dt><code>SYNTAX_2OP</code></dt> +<dd><p>Two Operand Instruction; +</p> +</dd> +<dt><code>SYNTAX_3OP</code></dt> +<dd><p>Three Operand Instruction. +</p> +</dd> +<dt><code>SYNTAX_1OP</code></dt> +<dd><p>One Operand Instruction. +</p> +</dd> +<dt><code>SYNTAX_NOP</code></dt> +<dd><p>No Operand Instruction. +</p></dd> +</dl> + +<p>The syntax class may be followed by ‘<samp>|</samp>’ and one of the following +modifiers. +</p><dl compact="compact"> +<dt><code>OP1_MUST_BE_IMM</code></dt> +<dd><p>Modifies syntax class <code>SYNTAX_3OP</code>, specifying that the first +operand of a three-operand instruction must be an immediate (i.e., the +result is discarded). This is usually used to set the flags using +specific instructions and not retain results. +</p> +</dd> +<dt><code>OP1_IMM_IMPLIED</code></dt> +<dd><p>Modifies syntax class <code>SYNTAX_20P</code>, specifying that there is an +implied immediate destination operand which does not appear in the +syntax. +</p> +<p>For example, if the source code contains an instruction like: +</p><div class="example"> +<pre class="example">inst r1,r2 +</pre></div> +<p>the first argument is an implied immediate (that is, the result is +discarded). This is the same as though the source code were: inst +0,r1,r2. +</p> +</dd> +</dl> + +<p>For example, defining a 64-bit multiplier with immediate operands: +</p><div class="example"> +<pre class="example"> .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, + SYNTAX_3OP|OP1_MUST_BE_IMM +</pre></div> +<p>which specifies an extension instruction named <code>mp64</code> with 3 +operands. It sets the flags and can be used with a condition code, +for which the first operand is an immediate, i.e. equivalent to +discarding the result of the operation. +</p> +<p>A two operands instruction variant would be: +</p><div class="example"> +<pre class="example"> .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, + SYNTAX_2OP|OP1_IMM_IMPLIED +</pre></div> +<p>which describes a two operand instruction with an implicit first +immediate operand. The result of this operation would be discarded. +</p> +<a name="index-_002earc_005fattribute-directive_002c-ARC"></a> +</dd> +<dt><code>.arc_attribute <var>tag</var>, <var>value</var></code></dt> +<dd><p>Set the ARC object attribute <var>tag</var> to <var>value</var>. +</p> +<p>The <var>tag</var> is either an attribute number, or one of the following: +<code>Tag_ARC_PCS_config</code>, <code>Tag_ARC_CPU_base</code>, +<code>Tag_ARC_CPU_variation</code>, <code>Tag_ARC_CPU_name</code>, +<code>Tag_ARC_ABI_rf16</code>, <code>Tag_ARC_ABI_osver</code>, <code>Tag_ARC_ABI_sda</code>, +<code>Tag_ARC_ABI_pic</code>, <code>Tag_ARC_ABI_tls</code>, <code>Tag_ARC_ABI_enumsize</code>, +<code>Tag_ARC_ABI_exceptions</code>, <code>Tag_ARC_ABI_double_size</code>, +<code>Tag_ARC_ISA_config</code>, <code>Tag_ARC_ISA_apex</code>, +<code>Tag_ARC_ISA_mpy_option</code> +</p> +<p>The <var>value</var> is either a <code>number</code>, <code>"string"</code>, or +<code>number, "string"</code> depending on the tag. +</p> +</dd> +</dl> + +<hr> +<a name="ARC-Modifiers"></a> +<div class="header"> +<p> +Next: <a href="#ARC-Symbols" accesskey="n" rel="next">ARC Symbols</a>, Previous: <a href="#ARC-Directives" accesskey="p" rel="previous">ARC Directives</a>, Up: <a href="#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="ARC-Assembler-Modifiers"></a> +<h4 class="subsection">9.3.4 ARC Assembler Modifiers</h4> + +<p>The following additional assembler modifiers have been added for +position-independent code. These modifiers are available only with +the ARC 700 and above processors and generate relocation entries, +which are interpreted by the linker as follows: +</p> +<dl compact="compact"> +<dt><code>@pcl(<var>symbol</var>)</code></dt> +<dd><a name="index-_0040pcl_0028symbol_0029_002c-ARC-modifier"></a> +<p>Relative distance of <var>symbol</var>’s from the current program counter +location. +</p> +</dd> +<dt><code>@gotpc(<var>symbol</var>)</code></dt> +<dd><a name="index-_0040gotpc_0028symbol_0029_002c-ARC-modifier"></a> +<p>Relative distance of <var>symbol</var>’s Global Offset Table entry from the +current program counter location. +</p> +</dd> +<dt><code>@gotoff(<var>symbol</var>)</code></dt> +<dd><a name="index-_0040gotoff_0028symbol_0029_002c-ARC-modifier"></a> +<p>Distance of <var>symbol</var> from the base of the Global Offset Table. +</p> +</dd> +<dt><code>@plt(<var>symbol</var>)</code></dt> +<dd><a name="index-_0040plt_0028symbol_0029_002c-ARC-modifier"></a> +<p>Distance of <var>symbol</var>’s Procedure Linkage Table entry from the +current program counter. This is valid only with branch and link +instructions and PC-relative calls. +</p> +</dd> +<dt><code>@sda(<var>symbol</var>)</code></dt> +<dd><a name="index-_0040sda_0028symbol_0029_002c-ARC-modifier"></a> +<p>Relative distance of <var>symbol</var> from the base of the Small Data +Pointer. +</p> +</dd> +</dl> + +<hr> +<a name="ARC-Symbols"></a> +<div class="header"> +<p> +Next: <a href="#ARC-Opcodes" accesskey="n" rel="next">ARC Opcodes</a>, Previous: <a href="#ARC-Modifiers" accesskey="p" rel="previous">ARC Modifiers</a>, Up: <a href="#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="ARC-Pre_002ddefined-Symbols"></a> +<h4 class="subsection">9.3.5 ARC Pre-defined Symbols</h4> + +<p>The following assembler symbols will prove useful when developing +position-independent code. These symbols are available only with the +ARC 700 and above processors. +</p> +<dl compact="compact"> +<dt><code>__GLOBAL_OFFSET_TABLE__</code></dt> +<dd><a name="index-_005f_005fGLOBAL_005fOFFSET_005fTABLE_005f_005f_002c-ARC-pre_002ddefined-symbol"></a> +<p>Symbol referring to the base of the Global Offset Table. +</p> +</dd> +<dt><code>__DYNAMIC__</code></dt> +<dd><a name="index-_005f_005fDYNAMIC_005f_005f_002c-ARC-pre_002ddefined-symbol"></a> +<p>An alias for the Global Offset Table +<code>Base__GLOBAL_OFFSET_TABLE__</code>. It can be used only with +<code>@gotpc</code> modifiers. +</p> +</dd> +</dl> + +<hr> +<a name="ARC-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#ARC-Symbols" accesskey="p" rel="previous">ARC Symbols</a>, Up: <a href="#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-2"></a> +<h4 class="subsection">9.3.6 Opcodes</h4> + +<a name="index-ARC-opcodes"></a> +<a name="index-opcodes-for-ARC"></a> + +<p>For information on the ARC instruction set, see <cite>ARC Programmers +Reference Manual</cite>, available where you download the processor IP library. +</p> + +<hr> +<a name="ARM_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#AVR_002dDependent" accesskey="n" rel="next">AVR-Dependent</a>, Previous: <a href="#ARC_002dDependent" accesskey="p" rel="previous">ARC-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="ARM-Dependent-Features"></a> +<h3 class="section">9.4 ARM Dependent Features</h3> + + +<a name="index-ARM-support"></a> +<a name="index-Thumb-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#ARM-Options" accesskey="1">ARM Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM-Syntax" accesskey="2">ARM Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM-Floating-Point" accesskey="3">ARM Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM-Directives" accesskey="4">ARM Directives</a>:</td><td> </td><td align="left" valign="top">ARM Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM-Opcodes" accesskey="5">ARM Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM-Mapping-Symbols" accesskey="6">ARM Mapping Symbols</a>:</td><td> </td><td align="left" valign="top">Mapping Symbols +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM-Unwinding-Tutorial" accesskey="7">ARM Unwinding Tutorial</a>:</td><td> </td><td align="left" valign="top">Unwinding +</td></tr> +</table> + +<hr> +<a name="ARM-Options"></a> +<div class="header"> +<p> +Next: <a href="#ARM-Syntax" accesskey="n" rel="next">ARM Syntax</a>, Up: <a href="#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-3"></a> +<h4 class="subsection">9.4.1 Options</h4> +<a name="index-ARM-options-_0028none_0029"></a> +<a name="index-options-for-ARM-_0028none_0029"></a> + +<dl compact="compact"> +<dd> +<a name="index-_002dmcpu_003d-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mcpu=<var>processor</var>[+<var>extension</var>…]</code></dt> +<dd><p>This option specifies the target processor. The assembler will issue an +error message if an attempt is made to assemble an instruction which +will not execute on the target processor. The following processor names are +recognized: +<code>arm1</code>, +<code>arm2</code>, +<code>arm250</code>, +<code>arm3</code>, +<code>arm6</code>, +<code>arm60</code>, +<code>arm600</code>, +<code>arm610</code>, +<code>arm620</code>, +<code>arm7</code>, +<code>arm7m</code>, +<code>arm7d</code>, +<code>arm7dm</code>, +<code>arm7di</code>, +<code>arm7dmi</code>, +<code>arm70</code>, +<code>arm700</code>, +<code>arm700i</code>, +<code>arm710</code>, +<code>arm710t</code>, +<code>arm720</code>, +<code>arm720t</code>, +<code>arm740t</code>, +<code>arm710c</code>, +<code>arm7100</code>, +<code>arm7500</code>, +<code>arm7500fe</code>, +<code>arm7t</code>, +<code>arm7tdmi</code>, +<code>arm7tdmi-s</code>, +<code>arm8</code>, +<code>arm810</code>, +<code>strongarm</code>, +<code>strongarm1</code>, +<code>strongarm110</code>, +<code>strongarm1100</code>, +<code>strongarm1110</code>, +<code>arm9</code>, +<code>arm920</code>, +<code>arm920t</code>, +<code>arm922t</code>, +<code>arm940t</code>, +<code>arm9tdmi</code>, +<code>fa526</code> (Faraday FA526 processor), +<code>fa626</code> (Faraday FA626 processor), +<code>arm9e</code>, +<code>arm926e</code>, +<code>arm926ej-s</code>, +<code>arm946e-r0</code>, +<code>arm946e</code>, +<code>arm946e-s</code>, +<code>arm966e-r0</code>, +<code>arm966e</code>, +<code>arm966e-s</code>, +<code>arm968e-s</code>, +<code>arm10t</code>, +<code>arm10tdmi</code>, +<code>arm10e</code>, +<code>arm1020</code>, +<code>arm1020t</code>, +<code>arm1020e</code>, +<code>arm1022e</code>, +<code>arm1026ej-s</code>, +<code>fa606te</code> (Faraday FA606TE processor), +<code>fa616te</code> (Faraday FA616TE processor), +<code>fa626te</code> (Faraday FA626TE processor), +<code>fmp626</code> (Faraday FMP626 processor), +<code>fa726te</code> (Faraday FA726TE processor), +<code>arm1136j-s</code>, +<code>arm1136jf-s</code>, +<code>arm1156t2-s</code>, +<code>arm1156t2f-s</code>, +<code>arm1176jz-s</code>, +<code>arm1176jzf-s</code>, +<code>mpcore</code>, +<code>mpcorenovfp</code>, +<code>cortex-a5</code>, +<code>cortex-a7</code>, +<code>cortex-a8</code>, +<code>cortex-a9</code>, +<code>cortex-a15</code>, +<code>cortex-a17</code>, +<code>cortex-a32</code>, +<code>cortex-a35</code>, +<code>cortex-a53</code>, +<code>cortex-a55</code>, +<code>cortex-a57</code>, +<code>cortex-a72</code>, +<code>cortex-a73</code>, +<code>cortex-a75</code>, +<code>cortex-a76</code>, +<code>cortex-a76ae</code>, +<code>cortex-a77</code>, +<code>cortex-a78</code>, +<code>cortex-a78ae</code>, +<code>cortex-a78c</code>, +<code>cortex-a710</code>, +<code>ares</code>, +<code>cortex-r4</code>, +<code>cortex-r4f</code>, +<code>cortex-r5</code>, +<code>cortex-r7</code>, +<code>cortex-r8</code>, +<code>cortex-r52</code>, +<code>cortex-r52plus</code>, +<code>cortex-m35p</code>, +<code>cortex-m33</code>, +<code>cortex-m23</code>, +<code>cortex-m7</code>, +<code>cortex-m4</code>, +<code>cortex-m3</code>, +<code>cortex-m1</code>, +<code>cortex-m0</code>, +<code>cortex-m0plus</code>, +<code>cortex-x1</code>, +<code>cortex-x1c</code>, +<code>exynos-m1</code>, +<code>marvell-pj4</code>, +<code>marvell-whitney</code>, +<code>neoverse-n1</code>, +<code>neoverse-n2</code>, +<code>neoverse-v1</code>, +<code>xgene1</code>, +<code>xgene2</code>, +<code>ep9312</code> (ARM920 with Cirrus Maverick coprocessor), +<code>i80200</code> (Intel XScale processor) +<code>iwmmxt</code> (Intel XScale processor with Wireless MMX technology coprocessor) +and +<code>xscale</code>. +The special name <code>all</code> may be used to allow the +assembler to accept instructions valid for any ARM processor. +</p> +<p>In addition to the basic instruction set, the assembler can be told to +accept various extension mnemonics that extend the processor using the +co-processor instruction space. For example, <code>-mcpu=arm920+maverick</code> +is equivalent to specifying <code>-mcpu=ep9312</code>. +</p> +<p>Multiple extensions may be specified, separated by a <code>+</code>. The +extensions should be specified in ascending alphabetical order. +</p> +<p>Some extensions may be restricted to particular architectures; this is +documented in the list of extensions below. +</p> +<p>Extension mnemonics may also be removed from those the assembler accepts. +This is done be prepending <code>no</code> to the option that adds the extension. +Extensions that are removed should be listed after all extensions which have +been added, again in ascending alphabetical order. For example, +<code>-mcpu=ep9312+nomaverick</code> is equivalent to specifying <code>-mcpu=arm920</code>. +</p> + +<p>The following extensions are currently supported: +<code>bf16</code> (BFloat16 extensions for v8.6-A architecture), +<code>i8mm</code> (Int8 Matrix Multiply extensions for v8.6-A architecture), +<code>crc</code> +<code>crypto</code> (Cryptography Extensions for v8-A architecture, implies <code>fp+simd</code>), +<code>dotprod</code> (Dot Product Extensions for v8.2-A architecture, implies <code>fp+simd</code>), +<code>fp</code> (Floating Point Extensions for v8-A architecture), +<code>fp16</code> (FP16 Extensions for v8.2-A architecture, implies <code>fp</code>), +<code>fp16fml</code> (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies <code>fp16</code>), +<code>idiv</code> (Integer Divide Extensions for v7-A and v7-R architectures), +<code>iwmmxt</code>, +<code>iwmmxt2</code>, +<code>xscale</code>, +<code>maverick</code>, +<code>mp</code> (Multiprocessing Extensions for v7-A and v7-R +architectures), +<code>os</code> (Operating System for v6M architecture), +<code>predres</code> (Execution and Data Prediction Restriction Instruction for +v8-A architectures, added by default from v8.5-A), +<code>sb</code> (Speculation Barrier Instruction for v8-A architectures, added by +default from v8.5-A), +<code>sec</code> (Security Extensions for v6K and v7-A architectures), +<code>simd</code> (Advanced SIMD Extensions for v8-A architecture, implies <code>fp</code>), +<code>virt</code> (Virtualization Extensions for v7-A architecture, implies +<code>idiv</code>), +<code>pan</code> (Privileged Access Never Extensions for v8-A architecture), +<code>ras</code> (Reliability, Availability and Serviceability extensions +for v8-A architecture), +<code>rdma</code> (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies +<code>simd</code>) +and +<code>xscale</code>. +</p> +<a name="index-_002dmarch_003d-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-march=<var>architecture</var>[+<var>extension</var>…]</code></dt> +<dd><p>This option specifies the target architecture. The assembler will issue +an error message if an attempt is made to assemble an instruction which +will not execute on the target architecture. The following architecture +names are recognized: +<code>armv1</code>, +<code>armv2</code>, +<code>armv2a</code>, +<code>armv2s</code>, +<code>armv3</code>, +<code>armv3m</code>, +<code>armv4</code>, +<code>armv4xm</code>, +<code>armv4t</code>, +<code>armv4txm</code>, +<code>armv5</code>, +<code>armv5t</code>, +<code>armv5txm</code>, +<code>armv5te</code>, +<code>armv5texp</code>, +<code>armv6</code>, +<code>armv6j</code>, +<code>armv6k</code>, +<code>armv6z</code>, +<code>armv6kz</code>, +<code>armv6-m</code>, +<code>armv6s-m</code>, +<code>armv7</code>, +<code>armv7-a</code>, +<code>armv7ve</code>, +<code>armv7-r</code>, +<code>armv7-m</code>, +<code>armv7e-m</code>, +<code>armv8-a</code>, +<code>armv8.1-a</code>, +<code>armv8.2-a</code>, +<code>armv8.3-a</code>, +<code>armv8-r</code>, +<code>armv8.4-a</code>, +<code>armv8.5-a</code>, +<code>armv8-m.base</code>, +<code>armv8-m.main</code>, +<code>armv8.1-m.main</code>, +<code>armv8.6-a</code>, +<code>armv8.7-a</code>, +<code>armv8.8-a</code>, +<code>armv9-a</code>, +<code>iwmmxt</code>, +<code>iwmmxt2</code> +and +<code>xscale</code>. +If both <code>-mcpu</code> and +<code>-march</code> are specified, the assembler will use +the setting for <code>-mcpu</code>. +</p> +<p>The architecture option can be extended with a set extension options. These +extensions are context sensitive, i.e. the same extension may mean different +things when used with different architectures. When used together with a +<code>-mfpu</code> option, the union of both feature enablement is taken. +See their availability and meaning below: +</p> +<p>For <code>armv5te</code>, <code>armv5texp</code>, <code>armv5tej</code>, <code>armv6</code>, <code>armv6j</code>, <code>armv6k</code>, <code>armv6z</code>, <code>armv6kz</code>, <code>armv6zk</code>, <code>armv6t2</code>, <code>armv6kt2</code> and <code>armv6zt2</code>: +</p> +<p><code>+fp</code>: Enables VFPv2 instructions. +<code>+nofp</code>: Disables all FPU instrunctions. +</p> +<p>For <code>armv7</code>: +</p> +<p><code>+fp</code>: Enables VFPv3 instructions with 16 double-word registers. +<code>+nofp</code>: Disables all FPU instructions. +</p> +<p>For <code>armv7-a</code>: +</p> +<p><code>+fp</code>: Enables VFPv3 instructions with 16 double-word registers. +<code>+vfpv3-d16</code>: Alias for <code>+fp</code>. +<code>+vfpv3</code>: Enables VFPv3 instructions with 32 double-word registers. +<code>+vfpv3-d16-fp16</code>: Enables VFPv3 with half precision floating-point +conversion instructions and 16 double-word registers. +<code>+vfpv3-fp16</code>: Enables VFPv3 with half precision floating-point conversion +instructions and 32 double-word registers. +<code>+vfpv4-d16</code>: Enables VFPv4 instructions with 16 double-word registers. +<code>+vfpv4</code>: Enables VFPv4 instructions with 32 double-word registers. +<code>+simd</code>: Enables VFPv3 and NEONv1 instructions with 32 double-word +registers. +<code>+neon</code>: Alias for <code>+simd</code>. +<code>+neon-vfpv3</code>: Alias for <code>+simd</code>. +<code>+neon-fp16</code>: Enables VFPv3, half precision floating-point conversion and +NEONv1 instructions with 32 double-word registers. +<code>+neon-vfpv4</code>: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 +double-word registers. +<code>+mp</code>: Enables Multiprocessing Extensions. +<code>+sec</code>: Enables Security Extensions. +<code>+nofp</code>: Disables all FPU and NEON instructions. +<code>+nosimd</code>: Disables all NEON instructions. +</p> +<p>For <code>armv7ve</code>: +</p> +<p><code>+fp</code>: Enables VFPv4 instructions with 16 double-word registers. +<code>+vfpv4-d16</code>: Alias for <code>+fp</code>. +<code>+vfpv3-d16</code>: Enables VFPv3 instructions with 16 double-word registers. +<code>+vfpv3</code>: Enables VFPv3 instructions with 32 double-word registers. +<code>+vfpv3-d16-fp16</code>: Enables VFPv3 with half precision floating-point +conversion instructions and 16 double-word registers. +<code>+vfpv3-fp16</code>: Enables VFPv3 with half precision floating-point conversion +instructions and 32 double-word registers. +<code>+vfpv4</code>: Enables VFPv4 instructions with 32 double-word registers. +<code>+simd</code>: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 +double-word registers. +<code>+neon-vfpv4</code>: Alias for <code>+simd</code>. +<code>+neon</code>: Enables VFPv3 and NEONv1 instructions with 32 double-word +registers. +<code>+neon-vfpv3</code>: Alias for <code>+neon</code>. +<code>+neon-fp16</code>: Enables VFPv3, half precision floating-point conversion and +NEONv1 instructions with 32 double-word registers. +double-word registers. +<code>+nofp</code>: Disables all FPU and NEON instructions. +<code>+nosimd</code>: Disables all NEON instructions. +</p> +<p>For <code>armv7-r</code>: +</p> +<p><code>+fp.sp</code>: Enables single-precision only VFPv3 instructions with 16 +double-word registers. +<code>+vfpv3xd</code>: Alias for <code>+fp.sp</code>. +<code>+fp</code>: Enables VFPv3 instructions with 16 double-word registers. +<code>+vfpv3-d16</code>: Alias for <code>+fp</code>. +<code>+vfpv3xd-fp16</code>: Enables single-precision only VFPv3 and half +floating-point conversion instructions with 16 double-word registers. +<code>+vfpv3-d16-fp16</code>: Enables VFPv3 and half precision floating-point +conversion instructions with 16 double-word registers. +<code>+idiv</code>: Enables integer division instructions in ARM mode. +<code>+nofp</code>: Disables all FPU instructions. +</p> +<p>For <code>armv7e-m</code>: +</p> +<p><code>+fp</code>: Enables single-precision only VFPv4 instructions with 16 +double-word registers. +<code>+vfpvf4-sp-d16</code>: Alias for <code>+fp</code>. +<code>+fpv5</code>: Enables single-precision only VFPv5 instructions with 16 +double-word registers. +<code>+fp.dp</code>: Enables VFPv5 instructions with 16 double-word registers. +<code>+fpv5-d16"</code>: Alias for <code>+fp.dp</code>. +<code>+nofp</code>: Disables all FPU instructions. +</p> +<p>For <code>armv8-m.main</code>: +</p> +<p><code>+dsp</code>: Enables DSP Extension. +<code>+fp</code>: Enables single-precision only VFPv5 instructions with 16 +double-word registers. +<code>+fp.dp</code>: Enables VFPv5 instructions with 16 double-word registers. +<code>+cdecp0</code> (CDE extensions for v8-m architecture with coprocessor 0), +<code>+cdecp1</code> (CDE extensions for v8-m architecture with coprocessor 1), +<code>+cdecp2</code> (CDE extensions for v8-m architecture with coprocessor 2), +<code>+cdecp3</code> (CDE extensions for v8-m architecture with coprocessor 3), +<code>+cdecp4</code> (CDE extensions for v8-m architecture with coprocessor 4), +<code>+cdecp5</code> (CDE extensions for v8-m architecture with coprocessor 5), +<code>+cdecp6</code> (CDE extensions for v8-m architecture with coprocessor 6), +<code>+cdecp7</code> (CDE extensions for v8-m architecture with coprocessor 7), +<code>+nofp</code>: Disables all FPU instructions. +<code>+nodsp</code>: Disables DSP Extension. +</p> +<p>For <code>armv8.1-m.main</code>: +</p> +<p><code>+dsp</code>: Enables DSP Extension. +<code>+fp</code>: Enables single and half precision scalar Floating Point Extensions +for Armv8.1-M Mainline with 16 double-word registers. +<code>+fp.dp</code>: Enables double precision scalar Floating Point Extensions for +Armv8.1-M Mainline, implies <code>+fp</code>. +<code>+mve</code>: Enables integer only M-profile Vector Extension for +Armv8.1-M Mainline, implies <code>+dsp</code>. +<code>+mve.fp</code>: Enables Floating Point M-profile Vector Extension for +Armv8.1-M Mainline, implies <code>+mve</code> and <code>+fp</code>. +<code>+nofp</code>: Disables all FPU instructions. +<code>+nodsp</code>: Disables DSP Extension. +<code>+nomve</code>: Disables all M-profile Vector Extensions. +</p> +<p>For <code>armv8-a</code>: +</p> +<p><code>+crc</code>: Enables CRC32 Extension. +<code>+simd</code>: Enables VFP and NEON for Armv8-A. +<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies +<code>+simd</code>. +<code>+sb</code>: Enables Speculation Barrier Instruction for Armv8-A. +<code>+predres</code>: Enables Execution and Data Prediction Restriction Instruction +for Armv8-A. +<code>+nofp</code>: Disables all FPU, NEON and Cryptography Extensions. +<code>+nocrypto</code>: Disables Cryptography Extensions. +</p> +<p>For <code>armv8.1-a</code>: +</p> +<p><code>+simd</code>: Enables VFP and NEON for Armv8.1-A. +<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies +<code>+simd</code>. +<code>+sb</code>: Enables Speculation Barrier Instruction for Armv8-A. +<code>+predres</code>: Enables Execution and Data Prediction Restriction Instruction +for Armv8-A. +<code>+nofp</code>: Disables all FPU, NEON and Cryptography Extensions. +<code>+nocrypto</code>: Disables Cryptography Extensions. +</p> +<p>For <code>armv8.2-a</code> and <code>armv8.3-a</code>: +</p> +<p><code>+simd</code>: Enables VFP and NEON for Armv8.1-A. +<code>+fp16</code>: Enables FP16 Extension for Armv8.2-A, implies <code>+simd</code>. +<code>+fp16fml</code>: Enables FP16 Floating Point Multiplication Variant Extensions +for Armv8.2-A, implies <code>+fp16</code>. +<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies +<code>+simd</code>. +<code>+dotprod</code>: Enables Dot Product Extensions for Armv8.2-A, implies +<code>+simd</code>. +<code>+sb</code>: Enables Speculation Barrier Instruction for Armv8-A. +<code>+predres</code>: Enables Execution and Data Prediction Restriction Instruction +for Armv8-A. +<code>+nofp</code>: Disables all FPU, NEON, Cryptography and Dot Product Extensions. +<code>+nocrypto</code>: Disables Cryptography Extensions. +</p> +<p>For <code>armv8.4-a</code>: +</p> +<p><code>+simd</code>: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for +Armv8.2-A. +<code>+fp16</code>: Enables FP16 Floating Point and Floating Point Multiplication +Variant Extensions for Armv8.2-A, implies <code>+simd</code>. +<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies +<code>+simd</code>. +<code>+sb</code>: Enables Speculation Barrier Instruction for Armv8-A. +<code>+predres</code>: Enables Execution and Data Prediction Restriction Instruction +for Armv8-A. +<code>+nofp</code>: Disables all FPU, NEON, Cryptography and Dot Product Extensions. +<code>+nocryptp</code>: Disables Cryptography Extensions. +</p> +<p>For <code>armv8.5-a</code>: +</p> +<p><code>+simd</code>: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for +Armv8.2-A. +<code>+fp16</code>: Enables FP16 Floating Point and Floating Point Multiplication +Variant Extensions for Armv8.2-A, implies <code>+simd</code>. +<code>+crypto</code>: Enables Cryptography Extensions for Armv8-A, implies +<code>+simd</code>. +<code>+nofp</code>: Disables all FPU, NEON, Cryptography and Dot Product Extensions. +<code>+nocryptp</code>: Disables Cryptography Extensions. +</p> + +<a name="index-_002dmfpu_003d-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mfpu=<var>floating-point-format</var></code></dt> +<dd> +<p>This option specifies the floating point format to assemble for. The +assembler will issue an error message if an attempt is made to assemble +an instruction which will not execute on the target floating point unit. +The following format options are recognized: +<code>softfpa</code>, +<code>fpe</code>, +<code>fpe2</code>, +<code>fpe3</code>, +<code>fpa</code>, +<code>fpa10</code>, +<code>fpa11</code>, +<code>arm7500fe</code>, +<code>softvfp</code>, +<code>softvfp+vfp</code>, +<code>vfp</code>, +<code>vfp10</code>, +<code>vfp10-r0</code>, +<code>vfp9</code>, +<code>vfpxd</code>, +<code>vfpv2</code>, +<code>vfpv3</code>, +<code>vfpv3-fp16</code>, +<code>vfpv3-d16</code>, +<code>vfpv3-d16-fp16</code>, +<code>vfpv3xd</code>, +<code>vfpv3xd-d16</code>, +<code>vfpv4</code>, +<code>vfpv4-d16</code>, +<code>fpv4-sp-d16</code>, +<code>fpv5-sp-d16</code>, +<code>fpv5-d16</code>, +<code>fp-armv8</code>, +<code>arm1020t</code>, +<code>arm1020e</code>, +<code>arm1136jf-s</code>, +<code>maverick</code>, +<code>neon</code>, +<code>neon-vfpv3</code>, +<code>neon-fp16</code>, +<code>neon-vfpv4</code>, +<code>neon-fp-armv8</code>, +<code>crypto-neon-fp-armv8</code>, +<code>neon-fp-armv8.1</code> +and +<code>crypto-neon-fp-armv8.1</code>. +</p> +<p>In addition to determining which instructions are assembled, this option +also affects the way in which the <code>.double</code> assembler directive behaves +when assembling little-endian code. +</p> +<p>The default is dependent on the processor selected. For Architecture 5 or +later, the default is to assemble for VFP instructions; for earlier +architectures the default is to assemble for FPA instructions. +</p> +<a name="index-_002dmfp16_002dformat_003d-command_002dline-option"></a> +</dd> +<dt><code>-mfp16-format=<var>format</var></code></dt> +<dd><p>This option specifies the half-precision floating point format to use +when assembling floating point numbers emitted by the <code>.float16</code> +directive. +The following format options are recognized: +<code>ieee</code>, +<code>alternative</code>. +If <code>ieee</code> is specified then the IEEE 754-2008 half-precision floating +point format is used, if <code>alternative</code> is specified then the Arm +alternative half-precision format is used. If this option is set on the +command line then the format is fixed and cannot be changed with +the <code>float16_format</code> directive. If this value is not set then +the IEEE 754-2008 format is used until the format is explicitly set with +the <code>float16_format</code> directive. +</p> +<a name="index-_002dmthumb-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mthumb</code></dt> +<dd><p>This option specifies that the assembler should start assembling Thumb +instructions; that is, it should behave as though the file starts with a +<code>.code 16</code> directive. +</p> +<a name="index-_002dmthumb_002dinterwork-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mthumb-interwork</code></dt> +<dd><p>This option specifies that the output generated by the assembler should +be marked as supporting interworking. It also affects the behaviour +of the <code>ADR</code> and <code>ADRL</code> pseudo opcodes. +</p> +<a name="index-_002dmimplicit_002dit-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mimplicit-it=never</code></dt> +<dt><code>-mimplicit-it=always</code></dt> +<dt><code>-mimplicit-it=arm</code></dt> +<dt><code>-mimplicit-it=thumb</code></dt> +<dd><p>The <code>-mimplicit-it</code> option controls the behavior of the assembler when +conditional instructions are not enclosed in IT blocks. +There are four possible behaviors. +If <code>never</code> is specified, such constructs cause a warning in ARM +code and an error in Thumb-2 code. +If <code>always</code> is specified, such constructs are accepted in both +ARM and Thumb-2 code, where the IT instruction is added implicitly. +If <code>arm</code> is specified, such constructs are accepted in ARM code +and cause an error in Thumb-2 code. +If <code>thumb</code> is specified, such constructs cause a warning in ARM +code and are accepted in Thumb-2 code. If you omit this option, the +behavior is equivalent to <code>-mimplicit-it=arm</code>. +</p> +<a name="index-_002dmapcs_002d26-command_002dline-option_002c-ARM"></a> +<a name="index-_002dmapcs_002d32-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mapcs-26</code></dt> +<dt><code>-mapcs-32</code></dt> +<dd><p>These options specify that the output generated by the assembler should +be marked as supporting the indicated version of the Arm Procedure. +Calling Standard. +</p> +<a name="index-_002dmatpcs-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-matpcs</code></dt> +<dd><p>This option specifies that the output generated by the assembler should +be marked as supporting the Arm/Thumb Procedure Calling Standard. If +enabled this option will cause the assembler to create an empty +debugging section in the object file called .arm.atpcs. Debuggers can +use this to determine the ABI being used by. +</p> +<a name="index-_002dmapcs_002dfloat-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mapcs-float</code></dt> +<dd><p>This indicates the floating point variant of the APCS should be +used. In this variant floating point arguments are passed in FP +registers rather than integer registers. +</p> +<a name="index-_002dmapcs_002dreentrant-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mapcs-reentrant</code></dt> +<dd><p>This indicates that the reentrant variant of the APCS should be used. +This variant supports position independent code. +</p> +<a name="index-_002dmfloat_002dabi_003d-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mfloat-abi=<var>abi</var></code></dt> +<dd><p>This option specifies that the output generated by the assembler should be +marked as using specified floating point ABI. +The following values are recognized: +<code>soft</code>, +<code>softfp</code> +and +<code>hard</code>. +</p> +<a name="index-_002deabi_003d-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-meabi=<var>ver</var></code></dt> +<dd><p>This option specifies which EABI version the produced object files should +conform to. +The following values are recognized: +<code>gnu</code>, +<code>4</code> +and +<code>5</code>. +</p> +<a name="index-_002dEB-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-EB</code></dt> +<dd><p>This option specifies that the output generated by the assembler should +be marked as being encoded for a big-endian processor. +</p> +<p>Note: If a program is being built for a system with big-endian data +and little-endian instructions then it should be assembled with the +<samp>-EB</samp> option, (all of it, code and data) and then linked with +the <samp>--be8</samp> option. This will reverse the endianness of the +instructions back to little-endian, but leave the data as big-endian. +</p> +<a name="index-_002dEL-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-EL</code></dt> +<dd><p>This option specifies that the output generated by the assembler should +be marked as being encoded for a little-endian processor. +</p> +<a name="index-_002dk-command_002dline-option_002c-ARM"></a> +<a name="index-PIC-code-generation-for-ARM"></a> +</dd> +<dt><code>-k</code></dt> +<dd><p>This option specifies that the output of the assembler should be marked +as position-independent code (PIC). +</p> +<a name="index-_002d_002dfix_002dv4bx-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>--fix-v4bx</code></dt> +<dd><p>Allow <code>BX</code> instructions in ARMv4 code. This is intended for use with +the linker option of the same name. +</p> +<a name="index-_002dmwarn_002ddeprecated-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mwarn-deprecated</code></dt> +<dt><code>-mno-warn-deprecated</code></dt> +<dd><p>Enable or disable warnings about using deprecated options or +features. The default is to warn. +</p> +<a name="index-_002dmccs-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mccs</code></dt> +<dd><p>Turns on CodeComposer Studio assembly syntax compatibility mode. +</p> +<a name="index-_002dmwarn_002dsyms-command_002dline-option_002c-ARM"></a> +</dd> +<dt><code>-mwarn-syms</code></dt> +<dt><code>-mno-warn-syms</code></dt> +<dd><p>Enable or disable warnings about symbols that match the names of ARM +instructions. The default is to warn. +</p> +</dd> +</dl> + + +<hr> +<a name="ARM-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#ARM-Floating-Point" accesskey="n" rel="next">ARM Floating Point</a>, Previous: <a href="#ARM-Options" accesskey="p" rel="previous">ARM Options</a>, Up: <a href="#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-5"></a> +<h4 class="subsection">9.4.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#ARM_002dInstruction_002dSet" accesskey="1">ARM-Instruction-Set</a>:</td><td> </td><td align="left" valign="top">Instruction Set +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM_002dChars" accesskey="2">ARM-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM_002dRegs" accesskey="3">ARM-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM_002dRelocations" accesskey="4">ARM-Relocations</a>:</td><td> </td><td align="left" valign="top">Relocations +</td></tr> +<tr><td align="left" valign="top">• <a href="#ARM_002dNeon_002dAlignment" accesskey="5">ARM-Neon-Alignment</a>:</td><td> </td><td align="left" valign="top">NEON Alignment Specifiers +</td></tr> +</table> + +<hr> +<a name="ARM_002dInstruction_002dSet"></a> +<div class="header"> +<p> +Next: <a href="#ARM_002dChars" accesskey="n" rel="next">ARM-Chars</a>, Up: <a href="#ARM-Syntax" accesskey="u" rel="up">ARM Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-Set-Syntax"></a> +<h4 class="subsubsection">9.4.2.1 Instruction Set Syntax</h4> +<p>Two slightly different syntaxes are support for ARM and THUMB +instructions. The default, <code>divided</code>, uses the old style where +ARM and THUMB instructions had their own, separate syntaxes. The new, +<code>unified</code> syntax, which can be selected via the <code>.syntax</code> +directive, and has the following main features: +</p> +<ul> +<li> Immediate operands do not require a <code>#</code> prefix. + +</li><li> The <code>IT</code> instruction may appear, and if it does it is validated +against subsequent conditional affixes. In ARM mode it does not +generate machine code, in THUMB mode it does. + +</li><li> For ARM instructions the conditional affixes always appear at the end +of the instruction. For THUMB instructions conditional affixes can be +used, but only inside the scope of an <code>IT</code> instruction. + +</li><li> All of the instructions new to the V6T2 architecture (and later) are +available. (Only a few such instructions can be written in the +<code>divided</code> syntax). + +</li><li> The <code>.N</code> and <code>.W</code> suffixes are recognized and honored. + +</li><li> All instructions set the flags if and only if they have an <code>s</code> +affix. +</li></ul> + +<hr> +<a name="ARM_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#ARM_002dRegs" accesskey="n" rel="next">ARM-Regs</a>, Previous: <a href="#ARM_002dInstruction_002dSet" accesskey="p" rel="previous">ARM-Instruction-Set</a>, Up: <a href="#ARM-Syntax" accesskey="u" rel="up">ARM Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-3"></a> +<h4 class="subsubsection">9.4.2.2 Special Characters</h4> + +<a name="index-line-comment-character_002c-ARM"></a> +<a name="index-ARM-line-comment-character"></a> +<p>The presence of a ‘<samp>@</samp>’ anywhere on a line indicates the start of +a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-ARM"></a> +<a name="index-statement-separator_002c-ARM"></a> +<a name="index-ARM-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used instead of a newline to separate +statements. +</p> +<a name="index-immediate-character_002c-ARM"></a> +<a name="index-ARM-immediate-character"></a> +<p>Either ‘<samp>#</samp>’ or ‘<samp>$</samp>’ can be used to indicate immediate operands. +</p> +<a name="index-identifiers_002c-ARM"></a> +<a name="index-ARM-identifiers"></a> +<p>*TODO* Explain about /data modifier on symbols. +</p> +<hr> +<a name="ARM_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#ARM_002dRelocations" accesskey="n" rel="next">ARM-Relocations</a>, Previous: <a href="#ARM_002dChars" accesskey="p" rel="previous">ARM-Chars</a>, Up: <a href="#ARM-Syntax" accesskey="u" rel="up">ARM Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-3"></a> +<h4 class="subsubsection">9.4.2.3 Register Names</h4> + +<a name="index-ARM-register-names"></a> +<a name="index-register-names_002c-ARM"></a> +<p>*TODO* Explain about ARM register naming, and the predefined names. +</p> +<hr> +<a name="ARM_002dRelocations"></a> +<div class="header"> +<p> +Next: <a href="#ARM_002dNeon_002dAlignment" accesskey="n" rel="next">ARM-Neon-Alignment</a>, Previous: <a href="#ARM_002dRegs" accesskey="p" rel="previous">ARM-Regs</a>, Up: <a href="#ARM-Syntax" accesskey="u" rel="up">ARM Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="ARM-relocation-generation"></a> +<h4 class="subsubsection">9.4.2.4 ARM relocation generation</h4> + +<a name="index-data-relocations_002c-ARM"></a> +<a name="index-ARM-data-relocations"></a> +<p>Specific data relocations can be generated by putting the relocation name +in parentheses after the symbol name. For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> .word foo(TARGET1) +</pre></div> + +<p>This will generate an ‘<samp>R_ARM_TARGET1</samp>’ relocation against the symbol +<var>foo</var>. +The following relocations are supported: +<code>GOT</code>, +<code>GOTOFF</code>, +<code>TARGET1</code>, +<code>TARGET2</code>, +<code>SBREL</code>, +<code>TLSGD</code>, +<code>TLSLDM</code>, +<code>TLSLDO</code>, +<code>TLSDESC</code>, +<code>TLSCALL</code>, +<code>GOTTPOFF</code>, +<code>GOT_PREL</code> +and +<code>TPOFF</code>. +</p> +<p>For compatibility with older toolchains the assembler also accepts +<code>(PLT)</code> after branch targets. On legacy targets this will +generate the deprecated ‘<samp>R_ARM_PLT32</samp>’ relocation. On EABI +targets it will encode either the ‘<samp>R_ARM_CALL</samp>’ or +‘<samp>R_ARM_JUMP24</samp>’ relocation, as appropriate. +</p> +<a name="index-MOVW-and-MOVT-relocations_002c-ARM"></a> +<p>Relocations for ‘<samp>MOVW</samp>’ and ‘<samp>MOVT</samp>’ instructions can be generated +by prefixing the value with ‘<samp>#:lower16:</samp>’ and ‘<samp>#:upper16</samp>’ +respectively. For example to load the 32-bit address of foo into r0: +</p> +<div class="smallexample"> +<pre class="smallexample"> MOVW r0, #:lower16:foo + MOVT r0, #:upper16:foo +</pre></div> + +<p>Relocations ‘<samp>R_ARM_THM_ALU_ABS_G0_NC</samp>’, ‘<samp>R_ARM_THM_ALU_ABS_G1_NC</samp>’, +‘<samp>R_ARM_THM_ALU_ABS_G2_NC</samp>’ and ‘<samp>R_ARM_THM_ALU_ABS_G3_NC</samp>’ can be +generated by prefixing the value with ‘<samp>#:lower0_7:#</samp>’, +‘<samp>#:lower8_15:#</samp>’, ‘<samp>#:upper0_7:#</samp>’ and ‘<samp>#:upper8_15:#</samp>’ +respectively. For example to load the 32-bit address of foo into r0: +</p> +<div class="smallexample"> +<pre class="smallexample"> MOVS r0, #:upper8_15:#foo + LSLS r0, r0, #8 + ADDS r0, #:upper0_7:#foo + LSLS r0, r0, #8 + ADDS r0, #:lower8_15:#foo + LSLS r0, r0, #8 + ADDS r0, #:lower0_7:#foo +</pre></div> + +<hr> +<a name="ARM_002dNeon_002dAlignment"></a> +<div class="header"> +<p> +Previous: <a href="#ARM_002dRelocations" accesskey="p" rel="previous">ARM-Relocations</a>, Up: <a href="#ARM-Syntax" accesskey="u" rel="up">ARM Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="NEON-Alignment-Specifiers"></a> +<h4 class="subsubsection">9.4.2.5 NEON Alignment Specifiers</h4> + +<a name="index-alignment-for-NEON-instructions"></a> +<p>Some NEON load/store instructions allow an optional address +alignment qualifier. +The ARM documentation specifies that this is indicated by +‘<samp>@ <var>align</var></samp>’. However GAS already interprets +the ‘<samp>@</samp>’ character as a "line comment" start, +so ‘<samp>: <var>align</var></samp>’ is used instead. For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> vld1.8 {q0}, [r0, :128] +</pre></div> + +<hr> +<a name="ARM-Floating-Point"></a> +<div class="header"> +<p> +Next: <a href="#ARM-Directives" accesskey="n" rel="next">ARM Directives</a>, Previous: <a href="#ARM-Syntax" accesskey="p" rel="previous">ARM Syntax</a>, Up: <a href="#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-2"></a> +<h4 class="subsection">9.4.3 Floating Point</h4> + +<a name="index-floating-point_002c-ARM-_0028IEEE_0029"></a> +<a name="index-ARM-floating-point-_0028IEEE_0029"></a> +<p>The ARM family uses <small>IEEE</small> floating-point numbers. +</p> +<hr> +<a name="ARM-Directives"></a> +<div class="header"> +<p> +Next: <a href="#ARM-Opcodes" accesskey="n" rel="next">ARM Opcodes</a>, Previous: <a href="#ARM-Floating-Point" accesskey="p" rel="previous">ARM Floating Point</a>, Up: <a href="#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="ARM-Machine-Directives"></a> +<h4 class="subsection">9.4.4 ARM Machine Directives</h4> + +<a name="index-machine-directives_002c-ARM"></a> +<a name="index-ARM-machine-directives"></a> +<dl compact="compact"> +<dd> + + +<a name="index-_002ealign-directive_002c-ARM"></a> +</dd> +<dt><code>.align <var>expression</var> [, <var>expression</var>]</code></dt> +<dd><p>This is the generic <var>.align</var> directive. For the ARM however if the +first argument is zero (ie no alignment is needed) the assembler will +behave as if the argument had been 2 (ie pad to the next four byte +boundary). This is for compatibility with ARM’s own assembler. +</p> +<a name="index-_002earch-directive_002c-ARM"></a> +</dd> +<dt><code>.arch <var>name</var></code></dt> +<dd><p>Select the target architecture. Valid values for <var>name</var> are the same as +for the <samp>-march</samp> command-line option without the instruction set +extension. +</p> +<p>Specifying <code>.arch</code> clears any previously selected architecture +extensions. +</p> +<a name="index-_002earch_005fextension-directive_002c-ARM"></a> +</dd> +<dt><code>.arch_extension <var>name</var></code></dt> +<dd><p>Add or remove an architecture extension to the target architecture. Valid +values for <var>name</var> are the same as those accepted as architectural +extensions by the <samp>-mcpu</samp> and <samp>-march</samp> command-line options. +</p> +<p><code>.arch_extension</code> may be used multiple times to add or remove extensions +incrementally to the architecture being compiled for. +</p> +<a name="index-_002earm-directive_002c-ARM"></a> +</dd> +<dt><code>.arm</code></dt> +<dd><p>This performs the same action as <var>.code 32</var>. +</p> + +<a name="index-_002ebss-directive_002c-ARM"></a> +</dd> +<dt><code>.bss</code></dt> +<dd><p>This directive switches to the <code>.bss</code> section. +</p> + +<a name="index-_002ecantunwind-directive_002c-ARM"></a> +</dd> +<dt><code>.cantunwind</code></dt> +<dd><p>Prevents unwinding through the current function. No personality routine +or exception table data is required or permitted. +</p> +<a name="index-_002ecode-directive_002c-ARM"></a> +</dd> +<dt><code>.code <code>[16|32]</code></code></dt> +<dd><p>This directive selects the instruction set being generated. The value 16 +selects Thumb, with the value 32 selecting ARM. +</p> +<a name="index-_002ecpu-directive_002c-ARM"></a> +</dd> +<dt><code>.cpu <var>name</var></code></dt> +<dd><p>Select the target processor. Valid values for <var>name</var> are the same as +for the <samp>-mcpu</samp> command-line option without the instruction set +extension. +</p> +<p>Specifying <code>.cpu</code> clears any previously selected architecture +extensions. +</p> + +<a name="index-_002edn-and-_002eqn-directives_002c-ARM"></a> +</dd> +<dt><code><var>name</var> .dn <var>register name</var> [<var>.type</var>] [[<var>index</var>]]</code></dt> +<dt><code><var>name</var> .qn <var>register name</var> [<var>.type</var>] [[<var>index</var>]]</code></dt> +<dd> +<p>The <code>dn</code> and <code>qn</code> directives are used to create typed +and/or indexed register aliases for use in Advanced SIMD Extension +(Neon) instructions. The former should be used to create aliases +of double-precision registers, and the latter to create aliases of +quad-precision registers. +</p> +<p>If these directives are used to create typed aliases, those aliases can +be used in Neon instructions instead of writing types after the mnemonic +or after each operand. For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> x .dn d2.f32 + y .dn d3.f32 + z .dn d4.f32[1] + vmul x,y,z +</pre></div> + +<p>This is equivalent to writing the following: +</p> +<div class="smallexample"> +<pre class="smallexample"> vmul.f32 d2,d3,d4[1] +</pre></div> + +<p>Aliases created using <code>dn</code> or <code>qn</code> can be destroyed using +<code>unreq</code>. +</p> + +<a name="index-_002eeabi_005fattribute-directive_002c-ARM"></a> +</dd> +<dt><code>.eabi_attribute <var>tag</var>, <var>value</var></code></dt> +<dd><p>Set the EABI object attribute <var>tag</var> to <var>value</var>. +</p> +<p>The <var>tag</var> is either an attribute number, or one of the following: +<code>Tag_CPU_raw_name</code>, <code>Tag_CPU_name</code>, <code>Tag_CPU_arch</code>, +<code>Tag_CPU_arch_profile</code>, <code>Tag_ARM_ISA_use</code>, +<code>Tag_THUMB_ISA_use</code>, <code>Tag_FP_arch</code>, <code>Tag_WMMX_arch</code>, +<code>Tag_Advanced_SIMD_arch</code>, <code>Tag_MVE_arch</code>, <code>Tag_PCS_config</code>, +<code>Tag_ABI_PCS_R9_use</code>, <code>Tag_ABI_PCS_RW_data</code>, +<code>Tag_ABI_PCS_RO_data</code>, <code>Tag_ABI_PCS_GOT_use</code>, +<code>Tag_ABI_PCS_wchar_t</code>, <code>Tag_ABI_FP_rounding</code>, +<code>Tag_ABI_FP_denormal</code>, <code>Tag_ABI_FP_exceptions</code>, +<code>Tag_ABI_FP_user_exceptions</code>, <code>Tag_ABI_FP_number_model</code>, +<code>Tag_ABI_align_needed</code>, <code>Tag_ABI_align_preserved</code>, +<code>Tag_ABI_enum_size</code>, <code>Tag_ABI_HardFP_use</code>, +<code>Tag_ABI_VFP_args</code>, <code>Tag_ABI_WMMX_args</code>, +<code>Tag_ABI_optimization_goals</code>, <code>Tag_ABI_FP_optimization_goals</code>, +<code>Tag_compatibility</code>, <code>Tag_CPU_unaligned_access</code>, +<code>Tag_FP_HP_extension</code>, <code>Tag_ABI_FP_16bit_format</code>, +<code>Tag_MPextension_use</code>, <code>Tag_DIV_use</code>, +<code>Tag_nodefaults</code>, <code>Tag_also_compatible_with</code>, +<code>Tag_conformance</code>, <code>Tag_T2EE_use</code>, +<code>Tag_Virtualization_use</code> +</p> +<p>The <var>value</var> is either a <code>number</code>, <code>"string"</code>, or +<code>number, "string"</code> depending on the tag. +</p> +<p>Note - the following legacy values are also accepted by <var>tag</var>: +<code>Tag_VFP_arch</code>, <code>Tag_ABI_align8_needed</code>, +<code>Tag_ABI_align8_preserved</code>, <code>Tag_VFP_HP_extension</code>, +</p> +<a name="index-_002eeven-directive_002c-ARM"></a> +</dd> +<dt><code>.even</code></dt> +<dd><p>This directive aligns to an even-numbered address. +</p> +<a name="index-_002eextend-directive_002c-ARM"></a> +<a name="index-_002eldouble-directive_002c-ARM"></a> +</dd> +<dt><code>.extend <var>expression</var> [, <var>expression</var>]*</code></dt> +<dt><code>.ldouble <var>expression</var> [, <var>expression</var>]*</code></dt> +<dd><p>These directives write 12byte long double floating-point values to the +output section. These are not compatible with current ARM processors +or ABIs. +</p> + +<a name="index-_002efloat16-directive_002c-ARM"></a> +</dd> +<dt><code>.float16 <var>value [,...,value_n]</var></code></dt> +<dd><p>Place the half precision floating point representation of one or more +floating-point values into the current section. The exact format of the +encoding is specified by <code>.float16_format</code>. If the format has not +been explicitly set yet (either via the <code>.float16_format</code> directive or +the command line option) then the IEEE 754-2008 format is used. +</p> +<a name="index-_002efloat16_005fformat-directive_002c-ARM"></a> +</dd> +<dt><code>.float16_format <var>format</var></code></dt> +<dd><p>Set the format to use when encoding float16 values emitted by +the <code>.float16</code> directive. +Once the format has been set it cannot be changed. +<code>format</code> should be one of the following: <code>ieee</code> (encode in +the IEEE 754-2008 half precision format) or <code>alternative</code> (encode in +the Arm alternative half precision format). +</p> +<a name="arm_005ffnend"></a><a name="index-_002efnend-directive_002c-ARM"></a> +</dd> +<dt><code>.fnend</code></dt> +<dd><p>Marks the end of a function with an unwind table entry. The unwind index +table entry is created when this directive is processed. +</p> +<p>If no personality routine has been specified then standard personality +routine 0 or 1 will be used, depending on the number of unwind opcodes +required. +</p> +<a name="arm_005ffnstart"></a><a name="index-_002efnstart-directive_002c-ARM"></a> +</dd> +<dt><code>.fnstart</code></dt> +<dd><p>Marks the start of a function with an unwind table entry. +</p> +<a name="index-_002eforce_005fthumb-directive_002c-ARM"></a> +</dd> +<dt><code>.force_thumb</code></dt> +<dd><p>This directive forces the selection of Thumb instructions, even if the +target processor does not support those instructions +</p> +<a name="index-_002efpu-directive_002c-ARM"></a> +</dd> +<dt><code>.fpu <var>name</var></code></dt> +<dd><p>Select the floating-point unit to assemble for. Valid values for <var>name</var> +are the same as for the <samp>-mfpu</samp> command-line option. +</p> + +<a name="index-_002ehandlerdata-directive_002c-ARM"></a> +</dd> +<dt><code>.handlerdata</code></dt> +<dd><p>Marks the end of the current function, and the start of the exception table +entry for that function. Anything between this directive and the +<code>.fnend</code> directive will be added to the exception table entry. +</p> +<p>Must be preceded by a <code>.personality</code> or <code>.personalityindex</code> +directive. +</p> + +<a name="index-_002einst-directive_002c-ARM"></a> +</dd> +<dt><code>.inst <var>opcode</var> [ , … ]</code></dt> +<dt><code>.inst.n <var>opcode</var> [ , … ]</code></dt> +<dt><code>.inst.w <var>opcode</var> [ , … ]</code></dt> +<dd><p>Generates the instruction corresponding to the numerical value <var>opcode</var>. +<code>.inst.n</code> and <code>.inst.w</code> allow the Thumb instruction size to be +specified explicitly, overriding the normal encoding rules. +</p> + +</dd> +<dt><code>.ldouble <var>expression</var> [, <var>expression</var>]*</code></dt> +<dd><p>See <code>.extend</code>. +</p> +<a name="index-_002eltorg-directive_002c-ARM"></a> +</dd> +<dt><code>.ltorg</code></dt> +<dd><p>This directive causes the current contents of the literal pool to be +dumped into the current section (which is assumed to be the .text +section) at the current location (aligned to a word boundary). +<code>GAS</code> maintains a separate literal pool for each section and each +sub-section. The <code>.ltorg</code> directive will only affect the literal +pool of the current section and sub-section. At the end of assembly +all remaining, un-empty literal pools will automatically be dumped. +</p> +<p>Note - older versions of <code>GAS</code> would dump the current literal +pool any time a section change occurred. This is no longer done, since +it prevents accurate control of the placement of literal pools. +</p> + +<a name="index-_002emovsp-directive_002c-ARM"></a> +</dd> +<dt><code>.movsp <var>reg</var> [, #<var>offset</var>]</code></dt> +<dd><p>Tell the unwinder that <var>reg</var> contains an offset from the current +stack pointer. If <var>offset</var> is not specified then it is assumed to be +zero. +</p> + +<a name="index-_002eobject_005farch-directive_002c-ARM"></a> +</dd> +<dt><code>.object_arch <var>name</var></code></dt> +<dd><p>Override the architecture recorded in the EABI object attribute section. +Valid values for <var>name</var> are the same as for the <code>.arch</code> directive. +Typically this is useful when code uses runtime detection of CPU features. +</p> + +<a name="index-_002epacked-directive_002c-ARM"></a> +</dd> +<dt><code>.packed <var>expression</var> [, <var>expression</var>]*</code></dt> +<dd><p>This directive writes 12-byte packed floating-point values to the +output section. These are not compatible with current ARM processors +or ABIs. +</p> +<a name="arm_005fpacspval"></a><a name="index-_002epacspval-directive_002c-ARM"></a> +</dd> +<dt><code>.pacspval</code></dt> +<dd><p>Generate unwinder annotations to use effective vsp as modifier in PAC +validation. +</p> +<a name="arm_005fpad"></a><a name="index-_002epad-directive_002c-ARM"></a> +</dd> +<dt><code>.pad #<var>count</var></code></dt> +<dd><p>Generate unwinder annotations for a stack adjustment of <var>count</var> bytes. +A positive value indicates the function prologue allocated stack space by +decrementing the stack pointer. +</p> +<a name="index-_002epersonality-directive_002c-ARM"></a> +</dd> +<dt><code>.personality <var>name</var></code></dt> +<dd><p>Sets the personality routine for the current function to <var>name</var>. +</p> +<a name="index-_002epersonalityindex-directive_002c-ARM"></a> +</dd> +<dt><code>.personalityindex <var>index</var></code></dt> +<dd><p>Sets the personality routine for the current function to the EABI standard +routine number <var>index</var> +</p> +<a name="index-_002epool-directive_002c-ARM"></a> +</dd> +<dt><code>.pool</code></dt> +<dd><p>This is a synonym for .ltorg. +</p> + +<a name="index-_002ereq-directive_002c-ARM"></a> +</dd> +<dt><code><var>name</var> .req <var>register name</var></code></dt> +<dd><p>This creates an alias for <var>register name</var> called <var>name</var>. For +example: +</p> +<div class="smallexample"> +<pre class="smallexample"> foo .req r0 +</pre></div> + + +<a name="arm_005fsave"></a><a name="index-_002esave-directive_002c-ARM"></a> +</dd> +<dt><code>.save <var>reglist</var></code></dt> +<dd><p>Generate unwinder annotations to restore the registers in <var>reglist</var>. +The format of <var>reglist</var> is the same as the corresponding store-multiple +instruction. +</p> +<div class="smallexample"> +<pre class="smallexample"><em>core registers</em> +</pre><pre class="smallexample"> .save {r4, r5, r6, lr} + stmfd sp!, {r4, r5, r6, lr} +</pre><pre class="smallexample"><em>FPA registers</em> +</pre><pre class="smallexample"> .save f4, 2 + sfmfd f4, 2, [sp]! +</pre><pre class="smallexample"><em>VFP registers</em> +</pre><pre class="smallexample"> .save {d8, d9, d10} + fstmdx sp!, {d8, d9, d10} +</pre><pre class="smallexample"><em>iWMMXt registers</em> +</pre><pre class="smallexample"> .save {wr10, wr11} + wstrd wr11, [sp, #-8]! + wstrd wr10, [sp, #-8]! +or + .save wr11 + wstrd wr11, [sp, #-8]! + .save wr10 + wstrd wr10, [sp, #-8]! +</pre></div> + +<a name="arm_005fsetfp"></a><a name="index-_002esetfp-directive_002c-ARM"></a> +</dd> +<dt><code>.setfp <var>fpreg</var>, <var>spreg</var> [, #<var>offset</var>]</code></dt> +<dd><p>Make all unwinder annotations relative to a frame pointer. Without this +the unwinder will use offsets from the stack pointer. +</p> +<p>The syntax of this directive is the same as the <code>add</code> or <code>mov</code> +instruction used to set the frame pointer. <var>spreg</var> must be either +<code>sp</code> or mentioned in a previous <code>.movsp</code> directive. +</p> +<div class="smallexample"> +<pre class="smallexample">.movsp ip +mov ip, sp +… +.setfp fp, ip, #4 +add fp, ip, #4 +</pre></div> + +<a name="index-_002esecrel32-directive_002c-ARM"></a> +</dd> +<dt><code>.secrel32 <var>expression</var> [, <var>expression</var>]*</code></dt> +<dd><p>This directive emits relocations that evaluate to the section-relative +offset of each expression’s symbol. This directive is only supported +for PE targets. +</p> +<a name="index-_002esyntax-directive_002c-ARM"></a> +</dd> +<dt><code>.syntax [<code>unified</code> | <code>divided</code>]</code></dt> +<dd><p>This directive sets the Instruction Set Syntax as described in the +<a href="#ARM_002dInstruction_002dSet">ARM-Instruction-Set</a> section. +</p> + +<a name="index-_002ethumb-directive_002c-ARM"></a> +</dd> +<dt><code>.thumb</code></dt> +<dd><p>This performs the same action as <var>.code 16</var>. +</p> +<a name="index-_002ethumb_005ffunc-directive_002c-ARM"></a> +</dd> +<dt><code>.thumb_func</code></dt> +<dd><p>This directive specifies that the following symbol is the name of a +Thumb encoded function. This information is necessary in order to allow +the assembler and linker to generate correct code for interworking +between Arm and Thumb instructions and should be used even if +interworking is not going to be performed. The presence of this +directive also implies <code>.thumb</code> +</p> +<p>This directive is not necessary when generating EABI objects. On these +targets the encoding is implicit when generating Thumb code. +</p> +<a name="index-_002ethumb_005fset-directive_002c-ARM"></a> +</dd> +<dt><code>.thumb_set</code></dt> +<dd><p>This performs the equivalent of a <code>.set</code> directive in that it +creates a symbol which is an alias for another symbol (possibly not yet +defined). This directive also has the added property in that it marks +the aliased symbol as being a thumb function entry point, in the same +way that the <code>.thumb_func</code> directive does. +</p> +<a name="index-_002etlsdescseq-directive_002c-ARM"></a> +</dd> +<dt><code>.tlsdescseq <var>tls-variable</var></code></dt> +<dd><p>This directive is used to annotate parts of an inlined TLS descriptor +trampoline. Normally the trampoline is provided by the linker, and +this directive is not needed. +</p> + +<a name="index-_002eunreq-directive_002c-ARM"></a> +</dd> +<dt><code>.unreq <var>alias-name</var></code></dt> +<dd><p>This undefines a register alias which was previously defined using the +<code>req</code>, <code>dn</code> or <code>qn</code> directives. For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> foo .req r0 + .unreq foo +</pre></div> + +<p>An error occurs if the name is undefined. Note - this pseudo op can +be used to delete builtin in register name aliases (eg ’r0’). This +should only be done if it is really necessary. +</p> +<a name="index-_002eunwind_005fraw-directive_002c-ARM"></a> +</dd> +<dt><code>.unwind_raw <var>offset</var>, <var>byte1</var>, …</code></dt> +<dd><p>Insert one of more arbitrary unwind opcode bytes, which are known to adjust +the stack pointer by <var>offset</var> bytes. +</p> +<p>For example <code>.unwind_raw 4, 0xb1, 0x01</code> is equivalent to +<code>.save {r0}</code> +</p> + +<a name="index-_002evsave-directive_002c-ARM"></a> +</dd> +<dt><code>.vsave <var>vfp-reglist</var></code></dt> +<dd><p>Generate unwinder annotations to restore the VFP registers in <var>vfp-reglist</var> +using FLDMD. Also works for VFPv3 registers +that are to be restored using VLDM. +The format of <var>vfp-reglist</var> is the same as the corresponding store-multiple +instruction. +</p> +<div class="smallexample"> +<pre class="smallexample"><em>VFP registers</em> +</pre><pre class="smallexample"> .vsave {d8, d9, d10} + fstmdd sp!, {d8, d9, d10} +</pre><pre class="smallexample"><em>VFPv3 registers</em> +</pre><pre class="smallexample"> .vsave {d15, d16, d17} + vstm sp!, {d15, d16, d17} +</pre></div> + +<p>Since FLDMX and FSTMX are now deprecated, this directive should be +used in favour of <code>.save</code> for saving VFP registers for ARMv6 and above. +</p> + +</dd> +</dl> + +<hr> +<a name="ARM-Opcodes"></a> +<div class="header"> +<p> +Next: <a href="#ARM-Mapping-Symbols" accesskey="n" rel="next">ARM Mapping Symbols</a>, Previous: <a href="#ARM-Directives" accesskey="p" rel="previous">ARM Directives</a>, Up: <a href="#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-3"></a> +<h4 class="subsection">9.4.5 Opcodes</h4> + +<a name="index-ARM-opcodes"></a> +<a name="index-opcodes-for-ARM"></a> +<p><code>as</code> implements all the standard ARM opcodes. It also +implements several pseudo opcodes, including several synthetic load +instructions. +</p> +<dl compact="compact"> +<dd> +<a name="index-NOP-pseudo-op_002c-ARM"></a> +</dd> +<dt><code>NOP</code></dt> +<dd><div class="smallexample"> +<pre class="smallexample"> nop +</pre></div> + +<p>This pseudo op will always evaluate to a legal ARM instruction that does +nothing. Currently it will evaluate to MOV r0, r0. +</p> +<a name="index-LDR-reg_002c_003d_003clabel_003e-pseudo-op_002c-ARM"></a> +</dd> +<dt><code>LDR</code></dt> +<dd><div class="smallexample"> +<pre class="smallexample"> ldr <register> , = <expression> +</pre></div> + +<p>If expression evaluates to a numeric constant then a MOV or MVN +instruction will be used in place of the LDR instruction, if the +constant can be generated by either of these instructions. Otherwise +the constant will be placed into the nearest literal pool (if it not +already there) and a PC relative LDR instruction will be generated. +</p> +<a name="index-ADR-reg_002c_003clabel_003e-pseudo-op_002c-ARM"></a> +</dd> +<dt><code>ADR</code></dt> +<dd><div class="smallexample"> +<pre class="smallexample"> adr <register> <label> +</pre></div> + +<p>This instruction will load the address of <var>label</var> into the indicated +register. The instruction will evaluate to a PC relative ADD or SUB +instruction depending upon where the label is located. If the label is +out of range, or if it is not defined in the same file (and section) as +the ADR instruction, then an error will be generated. This instruction +will not make use of the literal pool. +</p> +<p>If <var>label</var> is a thumb function symbol, and thumb interworking has +been enabled via the <samp>-mthumb-interwork</samp> option then the bottom +bit of the value stored into <var>register</var> will be set. This allows +the following sequence to work as expected: +</p> +<div class="smallexample"> +<pre class="smallexample"> adr r0, thumb_function + blx r0 +</pre></div> + +<a name="index-ADRL-reg_002c_003clabel_003e-pseudo-op_002c-ARM"></a> +</dd> +<dt><code>ADRL</code></dt> +<dd><div class="smallexample"> +<pre class="smallexample"> adrl <register> <label> +</pre></div> + +<p>This instruction will load the address of <var>label</var> into the indicated +register. The instruction will evaluate to one or two PC relative ADD +or SUB instructions depending upon where the label is located. If a +second instruction is not needed a NOP instruction will be generated in +its place, so that this instruction is always 8 bytes long. +</p> +<p>If the label is out of range, or if it is not defined in the same file +(and section) as the ADRL instruction, then an error will be generated. +This instruction will not make use of the literal pool. +</p> +<p>If <var>label</var> is a thumb function symbol, and thumb interworking has +been enabled via the <samp>-mthumb-interwork</samp> option then the bottom +bit of the value stored into <var>register</var> will be set. +</p> +</dd> +</dl> + +<p>For information on the ARM or Thumb instruction sets, see <cite>ARM +Software Development Toolkit Reference Manual</cite>, Advanced RISC Machines +Ltd. +</p> +<hr> +<a name="ARM-Mapping-Symbols"></a> +<div class="header"> +<p> +Next: <a href="#ARM-Unwinding-Tutorial" accesskey="n" rel="next">ARM Unwinding Tutorial</a>, Previous: <a href="#ARM-Opcodes" accesskey="p" rel="previous">ARM Opcodes</a>, Up: <a href="#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Mapping-Symbols-1"></a> +<h4 class="subsection">9.4.6 Mapping Symbols</h4> + +<p>The ARM ELF specification requires that special symbols be inserted +into object files to mark certain features: +</p> +<dl compact="compact"> +<dd> +<a name="index-_0024a"></a> +</dd> +<dt><code>$a</code></dt> +<dd><p>At the start of a region of code containing ARM instructions. +</p> +<a name="index-_0024t"></a> +</dd> +<dt><code>$t</code></dt> +<dd><p>At the start of a region of code containing THUMB instructions. +</p> +<a name="index-_0024d-1"></a> +</dd> +<dt><code>$d</code></dt> +<dd><p>At the start of a region of data. +</p> +</dd> +</dl> + +<p>The assembler will automatically insert these symbols for you - there +is no need to code them yourself. Support for tagging symbols ($b, +$f, $p and $m) which is also mentioned in the current ARM ELF +specification is not implemented. This is because they have been +dropped from the new EABI and so tools cannot rely upon their +presence. +</p> +<hr> +<a name="ARM-Unwinding-Tutorial"></a> +<div class="header"> +<p> +Previous: <a href="#ARM-Mapping-Symbols" accesskey="p" rel="previous">ARM Mapping Symbols</a>, Up: <a href="#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Unwinding"></a> +<h4 class="subsection">9.4.7 Unwinding</h4> + +<p>The ABI for the ARM Architecture specifies a standard format for +exception unwind information. This information is used when an +exception is thrown to determine where control should be transferred. +In particular, the unwind information is used to determine which +function called the function that threw the exception, and which +function called that one, and so forth. This information is also used +to restore the values of callee-saved registers in the function +catching the exception. +</p> +<p>If you are writing functions in assembly code, and those functions +call other functions that throw exceptions, you must use assembly +pseudo ops to ensure that appropriate exception unwind information is +generated. Otherwise, if one of the functions called by your assembly +code throws an exception, the run-time library will be unable to +unwind the stack through your assembly code and your program will not +behave correctly. +</p> +<p>To illustrate the use of these pseudo ops, we will examine the code +that G++ generates for the following C++ input: +</p> +<pre class="verbatim">void callee (int *); + +int +caller () +{ + int i; + callee (&i); + return i; +} +</pre> +<p>This example does not show how to throw or catch an exception from +assembly code. That is a much more complex operation and should +always be done in a high-level language, such as C++, that directly +supports exceptions. +</p> +<p>The code generated by one particular version of G++ when compiling the +example above is: +</p> +<pre class="verbatim">_Z6callerv: + .fnstart +.LFB2: + @ Function supports interworking. + @ args = 0, pretend = 0, frame = 8 + @ frame_needed = 1, uses_anonymous_args = 0 + stmfd sp!, {fp, lr} + .save {fp, lr} +.LCFI0: + .setfp fp, sp, #4 + add fp, sp, #4 +.LCFI1: + .pad #8 + sub sp, sp, #8 +.LCFI2: + sub r3, fp, #8 + mov r0, r3 + bl _Z6calleePi + ldr r3, [fp, #-8] + mov r0, r3 + sub sp, fp, #4 + ldmfd sp!, {fp, lr} + bx lr +.LFE2: + .fnend +</pre> +<p>Of course, the sequence of instructions varies based on the options +you pass to GCC and on the version of GCC in use. The exact +instructions are not important since we are focusing on the pseudo ops +that are used to generate unwind information. +</p> +<p>An important assumption made by the unwinder is that the stack frame +does not change during the body of the function. In particular, since +we assume that the assembly code does not itself throw an exception, +the only point where an exception can be thrown is from a call, such +as the <code>bl</code> instruction above. At each call site, the same saved +registers (including <code>lr</code>, which indicates the return address) +must be located in the same locations relative to the frame pointer. +</p> +<p>The <code>.fnstart</code> (see <a href="#arm_005ffnstart">.fnstart pseudo op</a>) pseudo +op appears immediately before the first instruction of the function +while the <code>.fnend</code> (see <a href="#arm_005ffnend">.fnend pseudo op</a>) pseudo +op appears immediately after the last instruction of the function. +These pseudo ops specify the range of the function. +</p> +<p>Only the order of the other pseudos ops (e.g., <code>.setfp</code> or +<code>.pad</code>) matters; their exact locations are irrelevant. In the +example above, the compiler emits the pseudo ops with particular +instructions. That makes it easier to understand the code, but it is +not required for correctness. It would work just as well to emit all +of the pseudo ops other than <code>.fnend</code> in the same order, but +immediately after <code>.fnstart</code>. +</p> +<p>The <code>.save</code> (see <a href="#arm_005fsave">.save pseudo op</a>) pseudo op +indicates registers that have been saved to the stack so that they can +be restored before the function returns. The argument to the +<code>.save</code> pseudo op is a list of registers to save. If a register +is “callee-saved” (as specified by the ABI) and is modified by the +function you are writing, then your code must save the value before it +is modified and restore the original value before the function +returns. If an exception is thrown, the run-time library restores the +values of these registers from their locations on the stack before +returning control to the exception handler. (Of course, if an +exception is not thrown, the function that contains the <code>.save</code> +pseudo op restores these registers in the function epilogue, as is +done with the <code>ldmfd</code> instruction above.) +</p> +<p>You do not have to save callee-saved registers at the very beginning +of the function and you do not need to use the <code>.save</code> pseudo op +immediately following the point at which the registers are saved. +However, if you modify a callee-saved register, you must save it on +the stack before modifying it and before calling any functions which +might throw an exception. And, you must use the <code>.save</code> pseudo +op to indicate that you have done so. +</p> +<p>The <code>.pad</code> (see <a href="#arm_005fpad">.pad</a>) pseudo op indicates a +modification of the stack pointer that does not save any registers. +The argument is the number of bytes (in decimal) that are subtracted +from the stack pointer. (On ARM CPUs, the stack grows downwards, so +subtracting from the stack pointer increases the size of the stack.) +</p> +<p>The <code>.setfp</code> (see <a href="#arm_005fsetfp">.setfp pseudo op</a>) pseudo op +indicates the register that contains the frame pointer. The first +argument is the register that is set, which is typically <code>fp</code>. +The second argument indicates the register from which the frame +pointer takes its value. The third argument, if present, is the value +(in decimal) added to the register specified by the second argument to +compute the value of the frame pointer. You should not modify the +frame pointer in the body of the function. +</p> +<p>If you do not use a frame pointer, then you should not use the +<code>.setfp</code> pseudo op. If you do not use a frame pointer, then you +should avoid modifying the stack pointer outside of the function +prologue. Otherwise, the run-time library will be unable to find +saved registers when it is unwinding the stack. +</p> +<p>The pseudo ops described above are sufficient for writing assembly +code that calls functions which may throw exceptions. If you need to +know more about the object-file format used to represent unwind +information, you may consult the <cite>Exception Handling ABI for the +ARM Architecture</cite> available from <a href="http://infocenter.arm.com">http://infocenter.arm.com</a>. +</p> + + +<hr> +<a name="AVR_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Blackfin_002dDependent" accesskey="n" rel="next">Blackfin-Dependent</a>, Previous: <a href="#ARM_002dDependent" accesskey="p" rel="previous">ARM-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="AVR-Dependent-Features"></a> +<h3 class="section">9.5 AVR Dependent Features</h3> + + +<a name="index-AVR-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#AVR-Options" accesskey="1">AVR Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#AVR-Syntax" accesskey="2">AVR Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#AVR-Opcodes" accesskey="3">AVR Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +<tr><td align="left" valign="top">• <a href="#AVR-Pseudo-Instructions" accesskey="4">AVR Pseudo Instructions</a>:</td><td> </td><td align="left" valign="top">Pseudo Instructions +</td></tr> +</table> + +<hr> +<a name="AVR-Options"></a> +<div class="header"> +<p> +Next: <a href="#AVR-Syntax" accesskey="n" rel="next">AVR Syntax</a>, Up: <a href="#AVR_002dDependent" accesskey="u" rel="up">AVR-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-4"></a> +<h4 class="subsection">9.5.1 Options</h4> +<a name="index-AVR-options-_0028none_0029"></a> +<a name="index-options-for-AVR-_0028none_0029"></a> + +<dl compact="compact"> +<dd> +<a name="index-_002dmmcu_003d-command_002dline-option_002c-AVR"></a> +</dd> +<dt><code>-mmcu=<var>mcu</var></code></dt> +<dd><p>Specify ATMEL AVR instruction set or MCU type. +</p> +<p>Instruction set avr1 is for the minimal AVR core, not supported by the C +compiler, only for assembler programs (MCU types: at90s1200, +attiny11, attiny12, attiny15, attiny28). +</p> +<p>Instruction set avr2 (default) is for the classic AVR core with up to +8K program memory space (MCU types: at90s2313, at90s2323, at90s2333, at90s2343, +attiny22, attiny26, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534, +at90s8535). +</p> +<p>Instruction set avr25 is for the classic AVR core with up to 8K program memory +space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313, +attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84, +attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461, +attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, +attiny828, at86rf401, ata6289, ata5272). +</p> +<p>Instruction set avr3 is for the classic AVR core with up to 128K program +memory space (MCU types: at43usb355, at76c711). +</p> +<p>Instruction set avr31 is for the classic AVR core with exactly 128K program +memory space (MCU types: atmega103, at43usb320). +</p> +<p>Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP +instructions (MCU types: attiny167, attiny1634, at90usb82, at90usb162, +atmega8u2, atmega16u2, atmega32u2, ata5505). +</p> +<p>Instruction set avr4 is for the enhanced AVR core with up to 8K program +memory space (MCU types: atmega48, atmega48a, atmega48pa, atmega48p, atmega8, +atmega8a, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, +atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, +ata6285, ata6286). +</p> +<p>Instruction set avr5 is for the enhanced AVR core with up to 128K program +memory space (MCU types: at90pwm161, atmega16, atmega16a, atmega161, atmega162, +atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, +atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, +atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega323, atmega324a, +atmega324p, atmega324pa, atmega325, atmega325a, atmega32, atmega32a, atmega323, +atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, +atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, +atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, +atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, +atmega64rfr2, atmega644rfr2, atmega640, atmega644, atmega644a, atmega644p, +atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, +atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, +atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, +atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, at90can64, at90pwm161, +at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, +atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, +at90scr100, ata5790, ata5795). +</p> +<p>Instruction set avr51 is for the enhanced AVR core with exactly 128K +program memory space (MCU types: atmega128, atmega128a, atmega1280, +atmega1281, atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, +atmega1284rfr2, at90can128, at90usb1286, at90usb1287, m3000). +</p> +<p>Instruction set avr6 is for the enhanced AVR core with a 3-byte PC +(MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). +</p> +<p>Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K +program memory space and less than 64K data space (MCU types: +atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, +atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5, +atxmega8e5, atxmega32e5, atxmega32x1). +</p> +<p>Instruction set avrxmega3 is for the XMEGA AVR core with up to 64K +of combined program memory and RAM, and with program memory +visible in the RAM address space (MCU types: +attiny212, attiny214, attiny412, attiny414, attiny416, attiny417, +attiny814, attiny816, attiny817, attiny1614, attiny1616, attiny1617, +attiny3214, attiny3216, attiny3217). +</p> +<p>Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K +program memory space and less than 64K data space (MCU types: +atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, +atxmega64c3, atxmega64d3, atxmega64d4). +</p> +<p>Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K +program memory space and greater than 64K data space (MCU types: +atxmega64a1, atxmega64a1u). +</p> +<p>Instruction set avrxmega6 is for the XMEGA AVR core with larger than +64K program memory space and less than 64K data space (MCU types: +atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4, +atxmega192a3, atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3, +atxmega192d3, atxmega256a3, atxmega256a3u, atxmega256a3b, +atxmega256a3bu, atxmega256c3, atxmega256d3, atxmega384c3, +atxmega256d3). +</p> +<p>Instruction set avrxmega7 is for the XMEGA AVR core with larger than +64K program memory space and greater than 64K data space (MCU types: +atxmega128a1, atxmega128a1u, atxmega128a4u). +</p> +<p>Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 +microcontrollers. +</p> +<a name="index-_002dmall_002dopcodes-command_002dline-option_002c-AVR"></a> +</dd> +<dt><code>-mall-opcodes</code></dt> +<dd><p>Accept all AVR opcodes, even if not supported by <code>-mmcu</code>. +</p> +<a name="index-_002dmno_002dskip_002dbug-command_002dline-option_002c-AVR"></a> +</dd> +<dt><code>-mno-skip-bug</code></dt> +<dd><p>This option disable warnings for skipping two-word instructions. +</p> +<a name="index-_002dmno_002dwrap-command_002dline-option_002c-AVR"></a> +</dd> +<dt><code>-mno-wrap</code></dt> +<dd><p>This option reject <code>rjmp/rcall</code> instructions with 8K wrap-around. +</p> +<a name="index-_002dmrmw-command_002dline-option_002c-AVR"></a> +</dd> +<dt><code>-mrmw</code></dt> +<dd><p>Accept Read-Modify-Write (<code>XCH,LAC,LAS,LAT</code>) instructions. +</p> +<a name="index-_002dmlink_002drelax-command_002dline-option_002c-AVR"></a> +</dd> +<dt><code>-mlink-relax</code></dt> +<dd><p>Enable support for link-time relaxation. This is now on by default +and this flag no longer has any effect. +</p> +<a name="index-_002dmno_002dlink_002drelax-command_002dline-option_002c-AVR"></a> +</dd> +<dt><code>-mno-link-relax</code></dt> +<dd><p>Disable support for link-time relaxation. The assembler will resolve +relocations when it can, and may be able to better compress some debug +information. +</p> +<a name="index-_002dmgcc_002disr-command_002dline-option_002c-AVR"></a> +</dd> +<dt><code>-mgcc-isr</code></dt> +<dd><p>Enable the <code>__gcc_isr</code> pseudo instruction. +</p> +<a name="index-_002dmno_002ddollar_002dline_002dseparator-command-line-option_002c-AVR"></a> +</dd> +<dt><code>-mno-dollar-line-separator</code></dt> +<dd><p>Do not treat the <code>$</code> character as a line separator character. +This is for languages where <code>$</code> is valid character inside symbol +names. +</p> +</dd> +</dl> + + +<hr> +<a name="AVR-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#AVR-Opcodes" accesskey="n" rel="next">AVR Opcodes</a>, Previous: <a href="#AVR-Options" accesskey="p" rel="previous">AVR Options</a>, Up: <a href="#AVR_002dDependent" accesskey="u" rel="up">AVR-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-6"></a> +<h4 class="subsection">9.5.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#AVR_002dChars" accesskey="1">AVR-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#AVR_002dRegs" accesskey="2">AVR-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#AVR_002dModifiers" accesskey="3">AVR-Modifiers</a>:</td><td> </td><td align="left" valign="top">Relocatable Expression Modifiers +</td></tr> +</table> + +<hr> +<a name="AVR_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#AVR_002dRegs" accesskey="n" rel="next">AVR-Regs</a>, Up: <a href="#AVR-Syntax" accesskey="u" rel="up">AVR Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-4"></a> +<h4 class="subsubsection">9.5.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-AVR"></a> +<a name="index-AVR-line-comment-character"></a> + +<p>The presence of a ‘<samp>;</samp>’ anywhere on a line indicates the start of a +comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line, the whole line +is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-AVR"></a> +<a name="index-statement-separator_002c-AVR"></a> +<a name="index-AVR-line-separator"></a> + +<p>The ‘<samp>$</samp>’ character can be used instead of a newline to separate +statements. Note: the <samp>-mno-dollar-line-separator</samp> option +disables this behaviour. +</p> +<hr> +<a name="AVR_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#AVR_002dModifiers" accesskey="n" rel="next">AVR-Modifiers</a>, Previous: <a href="#AVR_002dChars" accesskey="p" rel="previous">AVR-Chars</a>, Up: <a href="#AVR-Syntax" accesskey="u" rel="up">AVR Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-4"></a> +<h4 class="subsubsection">9.5.2.2 Register Names</h4> + +<a name="index-AVR-register-names"></a> +<a name="index-register-names_002c-AVR"></a> + +<p>The AVR has 32 x 8-bit general purpose working registers ‘<samp>r0</samp>’, +‘<samp>r1</samp>’, ... ‘<samp>r31</samp>’. +Six of the 32 registers can be used as three 16-bit indirect address +register pointers for Data Space addressing. One of the these address +pointers can also be used as an address pointer for look up tables in +Flash program memory. These added function registers are the 16-bit +‘<samp>X</samp>’, ‘<samp>Y</samp>’ and ‘<samp>Z</samp>’ - registers. +</p> +<div class="smallexample"> +<pre class="smallexample">X = <span class="roman">r26:r27</span> +Y = <span class="roman">r28:r29</span> +Z = <span class="roman">r30:r31</span> +</pre></div> + +<hr> +<a name="AVR_002dModifiers"></a> +<div class="header"> +<p> +Previous: <a href="#AVR_002dRegs" accesskey="p" rel="previous">AVR-Regs</a>, Up: <a href="#AVR-Syntax" accesskey="u" rel="up">AVR Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Relocatable-Expression-Modifiers"></a> +<h4 class="subsubsection">9.5.2.3 Relocatable Expression Modifiers</h4> + +<a name="index-AVR-modifiers"></a> +<a name="index-syntax_002c-AVR"></a> + +<p>The assembler supports several modifiers when using relocatable addresses +in AVR instruction operands. The general syntax is the following: +</p> +<div class="smallexample"> +<pre class="smallexample">modifier(relocatable-expression) +</pre></div> + +<dl compact="compact"> +<dd><a name="index-symbol-modifiers"></a> + +</dd> +<dt><code>lo8</code></dt> +<dd> +<p>This modifier allows you to use bits 0 through 7 of +an address expression as an 8 bit relocatable expression. +</p> +</dd> +<dt><code>hi8</code></dt> +<dd> +<p>This modifier allows you to use bits 7 through 15 of an address expression +as an 8 bit relocatable expression. This is useful with, for example, the +AVR ‘<samp>ldi</samp>’ instruction and ‘<samp>lo8</samp>’ modifier. +</p> +<p>For example +</p> +<div class="smallexample"> +<pre class="smallexample">ldi r26, lo8(sym+10) +ldi r27, hi8(sym+10) +</pre></div> + +</dd> +<dt><code>hh8</code></dt> +<dd> +<p>This modifier allows you to use bits 16 through 23 of +an address expression as an 8 bit relocatable expression. +Also, can be useful for loading 32 bit constants. +</p> +</dd> +<dt><code>hlo8</code></dt> +<dd> +<p>Synonym of ‘<samp>hh8</samp>’. +</p> +</dd> +<dt><code>hhi8</code></dt> +<dd> +<p>This modifier allows you to use bits 24 through 31 of +an expression as an 8 bit expression. This is useful with, for example, the +AVR ‘<samp>ldi</samp>’ instruction and ‘<samp>lo8</samp>’, ‘<samp>hi8</samp>’, ‘<samp>hlo8</samp>’, +‘<samp>hhi8</samp>’, modifier. +</p> +<p>For example +</p> +<div class="smallexample"> +<pre class="smallexample">ldi r26, lo8(285774925) +ldi r27, hi8(285774925) +ldi r28, hlo8(285774925) +ldi r29, hhi8(285774925) +; r29,r28,r27,r26 = 285774925 +</pre></div> + +</dd> +<dt><code>pm_lo8</code></dt> +<dd> +<p>This modifier allows you to use bits 0 through 7 of +an address expression as an 8 bit relocatable expression. +This modifier is useful for addressing data or code from +Flash/Program memory by two-byte words. The use of ‘<samp>pm_lo8</samp>’ +is similar to ‘<samp>lo8</samp>’. +</p> +</dd> +<dt><code>pm_hi8</code></dt> +<dd> +<p>This modifier allows you to use bits 8 through 15 of +an address expression as an 8 bit relocatable expression. +This modifier is useful for addressing data or code from +Flash/Program memory by two-byte words. +</p> +<p>For example, when setting the AVR ‘<samp>Z</samp>’ register with the ‘<samp>ldi</samp>’ +instruction for subsequent use by the ‘<samp>ijmp</samp>’ instruction: +</p> +<div class="smallexample"> +<pre class="smallexample">ldi r30, pm_lo8(sym) +ldi r31, pm_hi8(sym) +ijmp +</pre></div> + +</dd> +<dt><code>pm_hh8</code></dt> +<dd> +<p>This modifier allows you to use bits 15 through 23 of +an address expression as an 8 bit relocatable expression. +This modifier is useful for addressing data or code from +Flash/Program memory by two-byte words. +</p> +</dd> +</dl> + +<hr> +<a name="AVR-Opcodes"></a> +<div class="header"> +<p> +Next: <a href="#AVR-Pseudo-Instructions" accesskey="n" rel="next">AVR Pseudo Instructions</a>, Previous: <a href="#AVR-Syntax" accesskey="p" rel="previous">AVR Syntax</a>, Up: <a href="#AVR_002dDependent" accesskey="u" rel="up">AVR-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-4"></a> +<h4 class="subsection">9.5.3 Opcodes</h4> + +<a name="index-AVR-opcode-summary"></a> +<a name="index-opcode-summary_002c-AVR"></a> +<a name="index-mnemonics_002c-AVR"></a> +<a name="index-instruction-summary_002c-AVR"></a> +<p>For detailed information on the AVR machine instruction set, see +<a href="www.atmel.com/products/AVR">www.atmel.com/products/AVR</a>. +</p> +<p><code>as</code> implements all the standard AVR opcodes. +The following table summarizes the AVR opcodes, and their arguments. +</p> +<div class="smallexample"> +<pre class="smallexample"><i>Legend:</i> + r <span class="roman">any register</span> + d <span class="roman">‘ldi’ register (r16-r31)</span> + v <span class="roman">‘movw’ even register (r0, r2, ..., r28, r30)</span> + a <span class="roman">‘fmul’ register (r16-r23)</span> + w <span class="roman">‘adiw’ register (r24,r26,r28,r30)</span> + e <span class="roman">pointer registers (X,Y,Z)</span> + b <span class="roman">base pointer register and displacement ([YZ]+disp)</span> + z <span class="roman">Z pointer register (for [e]lpm Rd,Z[+])</span> + M <span class="roman">immediate value from 0 to 255</span> + n <span class="roman">immediate value from 0 to 255 ( n = ~M ). Relocation impossible</span> + s <span class="roman">immediate value from 0 to 7</span> + P <span class="roman">Port address value from 0 to 63. (in, out)</span> + p <span class="roman">Port address value from 0 to 31. (cbi, sbi, sbic, sbis)</span> + K <span class="roman">immediate value from 0 to 63 (used in ‘adiw’, ‘sbiw’)</span> + i <span class="roman">immediate value</span> + l <span class="roman">signed pc relative offset from -64 to 63</span> + L <span class="roman">signed pc relative offset from -2048 to 2047</span> + h <span class="roman">absolute code address (call, jmp)</span> + S <span class="roman">immediate value from 0 to 7 (S = s << 4)</span> + ? <span class="roman">use this opcode entry if no parameters, else use next opcode entry</span> + +1001010010001000 clc +1001010011011000 clh +1001010011111000 cli +1001010010101000 cln +1001010011001000 cls +1001010011101000 clt +1001010010111000 clv +1001010010011000 clz +1001010000001000 sec +1001010001011000 seh +1001010001111000 sei +1001010000101000 sen +1001010001001000 ses +1001010001101000 set +1001010000111000 sev +1001010000011000 sez +100101001SSS1000 bclr S +100101000SSS1000 bset S +1001010100001001 icall +1001010000001001 ijmp +1001010111001000 lpm ? +1001000ddddd010+ lpm r,z +1001010111011000 elpm ? +1001000ddddd011+ elpm r,z +0000000000000000 nop +1001010100001000 ret +1001010100011000 reti +1001010110001000 sleep +1001010110011000 break +1001010110101000 wdr +1001010111101000 spm +000111rdddddrrrr adc r,r +000011rdddddrrrr add r,r +001000rdddddrrrr and r,r +000101rdddddrrrr cp r,r +000001rdddddrrrr cpc r,r +000100rdddddrrrr cpse r,r +001001rdddddrrrr eor r,r +001011rdddddrrrr mov r,r +100111rdddddrrrr mul r,r +001010rdddddrrrr or r,r +000010rdddddrrrr sbc r,r +000110rdddddrrrr sub r,r +001001rdddddrrrr clr r +000011rdddddrrrr lsl r +000111rdddddrrrr rol r +001000rdddddrrrr tst r +0111KKKKddddKKKK andi d,M +0111KKKKddddKKKK cbr d,n +1110KKKKddddKKKK ldi d,M +11101111dddd1111 ser d +0110KKKKddddKKKK ori d,M +0110KKKKddddKKKK sbr d,M +0011KKKKddddKKKK cpi d,M +0100KKKKddddKKKK sbci d,M +0101KKKKddddKKKK subi d,M +1111110rrrrr0sss sbrc r,s +1111111rrrrr0sss sbrs r,s +1111100ddddd0sss bld r,s +1111101ddddd0sss bst r,s +10110PPdddddPPPP in r,P +10111PPrrrrrPPPP out P,r +10010110KKddKKKK adiw w,K +10010111KKddKKKK sbiw w,K +10011000pppppsss cbi p,s +10011010pppppsss sbi p,s +10011001pppppsss sbic p,s +10011011pppppsss sbis p,s +111101lllllll000 brcc l +111100lllllll000 brcs l +111100lllllll001 breq l +111101lllllll100 brge l +111101lllllll101 brhc l +111100lllllll101 brhs l +111101lllllll111 brid l +111100lllllll111 brie l +111100lllllll000 brlo l +111100lllllll100 brlt l +111100lllllll010 brmi l +111101lllllll001 brne l +111101lllllll010 brpl l +111101lllllll000 brsh l +111101lllllll110 brtc l +111100lllllll110 brts l +111101lllllll011 brvc l +111100lllllll011 brvs l +111101lllllllsss brbc s,l +111100lllllllsss brbs s,l +1101LLLLLLLLLLLL rcall L +1100LLLLLLLLLLLL rjmp L +1001010hhhhh111h call h +1001010hhhhh110h jmp h +1001010rrrrr0101 asr r +1001010rrrrr0000 com r +1001010rrrrr1010 dec r +1001010rrrrr0011 inc r +1001010rrrrr0110 lsr r +1001010rrrrr0001 neg r +1001000rrrrr1111 pop r +1001001rrrrr1111 push r +1001010rrrrr0111 ror r +1001010rrrrr0010 swap r +00000001ddddrrrr movw v,v +00000010ddddrrrr muls d,d +000000110ddd0rrr mulsu a,a +000000110ddd1rrr fmul a,a +000000111ddd0rrr fmuls a,a +000000111ddd1rrr fmulsu a,a +1001001ddddd0000 sts i,r +1001000ddddd0000 lds r,i +10o0oo0dddddbooo ldd r,b +100!000dddddee-+ ld r,e +10o0oo1rrrrrbooo std b,r +100!001rrrrree-+ st e,r +1001010100011001 eicall +1001010000011001 eijmp +</pre></div> + +<hr> +<a name="AVR-Pseudo-Instructions"></a> +<div class="header"> +<p> +Previous: <a href="#AVR-Opcodes" accesskey="p" rel="previous">AVR Opcodes</a>, Up: <a href="#AVR_002dDependent" accesskey="u" rel="up">AVR-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Pseudo-Instructions"></a> +<h4 class="subsection">9.5.4 Pseudo Instructions</h4> + +<p>The only available pseudo-instruction <code>__gcc_isr</code> can be activated by +option <samp>-mgcc-isr</samp>. +</p> +<dl compact="compact"> +<dt><code>__gcc_isr 1</code></dt> +<dd><p>Emit code chunk to be used in avr-gcc ISR prologue. +It will expand to at most six 1-word instructions, all optional: +push of <code>tmp_reg</code>, push of <code>SREG</code>, +push and clear of <code>zero_reg</code>, push of <var>Reg</var>. +</p> +</dd> +<dt><code>__gcc_isr 2</code></dt> +<dd><p>Emit code chunk to be used in an avr-gcc ISR epilogue. +It will expand to at most five 1-word instructions, all optional: +pop of <var>Reg</var>, pop of <code>zero_reg</code>, +pop of <code>SREG</code>, pop of <code>tmp_reg</code>. +</p> +</dd> +<dt><code>__gcc_isr 0, <var>Reg</var></code></dt> +<dd><p>Finish avr-gcc ISR function. Scan code since the last prologue +for usage of: <code>SREG</code>, <code>tmp_reg</code>, <code>zero_reg</code>. +Prologue chunk and epilogue chunks will be replaced by appropriate code +to save / restore <code>SREG</code>, <code>tmp_reg</code>, <code>zero_reg</code> and <var>Reg</var>. +</p> +</dd> +</dl> + +<p>Example input: +</p> +<div class="example"> +<pre class="example">__vector1: + __gcc_isr 1 + lds r24, var + inc r24 + sts var, r24 + __gcc_isr 2 + reti + __gcc_isr 0, r24 +</pre></div> + +<p>Example output: +</p> +<div class="example"> +<pre class="example">00000000 <__vector1>: + 0: 8f 93 push r24 + 2: 8f b7 in r24, 0x3f + 4: 8f 93 push r24 + 6: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <var> + a: 83 95 inc r24 + c: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <var> + 10: 8f 91 pop r24 + 12: 8f bf out 0x3f, r24 + 14: 8f 91 pop r24 + 16: 18 95 reti +</pre></div> + + +<hr> +<a name="Blackfin_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#BPF_002dDependent" accesskey="n" rel="next">BPF-Dependent</a>, Previous: <a href="#AVR_002dDependent" accesskey="p" rel="previous">AVR-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Blackfin-Dependent-Features"></a> +<h3 class="section">9.6 Blackfin Dependent Features</h3> + + +<a name="index-Blackfin-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Blackfin-Options" accesskey="1">Blackfin Options</a>:</td><td> </td><td align="left" valign="top">Blackfin Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#Blackfin-Syntax" accesskey="2">Blackfin Syntax</a>:</td><td> </td><td align="left" valign="top">Blackfin Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#Blackfin-Directives" accesskey="3">Blackfin Directives</a>:</td><td> </td><td align="left" valign="top">Blackfin Directives +</td></tr> +</table> + +<hr> +<a name="Blackfin-Options"></a> +<div class="header"> +<p> +Next: <a href="#Blackfin-Syntax" accesskey="n" rel="next">Blackfin Syntax</a>, Up: <a href="#Blackfin_002dDependent" accesskey="u" rel="up">Blackfin-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-5"></a> +<h4 class="subsection">9.6.1 Options</h4> +<a name="index-Blackfin-options-_0028none_0029"></a> +<a name="index-options-for-Blackfin-_0028none_0029"></a> + +<dl compact="compact"> +<dd> +<a name="index-_002dmcpu_003d-command_002dline-option_002c-Blackfin"></a> +</dd> +<dt><code>-mcpu=<var>processor</var><span class="roman">[</span>-<var>sirevision</var><span class="roman">]</span></code></dt> +<dd><p>This option specifies the target processor. The optional <var>sirevision</var> +is not used in assembler. It’s here such that GCC can easily pass down its +<code>-mcpu=</code> option. The assembler will issue an +error message if an attempt is made to assemble an instruction which +will not execute on the target processor. The following processor names are +recognized: +<code>bf504</code>, +<code>bf506</code>, +<code>bf512</code>, +<code>bf514</code>, +<code>bf516</code>, +<code>bf518</code>, +<code>bf522</code>, +<code>bf523</code>, +<code>bf524</code>, +<code>bf525</code>, +<code>bf526</code>, +<code>bf527</code>, +<code>bf531</code>, +<code>bf532</code>, +<code>bf533</code>, +<code>bf534</code>, +<code>bf535</code> (not implemented yet), +<code>bf536</code>, +<code>bf537</code>, +<code>bf538</code>, +<code>bf539</code>, +<code>bf542</code>, +<code>bf542m</code>, +<code>bf544</code>, +<code>bf544m</code>, +<code>bf547</code>, +<code>bf547m</code>, +<code>bf548</code>, +<code>bf548m</code>, +<code>bf549</code>, +<code>bf549m</code>, +<code>bf561</code>, +and +<code>bf592</code>. +</p> +<a name="index-_002dmfdpic-command_002dline-option_002c-Blackfin"></a> +</dd> +<dt><code>-mfdpic</code></dt> +<dd><p>Assemble for the FDPIC ABI. +</p> +<a name="index-_002dmno_002dfdpic-command_002dline-option_002c-Blackfin"></a> +<a name="index-_002dmnopic-command_002dline-option_002c-Blackfin"></a> +</dd> +<dt><code>-mno-fdpic</code></dt> +<dt><code>-mnopic</code></dt> +<dd><p>Disable -mfdpic. +</p></dd> +</dl> + +<hr> +<a name="Blackfin-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#Blackfin-Directives" accesskey="n" rel="next">Blackfin Directives</a>, Previous: <a href="#Blackfin-Options" accesskey="p" rel="previous">Blackfin Options</a>, Up: <a href="#Blackfin_002dDependent" accesskey="u" rel="up">Blackfin-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-7"></a> +<h4 class="subsection">9.6.2 Syntax</h4> +<a name="index-Blackfin-syntax"></a> +<a name="index-syntax_002c-Blackfin"></a> + +<dl compact="compact"> +<dt><code>Special Characters</code></dt> +<dd><p>Assembler input is free format and may appear anywhere on the line. +One instruction may extend across multiple lines or more than one +instruction may appear on the same line. White space (space, tab, +comments or newline) may appear anywhere between tokens. A token must +not have embedded spaces. Tokens include numbers, register names, +keywords, user identifiers, and also some multicharacter special +symbols like "+=", "/*" or "||". +</p> +<p>Comments are introduced by the ‘<samp>#</samp>’ character and extend to the +end of the current line. If the ‘<samp>#</samp>’ appears as the first +character of a line, the whole line is treated as a comment, but in +this case the line can also be a logical line number directive +(see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +</dd> +<dt><code>Instruction Delimiting</code></dt> +<dd><p>A semicolon must terminate every instruction. Sometimes a complete +instruction will consist of more than one operation. There are two +cases where this occurs. The first is when two general operations +are combined. Normally a comma separates the different parts, as in +</p> +<div class="smallexample"> +<pre class="smallexample">a0= r3.h * r2.l, a1 = r3.l * r2.h ; +</pre></div> + +<p>The second case occurs when a general instruction is combined with one +or two memory references for joint issue. The latter portions are +set off by a "||" token. +</p> +<div class="smallexample"> +<pre class="smallexample">a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; +</pre></div> + +<p>Multiple instructions can occur on the same line. Each must be +terminated by a semicolon character. +</p> +</dd> +<dt><code>Register Names</code></dt> +<dd> +<p>The assembler treats register names and instruction keywords in a case +insensitive manner. User identifiers are case sensitive. Thus, R3.l, +R3.L, r3.l and r3.L are all equivalent input to the assembler. +</p> +<p>Register names are reserved and may not be used as program identifiers. +</p> +<p>Some operations (such as "Move Register") require a register pair. +Register pairs are always data registers and are denoted using a colon, +eg., R3:2. The larger number must be written firsts. Note that the +hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0. +</p> +<p>Some instructions (such as –SP (Push Multiple)) require a group of +adjacent registers. Adjacent registers are denoted in the syntax by +the range enclosed in parentheses and separated by a colon, eg., (R7:3). +Again, the larger number appears first. +</p> +<p>Portions of a particular register may be individually specified. This +is written with a dot (".") following the register name and then a +letter denoting the desired portion. For 32-bit registers, ".H" +denotes the most significant ("High") portion. ".L" denotes the +least-significant portion. The subdivisions of the 40-bit registers +are described later. +</p> +</dd> +<dt><code>Accumulators</code></dt> +<dd><p>The set of 40-bit registers A1 and A0 that normally contain data that +is being manipulated. Each accumulator can be accessed in four ways. +</p> +<dl compact="compact"> +<dt><code>one 40-bit register</code></dt> +<dd><p>The register will be referred to as A1 or A0. +</p></dd> +<dt><code>one 32-bit register</code></dt> +<dd><p>The registers are designated as A1.W or A0.W. +</p></dd> +<dt><code>two 16-bit registers</code></dt> +<dd><p>The registers are designated as A1.H, A1.L, A0.H or A0.L. +</p></dd> +<dt><code>one 8-bit register</code></dt> +<dd><p>The registers are designated as A1.X or A0.X for the bits that +extend beyond bit 31. +</p></dd> +</dl> + +</dd> +<dt><code>Data Registers</code></dt> +<dd><p>The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that +normally contain data for manipulation. These are abbreviated as +D-register or Dreg. Data registers can be accessed as 32-bit registers +or as two independent 16-bit registers. The least significant 16 bits +of each register is called the "low" half and is designated with ".L" +following the register name. The most significant 16 bits are called +the "high" half and is designated with ".H" following the name. +</p> +<div class="smallexample"> +<pre class="smallexample"> R7.L, r2.h, r4.L, R0.H +</pre></div> + +</dd> +<dt><code>Pointer Registers</code></dt> +<dd><p>The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that +normally contain byte addresses of data structures. These are +abbreviated as P-register or Preg. +</p> +<div class="smallexample"> +<pre class="smallexample">p2, p5, fp, sp +</pre></div> + +</dd> +<dt><code>Stack Pointer SP</code></dt> +<dd><p>The stack pointer contains the 32-bit address of the last occupied +byte location in the stack. The stack grows by decrementing the +stack pointer. +</p> +</dd> +<dt><code>Frame Pointer FP</code></dt> +<dd><p>The frame pointer contains the 32-bit address of the previous frame +pointer in the stack. It is located at the top of a frame. +</p> +</dd> +<dt><code>Loop Top</code></dt> +<dd><p>LT0 and LT1. These registers contain the 32-bit address of the top of +a zero overhead loop. +</p> +</dd> +<dt><code>Loop Count</code></dt> +<dd><p>LC0 and LC1. These registers contain the 32-bit counter of the zero +overhead loop executions. +</p> +</dd> +<dt><code>Loop Bottom</code></dt> +<dd><p>LB0 and LB1. These registers contain the 32-bit address of the bottom +of a zero overhead loop. +</p> +</dd> +<dt><code>Index Registers</code></dt> +<dd><p>The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte +addresses of data structures. Abbreviated I-register or Ireg. +</p> +</dd> +<dt><code>Modify Registers</code></dt> +<dd><p>The set of 32-bit registers (M0, M1, M2, M3) that normally contain +offset values that are added and subtracted to one of the index +registers. Abbreviated as Mreg. +</p> +</dd> +<dt><code>Length Registers</code></dt> +<dd><p>The set of 32-bit registers (L0, L1, L2, L3) that normally contain the +length in bytes of the circular buffer. Abbreviated as Lreg. Clear +the Lreg to disable circular addressing for the corresponding Ireg. +</p> +</dd> +<dt><code>Base Registers</code></dt> +<dd><p>The set of 32-bit registers (B0, B1, B2, B3) that normally contain the +base address in bytes of the circular buffer. Abbreviated as Breg. +</p> +</dd> +<dt><code>Floating Point</code></dt> +<dd><p>The Blackfin family has no hardware floating point but the .float +directive generates ieee floating point numbers for use with software +floating point libraries. +</p> +</dd> +<dt><code>Blackfin Opcodes</code></dt> +<dd><p>For detailed information on the Blackfin machine instruction set, see +the Blackfin Processor Instruction Set Reference. +</p> +</dd> +</dl> + +<hr> +<a name="Blackfin-Directives"></a> +<div class="header"> +<p> +Previous: <a href="#Blackfin-Syntax" accesskey="p" rel="previous">Blackfin Syntax</a>, Up: <a href="#Blackfin_002dDependent" accesskey="u" rel="up">Blackfin-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives"></a> +<h4 class="subsection">9.6.3 Directives</h4> +<a name="index-Blackfin-directives"></a> +<a name="index-directives_002c-Blackfin"></a> + +<p>The following directives are provided for compatibility with the VDSP assembler. +</p> +<dl compact="compact"> +<dt><code>.byte2</code></dt> +<dd><p>Initializes a two byte data object. +</p> +<p>This maps to the <code>.short</code> directive. +</p></dd> +<dt><code>.byte4</code></dt> +<dd><p>Initializes a four byte data object. +</p> +<p>This maps to the <code>.int</code> directive. +</p></dd> +<dt><code>.db</code></dt> +<dd><p>Initializes a single byte data object. +</p> +<p>This directive is a synonym for <code>.byte</code>. +</p></dd> +<dt><code>.dw</code></dt> +<dd><p>Initializes a two byte data object. +</p> +<p>This directive is a synonym for <code>.byte2</code>. +</p></dd> +<dt><code>.dd</code></dt> +<dd><p>Initializes a four byte data object. +</p> +<p>This directive is a synonym for <code>.byte4</code>. +</p></dd> +<dt><code>.var</code></dt> +<dd><p>Define and initialize a 32 bit data object. +</p></dd> +</dl> + + +<hr> +<a name="BPF_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#CR16_002dDependent" accesskey="n" rel="next">CR16-Dependent</a>, Previous: <a href="#Blackfin_002dDependent" accesskey="p" rel="previous">Blackfin-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="BPF-Dependent-Features"></a> +<h3 class="section">9.7 BPF Dependent Features</h3> + + +<a name="index-BPF-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#BPF-Options" accesskey="1">BPF Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#BPF-Syntax" accesskey="2">BPF Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#BPF-Directives" accesskey="3">BPF Directives</a>:</td><td> </td><td align="left" valign="top">Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#BPF-Opcodes" accesskey="4">BPF Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +<tr><td align="left" valign="top">• <a href="#BPF-Pseudo_002dC-Syntax" accesskey="5">BPF Pseudo-C Syntax</a>:</td><td> </td><td align="left" valign="top">Alternative Pseudo-C Assembly Syntax +</td></tr> +</table> + +<hr> +<a name="BPF-Options"></a> +<div class="header"> +<p> +Next: <a href="#BPF-Syntax" accesskey="n" rel="next">BPF Syntax</a>, Up: <a href="#BPF_002dDependent" accesskey="u" rel="up">BPF-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-6"></a> +<h4 class="subsection">9.7.1 Options</h4> +<a name="index-BPF-options-_0028none_0029"></a> +<a name="index-options-for-BPF-_0028none_0029"></a> + +<dl compact="compact"> +<dd> +<a name="index-_002dEB-command_002dline-option_002c-BPF"></a> +</dd> +<dt><code>-EB</code></dt> +<dd><p>This option specifies that the assembler should emit big-endian eBPF. +</p> +<a name="index-_002dEL-command_002dline-option_002c-BPF"></a> +</dd> +<dt><code>-EL</code></dt> +<dd><p>This option specifies that the assembler should emit little-endian +eBPF. +</p></dd> +</dl> + +<p>Note that if no endianness option is specified in the command line, +the host endianness is used. +</p> +<hr> +<a name="BPF-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#BPF-Directives" accesskey="n" rel="next">BPF Directives</a>, Previous: <a href="#BPF-Options" accesskey="p" rel="previous">BPF Options</a>, Up: <a href="#BPF_002dDependent" accesskey="u" rel="up">BPF-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-8"></a> +<h4 class="subsection">9.7.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#BPF_002dChars" accesskey="1">BPF-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#BPF_002dRegs" accesskey="2">BPF-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#BPF_002dPseudo_002dMaps" accesskey="3">BPF-Pseudo-Maps</a>:</td><td> </td><td align="left" valign="top">Pseudo map fds +</td></tr> +</table> + +<hr> +<a name="BPF_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#BPF_002dRegs" accesskey="n" rel="next">BPF-Regs</a>, Up: <a href="#BPF-Syntax" accesskey="u" rel="up">BPF Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-5"></a> +<h4 class="subsubsection">9.7.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-BPF"></a> +<a name="index-BPF-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ on a line indicates the start of a comment +that extends to the end of the current line. If a ‘<samp>#</samp>’ appears as +the first character of a line, the whole line is treated as a comment. +</p> +<a name="index-statement-separator_002c-BPF"></a> +<p>Statements and assembly directives are separated by newlines. +</p> +<hr> +<a name="BPF_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#BPF_002dPseudo_002dMaps" accesskey="n" rel="next">BPF-Pseudo-Maps</a>, Previous: <a href="#BPF_002dChars" accesskey="p" rel="previous">BPF-Chars</a>, Up: <a href="#BPF-Syntax" accesskey="u" rel="up">BPF Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-5"></a> +<h4 class="subsubsection">9.7.2.2 Register Names</h4> + +<a name="index-BPF-register-names"></a> +<a name="index-register-names_002c-BPF"></a> +<p>The eBPF processor provides ten general-purpose 64-bit registers, +which are read-write, and a read-only frame pointer register: +</p> +<dl compact="compact"> +<dt>‘<samp>%r0 .. %r9</samp>’</dt> +<dd><p>General-purpose registers. +</p></dd> +<dt>‘<samp>%r10</samp>’</dt> +<dd><p>Frame pointer register. +</p></dd> +</dl> + +<p>Some registers have additional names, to reflect their role in the +eBPF ABI: +</p> +<dl compact="compact"> +<dt>‘<samp>%a</samp>’</dt> +<dd><p>This is ‘<samp>%r0</samp>’. +</p></dd> +<dt>‘<samp>%ctx</samp>’</dt> +<dd><p>This is ‘<samp>%r6</samp>’. +</p></dd> +<dt>‘<samp>%fp</samp>’</dt> +<dd><p>This is ‘<samp>%r10</samp>’. +</p></dd> +</dl> + +<hr> +<a name="BPF_002dPseudo_002dMaps"></a> +<div class="header"> +<p> +Previous: <a href="#BPF_002dRegs" accesskey="p" rel="previous">BPF-Regs</a>, Up: <a href="#BPF-Syntax" accesskey="u" rel="up">BPF Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Pseudo-Maps"></a> +<h4 class="subsubsection">9.7.2.3 Pseudo Maps</h4> + +<a name="index-pseudo-map-fd_002c-BPF"></a> +<p>The ‘<samp>LDDW</samp>’ instruction can take a literal pseudo map file +descriptor as its second argument. This uses the syntax +‘<samp>%map_fd(N)</samp>’ where ‘<samp>N</samp>’ is a signed number. +</p> +<p>For example, to load the address of the pseudo map with file +descriptor ‘<samp>2</samp>’ in register ‘<samp>r1</samp>’ we would do: +</p> +<div class="smallexample"> +<pre class="smallexample"> lddw %r1, %map_fd(2) +</pre></div> + +<hr> +<a name="BPF-Directives"></a> +<div class="header"> +<p> +Next: <a href="#BPF-Opcodes" accesskey="n" rel="next">BPF Opcodes</a>, Previous: <a href="#BPF-Syntax" accesskey="p" rel="previous">BPF Syntax</a>, Up: <a href="#BPF_002dDependent" accesskey="u" rel="up">BPF-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Machine-Directives"></a> +<h4 class="subsection">9.7.3 Machine Directives</h4> + +<a name="index-machine-directives_002c-BPF"></a> + +<p>The BPF version of <code>as</code> supports the following additional +machine directives: +</p> +<dl compact="compact"> +<dd><a name="index-half-directive_002c-BPF"></a> +</dd> +<dt><code>.word</code></dt> +<dd><p>The <code>.half</code> directive produces a 16 bit value. +</p> +<a name="index-word-directive_002c-BPF"></a> +</dd> +<dt><code>.word</code></dt> +<dd><p>The <code>.word</code> directive produces a 32 bit value. +</p> +<a name="index-dword-directive_002c-BPF"></a> +</dd> +<dt><code>.dword</code></dt> +<dd><p>The <code>.dword</code> directive produces a 64 bit value. +</p></dd> +</dl> + +<hr> +<a name="BPF-Opcodes"></a> +<div class="header"> +<p> +Next: <a href="#BPF-Pseudo_002dC-Syntax" accesskey="n" rel="next">BPF Pseudo-C Syntax</a>, Previous: <a href="#BPF-Directives" accesskey="p" rel="previous">BPF Directives</a>, Up: <a href="#BPF_002dDependent" accesskey="u" rel="up">BPF-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-5"></a> +<h4 class="subsection">9.7.4 Opcodes</h4> + +<a name="index-BPF-opcodes"></a> +<a name="index-opcodes-for-BPF"></a> +<p>In the instruction descriptions below the following field descriptors +are used: +</p> +<dl compact="compact"> +<dt><code>%d</code></dt> +<dd><p>Destination general-purpose register whose role is to be destination +of an operation. +</p></dd> +<dt><code>%s</code></dt> +<dd><p>Source general-purpose register whose role is to be the source of an +operation. +</p></dd> +<dt><code>disp16</code></dt> +<dd><p>16-bit signed PC-relative offset, measured in number of 64-bit words, +minus one. +</p></dd> +<dt><code>disp32</code></dt> +<dd><p>32-bit signed PC-relative offset, measured in number of 64-bit words, +minus one. +</p></dd> +<dt><code>offset16</code></dt> +<dd><p>Signed 16-bit immediate. +</p></dd> +<dt><code>imm32</code></dt> +<dd><p>Signed 32-bit immediate. +</p></dd> +<dt><code>imm64</code></dt> +<dd><p>Signed 64-bit immediate. +</p></dd> +</dl> + +<a name="Arithmetic-instructions"></a> +<h4 class="subsubsection">9.7.4.1 Arithmetic instructions</h4> + +<p>The destination register in these instructions act like an +accumulator. +</p> +<dl compact="compact"> +<dt><code>add %d, (%s|imm32)</code></dt> +<dd><p>64-bit arithmetic addition. +</p></dd> +<dt><code>sub %d, (%s|imm32)</code></dt> +<dd><p>64-bit arithmetic subtraction. +</p></dd> +<dt><code>mul %d, (%s|imm32)</code></dt> +<dd><p>64-bit arithmetic multiplication. +</p></dd> +<dt><code>div %d, (%s|imm32)</code></dt> +<dd><p>64-bit arithmetic integer division. +</p></dd> +<dt><code>mod %d, (%s|imm32)</code></dt> +<dd><p>64-bit integer remainder. +</p></dd> +<dt><code>and %d, (%s|imm32)</code></dt> +<dd><p>64-bit bit-wise “and” operation. +</p></dd> +<dt><code>or %d, (%s|imm32)</code></dt> +<dd><p>64-bit bit-wise “or” operation. +</p></dd> +<dt><code>xor %d, (%s|imm32)</code></dt> +<dd><p>64-bit bit-wise exclusive-or operation. +</p></dd> +<dt><code>lsh %d, (%s|imm32)</code></dt> +<dd><p>64-bit left shift, by <code>%s</code> or <code>imm32</code> bits. +</p></dd> +<dt><code>rsh %d, (%s|imm32)</code></dt> +<dd><p>64-bit right logical shift, by <code>%s</code> or <code>imm32</code> bits. +</p></dd> +<dt><code>arsh %d, (%s|imm32)</code></dt> +<dd><p>64-bit right arithmetic shift, by <code>%s</code> or <code>imm32</code> bits. +</p></dd> +<dt><code>neg %d</code></dt> +<dd><p>64-bit arithmetic negation. +</p></dd> +<dt><code>mov %d, (%s|imm32)</code></dt> +<dd><p>Move the 64-bit value of <code>%s</code> in <code>%d</code>, or load <code>imm32</code> +in <code>%d</code>. +</p></dd> +</dl> + +<a name="g_t32_002dbit-arithmetic-instructions"></a> +<h4 class="subsubsection">9.7.4.2 32-bit arithmetic instructions</h4> + +<p>The destination register in these instructions act as an accumulator. +</p> +<dl compact="compact"> +<dt><code>add32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit arithmetic addition. +</p></dd> +<dt><code>sub32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit arithmetic subtraction. +</p></dd> +<dt><code>mul32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit arithmetic multiplication. +</p></dd> +<dt><code>div32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit arithmetic integer division. +</p></dd> +<dt><code>mod32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit integer remainder. +</p></dd> +<dt><code>and32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit bit-wise “and” operation. +</p></dd> +<dt><code>or32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit bit-wise “or” operation. +</p></dd> +<dt><code>xor32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit bit-wise exclusive-or operation. +</p></dd> +<dt><code>lsh32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit left shift, by <code>%s</code> or <code>imm32</code> bits. +</p></dd> +<dt><code>rsh32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit right logical shift, by <code>%s</code> or <code>imm32</code> bits. +</p></dd> +<dt><code>arsh32 %d, (%s|imm32)</code></dt> +<dd><p>32-bit right arithmetic shift, by <code>%s</code> or <code>imm32</code> bits. +</p></dd> +<dt><code>neg32 %d</code></dt> +<dd><p>32-bit arithmetic negation. +</p></dd> +<dt><code>mov32 %d, (%s|imm32)</code></dt> +<dd><p>Move the 32-bit value of <code>%s</code> in <code>%d</code>, or load <code>imm32</code> +in <code>%d</code>. +</p></dd> +</dl> + +<a name="Endianness-conversion-instructions"></a> +<h4 class="subsubsection">9.7.4.3 Endianness conversion instructions</h4> + +<dl compact="compact"> +<dt><code>endle %d, (16|32|64)</code></dt> +<dd><p>Convert the 16-bit, 32-bit or 64-bit value in <code>%d</code> to +little-endian. +</p></dd> +<dt><code>endbe %d, (16|32|64)</code></dt> +<dd><p>Convert the 16-bit, 32-bit or 64-bit value in <code>%d</code> to big-endian. +</p></dd> +</dl> + +<a name="g_t64_002dbit-load-and-pseudo-maps"></a> +<h4 class="subsubsection">9.7.4.4 64-bit load and pseudo maps</h4> + +<dl compact="compact"> +<dt><code>lddw %d, imm64</code></dt> +<dd><p>Load the given signed 64-bit immediate, or pseudo map descriptor, to +the destination register <code>%d</code>. +</p></dd> +<dt><code>lddw %d, %map_fd(N)</code></dt> +<dd><p>Load the address of the given pseudo map fd <em>N</em> to the +destination register <code>%d</code>. +</p></dd> +</dl> + +<a name="Load-instructions-for-socket-filters"></a> +<h4 class="subsubsection">9.7.4.5 Load instructions for socket filters</h4> + +<p>The following instructions are intended to be used in socket filters, +and are therefore not general-purpose: they make assumptions on the +contents of several registers. See the file +<samp>Documentation/networking/filter.txt</samp> in the Linux kernel source +tree for more information. +</p> +<p>Absolute loads: +</p> +<dl compact="compact"> +<dt><code>ldabsdw imm32</code></dt> +<dd><p>Absolute 64-bit load. +</p></dd> +<dt><code>ldabsw imm32</code></dt> +<dd><p>Absolute 32-bit load. +</p></dd> +<dt><code>ldabsh imm32</code></dt> +<dd><p>Absolute 16-bit load. +</p></dd> +<dt><code>ldabsb imm32</code></dt> +<dd><p>Absolute 8-bit load. +</p></dd> +</dl> + +<p>Indirect loads: +</p> +<dl compact="compact"> +<dt><code>ldinddw %s, imm32</code></dt> +<dd><p>Indirect 64-bit load. +</p></dd> +<dt><code>ldindw %s, imm32</code></dt> +<dd><p>Indirect 32-bit load. +</p></dd> +<dt><code>ldindh %s, imm32</code></dt> +<dd><p>Indirect 16-bit load. +</p></dd> +<dt><code>ldindb %s, imm32</code></dt> +<dd><p>Indirect 8-bit load. +</p></dd> +</dl> + +<a name="Generic-load_002fstore-instructions"></a> +<h4 class="subsubsection">9.7.4.6 Generic load/store instructions</h4> + +<p>General-purpose load and store instructions are provided for several +word sizes. +</p> +<p>Load to register instructions: +</p> +<dl compact="compact"> +<dt><code>ldxdw %d, [%s+offset16]</code></dt> +<dd><p>Generic 64-bit load. +</p></dd> +<dt><code>ldxw %d, [%s+offset16]</code></dt> +<dd><p>Generic 32-bit load. +</p></dd> +<dt><code>ldxh %d, [%s+offset16]</code></dt> +<dd><p>Generic 16-bit load. +</p></dd> +<dt><code>ldxb %d, [%s+offset16]</code></dt> +<dd><p>Generic 8-bit load. +</p></dd> +</dl> + +<p>Store from register instructions: +</p> +<dl compact="compact"> +<dt><code>stxdw [%d+offset16], %s</code></dt> +<dd><p>Generic 64-bit store. +</p></dd> +<dt><code>stxw [%d+offset16], %s</code></dt> +<dd><p>Generic 32-bit store. +</p></dd> +<dt><code>stxh [%d+offset16], %s</code></dt> +<dd><p>Generic 16-bit store. +</p></dd> +<dt><code>stxb [%d+offset16], %s</code></dt> +<dd><p>Generic 8-bit store. +</p></dd> +</dl> + +<p>Store from immediates instructions: +</p> +<dl compact="compact"> +<dt><code>stddw [%d+offset16], imm32</code></dt> +<dd><p>Store immediate as 64-bit. +</p></dd> +<dt><code>stdw [%d+offset16], imm32</code></dt> +<dd><p>Store immediate as 32-bit. +</p></dd> +<dt><code>stdh [%d+offset16], imm32</code></dt> +<dd><p>Store immediate as 16-bit. +</p></dd> +<dt><code>stdb [%d+offset16], imm32</code></dt> +<dd><p>Store immediate as 8-bit. +</p></dd> +</dl> + +<a name="Jump-instructions"></a> +<h4 class="subsubsection">9.7.4.7 Jump instructions</h4> + +<p>eBPF provides the following compare-and-jump instructions, which +compare the values of the two given registers, or the values of a +register and an immediate, and perform a branch in case the comparison +holds true. +</p> +<dl compact="compact"> +<dt><code>ja %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump-always. +</p></dd> +<dt><code>jeq %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if equal, unsigned. +</p></dd> +<dt><code>jgt %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if greater, unsigned. +</p></dd> +<dt><code>jge %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if greater or equal. +</p></dd> +<dt><code>jlt %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if lesser. +</p></dd> +<dt><code>jle %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if lesser or equal. +</p></dd> +<dt><code>jset %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if signed equal. +</p></dd> +<dt><code>jne %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if not equal. +</p></dd> +<dt><code>jsgt %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if signed greater. +</p></dd> +<dt><code>jsge %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if signed greater or equal. +</p></dd> +<dt><code>jslt %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if signed lesser. +</p></dd> +<dt><code>jsle %d,(%s|imm32),disp16</code></dt> +<dd><p>Jump if signed lesser or equal. +</p></dd> +</dl> + +<p>A call instruction is provided in order to perform calls to other eBPF +functions, or to external kernel helpers: +</p> +<dl compact="compact"> +<dt><code>call (disp32|imm32)</code></dt> +<dd><p>Jump and link to the offset <em>disp32</em>, or to the kernel helper +function identified by <em>imm32</em>. +</p></dd> +</dl> + +<p>Finally: +</p> +<dl compact="compact"> +<dt><code>exit</code></dt> +<dd><p>Terminate the eBPF program. +</p></dd> +</dl> + +<a name="Atomic-instructions"></a> +<h4 class="subsubsection">9.7.4.8 Atomic instructions</h4> + +<p>Atomic exchange-and-add instructions are provided in two flavors: one +for swapping 64-bit quantities and another for 32-bit quantities. +</p> +<dl compact="compact"> +<dt><code>xadddw [%d+offset16],%s</code></dt> +<dd><p>Exchange-and-add a 64-bit value at the specified location. +</p></dd> +<dt><code>xaddw [%d+offset16],%s</code></dt> +<dd><p>Exchange-and-add a 32-bit value at the specified location. +</p></dd> +</dl> + +<hr> +<a name="BPF-Pseudo_002dC-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#BPF-Opcodes" accesskey="p" rel="previous">BPF Opcodes</a>, Up: <a href="#BPF_002dDependent" accesskey="u" rel="up">BPF-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="BPF-Pseudo_002dC-Syntax-1"></a> +<h4 class="subsection">9.7.5 BPF Pseudo-C Syntax</h4> + +<p>This assembler supports another syntax to denote BPF instructions, +which is an alternative to the normal looking syntax documented above. +This alternatative syntax, which we call <em>pseudo-C syntax</em>, is +supported by the LLVM/clang integrated assembler. +</p> +<p>This syntax is very unconventional, but we need to support it in order +to support inline assembly in existing BPF programs. +</p> +<p>Note that the assembler is able to parse sources in which both +syntaxes coexist: some instructions can use the usual assembly like +syntax, whereas some other instructions in the same file can use the +pseudo-C syntax. +</p> +<a name="Pseudo_002dC-Register-Names"></a> +<h4 class="subsubsection">9.7.5.1 Pseudo-C Register Names</h4> + +<p>All BPF registers are 64-bit long. However, in the Pseudo-C syntax +registers can be referred using different names, which actually +reflect the kind of instruction they appear on: +</p> +<dl compact="compact"> +<dt>‘<samp>r0..r9</samp>’</dt> +<dd><p>General-purpose register in an instruction that operates on its value +as if it was a 64-bit value. +</p></dd> +<dt>‘<samp>w0..w9</samp>’</dt> +<dd><p>General-purpose register in an instruction that operates on its value +as if it was a 32-bit value. +</p></dd> +</dl> + +<p>Note that in the Pseudo-C syntax register names are not preceded by +<code>%</code> characters. +</p> +<a name="Arithmetic-instructions-1"></a> +<h4 class="subsubsection">9.7.5.2 Arithmetic instructions</h4> + +<p>In all the instructions below, the operations are 64-bit or 32-bit +depending on the names used to refer to the registers. For example +<code>r3 += r2</code> will perform 64-bit addition, whereas <code>w3 += w2</code> +will perform 32-bit addition. Mixing register prefixes is an error, +for example <code>r3 += w2</code>. +</p> +<dl compact="compact"> +<dt><code>dst_reg += (imm32|src_reg)</code></dt> +<dd><p>Arithmetic addition. +</p></dd> +<dt><code>dst_reg -= (imm32|src_reg)</code></dt> +<dd><p>Arithmetic subtraction. +</p></dd> +<dt><code>dst_reg *= (imm32|src_reg)</code></dt> +<dd><p>Arithmetic multiplication. +</p></dd> +<dt><code>dst_reg /= (imm32|src_reg)</code></dt> +<dd><p>Arithmetic integer unsigned division. +</p></dd> +<dt><code>dst_reg %= (imm32|src_reg)</code></dt> +<dd><p>Arithmetic integer unsigned remainder. +</p></dd> +<dt><code>dst_reg &= (imm32|src_reg)</code></dt> +<dd><p>Bit-wise “and” operation. +</p></dd> +<dt><code>dst_reg |= (imm32|src_reg)</code></dt> +<dd><p>Bit-wise “or” operation. +</p></dd> +<dt><code>dst_reg ^= (imm32|src_reg)</code></dt> +<dd><p>Bit-wise exclusive-or operation. +</p></dd> +<dt><code>dst_reg <<= (imm32|src_reg)</code></dt> +<dd><p>Left shift, by whatever specified number of bits. +</p></dd> +<dt><code>dst_reg >>= (imm32|src_reg)</code></dt> +<dd><p>Right logical shift, by whatever specified number of bits. +</p></dd> +<dt><code>dst_reg s>>= (imm32|src_reg)</code></dt> +<dd><p>Right arithmetic shift, by whatever specified number of bits. +</p></dd> +<dt><code>dst_reg = (imm32|src_reg)</code></dt> +<dd><p>Move the value in <code>imm32</code> or <code>src_reg</code> in <code>dst_reg</code>. +</p></dd> +<dt><code>dst_reg = -dst_reg</code></dt> +<dd><p>Arithmetic negation. +</p></dd> +</dl> + +<a name="Endianness-conversion-instructions-1"></a> +<h4 class="subsubsection">9.7.5.3 Endianness conversion instructions</h4> + +<dl compact="compact"> +<dt><code>dst_reg = le16 src_reg</code></dt> +<dd><p>Convert the 16-bit value in <code>src_reg</code> to little-endian. +</p></dd> +<dt><code>dst_reg = le32 src_reg</code></dt> +<dd><p>Convert the 32-bit value in <code>src_reg</code> to little-endian. +</p></dd> +<dt><code>dst_reg = le64 src_reg</code></dt> +<dd><p>Convert the 64-bit value in <code>src_reg</code> to little-endian. +</p></dd> +<dt><code>dst_reg = be16 src_reg</code></dt> +<dd><p>Convert the 16-bit value in <code>src_reg</code> to big-endian. +</p></dd> +<dt><code>dst_reg = be32 src_reg</code></dt> +<dd><p>Convert the 32-bit value in <code>src_reg</code> to big-endian. +</p></dd> +<dt><code>dst_reg = be64 src_reg</code></dt> +<dd><p>Convert the 64-bit value in <code>src_reg</code> to big-endian. +</p></dd> +</dl> + +<a name="g_t64_002dbit-load-and-pseudo-maps-1"></a> +<h4 class="subsubsection">9.7.5.4 64-bit load and pseudo maps</h4> + +<dl compact="compact"> +<dt><code>dst_reg = imm64 ll</code></dt> +<dd><p>Load the given signed 64-bit immediate, or pseudo map descriptor, to +the destination register <code>dst_reg</code>. +</p></dd> +</dl> + +<a name="Load-instructions-for-socket-filters-1"></a> +<h4 class="subsubsection">9.7.5.5 Load instructions for socket filters</h4> + +<dl compact="compact"> +<dt><code>r0 = *(u8 *)skb[imm32]</code></dt> +<dd><p>Absolute 8-bit load. +</p></dd> +<dt><code>r0 = *(u16 *)skb[imm32]</code></dt> +<dd><p>Absolute 16-bit load. +</p></dd> +<dt><code>r0 = *(u32 *)skb[imm32]</code></dt> +<dd><p>Absolute 32-bit load. +</p></dd> +<dt><code>r0 = *(u64 *)skb[imm32]</code></dt> +<dd><p>Absolute 64-bit load. +</p></dd> +<dt><code>r0 = *(u8 *)skb[src_reg + imm32]</code></dt> +<dd><p>Indirect 8-bit load. +</p></dd> +<dt><code>r0 = *(u16 *)skb[src_reg + imm32]</code></dt> +<dd><p>Indirect 16-bit load. +</p></dd> +<dt><code>r0 = *(u32 *)skb[src_reg + imm32]</code></dt> +<dd><p>Indirect 32-bit load. +</p></dd> +<dt><code>r0 = *(u64 *)skb[src_reg + imm32]</code></dt> +<dd><p>Indirect 64-bit load. +</p></dd> +</dl> + +<a name="Generic-load_002fstore-instructions-1"></a> +<h4 class="subsubsection">9.7.5.6 Generic load/store instructions</h4> + +<dl compact="compact"> +<dt><code>dst_reg = *(u8 *)(src_reg + offset16)</code></dt> +<dd><p>Generic 8-bit load. +</p></dd> +<dt><code>dst_reg = *(u16 *)(src_reg + offset16)</code></dt> +<dd><p>Generic 16-bit load. +</p></dd> +<dt><code>dst_reg = *(u32 *)(src_reg + offset16)</code></dt> +<dd><p>Generic 32-bit load. +</p></dd> +<dt><code>dst_reg = *(u64 *)(src_reg + offset16)</code></dt> +<dd><p>Generic 64-bit load. +</p></dd> +<dt><code>*(u8 *)(dst_reg + offset16) = src_reg</code></dt> +<dd><p>Generic 8-bit store. +</p></dd> +<dt><code>*(u16 *)(dst_reg + offset16) = src_reg</code></dt> +<dd><p>Generic 16-bit store. +</p></dd> +<dt><code>*(u32 *)(dst_reg + offset16) = src_reg</code></dt> +<dd><p>Generic 32-bit store. +</p></dd> +<dt><code>*(u64 *)(dst_reg + offset16) = src_reg</code></dt> +<dd><p>Generic 64-bit store. +</p></dd> +</dl> + +<a name="Jump-instructions-1"></a> +<h4 class="subsubsection">9.7.5.7 Jump instructions</h4> + +<dl compact="compact"> +<dt><code>goto disp16</code></dt> +<dd><p>Jump-always. +</p></dd> +<dt><code>if dst_reg == (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if equal. +</p></dd> +<dt><code>if dst_reg & (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if signed equal. +</p></dd> +<dt><code>if dst_reg != (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if not equal. +</p></dd> +<dt><code>if dst_reg > (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if bigger, unsigned. +</p></dd> +<dt><code>if dst_reg < (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if smaller, unsigned. +</p></dd> +<dt><code>if dst_reg >= (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if bigger or equal, unsigned. +</p></dd> +<dt><code>if dst_reg <= (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if smaller or equal, unsigned. +</p></dd> +<dt><code>if dst_reg s> (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if bigger, signed. +</p></dd> +<dt><code>if dst_reg s< (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if smaller, signed. +</p></dd> +<dt><code>if dst_reg s>= (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if bigger or equal, signed. +</p></dd> +<dt><code>if dst_reg s<= (imm32|src_reg) goto disp16</code></dt> +<dd><p>Jump if smaller or equal, signed. +</p></dd> +<dt><code>call imm32</code></dt> +<dd><p>Jump and link. +</p></dd> +<dt><code>exit</code></dt> +<dd><p>Terminate the eBPF program. +</p></dd> +</dl> + +<a name="Atomic-instructions-1"></a> +<h4 class="subsubsection">9.7.5.8 Atomic instructions</h4> + +<dl compact="compact"> +<dt><code>lock *(u64 *)(dst_reg + offset16) += src_reg</code></dt> +<dd><p>Exchange-and-add a 64-bit value at the specified location. +</p></dd> +<dt><code>lock *(u32 *)(dst_reg + offset16) += src_reg</code></dt> +<dd><p>Exchange-and-add a 32-bit value at the specified location. +</p></dd> +</dl> + + +<hr> +<a name="CR16_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#CRIS_002dDependent" accesskey="n" rel="next">CRIS-Dependent</a>, Previous: <a href="#BPF_002dDependent" accesskey="p" rel="previous">BPF-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="CR16-Dependent-Features"></a> +<h3 class="section">9.8 CR16 Dependent Features</h3> + +<a name="index-CR16-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#CR16-Operand-Qualifiers" accesskey="1">CR16 Operand Qualifiers</a>:</td><td> </td><td align="left" valign="top">CR16 Machine Operand Qualifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#CR16-Syntax" accesskey="2">CR16 Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax for the CR16 +</td></tr> +</table> + +<hr> +<a name="CR16-Operand-Qualifiers"></a> +<div class="header"> +<p> +Next: <a href="#CR16-Syntax" accesskey="n" rel="next">CR16 Syntax</a>, Up: <a href="#CR16_002dDependent" accesskey="u" rel="up">CR16-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="CR16-Operand-Qualifiers-1"></a> +<h4 class="subsection">9.8.1 CR16 Operand Qualifiers</h4> +<a name="index-CR16-Operand-Qualifiers"></a> + +<p>The National Semiconductor CR16 target of <code>as</code> has a few machine dependent operand qualifiers. +</p> +<p>Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The <code>@</code> is required. CR16 architecture uses one of the following expression qualifiers: +</p> +<dl compact="compact"> +<dt><code>s</code></dt> +<dd><p>- <code>Specifies expression operand type as small</code> +</p></dd> +<dt><code>m</code></dt> +<dd><p>- <code>Specifies expression operand type as medium</code> +</p></dd> +<dt><code>l</code></dt> +<dd><p>- <code>Specifies expression operand type as large</code> +</p></dd> +<dt><code>c</code></dt> +<dd><p>- <code>Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.</code> +</p></dd> +<dt><code>got/GOT</code></dt> +<dd><p>- <code>Specifies the CR16 Assembler generates a relocation entry for the operand, offset from Global Offset Table. The linker uses this relocation entry to update the operand address at link time</code> +</p></dd> +<dt><code>cgot/cGOT</code></dt> +<dd><p>- <code>Specifies the CompactRISC Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.</code> +</p></dd> +</dl> + +<p>CR16 target operand qualifiers and its size (in bits): +</p> +<dl compact="compact"> +<dt>‘<samp>Immediate Operand: s</samp>’</dt> +<dd><p>4 bits. +</p> +</dd> +<dt>‘<samp>Immediate Operand: m</samp>’</dt> +<dd><p>16 bits, for movb and movw instructions. +</p> +</dd> +<dt>‘<samp>Immediate Operand: m</samp>’</dt> +<dd><p>20 bits, movd instructions. +</p> +</dd> +<dt>‘<samp>Immediate Operand: l</samp>’</dt> +<dd><p>32 bits. +</p> +</dd> +<dt>‘<samp>Absolute Operand: s</samp>’</dt> +<dd><p>Illegal specifier for this operand. +</p> +</dd> +<dt>‘<samp>Absolute Operand: m</samp>’</dt> +<dd><p>20 bits, movd instructions. +</p> +</dd> +<dt>‘<samp>Displacement Operand: s</samp>’</dt> +<dd><p>8 bits. +</p> +</dd> +<dt>‘<samp>Displacement Operand: m</samp>’</dt> +<dd><p>16 bits. +</p> +</dd> +<dt>‘<samp>Displacement Operand: l</samp>’</dt> +<dd><p>24 bits. +</p> +</dd> +</dl> + +<p>For example: +</p><div class="example"> +<pre class="example">1 <code>movw $_myfun@c,r1</code> + + This loads the address of _myfun, shifted right by 1, into r1. + +2 <code>movd $_myfun@c,(r2,r1)</code> + + This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. + +3 <code>_myfun_ptr:</code> + <code>.long _myfun@c</code> + <code>loadd _myfun_ptr, (r1,r0)</code> + <code>jal (r1,r0)</code> + + This .long directive, the address of _myfunc, shifted right by 1 at link time. + +4 <code>loadd _data1@GOT(r12), (r1,r0)</code> + + This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. + +5 <code>loadd _myfunc@cGOT(r12), (r1,r0)</code> + + This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. +</pre></div> + +<hr> +<a name="CR16-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#CR16-Operand-Qualifiers" accesskey="p" rel="previous">CR16 Operand Qualifiers</a>, Up: <a href="#CR16_002dDependent" accesskey="u" rel="up">CR16-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="CR16-Syntax-1"></a> +<h4 class="subsection">9.8.2 CR16 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#CR16_002dChars" accesskey="1">CR16-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="CR16_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#CR16-Syntax" accesskey="u" rel="up">CR16 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-6"></a> +<h4 class="subsubsection">9.8.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-CR16"></a> +<a name="index-CR16-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ on a line indicates the start of a comment +that extends to the end of the current line. If the ‘<samp>#</samp>’ appears +as the first character of a line, the whole line is treated as a +comment, but in this case the line can also be a logical line number +directive (see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-CR16"></a> +<a name="index-statement-separator_002c-CR16"></a> +<a name="index-CR16-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="CRIS_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#C_002dSKY_002dDependent" accesskey="n" rel="next">C-SKY-Dependent</a>, Previous: <a href="#CR16_002dDependent" accesskey="p" rel="previous">CR16-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="CRIS-Dependent-Features"></a> +<h3 class="section">9.9 CRIS Dependent Features</h3> + +<a name="index-CRIS-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#CRIS_002dOpts" accesskey="1">CRIS-Opts</a>:</td><td> </td><td align="left" valign="top">Command-line Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#CRIS_002dExpand" accesskey="2">CRIS-Expand</a>:</td><td> </td><td align="left" valign="top">Instruction expansion +</td></tr> +<tr><td align="left" valign="top">• <a href="#CRIS_002dSymbols" accesskey="3">CRIS-Symbols</a>:</td><td> </td><td align="left" valign="top">Symbols +</td></tr> +<tr><td align="left" valign="top">• <a href="#CRIS_002dSyntax" accesskey="4">CRIS-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +</table> + +<hr> +<a name="CRIS_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#CRIS_002dExpand" accesskey="n" rel="next">CRIS-Expand</a>, Up: <a href="#CRIS_002dDependent" accesskey="u" rel="up">CRIS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Command_002dline-Options"></a> +<h4 class="subsection">9.9.1 Command-line Options</h4> + +<a name="index-options_002c-CRIS"></a> +<a name="index-CRIS-options"></a> +<p>The CRIS version of <code>as</code> has these +machine-dependent command-line options. +</p> +<a name="index-_002d_002demulation_003dcriself-command_002dline-option_002c-CRIS"></a> +<a name="index-_002d_002demulation_003dcrisaout-command_002dline-option_002c-CRIS"></a> +<a name="index-CRIS-_002d_002demulation_003dcriself-command_002dline-option"></a> +<a name="index-CRIS-_002d_002demulation_003dcrisaout-command_002dline-option"></a> + +<p>The format of the generated object files can be either ELF or +a.out, specified by the command-line options +<samp>--emulation=crisaout</samp> and <samp>--emulation=criself</samp>. +The default is ELF (criself), unless <code>as</code> has been +configured specifically for a.out by using the configuration +name <code>cris-axis-aout</code>. +</p> +<a name="index-_002d_002dunderscore-command_002dline-option_002c-CRIS"></a> +<a name="index-_002d_002dno_002dunderscore-command_002dline-option_002c-CRIS"></a> +<a name="index-CRIS-_002d_002dunderscore-command_002dline-option"></a> +<a name="index-CRIS-_002d_002dno_002dunderscore-command_002dline-option"></a> +<p>There are two different link-incompatible ELF object file +variants for CRIS, for use in environments where symbols are +expected to be prefixed by a leading ‘<samp>_</samp>’ character and for +environments without such a symbol prefix. The variant used for +GNU/Linux port has no symbol prefix. Which variant to produce +is specified by either of the options <samp>--underscore</samp> and +<samp>--no-underscore</samp>. The default is <samp>--underscore</samp>. +Since symbols in CRIS a.out objects are expected to have a +‘<samp>_</samp>’ prefix, specifying <samp>--no-underscore</samp> when +generating a.out objects is an error. Besides the object format +difference, the effect of this option is to parse register names +differently (see <a href="#crisnous">crisnous</a>). The <samp>--no-underscore</samp> +option makes a ‘<samp>$</samp>’ register prefix mandatory. +</p> +<a name="index-_002d_002dpic-command_002dline-option_002c-CRIS"></a> +<a name="index-CRIS-_002d_002dpic-command_002dline-option"></a> +<a name="index-Position_002dindependent-code_002c-CRIS"></a> +<a name="index-CRIS-position_002dindependent-code"></a> +<p>The option <samp>--pic</samp> must be passed to <code>as</code> in +order to recognize the symbol syntax used for ELF (SVR4 PIC) +position-independent-code (see <a href="#crispic">crispic</a>). This will also +affect expansion of instructions. The expansion with +<samp>--pic</samp> will use PC-relative rather than (slightly +faster) absolute addresses in those expansions. This option is only +valid when generating ELF format object files. +</p> +<a name="index-_002d_002dmarch_003darchitecture-command_002dline-option_002c-CRIS"></a> +<a name="index-CRIS-_002d_002dmarch_003darchitecture-command_002dline-option"></a> +<a name="index-Architecture-variant-option_002c-CRIS"></a> +<a name="index-CRIS-architecture-variant-option"></a> +<p>The option <samp>--march=<var>architecture</var></samp> +<a name="march_002doption"></a>specifies the recognized instruction set +and recognized register names. It also controls the +architecture type of the object file. Valid values for +<var>architecture</var> are: +</p><dl compact="compact"> +<dt><code>v0_v10</code></dt> +<dd><p>All instructions and register names for any architecture variant +in the set v0…v10 are recognized. This is the +default if the target is configured as cris-*. +</p> +</dd> +<dt><code>v10</code></dt> +<dd><p>Only instructions and register names for CRIS v10 (as found in +ETRAX 100 LX) are recognized. This is the default if the target +is configured as crisv10-*. +</p> +</dd> +<dt><code>v32</code></dt> +<dd><p>Only instructions and register names for CRIS v32 (code name +Guinness) are recognized. This is the default if the target is +configured as crisv32-*. This value implies +<samp>--no-mul-bug-abort</samp>. (A subsequent +<samp>--mul-bug-abort</samp> will turn it back on.) +</p> +</dd> +<dt><code>common_v10_v32</code></dt> +<dd><p>Only instructions with register names and addressing modes with +opcodes common to the v10 and v32 are recognized. +</p></dd> +</dl> + +<a name="index-_002dN-command_002dline-option_002c-CRIS"></a> +<a name="index-CRIS-_002dN-command_002dline-option"></a> +<p>When <samp>-N</samp> is specified, <code>as</code> will emit a +warning when a 16-bit branch instruction is expanded into a +32-bit multiple-instruction construct (see <a href="#CRIS_002dExpand">CRIS-Expand</a>). +</p> +<a name="index-_002d_002dno_002dmul_002dbug_002dabort-command_002dline-option_002c-CRIS"></a> +<a name="index-_002d_002dmul_002dbug_002dabort-command_002dline-option_002c-CRIS"></a> +<a name="index-CRIS-_002d_002dno_002dmul_002dbug_002dabort-command_002dline-option"></a> +<a name="index-CRIS-_002d_002dmul_002dbug_002dabort-command_002dline-option"></a> + +<p>Some versions of the CRIS v10, for example in the Etrax 100 LX, +contain a bug that causes destabilizing memory accesses when a +multiply instruction is executed with certain values in the +first operand just before a cache-miss. When the +<samp>--mul-bug-abort</samp> command-line option is active (the +default value), <code>as</code> will refuse to assemble a file +containing a multiply instruction at a dangerous offset, one +that could be the last on a cache-line, or is in a section with +insufficient alignment. This placement checking does not catch +any case where the multiply instruction is dangerously placed +because it is located in a delay-slot. The +<samp>--mul-bug-abort</samp> command-line option turns off the +checking. +</p> +<hr> +<a name="CRIS_002dExpand"></a> +<div class="header"> +<p> +Next: <a href="#CRIS_002dSymbols" accesskey="n" rel="next">CRIS-Symbols</a>, Previous: <a href="#CRIS_002dOpts" accesskey="p" rel="previous">CRIS-Opts</a>, Up: <a href="#CRIS_002dDependent" accesskey="u" rel="up">CRIS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-expansion"></a> +<h4 class="subsection">9.9.2 Instruction expansion</h4> + +<a name="index-instruction-expansion_002c-CRIS"></a> +<a name="index-CRIS-instruction-expansion"></a> +<p><code>as</code> will silently choose an instruction that fits +the operand size for ‘<samp>[register+constant]</samp>’ operands. For +example, the offset <code>127</code> in <code>move.d [r3+127],r4</code> fits +in an instruction using a signed-byte offset. Similarly, +<code>move.d [r2+32767],r1</code> will generate an instruction using a +16-bit offset. For symbolic expressions and constants that do +not fit in 16 bits including the sign bit, a 32-bit offset is +generated. +</p> +<p>For branches, <code>as</code> will expand from a 16-bit branch +instruction into a sequence of instructions that can reach a +full 32-bit address. Since this does not correspond to a single +instruction, such expansions can optionally be warned about. +See <a href="#CRIS_002dOpts">CRIS-Opts</a>. +</p> +<p>If the operand is found to fit the range, a <code>lapc</code> mnemonic +will translate to a <code>lapcq</code> instruction. Use <code>lapc.d</code> +to force the 32-bit <code>lapc</code> instruction. +</p> +<p>Similarly, the <code>addo</code> mnemonic will translate to the +shortest fitting instruction of <code>addoq</code>, <code>addo.w</code> and +<code>addo.d</code>, when used with a operand that is a constant known +at assembly time. +</p> +<hr> +<a name="CRIS_002dSymbols"></a> +<div class="header"> +<p> +Next: <a href="#CRIS_002dSyntax" accesskey="n" rel="next">CRIS-Syntax</a>, Previous: <a href="#CRIS_002dExpand" accesskey="p" rel="previous">CRIS-Expand</a>, Up: <a href="#CRIS_002dDependent" accesskey="u" rel="up">CRIS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbols-3"></a> +<h4 class="subsection">9.9.3 Symbols</h4> +<a name="index-Symbols_002c-built_002din_002c-CRIS"></a> +<a name="index-Symbols_002c-CRIS_002c-built_002din"></a> +<a name="index-CRIS-built_002din-symbols"></a> +<a name="index-Built_002din-symbols_002c-CRIS"></a> + +<p>Some symbols are defined by the assembler. They’re intended to +be used in conditional assembly, for example: +</p><div class="smallexample"> +<pre class="smallexample"> .if ..asm.arch.cris.v32 + <var>code for CRIS v32</var> + .elseif ..asm.arch.cris.common_v10_v32 + <var>code common to CRIS v32 and CRIS v10</var> + .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 + <var>code for v10</var> + .else + .error "Code needs to be added here." + .endif +</pre></div> + +<p>These symbols are defined in the assembler, reflecting +command-line options, either when specified or the default. +They are always defined, to 0 or 1. +</p><dl compact="compact"> +<dt><code>..asm.arch.cris.any_v0_v10</code></dt> +<dd><p>This symbol is non-zero when <samp>--march=v0_v10</samp> is specified +or the default. +</p> +</dd> +<dt><code>..asm.arch.cris.common_v10_v32</code></dt> +<dd><p>Set according to the option <samp>--march=common_v10_v32</samp>. +</p> +</dd> +<dt><code>..asm.arch.cris.v10</code></dt> +<dd><p>Reflects the option <samp>--march=v10</samp>. +</p> +</dd> +<dt><code>..asm.arch.cris.v32</code></dt> +<dd><p>Corresponds to <samp>--march=v10</samp>. +</p></dd> +</dl> + +<p>Speaking of symbols, when a symbol is used in code, it can have +a suffix modifying its value for use in position-independent +code. See <a href="#CRIS_002dPic">CRIS-Pic</a>. +</p> +<hr> +<a name="CRIS_002dSyntax"></a> +<div class="header"> +<p> +Previous: <a href="#CRIS_002dSymbols" accesskey="p" rel="previous">CRIS-Symbols</a>, Up: <a href="#CRIS_002dDependent" accesskey="u" rel="up">CRIS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-9"></a> +<h4 class="subsection">9.9.4 Syntax</h4> + +<p>There are different aspects of the CRIS assembly syntax. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#CRIS_002dChars" accesskey="1">CRIS-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#CRIS_002dPic" accesskey="2">CRIS-Pic</a>:</td><td> </td><td align="left" valign="top">Position-Independent Code Symbols +</td></tr> +<tr><td align="left" valign="top">• <a href="#CRIS_002dRegs" accesskey="3">CRIS-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#CRIS_002dPseudos" accesskey="4">CRIS-Pseudos</a>:</td><td> </td><td align="left" valign="top">Assembler Directives +</td></tr> +</table> + +<hr> +<a name="CRIS_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#CRIS_002dPic" accesskey="n" rel="next">CRIS-Pic</a>, Up: <a href="#CRIS_002dSyntax" accesskey="u" rel="up">CRIS-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-7"></a> +<h4 class="subsubsection">9.9.4.1 Special Characters</h4> +<a name="index-line-comment-characters_002c-CRIS"></a> +<a name="index-CRIS-line-comment-characters"></a> + +<p>The character ‘<samp>#</samp>’ is a line comment character. It starts a +comment if and only if it is placed at the beginning of a line. +</p> +<p>A ‘<samp>;</samp>’ character starts a comment anywhere on the line, +causing all characters up to the end of the line to be ignored. +</p> +<p>A ‘<samp>@</samp>’ character is handled as a line separator equivalent +to a logical new-line character (except in a comment), so +separate instructions can be specified on a single line. +</p> +<hr> +<a name="CRIS_002dPic"></a> +<div class="header"> +<p> +Next: <a href="#CRIS_002dRegs" accesskey="n" rel="next">CRIS-Regs</a>, Previous: <a href="#CRIS_002dChars" accesskey="p" rel="previous">CRIS-Chars</a>, Up: <a href="#CRIS_002dSyntax" accesskey="u" rel="up">CRIS-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbols-in-position_002dindependent-code"></a> +<h4 class="subsubsection">9.9.4.2 Symbols in position-independent code</h4> +<a name="index-Symbols-in-position_002dindependent-code_002c-CRIS"></a> +<a name="index-CRIS-symbols-in-position_002dindependent-code"></a> +<a name="index-Position_002dindependent-code_002c-symbols-in_002c-CRIS"></a> + +<p>When generating <a name="crispic"></a>position-independent code (SVR4 +PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu +shared libraries, symbol +suffixes are used to specify what kind of run-time symbol lookup +will be used, expressed in the object as different +<em>relocation types</em>. Usually, all absolute symbol values +must be located in a table, the <em>global offset table</em>, +leaving the code position-independent; independent of values of +global symbols and independent of the address of the code. The +suffix modifies the value of the symbol, into for example an +index into the global offset table where the real symbol value +is entered, or a PC-relative value, or a value relative to the +start of the global offset table. All symbol suffixes start +with the character ‘<samp>:</samp>’ (omitted in the list below). Every +symbol use in code or a read-only section must therefore have a +PIC suffix to enable a useful shared library to be created. +Usually, these constructs must not be used with an additive +constant offset as is usually allowed, i.e. no 4 as in +<code>symbol + 4</code> is allowed. This restriction is checked at +link-time, not at assembly-time. +</p> +<dl compact="compact"> +<dt><code>GOT</code></dt> +<dd> +<p>Attaching this suffix to a symbol in an instruction causes the +symbol to be entered into the global offset table. The value is +a 32-bit index for that symbol into the global offset table. +The name of the corresponding relocation is +‘<samp>R_CRIS_32_GOT</samp>’. Example: <code>move.d +[$r0+extsym:GOT],$r9</code> +</p> +</dd> +<dt><code>GOT16</code></dt> +<dd> +<p>Same as for ‘<samp>GOT</samp>’, but the value is a 16-bit index into the +global offset table. The corresponding relocation is +‘<samp>R_CRIS_16_GOT</samp>’. Example: <code>move.d +[$r0+asymbol:GOT16],$r10</code> +</p> +</dd> +<dt><code>PLT</code></dt> +<dd> +<p>This suffix is used for function symbols. It causes a +<em>procedure linkage table</em>, an array of code stubs, to be +created at the time the shared object is created or linked +against, together with a global offset table entry. The value +is a pc-relative offset to the corresponding stub code in the +procedure linkage table. This arrangement causes the run-time +symbol resolver to be called to look up and set the value of the +symbol the first time the function is called (at latest; +depending environment variables). It is only safe to leave the +symbol unresolved this way if all references are function calls. +The name of the relocation is ‘<samp>R_CRIS_32_PLT_PCREL</samp>’. +Example: <code>add.d fnname:PLT,$pc</code> +</p> +</dd> +<dt><code>PLTG</code></dt> +<dd> +<p>Like PLT, but the value is relative to the beginning of the +global offset table. The relocation is +‘<samp>R_CRIS_32_PLT_GOTREL</samp>’. Example: <code>move.d +fnname:PLTG,$r3</code> +</p> +</dd> +<dt><code>GOTPLT</code></dt> +<dd> +<p>Similar to ‘<samp>PLT</samp>’, but the value of the symbol is a 32-bit +index into the global offset table. This is somewhat of a mix +between the effect of the ‘<samp>GOT</samp>’ and the ‘<samp>PLT</samp>’ suffix; +the difference to ‘<samp>GOT</samp>’ is that there will be a procedure +linkage table entry created, and that the symbol is assumed to +be a function entry and will be resolved by the run-time +resolver as with ‘<samp>PLT</samp>’. The relocation is +‘<samp>R_CRIS_32_GOTPLT</samp>’. Example: <code>jsr +[$r0+fnname:GOTPLT]</code> +</p> +</dd> +<dt><code>GOTPLT16</code></dt> +<dd> +<p>A variant of ‘<samp>GOTPLT</samp>’ giving a 16-bit value. Its +relocation name is ‘<samp>R_CRIS_16_GOTPLT</samp>’. Example: <code>jsr +[$r0+fnname:GOTPLT16]</code> +</p> +</dd> +<dt><code>GOTOFF</code></dt> +<dd> +<p>This suffix must only be attached to a local symbol, but may be +used in an expression adding an offset. The value is the +address of the symbol relative to the start of the global offset +table. The relocation name is ‘<samp>R_CRIS_32_GOTREL</samp>’. +Example: <code>move.d [$r0+localsym:GOTOFF],r3</code> +</p></dd> +</dl> + +<hr> +<a name="CRIS_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#CRIS_002dPseudos" accesskey="n" rel="next">CRIS-Pseudos</a>, Previous: <a href="#CRIS_002dPic" accesskey="p" rel="previous">CRIS-Pic</a>, Up: <a href="#CRIS_002dSyntax" accesskey="u" rel="up">CRIS-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-names"></a> +<h4 class="subsubsection">9.9.4.3 Register names</h4> +<a name="index-register-names_002c-CRIS"></a> +<a name="index-CRIS-register-names"></a> + +<p>A ‘<samp>$</samp>’ character may always prefix a general or special +register name in an instruction operand but is mandatory when +the option <samp>--no-underscore</samp> is specified or when the +<code>.syntax register_prefix</code> directive is in effect +(see <a href="#crisnous">crisnous</a>). Register names are case-insensitive. +</p> +<hr> +<a name="CRIS_002dPseudos"></a> +<div class="header"> +<p> +Previous: <a href="#CRIS_002dRegs" accesskey="p" rel="previous">CRIS-Regs</a>, Up: <a href="#CRIS_002dSyntax" accesskey="u" rel="up">CRIS-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives-1"></a> +<h4 class="subsubsection">9.9.4.4 Assembler Directives</h4> +<a name="index-assembler-directives_002c-CRIS"></a> +<a name="index-pseudo_002dops_002c-CRIS"></a> +<a name="index-CRIS-assembler-directives"></a> +<a name="index-CRIS-pseudo_002dops"></a> + +<p>There are a few CRIS-specific pseudo-directives in addition to +the generic ones. See <a href="#Pseudo-Ops">Pseudo Ops</a>. Constants emitted by +pseudo-directives are in little-endian order for CRIS. There is +no support for floating-point-specific directives for CRIS. +</p> +<dl compact="compact"> +<dt><code>.dword EXPRESSIONS</code></dt> +<dd><a name="index-assembler-directive-_002edword_002c-CRIS"></a> +<a name="index-pseudo_002dop-_002edword_002c-CRIS"></a> +<a name="index-CRIS-assembler-directive-_002edword"></a> +<a name="index-CRIS-pseudo_002dop-_002edword"></a> + +<p>The <code>.dword</code> directive is a synonym for <code>.int</code>, +expecting zero or more EXPRESSIONS, separated by commas. For +each expression, a 32-bit little-endian constant is emitted. +</p> +</dd> +<dt><code>.syntax ARGUMENT</code></dt> +<dd><a name="index-assembler-directive-_002esyntax_002c-CRIS"></a> +<a name="index-pseudo_002dop-_002esyntax_002c-CRIS"></a> +<a name="index-CRIS-assembler-directive-_002esyntax"></a> +<a name="index-CRIS-pseudo_002dop-_002esyntax"></a> +<p>The <code>.syntax</code> directive takes as <var>ARGUMENT</var> one of the +following case-sensitive choices. +</p> +<dl compact="compact"> +<dt><code>no_register_prefix</code></dt> +<dd> +<p>The <code>.syntax no_register_prefix</code> <a name="crisnous"></a>directive +makes a ‘<samp>$</samp>’ character prefix on all registers optional. It +overrides a previous setting, including the corresponding effect +of the option <samp>--no-underscore</samp>. If this directive is +used when ordinary symbols do not have a ‘<samp>_</samp>’ character +prefix, care must be taken to avoid ambiguities whether an +operand is a register or a symbol; using symbols with names the +same as general or special registers then invoke undefined +behavior. +</p> +</dd> +<dt><code>register_prefix</code></dt> +<dd> +<p>This directive makes a ‘<samp>$</samp>’ character prefix on all +registers mandatory. It overrides a previous setting, including +the corresponding effect of the option <samp>--underscore</samp>. +</p> +</dd> +<dt><code>leading_underscore</code></dt> +<dd> +<p>This is an assertion directive, emitting an error if the +<samp>--no-underscore</samp> option is in effect. +</p> +</dd> +<dt><code>no_leading_underscore</code></dt> +<dd> +<p>This is the opposite of the <code>.syntax leading_underscore</code> +directive and emits an error if the option <samp>--underscore</samp> +is in effect. +</p></dd> +</dl> + +</dd> +<dt><code>.arch ARGUMENT</code></dt> +<dd><a name="index-assembler-directive-_002earch_002c-CRIS"></a> +<a name="index-pseudo_002dop-_002earch_002c-CRIS"></a> +<a name="index-CRIS-assembler-directive-_002earch"></a> +<a name="index-CRIS-pseudo_002dop-_002earch"></a> +<p>This is an assertion directive, giving an error if the specified +<var>ARGUMENT</var> is not the same as the specified or default value +for the <samp>--march=<var>architecture</var></samp> option +(see <a href="#march_002doption">march-option</a>). +</p> +</dd> +</dl> + +<hr> +<a name="C_002dSKY_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#D10V_002dDependent" accesskey="n" rel="next">D10V-Dependent</a>, Previous: <a href="#CRIS_002dDependent" accesskey="p" rel="previous">CRIS-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="C_002dSKY-Dependent-Features"></a> +<h3 class="section">9.10 C-SKY Dependent Features</h3> + +<a name="index-C_002dSKY-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#C_002dSKY-Options" accesskey="1">C-SKY Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#C_002dSKY-Syntax" accesskey="2">C-SKY Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +</table> + +<hr> +<a name="C_002dSKY-Options"></a> +<div class="header"> +<p> +Next: <a href="#C_002dSKY-Syntax" accesskey="n" rel="next">C-SKY Syntax</a>, Up: <a href="#C_002dSKY_002dDependent" accesskey="u" rel="up">C-SKY-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-7"></a> +<h4 class="subsection">9.10.1 Options</h4> +<a name="index-C_002dSKY-options"></a> +<a name="index-options-for-C_002dSKY"></a> + +<dl compact="compact"> +<dd> +<a name="index-march-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-march=<var>archname</var></code></dt> +<dd><p>Assemble for architecture <var>archname</var>. The <samp>--help</samp> option +lists valid values for <var>archname</var>. +</p> +<a name="index-mcpu-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mcpu=<var>cpuname</var></code></dt> +<dd><p>Assemble for architecture <var>cpuname</var>. The <samp>--help</samp> option +lists valid values for <var>cpuname</var>. +</p> +<a name="index-EL-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mlittle_002dendian-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-EL</code></dt> +<dt><code>-mlittle-endian</code></dt> +<dd><p>Generate little-endian output. +</p> +<a name="index-EB-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mbig_002dendian-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-EB</code></dt> +<dt><code>-mbig-endian</code></dt> +<dd><p>Generate big-endian output. +</p> +<a name="index-fpic-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-pic-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-fpic</code></dt> +<dt><code>-pic</code></dt> +<dd><p>Generate position-independent code. +</p> +<a name="index-mljump-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002dljump-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mljump</code></dt> +<dt><code>-mno-ljump</code></dt> +<dd><p>Enable/disable transformation of the short branch instructions +<code>jbf</code>, <code>jbt</code>, and <code>jbr</code> to <code>jmpi</code>. +This option is for V2 processors only. +It is ignored on CK801 and CK802 targets, which do not support the <code>jmpi</code> +instruction, and is enabled by default for other processors. +</p> +<a name="index-mbranch_002dstub-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002dbranch_002dstub-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mbranch-stub</code></dt> +<dt><code>-mno-branch-stub</code></dt> +<dd><p>Pass through <code>R_CKCORE_PCREL_IMM26BY2</code> relocations for <code>bsr</code> +instructions to the linker. +</p> +<p>This option is only available for bare-metal C-SKY V2 ELF targets, +where it is enabled by default. It cannot be used in code that will be +dynamically linked against shared libraries. +</p> +<a name="index-force2bsr-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mforce2bsr-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-no_002dforce2bsr-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002dforce2bsr-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-force2bsr</code></dt> +<dt><code>-mforce2bsr</code></dt> +<dt><code>-no-force2bsr</code></dt> +<dt><code>-mno-force2bsr</code></dt> +<dd><p>Enable/disable transformation of <code>jbsr</code> instructions to <code>bsr</code>. +This option is always enabled (and <samp>-mno-force2bsr</samp> is ignored) +for CK801/CK802 targets. It is also always enabled when +<samp>-mbranch-stub</samp> is in effect. +</p> +<a name="index-jsri2bsr-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mjsri2bsr-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-no_002djsri2bsr-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002djsri2bsr-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-jsri2bsr</code></dt> +<dt><code>-mjsri2bsr</code></dt> +<dt><code>-no-jsri2bsr</code></dt> +<dt><code>-mno-jsri2bsr</code></dt> +<dd><p>Enable/disable transformation of <code>jsri</code> instructions to <code>bsr</code>. +This option is enabled by default. +</p> +<a name="index-mnolrw-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002dlrw-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mnolrw</code></dt> +<dt><code>-mno-lrw</code></dt> +<dd><p>Enable/disable transformation of <code>lrw</code> instructions into a +<code>movih</code>/<code>ori</code> pair. +</p> +<a name="index-melrw-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002delrw-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-melrw</code></dt> +<dt><code>-mno-elrw</code></dt> +<dd><p>Enable/disable extended <code>lrw</code> instructions. +This option is enabled by default for CK800-series processors. +</p> +<a name="index-mlaf-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mliterals_002dafter_002dfunc-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002dlaf-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002dliterals_002dafter_002dfunc-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mlaf</code></dt> +<dt><code>-mliterals-after-func</code></dt> +<dt><code>-mno-laf</code></dt> +<dt><code>-mno-literals-after-func</code></dt> +<dd><p>Enable/disable placement of literal pools after each function. +</p> +<a name="index-mlabr-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mliterals_002dafter_002dbr-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002dlabr-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mnoliterals_002dafter_002dbr-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mlabr</code></dt> +<dt><code>-mliterals-after-br</code></dt> +<dt><code>-mno-labr</code></dt> +<dt><code>-mnoliterals-after-br</code></dt> +<dd><p>Enable/disable placement of literal pools after unconditional branches. +This option is enabled by default. +</p> +<a name="index-mistack-command_002dline-option_002c-C_002dSKY"></a> +<a name="index-mno_002distack-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mistack</code></dt> +<dt><code>-mno-istack</code></dt> +<dd><p>Enable/disable interrupt stack instructions. This option is enabled by +default on CK801, CK802, and CK802 processors. +</p> +</dd> +</dl> + +<p>The following options explicitly enable certain optional instructions. +These features are also enabled implicitly by using <code>-mcpu=</code> to specify +a processor that supports it. +</p> +<dl compact="compact"> +<dd><a name="index-mhard_002dfloat-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mhard-float</code></dt> +<dd><p>Enable hard float instructions. +</p> +<a name="index-mmp-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mmp</code></dt> +<dd><p>Enable multiprocessor instructions. +</p> +<a name="index-mcp-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mcp</code></dt> +<dd><p>Enable coprocessor instructions. +</p> +<a name="index-mcache-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mcache</code></dt> +<dd><p>Enable cache prefetch instruction. +</p> +<a name="index-msecurity-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-msecurity</code></dt> +<dd><p>Enable C-SKY security instructions. +</p> +<a name="index-mtrust-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mtrust</code></dt> +<dd><p>Enable C-SKY trust instructions. +</p> +<a name="index-mdsp-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mdsp</code></dt> +<dd><p>Enable DSP instructions. +</p> +<a name="index-medsp-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-medsp</code></dt> +<dd><p>Enable enhanced DSP instructions. +</p> +<a name="index-mvdsp-command_002dline-option_002c-C_002dSKY"></a> +</dd> +<dt><code>-mvdsp</code></dt> +<dd><p>Enable vector DSP instructions. +</p> +</dd> +</dl> + +<hr> +<a name="C_002dSKY-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#C_002dSKY-Options" accesskey="p" rel="previous">C-SKY Options</a>, Up: <a href="#C_002dSKY_002dDependent" accesskey="u" rel="up">C-SKY-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-10"></a> +<h4 class="subsection">9.10.2 Syntax</h4> + +<p><code>as</code> implements the standard C-SKY assembler syntax +documented in the +<cite>C-SKY V2 CPU Applications Binary Interface Standards Manual</cite>. +</p> + +<hr> +<a name="D10V_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#D30V_002dDependent" accesskey="n" rel="next">D30V-Dependent</a>, Previous: <a href="#C_002dSKY_002dDependent" accesskey="p" rel="previous">C-SKY-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="D10V-Dependent-Features"></a> +<h3 class="section">9.11 D10V Dependent Features</h3> + +<a name="index-D10V-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#D10V_002dOpts" accesskey="1">D10V-Opts</a>:</td><td> </td><td align="left" valign="top">D10V Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#D10V_002dSyntax" accesskey="2">D10V-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#D10V_002dFloat" accesskey="3">D10V-Float</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#D10V_002dOpcodes" accesskey="4">D10V-Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="D10V_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#D10V_002dSyntax" accesskey="n" rel="next">D10V-Syntax</a>, Up: <a href="#D10V_002dDependent" accesskey="u" rel="up">D10V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="D10V-Options"></a> +<h4 class="subsection">9.11.1 D10V Options</h4> +<a name="index-options_002c-D10V"></a> +<a name="index-D10V-options"></a> +<p>The Mitsubishi D10V version of <code>as</code> has a few machine +dependent options. +</p> +<dl compact="compact"> +<dt>‘<samp>-O</samp>’</dt> +<dd><p>The D10V can often execute two sub-instructions in parallel. When this option +is used, <code>as</code> will attempt to optimize its output by detecting when +instructions can be executed in parallel. +</p></dd> +<dt>‘<samp>--nowarnswap</samp>’</dt> +<dd><p>To optimize execution performance, <code>as</code> will sometimes swap the +order of instructions. Normally this generates a warning. When this option +is used, no warning will be generated when instructions are swapped. +</p></dd> +<dt>‘<samp>--gstabs-packing</samp>’</dt> +<dt>‘<samp>--no-gstabs-packing</samp>’</dt> +<dd><p><code>as</code> packs adjacent short instructions into a single packed +instruction. ‘<samp>--no-gstabs-packing</samp>’ turns instruction packing off if +‘<samp>--gstabs</samp>’ is specified as well; ‘<samp>--gstabs-packing</samp>’ (the +default) turns instruction packing on even when ‘<samp>--gstabs</samp>’ is +specified. +</p></dd> +</dl> + +<hr> +<a name="D10V_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#D10V_002dFloat" accesskey="n" rel="next">D10V-Float</a>, Previous: <a href="#D10V_002dOpts" accesskey="p" rel="previous">D10V-Opts</a>, Up: <a href="#D10V_002dDependent" accesskey="u" rel="up">D10V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-11"></a> +<h4 class="subsection">9.11.2 Syntax</h4> +<a name="index-D10V-syntax"></a> +<a name="index-syntax_002c-D10V"></a> + +<p>The D10V syntax is based on the syntax in Mitsubishi’s D10V architecture manual. +The differences are detailed below. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#D10V_002dSize" accesskey="1">D10V-Size</a>:</td><td> </td><td align="left" valign="top">Size Modifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#D10V_002dSubs" accesskey="2">D10V-Subs</a>:</td><td> </td><td align="left" valign="top">Sub-Instructions +</td></tr> +<tr><td align="left" valign="top">• <a href="#D10V_002dChars" accesskey="3">D10V-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#D10V_002dRegs" accesskey="4">D10V-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#D10V_002dAddressing" accesskey="5">D10V-Addressing</a>:</td><td> </td><td align="left" valign="top">Addressing Modes +</td></tr> +<tr><td align="left" valign="top">• <a href="#D10V_002dWord" accesskey="6">D10V-Word</a>:</td><td> </td><td align="left" valign="top">@WORD Modifier +</td></tr> +</table> + + +<hr> +<a name="D10V_002dSize"></a> +<div class="header"> +<p> +Next: <a href="#D10V_002dSubs" accesskey="n" rel="next">D10V-Subs</a>, Up: <a href="#D10V_002dSyntax" accesskey="u" rel="up">D10V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Size-Modifiers"></a> +<h4 class="subsubsection">9.11.2.1 Size Modifiers</h4> +<a name="index-D10V-size-modifiers"></a> +<a name="index-size-modifiers_002c-D10V"></a> +<p>The D10V version of <code>as</code> uses the instruction names in the D10V +Architecture Manual. However, the names in the manual are sometimes ambiguous. +There are instruction names that can assemble to a short or long form opcode. +How does the assembler pick the correct form? <code>as</code> will always pick the +smallest form if it can. When dealing with a symbol that is not defined yet when a +line is being assembled, it will always use the long form. If you need to force the +assembler to use either the short or long form of the instruction, you can append +either ‘<samp>.s</samp>’ (short) or ‘<samp>.l</samp>’ (long) to it. For example, if you are writing +an assembly program and you want to do a branch to a symbol that is defined later +in your program, you can write ‘<samp>bra.s foo</samp>’. +Objdump and GDB will always append ‘<samp>.s</samp>’ or ‘<samp>.l</samp>’ to instructions which +have both short and long forms. +</p> +<hr> +<a name="D10V_002dSubs"></a> +<div class="header"> +<p> +Next: <a href="#D10V_002dChars" accesskey="n" rel="next">D10V-Chars</a>, Previous: <a href="#D10V_002dSize" accesskey="p" rel="previous">D10V-Size</a>, Up: <a href="#D10V_002dSyntax" accesskey="u" rel="up">D10V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Sub_002dInstructions"></a> +<h4 class="subsubsection">9.11.2.2 Sub-Instructions</h4> +<a name="index-D10V-sub_002dinstructions"></a> +<a name="index-sub_002dinstructions_002c-D10V"></a> +<p>The D10V assembler takes as input a series of instructions, either one-per-line, +or in the special two-per-line format described in the next section. Some of these +instructions will be short-form or sub-instructions. These sub-instructions can be packed +into a single instruction. The assembler will do this automatically. It will also detect +when it should not pack instructions. For example, when a label is defined, the next +instruction will never be packaged with the previous one. Whenever a branch and link +instruction is called, it will not be packaged with the next instruction so the return +address will be valid. Nops are automatically inserted when necessary. +</p> +<p>If you do not want the assembler automatically making these decisions, you can control +the packaging and execution type (parallel or sequential) with the special execution +symbols described in the next section. +</p> +<hr> +<a name="D10V_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#D10V_002dRegs" accesskey="n" rel="next">D10V-Regs</a>, Previous: <a href="#D10V_002dSubs" accesskey="p" rel="previous">D10V-Subs</a>, Up: <a href="#D10V_002dSyntax" accesskey="u" rel="up">D10V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-8"></a> +<h4 class="subsubsection">9.11.2.3 Special Characters</h4> +<a name="index-line-comment-character_002c-D10V"></a> +<a name="index-D10V-line-comment-character"></a> +<p>A semicolon (‘<samp>;</samp>’) can be used anywhere on a line to start a +comment that extends to the end of the line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line, the whole line +is treated as a comment, but in this case the line could also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-sub_002dinstruction-ordering_002c-D10V"></a> +<a name="index-D10V-sub_002dinstruction-ordering"></a> +<p>Sub-instructions may be executed in order, in reverse-order, or in parallel. +Instructions listed in the standard one-per-line format will be executed sequentially. +To specify the executing order, use the following symbols: +</p><dl compact="compact"> +<dt>‘<samp>-></samp>’</dt> +<dd><p>Sequential with instruction on the left first. +</p></dd> +<dt>‘<samp><-</samp>’</dt> +<dd><p>Sequential with instruction on the right first. +</p></dd> +<dt>‘<samp>||</samp>’</dt> +<dd><p>Parallel +</p></dd> +</dl> +<p>The D10V syntax allows either one instruction per line, one instruction per line with +the execution symbol, or two instructions per line. For example +</p><dl compact="compact"> +<dt><code>abs a1 -> abs r0</code></dt> +<dd><p>Execute these sequentially. The instruction on the right is in the right +container and is executed second. +</p></dd> +<dt><code>abs r0 <- abs a1</code></dt> +<dd><p>Execute these reverse-sequentially. The instruction on the right is in the right +container, and is executed first. +</p></dd> +<dt><code>ld2w r2,@r8+ || mac a0,r0,r7</code></dt> +<dd><p>Execute these in parallel. +</p></dd> +<dt><code>ld2w r2,@r8+ ||</code></dt> +<dt><code>mac a0,r0,r7</code></dt> +<dd><p>Two-line format. Execute these in parallel. +</p></dd> +<dt><code>ld2w r2,@r8+</code></dt> +<dt><code>mac a0,r0,r7</code></dt> +<dd><p>Two-line format. Execute these sequentially. Assembler will +put them in the proper containers. +</p></dd> +<dt><code>ld2w r2,@r8+ -></code></dt> +<dt><code>mac a0,r0,r7</code></dt> +<dd><p>Two-line format. Execute these sequentially. Same as above but +second instruction will always go into right container. +</p></dd> +</dl> +<a name="index-symbol-names_002c-_0024-in"></a> +<a name="index-_0024-in-symbol-names"></a> +<p>Since ‘<samp>$</samp>’ has no special meaning, you may use it in symbol names. +</p> +<hr> +<a name="D10V_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#D10V_002dAddressing" accesskey="n" rel="next">D10V-Addressing</a>, Previous: <a href="#D10V_002dChars" accesskey="p" rel="previous">D10V-Chars</a>, Up: <a href="#D10V_002dSyntax" accesskey="u" rel="up">D10V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-6"></a> +<h4 class="subsubsection">9.11.2.4 Register Names</h4> +<a name="index-D10V-registers"></a> +<a name="index-registers_002c-D10V"></a> +<p>You can use the predefined symbols ‘<samp>r0</samp>’ through ‘<samp>r15</samp>’ to refer to the D10V +registers. You can also use ‘<samp>sp</samp>’ as an alias for ‘<samp>r15</samp>’. The accumulators +are ‘<samp>a0</samp>’ and ‘<samp>a1</samp>’. There are special register-pair names that may +optionally be used in opcodes that require even-numbered registers. Register names are +not case sensitive. +</p> +<p>Register Pairs +</p><dl compact="compact"> +<dt><code>r0-r1</code></dt> +<dt><code>r2-r3</code></dt> +<dt><code>r4-r5</code></dt> +<dt><code>r6-r7</code></dt> +<dt><code>r8-r9</code></dt> +<dt><code>r10-r11</code></dt> +<dt><code>r12-r13</code></dt> +<dt><code>r14-r15</code></dt> +</dl> + +<p>The D10V also has predefined symbols for these control registers and status bits: +</p><dl compact="compact"> +<dt><code>psw</code></dt> +<dd><p>Processor Status Word +</p></dd> +<dt><code>bpsw</code></dt> +<dd><p>Backup Processor Status Word +</p></dd> +<dt><code>pc</code></dt> +<dd><p>Program Counter +</p></dd> +<dt><code>bpc</code></dt> +<dd><p>Backup Program Counter +</p></dd> +<dt><code>rpt_c</code></dt> +<dd><p>Repeat Count +</p></dd> +<dt><code>rpt_s</code></dt> +<dd><p>Repeat Start address +</p></dd> +<dt><code>rpt_e</code></dt> +<dd><p>Repeat End address +</p></dd> +<dt><code>mod_s</code></dt> +<dd><p>Modulo Start address +</p></dd> +<dt><code>mod_e</code></dt> +<dd><p>Modulo End address +</p></dd> +<dt><code>iba</code></dt> +<dd><p>Instruction Break Address +</p></dd> +<dt><code>f0</code></dt> +<dd><p>Flag 0 +</p></dd> +<dt><code>f1</code></dt> +<dd><p>Flag 1 +</p></dd> +<dt><code>c</code></dt> +<dd><p>Carry flag +</p></dd> +</dl> + +<hr> +<a name="D10V_002dAddressing"></a> +<div class="header"> +<p> +Next: <a href="#D10V_002dWord" accesskey="n" rel="next">D10V-Word</a>, Previous: <a href="#D10V_002dRegs" accesskey="p" rel="previous">D10V-Regs</a>, Up: <a href="#D10V_002dSyntax" accesskey="u" rel="up">D10V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Addressing-Modes"></a> +<h4 class="subsubsection">9.11.2.5 Addressing Modes</h4> +<a name="index-addressing-modes_002c-D10V"></a> +<a name="index-D10V-addressing-modes"></a> +<p><code>as</code> understands the following addressing modes for the D10V. +<code>R<var>n</var></code> in the following refers to any of the numbered +registers, but <em>not</em> the control registers. +</p><dl compact="compact"> +<dt><code>R<var>n</var></code></dt> +<dd><p>Register direct +</p></dd> +<dt><code>@R<var>n</var></code></dt> +<dd><p>Register indirect +</p></dd> +<dt><code>@R<var>n</var>+</code></dt> +<dd><p>Register indirect with post-increment +</p></dd> +<dt><code>@R<var>n</var>-</code></dt> +<dd><p>Register indirect with post-decrement +</p></dd> +<dt><code>@-SP</code></dt> +<dd><p>Register indirect with pre-decrement +</p></dd> +<dt><code>@(<var>disp</var>, R<var>n</var>)</code></dt> +<dd><p>Register indirect with displacement +</p></dd> +<dt><code><var>addr</var></code></dt> +<dd><p>PC relative address (for branch or rep). +</p></dd> +<dt><code>#<var>imm</var></code></dt> +<dd><p>Immediate data (the ‘<samp>#</samp>’ is optional and ignored) +</p></dd> +</dl> + +<hr> +<a name="D10V_002dWord"></a> +<div class="header"> +<p> +Previous: <a href="#D10V_002dAddressing" accesskey="p" rel="previous">D10V-Addressing</a>, Up: <a href="#D10V_002dSyntax" accesskey="u" rel="up">D10V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t_0040WORD-Modifier"></a> +<h4 class="subsubsection">9.11.2.6 @WORD Modifier</h4> +<a name="index-D10V-_0040word-modifier"></a> +<a name="index-_0040word-modifier_002c-D10V"></a> +<p>Any symbol followed by <code>@word</code> will be replaced by the symbol’s value +shifted right by 2. This is used in situations such as loading a register +with the address of a function (or any other code fragment). For example, if +you want to load a register with the location of the function <code>main</code> then +jump to that function, you could do it as follows: +</p><div class="smallexample"> +<pre class="smallexample">ldi r2, main@word +jmp r2 +</pre></div> + +<hr> +<a name="D10V_002dFloat"></a> +<div class="header"> +<p> +Next: <a href="#D10V_002dOpcodes" accesskey="n" rel="next">D10V-Opcodes</a>, Previous: <a href="#D10V_002dSyntax" accesskey="p" rel="previous">D10V-Syntax</a>, Up: <a href="#D10V_002dDependent" accesskey="u" rel="up">D10V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-3"></a> +<h4 class="subsection">9.11.3 Floating Point</h4> +<a name="index-floating-point_002c-D10V"></a> +<a name="index-D10V-floating-point"></a> +<p>The D10V has no hardware floating point, but the <code>.float</code> and <code>.double</code> +directives generates <small>IEEE</small> floating-point numbers for compatibility +with other development tools. +</p> +<hr> +<a name="D10V_002dOpcodes"></a> +<div class="header"> +<p> +Previous: <a href="#D10V_002dFloat" accesskey="p" rel="previous">D10V-Float</a>, Up: <a href="#D10V_002dDependent" accesskey="u" rel="up">D10V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-6"></a> +<h4 class="subsection">9.11.4 Opcodes</h4> +<a name="index-D10V-opcode-summary"></a> +<a name="index-opcode-summary_002c-D10V"></a> +<a name="index-mnemonics_002c-D10V"></a> +<a name="index-instruction-summary_002c-D10V"></a> +<p>For detailed information on the D10V machine instruction set, see +<cite>D10V Architecture: A VLIW Microprocessor for Multimedia Applications</cite> +(Mitsubishi Electric Corp.). +<code>as</code> implements all the standard D10V opcodes. The only changes are those +described in the section on size modifiers +</p> + +<hr> +<a name="D30V_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Epiphany_002dDependent" accesskey="n" rel="next">Epiphany-Dependent</a>, Previous: <a href="#D10V_002dDependent" accesskey="p" rel="previous">D10V-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="D30V-Dependent-Features"></a> +<h3 class="section">9.12 D30V Dependent Features</h3> + +<a name="index-D30V-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#D30V_002dOpts" accesskey="1">D30V-Opts</a>:</td><td> </td><td align="left" valign="top">D30V Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#D30V_002dSyntax" accesskey="2">D30V-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#D30V_002dFloat" accesskey="3">D30V-Float</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#D30V_002dOpcodes" accesskey="4">D30V-Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="D30V_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#D30V_002dSyntax" accesskey="n" rel="next">D30V-Syntax</a>, Up: <a href="#D30V_002dDependent" accesskey="u" rel="up">D30V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="D30V-Options"></a> +<h4 class="subsection">9.12.1 D30V Options</h4> +<a name="index-options_002c-D30V"></a> +<a name="index-D30V-options"></a> +<p>The Mitsubishi D30V version of <code>as</code> has a few machine +dependent options. +</p> +<dl compact="compact"> +<dt>‘<samp>-O</samp>’</dt> +<dd><p>The D30V can often execute two sub-instructions in parallel. When this option +is used, <code>as</code> will attempt to optimize its output by detecting when +instructions can be executed in parallel. +</p> +</dd> +<dt>‘<samp>-n</samp>’</dt> +<dd><p>When this option is used, <code>as</code> will issue a warning every +time it adds a nop instruction. +</p> +</dd> +<dt>‘<samp>-N</samp>’</dt> +<dd><p>When this option is used, <code>as</code> will issue a warning if it +needs to insert a nop after a 32-bit multiply before a load or 16-bit +multiply instruction. +</p></dd> +</dl> + +<hr> +<a name="D30V_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#D30V_002dFloat" accesskey="n" rel="next">D30V-Float</a>, Previous: <a href="#D30V_002dOpts" accesskey="p" rel="previous">D30V-Opts</a>, Up: <a href="#D30V_002dDependent" accesskey="u" rel="up">D30V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-12"></a> +<h4 class="subsection">9.12.2 Syntax</h4> +<a name="index-D30V-syntax"></a> +<a name="index-syntax_002c-D30V"></a> + +<p>The D30V syntax is based on the syntax in Mitsubishi’s D30V architecture manual. +The differences are detailed below. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#D30V_002dSize" accesskey="1">D30V-Size</a>:</td><td> </td><td align="left" valign="top">Size Modifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#D30V_002dSubs" accesskey="2">D30V-Subs</a>:</td><td> </td><td align="left" valign="top">Sub-Instructions +</td></tr> +<tr><td align="left" valign="top">• <a href="#D30V_002dChars" accesskey="3">D30V-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#D30V_002dGuarded" accesskey="4">D30V-Guarded</a>:</td><td> </td><td align="left" valign="top">Guarded Execution +</td></tr> +<tr><td align="left" valign="top">• <a href="#D30V_002dRegs" accesskey="5">D30V-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#D30V_002dAddressing" accesskey="6">D30V-Addressing</a>:</td><td> </td><td align="left" valign="top">Addressing Modes +</td></tr> +</table> + + +<hr> +<a name="D30V_002dSize"></a> +<div class="header"> +<p> +Next: <a href="#D30V_002dSubs" accesskey="n" rel="next">D30V-Subs</a>, Up: <a href="#D30V_002dSyntax" accesskey="u" rel="up">D30V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Size-Modifiers-1"></a> +<h4 class="subsubsection">9.12.2.1 Size Modifiers</h4> +<a name="index-D30V-size-modifiers"></a> +<a name="index-size-modifiers_002c-D30V"></a> +<p>The D30V version of <code>as</code> uses the instruction names in the D30V +Architecture Manual. However, the names in the manual are sometimes ambiguous. +There are instruction names that can assemble to a short or long form opcode. +How does the assembler pick the correct form? <code>as</code> will always pick the +smallest form if it can. When dealing with a symbol that is not defined yet when a +line is being assembled, it will always use the long form. If you need to force the +assembler to use either the short or long form of the instruction, you can append +either ‘<samp>.s</samp>’ (short) or ‘<samp>.l</samp>’ (long) to it. For example, if you are writing +an assembly program and you want to do a branch to a symbol that is defined later +in your program, you can write ‘<samp>bra.s foo</samp>’. +Objdump and GDB will always append ‘<samp>.s</samp>’ or ‘<samp>.l</samp>’ to instructions which +have both short and long forms. +</p> +<hr> +<a name="D30V_002dSubs"></a> +<div class="header"> +<p> +Next: <a href="#D30V_002dChars" accesskey="n" rel="next">D30V-Chars</a>, Previous: <a href="#D30V_002dSize" accesskey="p" rel="previous">D30V-Size</a>, Up: <a href="#D30V_002dSyntax" accesskey="u" rel="up">D30V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Sub_002dInstructions-1"></a> +<h4 class="subsubsection">9.12.2.2 Sub-Instructions</h4> +<a name="index-D30V-sub_002dinstructions"></a> +<a name="index-sub_002dinstructions_002c-D30V"></a> +<p>The D30V assembler takes as input a series of instructions, either one-per-line, +or in the special two-per-line format described in the next section. Some of these +instructions will be short-form or sub-instructions. These sub-instructions can be packed +into a single instruction. The assembler will do this automatically. It will also detect +when it should not pack instructions. For example, when a label is defined, the next +instruction will never be packaged with the previous one. Whenever a branch and link +instruction is called, it will not be packaged with the next instruction so the return +address will be valid. Nops are automatically inserted when necessary. +</p> +<p>If you do not want the assembler automatically making these decisions, you can control +the packaging and execution type (parallel or sequential) with the special execution +symbols described in the next section. +</p> +<hr> +<a name="D30V_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#D30V_002dGuarded" accesskey="n" rel="next">D30V-Guarded</a>, Previous: <a href="#D30V_002dSubs" accesskey="p" rel="previous">D30V-Subs</a>, Up: <a href="#D30V_002dSyntax" accesskey="u" rel="up">D30V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-9"></a> +<h4 class="subsubsection">9.12.2.3 Special Characters</h4> +<a name="index-line-comment-character_002c-D30V"></a> +<a name="index-D30V-line-comment-character"></a> +<p>A semicolon (‘<samp>;</samp>’) can be used anywhere on a line to start a +comment that extends to the end of the line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line, the whole line +is treated as a comment, but in this case the line could also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-sub_002dinstruction-ordering_002c-D30V"></a> +<a name="index-D30V-sub_002dinstruction-ordering"></a> +<p>Sub-instructions may be executed in order, in reverse-order, or in parallel. +Instructions listed in the standard one-per-line format will be executed +sequentially unless you use the ‘<samp>-O</samp>’ option. +</p> +<p>To specify the executing order, use the following symbols: +</p><dl compact="compact"> +<dt>‘<samp>-></samp>’</dt> +<dd><p>Sequential with instruction on the left first. +</p> +</dd> +<dt>‘<samp><-</samp>’</dt> +<dd><p>Sequential with instruction on the right first. +</p> +</dd> +<dt>‘<samp>||</samp>’</dt> +<dd><p>Parallel +</p></dd> +</dl> + +<p>The D30V syntax allows either one instruction per line, one instruction per line with +the execution symbol, or two instructions per line. For example +</p><dl compact="compact"> +<dt><code>abs r2,r3 -> abs r4,r5</code></dt> +<dd><p>Execute these sequentially. The instruction on the right is in the right +container and is executed second. +</p> +</dd> +<dt><code>abs r2,r3 <- abs r4,r5</code></dt> +<dd><p>Execute these reverse-sequentially. The instruction on the right is in the right +container, and is executed first. +</p> +</dd> +<dt><code>abs r2,r3 || abs r4,r5</code></dt> +<dd><p>Execute these in parallel. +</p> +</dd> +<dt><code>ldw r2,@(r3,r4) ||</code></dt> +<dt><code>mulx r6,r8,r9</code></dt> +<dd><p>Two-line format. Execute these in parallel. +</p> +</dd> +<dt><code>mulx a0,r8,r9</code></dt> +<dt><code>stw r2,@(r3,r4)</code></dt> +<dd><p>Two-line format. Execute these sequentially unless ‘<samp>-O</samp>’ option is +used. If the ‘<samp>-O</samp>’ option is used, the assembler will determine if +the instructions could be done in parallel (the above two instructions +can be done in parallel), and if so, emit them as parallel instructions. +The assembler will put them in the proper containers. In the above +example, the assembler will put the ‘<samp>stw</samp>’ instruction in left +container and the ‘<samp>mulx</samp>’ instruction in the right container. +</p> +</dd> +<dt><code>stw r2,@(r3,r4) -></code></dt> +<dt><code>mulx a0,r8,r9</code></dt> +<dd><p>Two-line format. Execute the ‘<samp>stw</samp>’ instruction followed by the +‘<samp>mulx</samp>’ instruction sequentially. The first instruction goes in the +left container and the second instruction goes into right container. +The assembler will give an error if the machine ordering constraints are +violated. +</p> +</dd> +<dt><code>stw r2,@(r3,r4) <-</code></dt> +<dt><code>mulx a0,r8,r9</code></dt> +<dd><p>Same as previous example, except that the ‘<samp>mulx</samp>’ instruction is +executed before the ‘<samp>stw</samp>’ instruction. +</p></dd> +</dl> + +<a name="index-symbol-names_002c-_0024-in-1"></a> +<a name="index-_0024-in-symbol-names-1"></a> +<p>Since ‘<samp>$</samp>’ has no special meaning, you may use it in symbol names. +</p> +<hr> +<a name="D30V_002dGuarded"></a> +<div class="header"> +<p> +Next: <a href="#D30V_002dRegs" accesskey="n" rel="next">D30V-Regs</a>, Previous: <a href="#D30V_002dChars" accesskey="p" rel="previous">D30V-Chars</a>, Up: <a href="#D30V_002dSyntax" accesskey="u" rel="up">D30V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Guarded-Execution"></a> +<h4 class="subsubsection">9.12.2.4 Guarded Execution</h4> +<a name="index-D30V-Guarded-Execution"></a> +<p><code>as</code> supports the full range of guarded execution +directives for each instruction. Just append the directive after the +instruction proper. The directives are: +</p> +<dl compact="compact"> +<dt>‘<samp>/tx</samp>’</dt> +<dd><p>Execute the instruction if flag f0 is true. +</p></dd> +<dt>‘<samp>/fx</samp>’</dt> +<dd><p>Execute the instruction if flag f0 is false. +</p></dd> +<dt>‘<samp>/xt</samp>’</dt> +<dd><p>Execute the instruction if flag f1 is true. +</p></dd> +<dt>‘<samp>/xf</samp>’</dt> +<dd><p>Execute the instruction if flag f1 is false. +</p></dd> +<dt>‘<samp>/tt</samp>’</dt> +<dd><p>Execute the instruction if both flags f0 and f1 are true. +</p></dd> +<dt>‘<samp>/tf</samp>’</dt> +<dd><p>Execute the instruction if flag f0 is true and flag f1 is false. +</p></dd> +</dl> + +<hr> +<a name="D30V_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#D30V_002dAddressing" accesskey="n" rel="next">D30V-Addressing</a>, Previous: <a href="#D30V_002dGuarded" accesskey="p" rel="previous">D30V-Guarded</a>, Up: <a href="#D30V_002dSyntax" accesskey="u" rel="up">D30V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-7"></a> +<h4 class="subsubsection">9.12.2.5 Register Names</h4> +<a name="index-D30V-registers"></a> +<a name="index-registers_002c-D30V"></a> +<p>You can use the predefined symbols ‘<samp>r0</samp>’ through ‘<samp>r63</samp>’ to refer +to the D30V registers. You can also use ‘<samp>sp</samp>’ as an alias for +‘<samp>r63</samp>’ and ‘<samp>link</samp>’ as an alias for ‘<samp>r62</samp>’. The accumulators +are ‘<samp>a0</samp>’ and ‘<samp>a1</samp>’. +</p> +<p>The D30V also has predefined symbols for these control registers and status bits: +</p><dl compact="compact"> +<dt><code>psw</code></dt> +<dd><p>Processor Status Word +</p></dd> +<dt><code>bpsw</code></dt> +<dd><p>Backup Processor Status Word +</p></dd> +<dt><code>pc</code></dt> +<dd><p>Program Counter +</p></dd> +<dt><code>bpc</code></dt> +<dd><p>Backup Program Counter +</p></dd> +<dt><code>rpt_c</code></dt> +<dd><p>Repeat Count +</p></dd> +<dt><code>rpt_s</code></dt> +<dd><p>Repeat Start address +</p></dd> +<dt><code>rpt_e</code></dt> +<dd><p>Repeat End address +</p></dd> +<dt><code>mod_s</code></dt> +<dd><p>Modulo Start address +</p></dd> +<dt><code>mod_e</code></dt> +<dd><p>Modulo End address +</p></dd> +<dt><code>iba</code></dt> +<dd><p>Instruction Break Address +</p></dd> +<dt><code>f0</code></dt> +<dd><p>Flag 0 +</p></dd> +<dt><code>f1</code></dt> +<dd><p>Flag 1 +</p></dd> +<dt><code>f2</code></dt> +<dd><p>Flag 2 +</p></dd> +<dt><code>f3</code></dt> +<dd><p>Flag 3 +</p></dd> +<dt><code>f4</code></dt> +<dd><p>Flag 4 +</p></dd> +<dt><code>f5</code></dt> +<dd><p>Flag 5 +</p></dd> +<dt><code>f6</code></dt> +<dd><p>Flag 6 +</p></dd> +<dt><code>f7</code></dt> +<dd><p>Flag 7 +</p></dd> +<dt><code>s</code></dt> +<dd><p>Same as flag 4 (saturation flag) +</p></dd> +<dt><code>v</code></dt> +<dd><p>Same as flag 5 (overflow flag) +</p></dd> +<dt><code>va</code></dt> +<dd><p>Same as flag 6 (sticky overflow flag) +</p></dd> +<dt><code>c</code></dt> +<dd><p>Same as flag 7 (carry/borrow flag) +</p></dd> +<dt><code>b</code></dt> +<dd><p>Same as flag 7 (carry/borrow flag) +</p></dd> +</dl> + +<hr> +<a name="D30V_002dAddressing"></a> +<div class="header"> +<p> +Previous: <a href="#D30V_002dRegs" accesskey="p" rel="previous">D30V-Regs</a>, Up: <a href="#D30V_002dSyntax" accesskey="u" rel="up">D30V-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Addressing-Modes-1"></a> +<h4 class="subsubsection">9.12.2.6 Addressing Modes</h4> +<a name="index-addressing-modes_002c-D30V"></a> +<a name="index-D30V-addressing-modes"></a> +<p><code>as</code> understands the following addressing modes for the D30V. +<code>R<var>n</var></code> in the following refers to any of the numbered +registers, but <em>not</em> the control registers. +</p><dl compact="compact"> +<dt><code>R<var>n</var></code></dt> +<dd><p>Register direct +</p></dd> +<dt><code>@R<var>n</var></code></dt> +<dd><p>Register indirect +</p></dd> +<dt><code>@R<var>n</var>+</code></dt> +<dd><p>Register indirect with post-increment +</p></dd> +<dt><code>@R<var>n</var>-</code></dt> +<dd><p>Register indirect with post-decrement +</p></dd> +<dt><code>@-SP</code></dt> +<dd><p>Register indirect with pre-decrement +</p></dd> +<dt><code>@(<var>disp</var>, R<var>n</var>)</code></dt> +<dd><p>Register indirect with displacement +</p></dd> +<dt><code><var>addr</var></code></dt> +<dd><p>PC relative address (for branch or rep). +</p></dd> +<dt><code>#<var>imm</var></code></dt> +<dd><p>Immediate data (the ‘<samp>#</samp>’ is optional and ignored) +</p></dd> +</dl> + +<hr> +<a name="D30V_002dFloat"></a> +<div class="header"> +<p> +Next: <a href="#D30V_002dOpcodes" accesskey="n" rel="next">D30V-Opcodes</a>, Previous: <a href="#D30V_002dSyntax" accesskey="p" rel="previous">D30V-Syntax</a>, Up: <a href="#D30V_002dDependent" accesskey="u" rel="up">D30V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-4"></a> +<h4 class="subsection">9.12.3 Floating Point</h4> +<a name="index-floating-point_002c-D30V"></a> +<a name="index-D30V-floating-point"></a> +<p>The D30V has no hardware floating point, but the <code>.float</code> and <code>.double</code> +directives generates <small>IEEE</small> floating-point numbers for compatibility +with other development tools. +</p> +<hr> +<a name="D30V_002dOpcodes"></a> +<div class="header"> +<p> +Previous: <a href="#D30V_002dFloat" accesskey="p" rel="previous">D30V-Float</a>, Up: <a href="#D30V_002dDependent" accesskey="u" rel="up">D30V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-7"></a> +<h4 class="subsection">9.12.4 Opcodes</h4> +<a name="index-D30V-opcode-summary"></a> +<a name="index-opcode-summary_002c-D30V"></a> +<a name="index-mnemonics_002c-D30V"></a> +<a name="index-instruction-summary_002c-D30V"></a> +<p>For detailed information on the D30V machine instruction set, see +<cite>D30V Architecture: A VLIW Microprocessor for Multimedia Applications</cite> +(Mitsubishi Electric Corp.). +<code>as</code> implements all the standard D30V opcodes. The only changes are those +described in the section on size modifiers +</p> + + +<hr> +<a name="Epiphany_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#H8_002f300_002dDependent" accesskey="n" rel="next">H8/300-Dependent</a>, Previous: <a href="#D30V_002dDependent" accesskey="p" rel="previous">D30V-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Epiphany-Dependent-Features"></a> +<h3 class="section">9.13 Epiphany Dependent Features</h3> + +<a name="index-Epiphany-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Epiphany-Options" accesskey="1">Epiphany Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#Epiphany-Syntax" accesskey="2">Epiphany Syntax</a>:</td><td> </td><td align="left" valign="top">Epiphany Syntax +</td></tr> +</table> + +<hr> +<a name="Epiphany-Options"></a> +<div class="header"> +<p> +Next: <a href="#Epiphany-Syntax" accesskey="n" rel="next">Epiphany Syntax</a>, Up: <a href="#Epiphany_002dDependent" accesskey="u" rel="up">Epiphany-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-8"></a> +<h4 class="subsection">9.13.1 Options</h4> + +<a name="index-Epiphany-options"></a> +<a name="index-options_002c-Epiphany"></a> +<p><code>as</code> has two additional command-line options for the Epiphany +architecture. +</p> +<dl compact="compact"> +<dd> +<a name="index-_002dmepiphany-command_002dline-option_002c-Epiphany"></a> +</dd> +<dt><code>-mepiphany</code></dt> +<dd><p>Specifies that the both 32 and 16 bit instructions are allowed. This is the +default behavior. +</p> +<a name="index-_002dmepiphany16-command_002dline-option_002c-Epiphany"></a> +</dd> +<dt><code>-mepiphany16</code></dt> +<dd><p>Restricts the permitted instructions to just the 16 bit set. +</p></dd> +</dl> + +<hr> +<a name="Epiphany-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#Epiphany-Options" accesskey="p" rel="previous">Epiphany Options</a>, Up: <a href="#Epiphany_002dDependent" accesskey="u" rel="up">Epiphany-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Epiphany-Syntax-1"></a> +<h4 class="subsection">9.13.2 Epiphany Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Epiphany_002dChars" accesskey="1">Epiphany-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="Epiphany_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#Epiphany-Syntax" accesskey="u" rel="up">Epiphany Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-10"></a> +<h4 class="subsubsection">9.13.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-Epiphany"></a> +<a name="index-Epiphany-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ on a line indicates the start +of a comment that extends to the end of the current line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-Epiphany"></a> +<a name="index-statement-separator_002c-Epiphany"></a> +<a name="index-Epiphany-line-separator"></a> +<p>The ‘<samp>`</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="H8_002f300_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#HPPA_002dDependent" accesskey="n" rel="next">HPPA-Dependent</a>, Previous: <a href="#Epiphany_002dDependent" accesskey="p" rel="previous">Epiphany-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="H8_002f300-Dependent-Features"></a> +<h3 class="section">9.14 H8/300 Dependent Features</h3> + +<a name="index-H8_002f300-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#H8_002f300-Options" accesskey="1">H8/300 Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#H8_002f300-Syntax" accesskey="2">H8/300 Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#H8_002f300-Floating-Point" accesskey="3">H8/300 Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#H8_002f300-Directives" accesskey="4">H8/300 Directives</a>:</td><td> </td><td align="left" valign="top">H8/300 Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#H8_002f300-Opcodes" accesskey="5">H8/300 Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="H8_002f300-Options"></a> +<div class="header"> +<p> +Next: <a href="#H8_002f300-Syntax" accesskey="n" rel="next">H8/300 Syntax</a>, Up: <a href="#H8_002f300_002dDependent" accesskey="u" rel="up">H8/300-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-9"></a> +<h4 class="subsection">9.14.1 Options</h4> + +<a name="index-H8_002f300-options"></a> +<a name="index-options_002c-H8_002f300"></a> +<p>The Renesas H8/300 version of <code>as</code> has one +machine-dependent option: +</p> +<dl compact="compact"> +<dt><code>-h-tick-hex</code></dt> +<dd><p>Support H’00 style hex constants in addition to 0x00 style. +</p> +</dd> +<dt><code>-mach=<var>name</var></code></dt> +<dd><p>Sets the H8300 machine variant. The following machine names +are recognised: +<code>h8300h</code>, +<code>h8300hn</code>, +<code>h8300s</code>, +<code>h8300sn</code>, +<code>h8300sx</code> and +<code>h8300sxn</code>. +</p> +</dd> +</dl> + +<hr> +<a name="H8_002f300-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#H8_002f300-Floating-Point" accesskey="n" rel="next">H8/300 Floating Point</a>, Previous: <a href="#H8_002f300-Options" accesskey="p" rel="previous">H8/300 Options</a>, Up: <a href="#H8_002f300_002dDependent" accesskey="u" rel="up">H8/300-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-13"></a> +<h4 class="subsection">9.14.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#H8_002f300_002dChars" accesskey="1">H8/300-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#H8_002f300_002dRegs" accesskey="2">H8/300-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#H8_002f300_002dAddressing" accesskey="3">H8/300-Addressing</a>:</td><td> </td><td align="left" valign="top">Addressing Modes +</td></tr> +</table> + +<hr> +<a name="H8_002f300_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#H8_002f300_002dRegs" accesskey="n" rel="next">H8/300-Regs</a>, Up: <a href="#H8_002f300-Syntax" accesskey="u" rel="up">H8/300 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-11"></a> +<h4 class="subsubsection">9.14.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-H8_002f300"></a> +<a name="index-H8_002f300-line-comment-character"></a> +<p>‘<samp>;</samp>’ is the line comment character. +</p> +<a name="index-line-separator_002c-H8_002f300"></a> +<a name="index-statement-separator_002c-H8_002f300"></a> +<a name="index-H8_002f300-line-separator"></a> +<p>‘<samp>$</samp>’ can be used instead of a newline to separate statements. +Therefore <em>you may not use ‘<samp>$</samp>’ in symbol names</em> on the H8/300. +</p> +<hr> +<a name="H8_002f300_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#H8_002f300_002dAddressing" accesskey="n" rel="next">H8/300-Addressing</a>, Previous: <a href="#H8_002f300_002dChars" accesskey="p" rel="previous">H8/300-Chars</a>, Up: <a href="#H8_002f300-Syntax" accesskey="u" rel="up">H8/300 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-8"></a> +<h4 class="subsubsection">9.14.2.2 Register Names</h4> + +<a name="index-H8_002f300-registers"></a> +<a name="index-register-names_002c-H8_002f300"></a> +<p>You can use predefined symbols of the form ‘<samp>r<var>n</var>h</samp>’ and +‘<samp>r<var>n</var>l</samp>’ to refer to the H8/300 registers as sixteen 8-bit +general-purpose registers. <var>n</var> is a digit from ‘<samp>0</samp>’ to +‘<samp>7</samp>’); for instance, both ‘<samp>r0h</samp>’ and ‘<samp>r7l</samp>’ are valid +register names. +</p> +<p>You can also use the eight predefined symbols ‘<samp>r<var>n</var></samp>’ to refer +to the H8/300 registers as 16-bit registers (you must use this form for +addressing). +</p> +<p>On the H8/300H, you can also use the eight predefined symbols +‘<samp>er<var>n</var></samp>’ (‘<samp>er0</samp>’ … ‘<samp>er7</samp>’) to refer to the 32-bit +general purpose registers. +</p> +<p>The two control registers are called <code>pc</code> (program counter; a +16-bit register, except on the H8/300H where it is 24 bits) and +<code>ccr</code> (condition code register; an 8-bit register). <code>r7</code> is +used as the stack pointer, and can also be called <code>sp</code>. +</p> +<hr> +<a name="H8_002f300_002dAddressing"></a> +<div class="header"> +<p> +Previous: <a href="#H8_002f300_002dRegs" accesskey="p" rel="previous">H8/300-Regs</a>, Up: <a href="#H8_002f300-Syntax" accesskey="u" rel="up">H8/300 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Addressing-Modes-2"></a> +<h4 class="subsubsection">9.14.2.3 Addressing Modes</h4> + +<a name="index-addressing-modes_002c-H8_002f300"></a> +<a name="index-H8_002f300-addressing-modes"></a> +<p>as understands the following addressing modes for the H8/300: +</p><dl compact="compact"> +<dt><code>r<var>n</var></code></dt> +<dd><p>Register direct +</p> +</dd> +<dt><code>@r<var>n</var></code></dt> +<dd><p>Register indirect +</p> +</dd> +<dt><code>@(<var>d</var>, r<var>n</var>)</code></dt> +<dt><code>@(<var>d</var>:16, r<var>n</var>)</code></dt> +<dt><code>@(<var>d</var>:24, r<var>n</var>)</code></dt> +<dd><p>Register indirect: 16-bit or 24-bit displacement <var>d</var> from register +<var>n</var>. (24-bit displacements are only meaningful on the H8/300H.) +</p> +</dd> +<dt><code>@r<var>n</var>+</code></dt> +<dd><p>Register indirect with post-increment +</p> +</dd> +<dt><code>@-r<var>n</var></code></dt> +<dd><p>Register indirect with pre-decrement +</p> +</dd> +<dt><code><code>@</code><var>aa</var></code></dt> +<dt><code><code>@</code><var>aa</var>:8</code></dt> +<dt><code><code>@</code><var>aa</var>:16</code></dt> +<dt><code><code>@</code><var>aa</var>:24</code></dt> +<dd><p>Absolute address <code>aa</code>. (The address size ‘<samp>:24</samp>’ only makes +sense on the H8/300H.) +</p> +</dd> +<dt><code>#<var>xx</var></code></dt> +<dt><code>#<var>xx</var>:8</code></dt> +<dt><code>#<var>xx</var>:16</code></dt> +<dt><code>#<var>xx</var>:32</code></dt> +<dd><p>Immediate data <var>xx</var>. You may specify the ‘<samp>:8</samp>’, ‘<samp>:16</samp>’, or +‘<samp>:32</samp>’ for clarity, if you wish; but <code>as</code> neither +requires this nor uses it—the data size required is taken from +context. +</p> +</dd> +<dt><code><code>@</code><code>@</code><var>aa</var></code></dt> +<dt><code><code>@</code><code>@</code><var>aa</var>:8</code></dt> +<dd><p>Memory indirect. You may specify the ‘<samp>:8</samp>’ for clarity, if you +wish; but <code>as</code> neither requires this nor uses it. +</p></dd> +</dl> + +<hr> +<a name="H8_002f300-Floating-Point"></a> +<div class="header"> +<p> +Next: <a href="#H8_002f300-Directives" accesskey="n" rel="next">H8/300 Directives</a>, Previous: <a href="#H8_002f300-Syntax" accesskey="p" rel="previous">H8/300 Syntax</a>, Up: <a href="#H8_002f300_002dDependent" accesskey="u" rel="up">H8/300-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-5"></a> +<h4 class="subsection">9.14.3 Floating Point</h4> + +<a name="index-floating-point_002c-H8_002f300-_0028IEEE_0029"></a> +<a name="index-H8_002f300-floating-point-_0028IEEE_0029"></a> +<p>The H8/300 family has no hardware floating point, but the <code>.float</code> +directive generates <small>IEEE</small> floating-point numbers for compatibility +with other development tools. +</p> +<hr> +<a name="H8_002f300-Directives"></a> +<div class="header"> +<p> +Next: <a href="#H8_002f300-Opcodes" accesskey="n" rel="next">H8/300 Opcodes</a>, Previous: <a href="#H8_002f300-Floating-Point" accesskey="p" rel="previous">H8/300 Floating Point</a>, Up: <a href="#H8_002f300_002dDependent" accesskey="u" rel="up">H8/300-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="H8_002f300-Machine-Directives"></a> +<h4 class="subsection">9.14.4 H8/300 Machine Directives</h4> + +<a name="index-H8_002f300-machine-directives-_0028none_0029"></a> +<a name="index-machine-directives_002c-H8_002f300-_0028none_0029"></a> +<a name="index-word-directive_002c-H8_002f300"></a> +<a name="index-int-directive_002c-H8_002f300"></a> +<p><code>as</code> has the following machine-dependent directives for +the H8/300: +</p> +<dl compact="compact"> +<dd><a name="index-H8_002f300H_002c-assembling-for"></a> +</dd> +<dt><code>.h8300h</code></dt> +<dd><p>Recognize and emit additional instructions for the H8/300H variant, and +also make <code>.int</code> emit 32-bit numbers rather than the usual (16-bit) +for the H8/300 family. +</p> +</dd> +<dt><code>.h8300s</code></dt> +<dd><p>Recognize and emit additional instructions for the H8S variant, and +also make <code>.int</code> emit 32-bit numbers rather than the usual (16-bit) +for the H8/300 family. +</p> +</dd> +<dt><code>.h8300hn</code></dt> +<dd><p>Recognize and emit additional instructions for the H8/300H variant in +normal mode, and also make <code>.int</code> emit 32-bit numbers rather than +the usual (16-bit) for the H8/300 family. +</p> +</dd> +<dt><code>.h8300sn</code></dt> +<dd><p>Recognize and emit additional instructions for the H8S variant in +normal mode, and also make <code>.int</code> emit 32-bit numbers rather than +the usual (16-bit) for the H8/300 family. +</p></dd> +</dl> + +<p>On the H8/300 family (including the H8/300H) ‘<samp>.word</samp>’ directives +generate 16-bit numbers. +</p> +<hr> +<a name="H8_002f300-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#H8_002f300-Directives" accesskey="p" rel="previous">H8/300 Directives</a>, Up: <a href="#H8_002f300_002dDependent" accesskey="u" rel="up">H8/300-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-8"></a> +<h4 class="subsection">9.14.5 Opcodes</h4> + +<a name="index-H8_002f300-opcode-summary"></a> +<a name="index-opcode-summary_002c-H8_002f300"></a> +<a name="index-mnemonics_002c-H8_002f300"></a> +<a name="index-instruction-summary_002c-H8_002f300"></a> +<p>For detailed information on the H8/300 machine instruction set, see +<cite>H8/300 Series Programming Manual</cite>. For information specific to +the H8/300H, see <cite>H8/300H Series Programming Manual</cite> (Renesas). +</p> +<p><code>as</code> implements all the standard H8/300 opcodes. No additional +pseudo-instructions are needed on this family. +</p> + +<a name="index-size-suffixes_002c-H8_002f300"></a> +<a name="index-H8_002f300-size-suffixes"></a> +<p>Four H8/300 instructions (<code>add</code>, <code>cmp</code>, <code>mov</code>, +<code>sub</code>) are defined with variants using the suffixes ‘<samp>.b</samp>’, +‘<samp>.w</samp>’, and ‘<samp>.l</samp>’ to specify the size of a memory operand. +<code>as</code> supports these suffixes, but does not require them; +since one of the operands is always a register, <code>as</code> can +deduce the correct size. +</p> +<p>For example, since <code>r0</code> refers to a 16-bit register, +</p><div class="example"> +<pre class="example">mov r0,@foo +</pre><pre class="example">is equivalent to +</pre><pre class="example">mov.w r0,@foo +</pre></div> + +<p>If you use the size suffixes, <code>as</code> issues a warning when +the suffix and the register size do not match. +</p> +<hr> +<a name="HPPA_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dDependent" accesskey="n" rel="next">i386-Dependent</a>, Previous: <a href="#H8_002f300_002dDependent" accesskey="p" rel="previous">H8/300-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="HPPA-Dependent-Features"></a> +<h3 class="section">9.15 HPPA Dependent Features</h3> + +<a name="index-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#HPPA-Notes" accesskey="1">HPPA Notes</a>:</td><td> </td><td align="left" valign="top">Notes +</td></tr> +<tr><td align="left" valign="top">• <a href="#HPPA-Options" accesskey="2">HPPA Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#HPPA-Syntax" accesskey="3">HPPA Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#HPPA-Floating-Point" accesskey="4">HPPA Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#HPPA-Directives" accesskey="5">HPPA Directives</a>:</td><td> </td><td align="left" valign="top">HPPA Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#HPPA-Opcodes" accesskey="6">HPPA Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="HPPA-Notes"></a> +<div class="header"> +<p> +Next: <a href="#HPPA-Options" accesskey="n" rel="next">HPPA Options</a>, Up: <a href="#HPPA_002dDependent" accesskey="u" rel="up">HPPA-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Notes-1"></a> +<h4 class="subsection">9.15.1 Notes</h4> +<p>As a back end for <small>GNU</small> <small>CC</small> <code>as</code> has been thoroughly tested and should +work extremely well. We have tested it only minimally on hand written assembly +code and no one has tested it much on the assembly output from the HP +compilers. +</p> +<p>The format of the debugging sections has changed since the original +<code>as</code> port (version 1.3X) was released; therefore, +you must rebuild all HPPA objects and libraries with the new +assembler so that you can debug the final executable. +</p> +<p>The HPPA <code>as</code> port generates a small subset of the relocations +available in the SOM and ELF object file formats. Additional relocation +support will be added as it becomes necessary. +</p> +<hr> +<a name="HPPA-Options"></a> +<div class="header"> +<p> +Next: <a href="#HPPA-Syntax" accesskey="n" rel="next">HPPA Syntax</a>, Previous: <a href="#HPPA-Notes" accesskey="p" rel="previous">HPPA Notes</a>, Up: <a href="#HPPA_002dDependent" accesskey="u" rel="up">HPPA-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-10"></a> +<h4 class="subsection">9.15.2 Options</h4> +<p><code>as</code> has no machine-dependent command-line options for the HPPA. +</p> +<a name="index-HPPA-Syntax"></a> +<hr> +<a name="HPPA-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#HPPA-Floating-Point" accesskey="n" rel="next">HPPA Floating Point</a>, Previous: <a href="#HPPA-Options" accesskey="p" rel="previous">HPPA Options</a>, Up: <a href="#HPPA_002dDependent" accesskey="u" rel="up">HPPA-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-14"></a> +<h4 class="subsection">9.15.3 Syntax</h4> +<p>The assembler syntax closely follows the HPPA instruction set +reference manual; assembler directives and general syntax closely follow the +HPPA assembly language reference manual, with a few noteworthy differences. +</p> +<p>First, a colon may immediately follow a label definition. This is +simply for compatibility with how most assembly language programmers +write code. +</p> +<p>Some obscure expression parsing problems may affect hand written code which +uses the <code>spop</code> instructions, or code which makes significant +use of the <code>!</code> line separator. +</p> +<p><code>as</code> is much less forgiving about missing arguments and other +similar oversights than the HP assembler. <code>as</code> notifies you +of missing arguments as syntax errors; this is regarded as a feature, not a +bug. +</p> +<p>Finally, <code>as</code> allows you to use an external symbol without +explicitly importing the symbol. <em>Warning:</em> in the future this will be +an error for HPPA targets. +</p> +<p>Special characters for HPPA targets include: +</p> +<p>‘<samp>;</samp>’ is the line comment character. +</p> +<p>‘<samp>!</samp>’ can be used instead of a newline to separate statements. +</p> +<p>Since ‘<samp>$</samp>’ has no special meaning, you may use it in symbol names. +</p> +<hr> +<a name="HPPA-Floating-Point"></a> +<div class="header"> +<p> +Next: <a href="#HPPA-Directives" accesskey="n" rel="next">HPPA Directives</a>, Previous: <a href="#HPPA-Syntax" accesskey="p" rel="previous">HPPA Syntax</a>, Up: <a href="#HPPA_002dDependent" accesskey="u" rel="up">HPPA-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-6"></a> +<h4 class="subsection">9.15.4 Floating Point</h4> +<a name="index-floating-point_002c-HPPA-_0028IEEE_0029"></a> +<a name="index-HPPA-floating-point-_0028IEEE_0029"></a> +<p>The HPPA family uses <small>IEEE</small> floating-point numbers. +</p> +<hr> +<a name="HPPA-Directives"></a> +<div class="header"> +<p> +Next: <a href="#HPPA-Opcodes" accesskey="n" rel="next">HPPA Opcodes</a>, Previous: <a href="#HPPA-Floating-Point" accesskey="p" rel="previous">HPPA Floating Point</a>, Up: <a href="#HPPA_002dDependent" accesskey="u" rel="up">HPPA-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="HPPA-Assembler-Directives"></a> +<h4 class="subsection">9.15.5 HPPA Assembler Directives</h4> + +<p><code>as</code> for the HPPA supports many additional directives for +compatibility with the native assembler. This section describes them only +briefly. For detailed information on HPPA-specific assembler directives, see +<cite>HP9000 Series 800 Assembly Language Reference Manual</cite> (HP 92432-90001). +</p> +<a name="index-HPPA-directives-not-supported"></a> +<p><code>as</code> does <em>not</em> support the following assembler directives +described in the HP manual: +</p> +<div class="example"> +<pre class="example">.endm .liston +.enter .locct +.leave .macro +.listoff +</pre></div> + +<a name="index-_002eparam-on-HPPA"></a> +<p>Beyond those implemented for compatibility, <code>as</code> supports one +additional assembler directive for the HPPA: <code>.param</code>. It conveys +register argument locations for static functions. Its syntax closely follows +the <code>.export</code> directive. +</p> +<a name="index-HPPA_002donly-directives"></a> +<p>These are the additional directives in <code>as</code> for the HPPA: +</p> +<dl compact="compact"> +<dt><code>.block <var>n</var></code></dt> +<dt><code>.blockz <var>n</var></code></dt> +<dd><p>Reserve <var>n</var> bytes of storage, and initialize them to zero. +</p> +</dd> +<dt><code>.call</code></dt> +<dd><p>Mark the beginning of a procedure call. Only the special case with <em>no +arguments</em> is allowed. +</p> +</dd> +<dt><code>.callinfo [ <var>param</var>=<var>value</var>, … ] [ <var>flag</var>, … ]</code></dt> +<dd><p>Specify a number of parameters and flags that define the environment for a +procedure. +</p> +<p><var>param</var> may be any of ‘<samp>frame</samp>’ (frame size), ‘<samp>entry_gr</samp>’ (end of +general register range), ‘<samp>entry_fr</samp>’ (end of float register range), +‘<samp>entry_sr</samp>’ (end of space register range). +</p> +<p>The values for <var>flag</var> are ‘<samp>calls</samp>’ or ‘<samp>caller</samp>’ (proc has +subroutines), ‘<samp>no_calls</samp>’ (proc does not call subroutines), ‘<samp>save_rp</samp>’ +(preserve return pointer), ‘<samp>save_sp</samp>’ (proc preserves stack pointer), +‘<samp>no_unwind</samp>’ (do not unwind this proc), ‘<samp>hpux_int</samp>’ (proc is interrupt +routine). +</p> +</dd> +<dt><code>.code</code></dt> +<dd><p>Assemble into the standard section called ‘<samp>$TEXT$</samp>’, subsection +‘<samp>$CODE$</samp>’. +</p> +</dd> +<dt><code>.copyright "<var>string</var>"</code></dt> +<dd><p>In the SOM object format, insert <var>string</var> into the object code, marked as a +copyright string. +</p> +</dd> +<dt><code>.copyright "<var>string</var>"</code></dt> +<dd><p>In the ELF object format, insert <var>string</var> into the object code, marked as a +version string. +</p> +</dd> +<dt><code>.enter</code></dt> +<dd><p>Not yet supported; the assembler rejects programs containing this directive. +</p> +</dd> +<dt><code>.entry</code></dt> +<dd><p>Mark the beginning of a procedure. +</p> +</dd> +<dt><code>.exit</code></dt> +<dd><p>Mark the end of a procedure. +</p> +</dd> +<dt><code>.export <var>name</var> [ ,<var>typ</var> ] [ ,<var>param</var>=<var>r</var> ]</code></dt> +<dd><p>Make a procedure <var>name</var> available to callers. <var>typ</var>, if present, must +be one of ‘<samp>absolute</samp>’, ‘<samp>code</samp>’ (ELF only, not SOM), ‘<samp>data</samp>’, +‘<samp>entry</samp>’, ‘<samp>data</samp>’, ‘<samp>entry</samp>’, ‘<samp>millicode</samp>’, ‘<samp>plabel</samp>’, +‘<samp>pri_prog</samp>’, or ‘<samp>sec_prog</samp>’. +</p> +<p><var>param</var>, if present, provides either relocation information for the +procedure arguments and result, or a privilege level. <var>param</var> may be +‘<samp>argw<var>n</var></samp>’ (where <var>n</var> ranges from <code>0</code> to <code>3</code>, and +indicates one of four one-word arguments); ‘<samp>rtnval</samp>’ (the procedure’s +result); or ‘<samp>priv_lev</samp>’ (privilege level). For arguments or the result, +<var>r</var> specifies how to relocate, and must be one of ‘<samp>no</samp>’ (not +relocatable), ‘<samp>gr</samp>’ (argument is in general register), ‘<samp>fr</samp>’ (in +floating point register), or ‘<samp>fu</samp>’ (upper half of float register). +For ‘<samp>priv_lev</samp>’, <var>r</var> is an integer. +</p> +</dd> +<dt><code>.half <var>n</var></code></dt> +<dd><p>Define a two-byte integer constant <var>n</var>; synonym for the portable +<code>as</code> directive <code>.short</code>. +</p> +</dd> +<dt><code>.import <var>name</var> [ ,<var>typ</var> ]</code></dt> +<dd><p>Converse of <code>.export</code>; make a procedure available to call. The arguments +use the same conventions as the first two arguments for <code>.export</code>. +</p> +</dd> +<dt><code>.label <var>name</var></code></dt> +<dd><p>Define <var>name</var> as a label for the current assembly location. +</p> +</dd> +<dt><code>.leave</code></dt> +<dd><p>Not yet supported; the assembler rejects programs containing this directive. +</p> +</dd> +<dt><code>.origin <var>lc</var></code></dt> +<dd><p>Advance location counter to <var>lc</var>. Synonym for the <code>as</code> +portable directive <code>.org</code>. +</p> +</dd> +<dt><code>.param <var>name</var> [ ,<var>typ</var> ] [ ,<var>param</var>=<var>r</var> ]</code></dt> +<dd><p>Similar to <code>.export</code>, but used for static procedures. +</p> +</dd> +<dt><code>.proc</code></dt> +<dd><p>Use preceding the first statement of a procedure. +</p> +</dd> +<dt><code>.procend</code></dt> +<dd><p>Use following the last statement of a procedure. +</p> +</dd> +<dt><code><var>label</var> .reg <var>expr</var></code></dt> +<dd><p>Synonym for <code>.equ</code>; define <var>label</var> with the absolute expression +<var>expr</var> as its value. +</p> +</dd> +<dt><code>.space <var>secname</var> [ ,<var>params</var> ]</code></dt> +<dd><p>Switch to section <var>secname</var>, creating a new section by that name if +necessary. You may only use <var>params</var> when creating a new section, not +when switching to an existing one. <var>secname</var> may identify a section by +number rather than by name. +</p> +<p>If specified, the list <var>params</var> declares attributes of the section, +identified by keywords. The keywords recognized are ‘<samp>spnum=<var>exp</var></samp>’ +(identify this section by the number <var>exp</var>, an absolute expression), +‘<samp>sort=<var>exp</var></samp>’ (order sections according to this sort key when linking; +<var>exp</var> is an absolute expression), ‘<samp>unloadable</samp>’ (section contains no +loadable data), ‘<samp>notdefined</samp>’ (this section defined elsewhere), and +‘<samp>private</samp>’ (data in this section not available to other programs). +</p> +</dd> +<dt><code>.spnum <var>secnam</var></code></dt> +<dd><p>Allocate four bytes of storage, and initialize them with the section number of +the section named <var>secnam</var>. (You can define the section number with the +HPPA <code>.space</code> directive.) +</p> +<a name="index-string-directive-on-HPPA"></a> +</dd> +<dt><code>.string "<var>str</var>"</code></dt> +<dd><p>Copy the characters in the string <var>str</var> to the object file. +See <a href="#Strings">Strings</a>, for information on escape sequences you can use in +<code>as</code> strings. +</p> +<p><em>Warning!</em> The HPPA version of <code>.string</code> differs from the +usual <code>as</code> definition: it does <em>not</em> write a zero byte +after copying <var>str</var>. +</p> +</dd> +<dt><code>.stringz "<var>str</var>"</code></dt> +<dd><p>Like <code>.string</code>, but appends a zero byte after copying <var>str</var> to object +file. +</p> +</dd> +<dt><code>.subspa <var>name</var> [ ,<var>params</var> ]</code></dt> +<dt><code>.nsubspa <var>name</var> [ ,<var>params</var> ]</code></dt> +<dd><p>Similar to <code>.space</code>, but selects a subsection <var>name</var> within the +current section. You may only specify <var>params</var> when you create a +subsection (in the first instance of <code>.subspa</code> for this <var>name</var>). +</p> +<p>If specified, the list <var>params</var> declares attributes of the subsection, +identified by keywords. The keywords recognized are ‘<samp>quad=<var>expr</var></samp>’ +(“quadrant” for this subsection), ‘<samp>align=<var>expr</var></samp>’ (alignment for +beginning of this subsection; a power of two), ‘<samp>access=<var>expr</var></samp>’ (value +for “access rights” field), ‘<samp>sort=<var>expr</var></samp>’ (sorting order for this +subspace in link), ‘<samp>code_only</samp>’ (subsection contains only code), +‘<samp>unloadable</samp>’ (subsection cannot be loaded into memory), ‘<samp>comdat</samp>’ +(subsection is comdat), ‘<samp>common</samp>’ (subsection is common block), +‘<samp>dup_comm</samp>’ (subsection may have duplicate names), or ‘<samp>zero</samp>’ +(subsection is all zeros, do not write in object file). +</p> +<p><code>.nsubspa</code> always creates a new subspace with the given name, even +if one with the same name already exists. +</p> +<p>‘<samp>comdat</samp>’, ‘<samp>common</samp>’ and ‘<samp>dup_comm</samp>’ can be used to implement +various flavors of one-only support when using the SOM linker. The SOM +linker only supports specific combinations of these flags. The details +are not documented. A brief description is provided here. +</p> +<p>‘<samp>comdat</samp>’ provides a form of linkonce support. It is useful for +both code and data subspaces. A ‘<samp>comdat</samp>’ subspace has a key symbol +marked by the ‘<samp>is_comdat</samp>’ flag or ‘<samp>ST_COMDAT</samp>’. Only the first +subspace for any given key is selected. The key symbol becomes universal +in shared links. This is similar to the behavior of ‘<samp>secondary_def</samp>’ +symbols. +</p> +<p>‘<samp>common</samp>’ provides Fortran named common support. It is only useful +for data subspaces. Symbols with the flag ‘<samp>is_common</samp>’ retain this +flag in shared links. Referencing a ‘<samp>is_common</samp>’ symbol in a shared +library from outside the library doesn’t work. Thus, ‘<samp>is_common</samp>’ +symbols must be output whenever they are needed. +</p> +<p>‘<samp>common</samp>’ and ‘<samp>dup_comm</samp>’ together provide Cobol common support. +The subspaces in this case must all be the same length. Otherwise, this +support is similar to the Fortran common support. +</p> +<p>‘<samp>dup_comm</samp>’ by itself provides a type of one-only support for code. +Only the first ‘<samp>dup_comm</samp>’ subspace is selected. There is a rather +complex algorithm to compare subspaces. Code symbols marked with the +‘<samp>dup_common</samp>’ flag are hidden. This support was intended for "C++ +duplicate inlines". +</p> +<p>A simplified technique is used to mark the flags of symbols based on +the flags of their subspace. A symbol with the scope SS_UNIVERSAL and +type ST_ENTRY, ST_CODE or ST_DATA is marked with the corresponding +settings of ‘<samp>comdat</samp>’, ‘<samp>common</samp>’ and ‘<samp>dup_comm</samp>’ from the +subspace, respectively. This avoids having to introduce additional +directives to mark these symbols. The HP assembler sets ‘<samp>is_common</samp>’ +from ‘<samp>common</samp>’. However, it doesn’t set the ‘<samp>dup_common</samp>’ from +‘<samp>dup_comm</samp>’. It doesn’t have ‘<samp>comdat</samp>’ support. +</p> +</dd> +<dt><code>.version "<var>str</var>"</code></dt> +<dd><p>Write <var>str</var> as version identifier in object code. +</p></dd> +</dl> + +<hr> +<a name="HPPA-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#HPPA-Directives" accesskey="p" rel="previous">HPPA Directives</a>, Up: <a href="#HPPA_002dDependent" accesskey="u" rel="up">HPPA-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-9"></a> +<h4 class="subsection">9.15.6 Opcodes</h4> +<p>For detailed information on the HPPA machine instruction set, see +<cite>PA-RISC Architecture and Instruction Set Reference Manual</cite> +(HP 09740-90039). +</p> + +<hr> +<a name="i386_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#IA_002d64_002dDependent" accesskey="n" rel="next">IA-64-Dependent</a>, Previous: <a href="#HPPA_002dDependent" accesskey="p" rel="previous">HPPA-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t80386-Dependent-Features"></a> +<h3 class="section">9.16 80386 Dependent Features</h3> + +<a name="index-i386-support"></a> +<a name="index-i80386-support"></a> +<a name="index-x86_002d64-support"></a> + +<p>The i386 version <code>as</code> supports both the original Intel 386 +architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture +extending the Intel architecture to 64-bits. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#i386_002dOptions" accesskey="1">i386-Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dDirectives" accesskey="2">i386-Directives</a>:</td><td> </td><td align="left" valign="top">X86 specific directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dSyntax" accesskey="3">i386-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntactical considerations +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dMnemonics" accesskey="4">i386-Mnemonics</a>:</td><td> </td><td align="left" valign="top">Instruction Naming +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dRegs" accesskey="5">i386-Regs</a>:</td><td> </td><td align="left" valign="top">Register Naming +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dPrefixes" accesskey="6">i386-Prefixes</a>:</td><td> </td><td align="left" valign="top">Instruction Prefixes +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dMemory" accesskey="7">i386-Memory</a>:</td><td> </td><td align="left" valign="top">Memory References +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dJumps" accesskey="8">i386-Jumps</a>:</td><td> </td><td align="left" valign="top">Handling of Jump Instructions +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dFloat" accesskey="9">i386-Float</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dSIMD">i386-SIMD</a>:</td><td> </td><td align="left" valign="top">Intel’s MMX and AMD’s 3DNow! SIMD Operations +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dLWP">i386-LWP</a>:</td><td> </td><td align="left" valign="top">AMD’s Lightweight Profiling Instructions +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dBMI">i386-BMI</a>:</td><td> </td><td align="left" valign="top">Bit Manipulation Instruction +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dTBM">i386-TBM</a>:</td><td> </td><td align="left" valign="top">AMD’s Trailing Bit Manipulation Instructions +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002d16bit">i386-16bit</a>:</td><td> </td><td align="left" valign="top">Writing 16-bit Code +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dArch">i386-Arch</a>:</td><td> </td><td align="left" valign="top">Specifying an x86 CPU architecture +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dISA">i386-ISA</a>:</td><td> </td><td align="left" valign="top">AMD64 ISA vs. Intel64 ISA +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dBugs">i386-Bugs</a>:</td><td> </td><td align="left" valign="top">AT&T Syntax bugs +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dNotes">i386-Notes</a>:</td><td> </td><td align="left" valign="top">Notes +</td></tr> +</table> + +<hr> +<a name="i386_002dOptions"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dDirectives" accesskey="n" rel="next">i386-Directives</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-11"></a> +<h4 class="subsection">9.16.1 Options</h4> + +<a name="index-options-for-i386"></a> +<a name="index-options-for-x86_002d64"></a> +<a name="index-i386-options"></a> +<a name="index-x86_002d64-options"></a> + +<p>The i386 version of <code>as</code> has a few machine +dependent options: +</p> +<dl compact="compact"> +<dd><a name="index-_002d_002d32-option_002c-i386"></a> +<a name="index-_002d_002d32-option_002c-x86_002d64"></a> +<a name="index-_002d_002dx32-option_002c-i386"></a> +<a name="index-_002d_002dx32-option_002c-x86_002d64"></a> +<a name="index-_002d_002d64-option_002c-i386"></a> +<a name="index-_002d_002d64-option_002c-x86_002d64"></a> +</dd> +<dt><code>--32 | --x32 | --64</code></dt> +<dd><p>Select the word size, either 32 bits or 64 bits. ‘<samp>--32</samp>’ +implies Intel i386 architecture, while ‘<samp>--x32</samp>’ and ‘<samp>--64</samp>’ +imply AMD x86-64 architecture with 32-bit or 64-bit word-size +respectively. +</p> +<p>These options are only available with the ELF object file format, and +require that the necessary BFD support has been included (on a 32-bit +platform you have to add –enable-64-bit-bfd to configure enable 64-bit +usage and use x86-64 as target platform). +</p> +</dd> +<dt><code>-n</code></dt> +<dd><p>By default, x86 GAS replaces multiple nop instructions used for +alignment within code sections with multi-byte nop instructions such +as leal 0(%esi,1),%esi. This switch disables the optimization if a single +byte nop (0x90) is explicitly specified as the fill byte for alignment. +</p> +<a name="index-_002d_002ddivide-option_002c-i386"></a> +</dd> +<dt><code>--divide</code></dt> +<dd><p>On SVR4-derived platforms, the character ‘<samp>/</samp>’ is treated as a comment +character, which means that it cannot be used in expressions. The +‘<samp>--divide</samp>’ option turns ‘<samp>/</samp>’ into a normal character. This does +not disable ‘<samp>/</samp>’ at the beginning of a line starting a comment, or +affect using ‘<samp>#</samp>’ for starting a comment. +</p> +<a name="index-_002dmarch_003d-option_002c-i386"></a> +<a name="index-_002dmarch_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-march=<var>CPU</var>[+<var>EXTENSION</var>…]</code></dt> +<dd><p>This option specifies the target processor. The assembler will +issue an error message if an attempt is made to assemble an instruction +which will not execute on the target processor. The following +processor names are recognized: +<code>i8086</code>, +<code>i186</code>, +<code>i286</code>, +<code>i386</code>, +<code>i486</code>, +<code>i586</code>, +<code>i686</code>, +<code>pentium</code>, +<code>pentiumpro</code>, +<code>pentiumii</code>, +<code>pentiumiii</code>, +<code>pentium4</code>, +<code>prescott</code>, +<code>nocona</code>, +<code>core</code>, +<code>core2</code>, +<code>corei7</code>, +<code>iamcu</code>, +<code>k6</code>, +<code>k6_2</code>, +<code>athlon</code>, +<code>opteron</code>, +<code>k8</code>, +<code>amdfam10</code>, +<code>bdver1</code>, +<code>bdver2</code>, +<code>bdver3</code>, +<code>bdver4</code>, +<code>znver1</code>, +<code>znver2</code>, +<code>znver3</code>, +<code>znver4</code>, +<code>btver1</code>, +<code>btver2</code>, +<code>generic32</code> and +<code>generic64</code>. +</p> +<p>In addition to the basic instruction set, the assembler can be told to +accept various extension mnemonics. For example, +<code>-march=i686+sse4+vmx</code> extends <var>i686</var> with <var>sse4</var> and +<var>vmx</var>. The following extensions are currently supported: +<code>8087</code>, +<code>287</code>, +<code>387</code>, +<code>687</code>, +<code>cmov</code>, +<code>fxsr</code>, +<code>mmx</code>, +<code>sse</code>, +<code>sse2</code>, +<code>sse3</code>, +<code>sse4a</code>, +<code>ssse3</code>, +<code>sse4.1</code>, +<code>sse4.2</code>, +<code>sse4</code>, +<code>avx</code>, +<code>avx2</code>, +<code>lahf_sahf</code>, +<code>monitor</code>, +<code>adx</code>, +<code>rdseed</code>, +<code>prfchw</code>, +<code>smap</code>, +<code>mpx</code>, +<code>sha</code>, +<code>rdpid</code>, +<code>ptwrite</code>, +<code>cet</code>, +<code>gfni</code>, +<code>vaes</code>, +<code>vpclmulqdq</code>, +<code>prefetchwt1</code>, +<code>clflushopt</code>, +<code>se1</code>, +<code>clwb</code>, +<code>movdiri</code>, +<code>movdir64b</code>, +<code>enqcmd</code>, +<code>serialize</code>, +<code>tsxldtrk</code>, +<code>kl</code>, +<code>widekl</code>, +<code>hreset</code>, +<code>avx512f</code>, +<code>avx512cd</code>, +<code>avx512er</code>, +<code>avx512pf</code>, +<code>avx512vl</code>, +<code>avx512bw</code>, +<code>avx512dq</code>, +<code>avx512ifma</code>, +<code>avx512vbmi</code>, +<code>avx512_4fmaps</code>, +<code>avx512_4vnniw</code>, +<code>avx512_vpopcntdq</code>, +<code>avx512_vbmi2</code>, +<code>avx512_vnni</code>, +<code>avx512_bitalg</code>, +<code>avx512_vp2intersect</code>, +<code>tdx</code>, +<code>avx512_bf16</code>, +<code>avx_vnni</code>, +<code>avx512_fp16</code>, +<code>prefetchi</code>, +<code>avx_ifma</code>, +<code>avx_vnni_int8</code>, +<code>cmpccxadd</code>, +<code>wrmsrns</code>, +<code>msrlist</code>, +<code>avx_ne_convert</code>, +<code>rao_int</code>, +<code>fred</code>, +<code>lkgs</code>, +<code>amx_int8</code>, +<code>amx_bf16</code>, +<code>amx_fp16</code>, +<code>amx_complex</code>, +<code>amx_tile</code>, +<code>vmx</code>, +<code>vmfunc</code>, +<code>smx</code>, +<code>xsave</code>, +<code>xsaveopt</code>, +<code>xsavec</code>, +<code>xsaves</code>, +<code>aes</code>, +<code>pclmul</code>, +<code>fsgsbase</code>, +<code>rdrnd</code>, +<code>f16c</code>, +<code>bmi2</code>, +<code>fma</code>, +<code>movbe</code>, +<code>ept</code>, +<code>lzcnt</code>, +<code>popcnt</code>, +<code>hle</code>, +<code>rtm</code>, +<code>tsx</code>, +<code>invpcid</code>, +<code>clflush</code>, +<code>mwaitx</code>, +<code>clzero</code>, +<code>wbnoinvd</code>, +<code>pconfig</code>, +<code>waitpkg</code>, +<code>uintr</code>, +<code>cldemote</code>, +<code>rdpru</code>, +<code>mcommit</code>, +<code>sev_es</code>, +<code>lwp</code>, +<code>fma4</code>, +<code>xop</code>, +<code>cx16</code>, +<code>syscall</code>, +<code>rdtscp</code>, +<code>3dnow</code>, +<code>3dnowa</code>, +<code>sse4a</code>, +<code>sse5</code>, +<code>snp</code>, +<code>invlpgb</code>, +<code>tlbsync</code>, +<code>svme</code> and +<code>padlock</code>. +Note that these extension mnemonics can be prefixed with <code>no</code> to revoke +the respective (and any dependent) functionality. +</p> +<p>When the <code>.arch</code> directive is used with <samp>-march</samp>, the +<code>.arch</code> directive will take precedent. +</p> +<a name="index-_002dmtune_003d-option_002c-i386"></a> +<a name="index-_002dmtune_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mtune=<var>CPU</var></code></dt> +<dd><p>This option specifies a processor to optimize for. When used in +conjunction with the <samp>-march</samp> option, only instructions +of the processor specified by the <samp>-march</samp> option will be +generated. +</p> +<p>Valid <var>CPU</var> values are identical to the processor list of +<samp>-march=<var>CPU</var></samp>. +</p> +<a name="index-_002dmsse2avx-option_002c-i386"></a> +<a name="index-_002dmsse2avx-option_002c-x86_002d64"></a> +</dd> +<dt><code>-msse2avx</code></dt> +<dd><p>This option specifies that the assembler should encode SSE instructions +with VEX prefix. +</p> +<a name="index-_002dmuse_002dunaligned_002dvector_002dmove-option_002c-i386"></a> +<a name="index-_002dmuse_002dunaligned_002dvector_002dmove-option_002c-x86_002d64"></a> +</dd> +<dt><code>-muse-unaligned-vector-move</code></dt> +<dd><p>This option specifies that the assembler should encode aligned vector +move as unaligned vector move. +</p> +<a name="index-_002dmsse_002dcheck_003d-option_002c-i386"></a> +<a name="index-_002dmsse_002dcheck_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-msse-check=<var>none</var></code></dt> +<dt><code>-msse-check=<var>warning</var></code></dt> +<dt><code>-msse-check=<var>error</var></code></dt> +<dd><p>These options control if the assembler should check SSE instructions. +<samp>-msse-check=<var>none</var></samp> will make the assembler not to check SSE +instructions, which is the default. <samp>-msse-check=<var>warning</var></samp> +will make the assembler issue a warning for any SSE instruction. +<samp>-msse-check=<var>error</var></samp> will make the assembler issue an error +for any SSE instruction. +</p> +<a name="index-_002dmavxscalar_003d-option_002c-i386"></a> +<a name="index-_002dmavxscalar_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mavxscalar=<var>128</var></code></dt> +<dt><code>-mavxscalar=<var>256</var></code></dt> +<dd><p>These options control how the assembler should encode scalar AVX +instructions. <samp>-mavxscalar=<var>128</var></samp> will encode scalar +AVX instructions with 128bit vector length, which is the default. +<samp>-mavxscalar=<var>256</var></samp> will encode scalar AVX instructions +with 256bit vector length. +</p> +<p>WARNING: Don’t use this for production code - due to CPU errata the +resulting code may not work on certain models. +</p> +<a name="index-_002dmvexwig_003d-option_002c-i386"></a> +<a name="index-_002dmvexwig_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mvexwig=<var>0</var></code></dt> +<dt><code>-mvexwig=<var>1</var></code></dt> +<dd><p>These options control how the assembler should encode VEX.W-ignored (WIG) +VEX instructions. <samp>-mvexwig=<var>0</var></samp> will encode WIG VEX +instructions with vex.w = 0, which is the default. +<samp>-mvexwig=<var>1</var></samp> will encode WIG EVEX instructions with +vex.w = 1. +</p> +<p>WARNING: Don’t use this for production code - due to CPU errata the +resulting code may not work on certain models. +</p> +<a name="index-_002dmevexlig_003d-option_002c-i386"></a> +<a name="index-_002dmevexlig_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mevexlig=<var>128</var></code></dt> +<dt><code>-mevexlig=<var>256</var></code></dt> +<dt><code>-mevexlig=<var>512</var></code></dt> +<dd><p>These options control how the assembler should encode length-ignored +(LIG) EVEX instructions. <samp>-mevexlig=<var>128</var></samp> will encode LIG +EVEX instructions with 128bit vector length, which is the default. +<samp>-mevexlig=<var>256</var></samp> and <samp>-mevexlig=<var>512</var></samp> will +encode LIG EVEX instructions with 256bit and 512bit vector length, +respectively. +</p> +<a name="index-_002dmevexwig_003d-option_002c-i386"></a> +<a name="index-_002dmevexwig_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mevexwig=<var>0</var></code></dt> +<dt><code>-mevexwig=<var>1</var></code></dt> +<dd><p>These options control how the assembler should encode w-ignored (WIG) +EVEX instructions. <samp>-mevexwig=<var>0</var></samp> will encode WIG +EVEX instructions with evex.w = 0, which is the default. +<samp>-mevexwig=<var>1</var></samp> will encode WIG EVEX instructions with +evex.w = 1. +</p> +<a name="index-_002dmmnemonic_003d-option_002c-i386"></a> +<a name="index-_002dmmnemonic_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mmnemonic=<var>att</var></code></dt> +<dt><code>-mmnemonic=<var>intel</var></code></dt> +<dd><p>This option specifies instruction mnemonic for matching instructions. +The <code>.att_mnemonic</code> and <code>.intel_mnemonic</code> directives will +take precedent. +</p> +<a name="index-_002dmsyntax_003d-option_002c-i386"></a> +<a name="index-_002dmsyntax_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-msyntax=<var>att</var></code></dt> +<dt><code>-msyntax=<var>intel</var></code></dt> +<dd><p>This option specifies instruction syntax when processing instructions. +The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will +take precedent. +</p> +<a name="index-_002dmnaked_002dreg-option_002c-i386"></a> +<a name="index-_002dmnaked_002dreg-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mnaked-reg</code></dt> +<dd><p>This option specifies that registers don’t require a ‘<samp>%</samp>’ prefix. +The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will take precedent. +</p> +<a name="index-_002dmadd_002dbnd_002dprefix-option_002c-i386"></a> +<a name="index-_002dmadd_002dbnd_002dprefix-option_002c-x86_002d64"></a> +</dd> +<dt><code>-madd-bnd-prefix</code></dt> +<dd><p>This option forces the assembler to add BND prefix to all branches, even +if such prefix was not explicitly specified in the source code. +</p> +<a name="index-_002dmshared-option_002c-i386"></a> +<a name="index-_002dmshared-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mno-shared</code></dt> +<dd><p>On ELF target, the assembler normally optimizes out non-PLT relocations +against defined non-weak global branch targets with default visibility. +The ‘<samp>-mshared</samp>’ option tells the assembler to generate code which +may go into a shared library where all non-weak global branch targets +with default visibility can be preempted. The resulting code is +slightly bigger. This option only affects the handling of branch +instructions. +</p> +<a name="index-_002dmbig_002dobj-option_002c-i386"></a> +<a name="index-_002dmbig_002dobj-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mbig-obj</code></dt> +<dd><p>On PE/COFF target this option forces the use of big object file +format, which allows more than 32768 sections. +</p> +<a name="index-_002dmomit_002dlock_002dprefix_003d-option_002c-i386"></a> +<a name="index-_002dmomit_002dlock_002dprefix_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-momit-lock-prefix=<var>no</var></code></dt> +<dt><code>-momit-lock-prefix=<var>yes</var></code></dt> +<dd><p>These options control how the assembler should encode lock prefix. +This option is intended as a workaround for processors, that fail on +lock prefix. This option can only be safely used with single-core, +single-thread computers +<samp>-momit-lock-prefix=<var>yes</var></samp> will omit all lock prefixes. +<samp>-momit-lock-prefix=<var>no</var></samp> will encode lock prefix as usual, +which is the default. +</p> +<a name="index-_002dmfence_002das_002dlock_002dadd_003d-option_002c-i386"></a> +<a name="index-_002dmfence_002das_002dlock_002dadd_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mfence-as-lock-add=<var>no</var></code></dt> +<dt><code>-mfence-as-lock-add=<var>yes</var></code></dt> +<dd><p>These options control how the assembler should encode lfence, mfence and +sfence. +<samp>-mfence-as-lock-add=<var>yes</var></samp> will encode lfence, mfence and +sfence as ‘<samp>lock addl $0x0, (%rsp)</samp>’ in 64-bit mode and +‘<samp>lock addl $0x0, (%esp)</samp>’ in 32-bit mode. +<samp>-mfence-as-lock-add=<var>no</var></samp> will encode lfence, mfence and +sfence as usual, which is the default. +</p> +<a name="index-_002dmrelax_002drelocations_003d-option_002c-i386"></a> +<a name="index-_002dmrelax_002drelocations_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mrelax-relocations=<var>no</var></code></dt> +<dt><code>-mrelax-relocations=<var>yes</var></code></dt> +<dd><p>These options control whether the assembler should generate relax +relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and +R_X86_64_REX_GOTPCRELX, in 64-bit mode. +<samp>-mrelax-relocations=<var>yes</var></samp> will generate relax relocations. +<samp>-mrelax-relocations=<var>no</var></samp> will not generate relax +relocations. The default can be controlled by a configure option +<samp>--enable-x86-relax-relocations</samp>. +</p> +<a name="index-_002dmalign_002dbranch_002dboundary_003d-option_002c-i386"></a> +<a name="index-_002dmalign_002dbranch_002dboundary_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-malign-branch-boundary=<var>NUM</var></code></dt> +<dd><p>This option controls how the assembler should align branches with segment +prefixes or NOP. <var>NUM</var> must be a power of 2. It should be 0 or +no less than 16. Branches will be aligned within <var>NUM</var> byte +boundary. <samp>-malign-branch-boundary=0</samp>, which is the default, +doesn’t align branches. +</p> +<a name="index-_002dmalign_002dbranch_003d-option_002c-i386"></a> +<a name="index-_002dmalign_002dbranch_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-malign-branch=<var>TYPE</var>[+<var>TYPE</var>...]</code></dt> +<dd><p>This option specifies types of branches to align. <var>TYPE</var> is +combination of ‘<samp>jcc</samp>’, which aligns conditional jumps, +‘<samp>fused</samp>’, which aligns fused conditional jumps, ‘<samp>jmp</samp>’, +which aligns unconditional jumps, ‘<samp>call</samp>’ which aligns calls, +‘<samp>ret</samp>’, which aligns rets, ‘<samp>indirect</samp>’, which aligns indirect +jumps and calls. The default is <samp>-malign-branch=jcc+fused+jmp</samp>. +</p> +<a name="index-_002dmalign_002dbranch_002dprefix_002dsize_003d-option_002c-i386"></a> +<a name="index-_002dmalign_002dbranch_002dprefix_002dsize_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-malign-branch-prefix-size=<var>NUM</var></code></dt> +<dd><p>This option specifies the maximum number of prefixes on an instruction +to align branches. <var>NUM</var> should be between 0 and 5. The default +<var>NUM</var> is 5. +</p> +<a name="index-_002dmbranches_002dwithin_002d32B_002dboundaries-option_002c-i386"></a> +<a name="index-_002dmbranches_002dwithin_002d32B_002dboundaries-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mbranches-within-32B-boundaries</code></dt> +<dd><p>This option aligns conditional jumps, fused conditional jumps and +unconditional jumps within 32 byte boundary with up to 5 segment prefixes +on an instruction. It is equivalent to +<samp>-malign-branch-boundary=32</samp> +<samp>-malign-branch=jcc+fused+jmp</samp> +<samp>-malign-branch-prefix-size=5</samp>. +The default doesn’t align branches. +</p> +<a name="index-_002dmlfence_002dafter_002dload_003d-option_002c-i386"></a> +<a name="index-_002dmlfence_002dafter_002dload_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mlfence-after-load=<var>no</var></code></dt> +<dt><code>-mlfence-after-load=<var>yes</var></code></dt> +<dd><p>These options control whether the assembler should generate lfence +after load instructions. <samp>-mlfence-after-load=<var>yes</var></samp> will +generate lfence. <samp>-mlfence-after-load=<var>no</var></samp> will not generate +lfence, which is the default. +</p> +<a name="index-_002dmlfence_002dbefore_002dindirect_002dbranch_003d-option_002c-i386"></a> +<a name="index-_002dmlfence_002dbefore_002dindirect_002dbranch_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mlfence-before-indirect-branch=<var>none</var></code></dt> +<dt><code>-mlfence-before-indirect-branch=<var>all</var></code></dt> +<dt><code>-mlfence-before-indirect-branch=<var>register</var></code></dt> +<dt><code>-mlfence-before-indirect-branch=<var>memory</var></code></dt> +<dd><p>These options control whether the assembler should generate lfence +before indirect near branch instructions. +<samp>-mlfence-before-indirect-branch=<var>all</var></samp> will generate lfence +before indirect near branch via register and issue a warning before +indirect near branch via memory. +It also implicitly sets <samp>-mlfence-before-ret=<var>shl</var></samp> when +there’s no explicit <samp>-mlfence-before-ret=</samp>. +<samp>-mlfence-before-indirect-branch=<var>register</var></samp> will generate +lfence before indirect near branch via register. +<samp>-mlfence-before-indirect-branch=<var>memory</var></samp> will issue a +warning before indirect near branch via memory. +<samp>-mlfence-before-indirect-branch=<var>none</var></samp> will not generate +lfence nor issue warning, which is the default. Note that lfence won’t +be generated before indirect near branch via register with +<samp>-mlfence-after-load=<var>yes</var></samp> since lfence will be generated +after loading branch target register. +</p> +<a name="index-_002dmlfence_002dbefore_002dret_003d-option_002c-i386"></a> +<a name="index-_002dmlfence_002dbefore_002dret_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mlfence-before-ret=<var>none</var></code></dt> +<dt><code>-mlfence-before-ret=<var>shl</var></code></dt> +<dt><code>-mlfence-before-ret=<var>or</var></code></dt> +<dt><code>-mlfence-before-ret=<var>yes</var></code></dt> +<dt><code>-mlfence-before-ret=<var>not</var></code></dt> +<dd><p>These options control whether the assembler should generate lfence +before ret. <samp>-mlfence-before-ret=<var>or</var></samp> will generate +generate or instruction with lfence. +<samp>-mlfence-before-ret=<var>shl/yes</var></samp> will generate shl instruction +with lfence. <samp>-mlfence-before-ret=<var>not</var></samp> will generate not +instruction with lfence. <samp>-mlfence-before-ret=<var>none</var></samp> will not +generate lfence, which is the default. +</p> +<a name="index-_002dmx86_002dused_002dnote_003d-option_002c-i386"></a> +<a name="index-_002dmx86_002dused_002dnote_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mx86-used-note=<var>no</var></code></dt> +<dt><code>-mx86-used-note=<var>yes</var></code></dt> +<dd><p>These options control whether the assembler should generate +GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED +GNU property notes. The default can be controlled by the +<samp>--enable-x86-used-note</samp> configure option. +</p> +<a name="index-_002dmevexrcig_003d-option_002c-i386"></a> +<a name="index-_002dmevexrcig_003d-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mevexrcig=<var>rne</var></code></dt> +<dt><code>-mevexrcig=<var>rd</var></code></dt> +<dt><code>-mevexrcig=<var>ru</var></code></dt> +<dt><code>-mevexrcig=<var>rz</var></code></dt> +<dd><p>These options control how the assembler should encode SAE-only +EVEX instructions. <samp>-mevexrcig=<var>rne</var></samp> will encode RC bits +of EVEX instruction with 00, which is the default. +<samp>-mevexrcig=<var>rd</var></samp>, <samp>-mevexrcig=<var>ru</var></samp> +and <samp>-mevexrcig=<var>rz</var></samp> will encode SAE-only EVEX instructions +with 01, 10 and 11 RC bits, respectively. +</p> +<a name="index-_002dmamd64-option_002c-x86_002d64"></a> +<a name="index-_002dmintel64-option_002c-x86_002d64"></a> +</dd> +<dt><code>-mamd64</code></dt> +<dt><code>-mintel64</code></dt> +<dd><p>This option specifies that the assembler should accept only AMD64 or +Intel64 ISA in 64-bit mode. The default is to accept common, Intel64 +only and AMD64 ISAs. +</p> +<a name="index-_002dO0-option_002c-i386"></a> +<a name="index-_002dO0-option_002c-x86_002d64"></a> +<a name="index-_002dO-option_002c-i386"></a> +<a name="index-_002dO-option_002c-x86_002d64"></a> +<a name="index-_002dO1-option_002c-i386"></a> +<a name="index-_002dO1-option_002c-x86_002d64"></a> +<a name="index-_002dO2-option_002c-i386"></a> +<a name="index-_002dO2-option_002c-x86_002d64"></a> +<a name="index-_002dOs-option_002c-i386"></a> +<a name="index-_002dOs-option_002c-x86_002d64"></a> +</dd> +<dt><code>-O0 | -O | -O1 | -O2 | -Os</code></dt> +<dd><p>Optimize instruction encoding with smaller instruction size. ‘<samp>-O</samp>’ +and ‘<samp>-O1</samp>’ encode 64-bit register load instructions with 64-bit +immediate as 32-bit register load instructions with 31-bit or 32-bits +immediates, encode 64-bit register clearing instructions with 32-bit +register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector +register clearing instructions with 128-bit VEX vector register +clearing instructions, encode 128-bit/256-bit EVEX vector +register load/store instructions with VEX vector register load/store +instructions, and encode 128-bit/256-bit EVEX packed integer logical +instructions with 128-bit/256-bit VEX packed integer logical. +</p> +<p>‘<samp>-O2</samp>’ includes ‘<samp>-O1</samp>’ optimization plus encodes +256-bit/512-bit EVEX vector register clearing instructions with 128-bit +EVEX vector register clearing instructions. In 64-bit mode VEX encoded +instructions with commutative source operands will also have their +source operands swapped if this allows using the 2-byte VEX prefix form +instead of the 3-byte one. Certain forms of AND as well as OR with the +same (register) operand specified twice will also be changed to TEST. +</p> +<p>‘<samp>-Os</samp>’ includes ‘<samp>-O2</samp>’ optimization plus encodes 16-bit, 32-bit +and 64-bit register tests with immediate as 8-bit register test with +immediate. ‘<samp>-O0</samp>’ turns off this optimization. +</p> +</dd> +</dl> + +<hr> +<a name="i386_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dSyntax" accesskey="n" rel="next">i386-Syntax</a>, Previous: <a href="#i386_002dOptions" accesskey="p" rel="previous">i386-Options</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="x86-specific-Directives"></a> +<h4 class="subsection">9.16.2 x86 specific Directives</h4> + +<a name="index-machine-directives_002c-x86"></a> +<a name="index-x86-machine-directives"></a> +<dl compact="compact"> +<dd> +<a name="index-lcomm-directive_002c-COFF"></a> +</dd> +<dt><code>.lcomm <var>symbol</var> , <var>length</var>[, <var>alignment</var>]</code></dt> +<dd><p>Reserve <var>length</var> (an absolute expression) bytes for a local common +denoted by <var>symbol</var>. The section and value of <var>symbol</var> are +those of the new local common. The addresses are allocated in the bss +section, so that at run-time the bytes start off zeroed. Since +<var>symbol</var> is not declared global, it is normally not visible to +<code>ld</code>. The optional third parameter, <var>alignment</var>, +specifies the desired alignment of the symbol in the bss section. +</p> +<p>This directive is only available for COFF based x86 targets. +</p> +<a name="index-largecomm-directive_002c-ELF"></a> +</dd> +<dt><code>.largecomm <var>symbol</var> , <var>length</var>[, <var>alignment</var>]</code></dt> +<dd><p>This directive behaves in the same way as the <code>comm</code> directive +except that the data is placed into the <var>.lbss</var> section instead of +the <var>.bss</var> section <a href="#Comm">Comm</a>. +</p> +<p>The directive is intended to be used for data which requires a large +amount of space, and it is only available for ELF based x86_64 +targets. +</p> +<a name="index-value-directive"></a> +</dd> +<dt><code>.value <var>expression</var> [, <var>expression</var>]</code></dt> +<dd><p>This directive behaves in the same way as the <code>.short</code> directive, +taking a series of comma separated expressions and storing them as +two-byte wide values into the current section. +</p> +<a name="index-insn-directive"></a> +</dd> +<dt><code>.insn [<var>prefix</var>[,...]] [<var>encoding</var>] <var>major-opcode</var>[<code>+r</code>|<code>/<var>extension</var></code>] [,<var>operand</var>[,...]]</code></dt> +<dd><p>This directive allows composing instructions which <code>as</code> +may not know about yet, or which it has no way of expressing (which +can be the case for certain alternative encodings). It assumes certain +basic structure in how operands are encoded, and it also only +recognizes - with a few extensions as per below - operands otherwise +valid for instructions. Therefore there is no guarantee that +everything can be expressed (e.g. the original Intel Xeon Phi’s MVEX +encodings cannot be expressed). +</p> +<ul> +<li> <var>prefix</var> expresses one or more opcode prefixes in the usual way. +Legacy encoding prefixes altering meaning (0x66, 0xF2, 0xF3) may be +specified as high byte of <major-opcode> (perhaps already including an +encoding space prefix). Note that there can only be one such prefix. +Segment overrides are better specified in the respective memory +operand, as long as there is one. + +</li><li> <var>encoding</var> is used to specify VEX, XOP, or EVEX encodings. The +syntax tries to resemble that used in documentation: +<ul> +<li> <code>VEX</code>[<code>.<var>len</var></code>][<code>.<var>prefix</var></code>][<code>.<var>space</var></code>][<code>.<var>w</var></code>] +</li><li> <code>EVEX</code>[<code>.<var>len</var></code>][<code>.<var>prefix</var></code>][<code>.<var>space</var></code>][<code>.<var>w</var></code>] +</li><li> <code>XOP</code><var>space</var>[<code>.<var>len</var></code>][<code>.<var>prefix</var></code>][<code>.<var>w</var></code>] +</li></ul> + +<p>Here +</p><ul> +<li> <var>len</var> can be <code>LIG</code>, <code>128</code>, <code>256</code>, or (EVEX +only) <code>512</code> as well as <code>L0</code> / <code>L1</code> for VEX / XOP and +<code>L0</code>...<code>L3</code> for EVEX +</li><li> <var>prefix</var> can be <code>NP</code>, <code>66</code>, <code>F3</code>, or <code>F2</code> +</li><li> <var>space</var> can be +<ul> +<li> <code>0f</code>, <code>0f38</code>, <code>0f3a</code>, or <code>M0</code>...<code>M31</code> +for VEX +</li><li> <code>08</code>...<code>1f</code> for XOP +</li><li> <code>0f</code>, <code>0f38</code>, <code>0f3a</code>, or <code>M0</code>...<code>M15</code> +for EVEX +</li></ul> +</li><li> <var>w</var> can be <code>WIG</code>, <code>W0</code>, or <code>W1</code> +</li></ul> + +<p>Defaults: +</p><ul> +<li> Omitted <var>len</var> means "infer from operand size" if there is at +least one sized vector operand, or <code>LIG</code> otherwise. (Obviously +<var>len</var> has to be omitted when there’s EVEX rounding control +specified later in the operands.) +</li><li> Omitted <var>prefix</var> means <code>NP</code>. +</li><li> Omitted <var>space</var> (VEX/EVEX only) implies encoding space is +taken from <var>major-opcode</var>. +</li><li> Omitted <var>w</var> means "infer from GPR operand size" in 64-bit +code if there is at least one GPR(-like) operand, or <code>WIG</code> +otherwise. +</li></ul> + +</li><li> <var>major-opcode</var> is an absolute expression specifying the instruction +opcode. Legacy encoding prefixes altering encoding space (0x0f, +0x0f38, 0x0f3a) have to be specified as high byte(s) here. +"Degenerate" ModR/M bytes, as present in e.g. certain FPU opcodes or +sub-spaces like that of major opcode 0x0f01, generally want encoding as +immediate operand (such opcodes wouldn’t normally have non-immediate +operands); in some cases it may be possible to also encode these as low +byte of the major opcode, but there are potential ambiguities. Also +note that after stripping encoding prefixes, the residual has to fit in +two bytes (16 bits). <code>+r</code> can be suffixed to the major opcode +expression to specify register-only encoding forms not using a ModR/M +byte. <code>/<var>extension</var></code> can alternatively be suffixed to the +major opcode expression to specify an extension opcode, encoded in bits +3-5 of the ModR/M byte. + +</li><li> <var>operand</var> is an instruction operand expressed the usual way. +Register operands are primarily used to express register numbers as +encoded in ModR/M byte and REX/VEX/XOP/EVEX prefixes. In certain +cases the register type (really: size) is also used to derive other +encoding attributes, if these aren’t specified explicitly. Note that +there is no consistency checking among operands, so entirely bogus +mixes of operands are possible. Note further that only operands +actually encoded in the instruction should be specified. Operands like +‘<samp>%cl</samp>’ in shift/rotate instructions have to be omitted, or else +they’ll be encoded as an ordinary (register) operand. Operand order +may also not match that of the actual instruction (see below). +</li></ul> + +<p>Encoding of operands: While for a memory operand (of which there can be +only one) it is clear how to encode it in the resulting ModR/M byte, +register operands are encoded strictly in this order (operand counts do +not include immediate ones in the enumeration below, and if there was an +extension opcode specified it counts as a register operand; VEX.vvvv +is meant to cover XOP and EVEX as well): +</p> +<ul> +<li> VEX.vvvv for 1-register-operand VEX/XOP/EVEX insns, +</li><li> ModR/M.rm, ModR/M.reg for 2-operand insns, +</li><li> ModR/M.rm, VEX.vvvv, ModR/M.reg for 3-operand insns, and +</li><li> Imm{4,5}, ModR/M.rm, VEX.vvvv, ModR/M.reg for 4-operand insns, +</li></ul> + +<p>obviously with the ModR/M.rm slot skipped when there is a memory +operand, and obviously with the ModR/M.reg slot skipped when there is +an extension opcode. For Intel syntax of course the opposite order +applies. With <code>+r</code> (and hence no ModR/M) there can only be a +single register operand for legacy encodings. VEX and alike can have +two register operands, where the second (first in Intel syntax) would +go into VEX.vvvv. +</p> +<p>Immediate operands (including immediate-like displacements, i.e. when +not part of ModR/M addressing) are emitted in the order specified, +regardless of AT&T or Intel syntax. Since it may not be possible to +infer the size of such immediates, they can be suffixed by +<code>{:s<var>n</var>}</code> or <code>{:u<var>n</var>}</code>, representing signed / +unsigned immediates of the given number of bits respectively. When +emitting such operands, the number of bits will be rounded up to the +smallest suitable of 8, 16, 32, or 64. Immediates wider than 32 bits +are permitted in 64-bit code only. +</p> +<p>For EVEX encoding memory operands with a displacement need to know +Disp8 scaling size in order to use an 8-bit displacement. For many +instructions this can be inferred from the types of other operands +specified. In Intel syntax ‘<samp>DWORD PTR</samp>’ and alike can be used to +specify the respective size. In AT&T syntax the memory operands can +be suffixed by <code>{:d<var>n</var>}</code> to specify the size (in bytes). +This can be combined with an embedded broadcast specifier: +‘<samp>8(%eax){1to8:d8}</samp>’. +</p> + +</dd> +</dl> + +<hr> +<a name="i386_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dMnemonics" accesskey="n" rel="next">i386-Mnemonics</a>, Previous: <a href="#i386_002dDirectives" accesskey="p" rel="previous">i386-Directives</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="i386-Syntactical-Considerations"></a> +<h4 class="subsection">9.16.3 i386 Syntactical Considerations</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#i386_002dVariations" accesskey="1">i386-Variations</a>:</td><td> </td><td align="left" valign="top">AT&T Syntax versus Intel Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#i386_002dChars" accesskey="2">i386-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="i386_002dVariations"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dChars" accesskey="n" rel="next">i386-Chars</a>, Up: <a href="#i386_002dSyntax" accesskey="u" rel="up">i386-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="AT_0026T-Syntax-versus-Intel-Syntax"></a> +<h4 class="subsubsection">9.16.3.1 AT&T Syntax versus Intel Syntax</h4> + +<a name="index-i386-intel_005fsyntax-pseudo-op"></a> +<a name="index-intel_005fsyntax-pseudo-op_002c-i386"></a> +<a name="index-i386-att_005fsyntax-pseudo-op"></a> +<a name="index-att_005fsyntax-pseudo-op_002c-i386"></a> +<a name="index-i386-syntax-compatibility"></a> +<a name="index-syntax-compatibility_002c-i386"></a> +<a name="index-x86_002d64-intel_005fsyntax-pseudo-op"></a> +<a name="index-intel_005fsyntax-pseudo-op_002c-x86_002d64"></a> +<a name="index-x86_002d64-att_005fsyntax-pseudo-op"></a> +<a name="index-att_005fsyntax-pseudo-op_002c-x86_002d64"></a> +<a name="index-x86_002d64-syntax-compatibility"></a> +<a name="index-syntax-compatibility_002c-x86_002d64"></a> + +<p><code>as</code> now supports assembly using Intel assembler syntax. +<code>.intel_syntax</code> selects Intel mode, and <code>.att_syntax</code> switches +back to the usual AT&T mode for compatibility with the output of +<code>gcc</code>. Either of these directives may have an optional +argument, <code>prefix</code>, or <code>noprefix</code> specifying whether registers +require a ‘<samp>%</samp>’ prefix. AT&T System V/386 assembler syntax is quite +different from Intel syntax. We mention these differences because +almost all 80386 documents use Intel syntax. Notable differences +between the two syntaxes are: +</p> +<a name="index-immediate-operands_002c-i386"></a> +<a name="index-i386-immediate-operands"></a> +<a name="index-register-operands_002c-i386"></a> +<a name="index-i386-register-operands"></a> +<a name="index-jump_002fcall-operands_002c-i386"></a> +<a name="index-i386-jump_002fcall-operands"></a> +<a name="index-operand-delimiters_002c-i386"></a> + +<a name="index-immediate-operands_002c-x86_002d64"></a> +<a name="index-x86_002d64-immediate-operands"></a> +<a name="index-register-operands_002c-x86_002d64"></a> +<a name="index-x86_002d64-register-operands"></a> +<a name="index-jump_002fcall-operands_002c-x86_002d64"></a> +<a name="index-x86_002d64-jump_002fcall-operands"></a> +<a name="index-operand-delimiters_002c-x86_002d64"></a> +<ul> +<li> AT&T immediate operands are preceded by ‘<samp>$</samp>’; Intel immediate +operands are undelimited (Intel ‘<samp>push 4</samp>’ is AT&T ‘<samp>pushl $4</samp>’). +AT&T register operands are preceded by ‘<samp>%</samp>’; Intel register operands +are undelimited. AT&T absolute (as opposed to PC relative) jump/call +operands are prefixed by ‘<samp>*</samp>’; they are undelimited in Intel syntax. + +</li><li> <a name="index-i386-source_002c-destination-operands"></a> +<a name="index-source_002c-destination-operands_003b-i386"></a> +<a name="index-x86_002d64-source_002c-destination-operands"></a> +<a name="index-source_002c-destination-operands_003b-x86_002d64"></a> +AT&T and Intel syntax use the opposite order for source and destination +operands. Intel ‘<samp>add eax, 4</samp>’ is ‘<samp>addl $4, %eax</samp>’. The +‘<samp>source, dest</samp>’ convention is maintained for compatibility with +previous Unix assemblers. Note that ‘<samp>bound</samp>’, ‘<samp>invlpga</samp>’, and +instructions with 2 immediate operands, such as the ‘<samp>enter</samp>’ +instruction, do <em>not</em> have reversed order. <a href="#i386_002dBugs">i386-Bugs</a>. + +</li><li> <a name="index-mnemonic-suffixes_002c-i386"></a> +<a name="index-sizes-operands_002c-i386"></a> +<a name="index-i386-size-suffixes"></a> +<a name="index-mnemonic-suffixes_002c-x86_002d64"></a> +<a name="index-sizes-operands_002c-x86_002d64"></a> +<a name="index-x86_002d64-size-suffixes"></a> +In AT&T syntax the size of memory operands is determined from the last +character of the instruction mnemonic. Mnemonic suffixes of ‘<samp>b</samp>’, +‘<samp>w</samp>’, ‘<samp>l</samp>’ and ‘<samp>q</samp>’ specify byte (8-bit), word (16-bit), long +(32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes +of ‘<samp>x</samp>’, ‘<samp>y</samp>’ and ‘<samp>z</samp>’ specify xmm (128-bit vector), ymm +(256-bit vector) and zmm (512-bit vector) memory references, only when there’s +no other way to disambiguate an instruction. Intel syntax accomplishes this by +prefixing memory operands (<em>not</em> the instruction mnemonics) with +‘<samp>byte ptr</samp>’, ‘<samp>word ptr</samp>’, ‘<samp>dword ptr</samp>’, ‘<samp>qword ptr</samp>’, +‘<samp>xmmword ptr</samp>’, ‘<samp>ymmword ptr</samp>’ and ‘<samp>zmmword ptr</samp>’. Thus, Intel +syntax ‘<samp>mov al, byte ptr <var>foo</var></samp>’ is ‘<samp>movb <var>foo</var>, %al</samp>’ in AT&T +syntax. In Intel syntax, ‘<samp>fword ptr</samp>’, ‘<samp>tbyte ptr</samp>’ and +‘<samp>oword ptr</samp>’ specify 48-bit, 80-bit and 128-bit memory references. + +<p>In 64-bit code, ‘<samp>movabs</samp>’ can be used to encode the ‘<samp>mov</samp>’ +instruction with the 64-bit displacement or immediate operand. +</p> +</li><li> <a name="index-return-instructions_002c-i386"></a> +<a name="index-i386-jump_002c-call_002c-return"></a> +<a name="index-return-instructions_002c-x86_002d64"></a> +<a name="index-x86_002d64-jump_002c-call_002c-return"></a> +Immediate form long jumps and calls are +‘<samp>lcall/ljmp $<var>section</var>, $<var>offset</var></samp>’ in AT&T syntax; the +Intel syntax is +‘<samp>call/jmp far <var>section</var>:<var>offset</var></samp>’. Also, the far return +instruction +is ‘<samp>lret $<var>stack-adjust</var></samp>’ in AT&T syntax; Intel syntax is +‘<samp>ret far <var>stack-adjust</var></samp>’. + +</li><li> <a name="index-sections_002c-i386"></a> +<a name="index-i386-sections"></a> +<a name="index-sections_002c-x86_002d64"></a> +<a name="index-x86_002d64-sections"></a> +The AT&T assembler does not provide support for multiple section +programs. Unix style systems expect all programs to be single sections. +</li></ul> + +<hr> +<a name="i386_002dChars"></a> +<div class="header"> +<p> +Previous: <a href="#i386_002dVariations" accesskey="p" rel="previous">i386-Variations</a>, Up: <a href="#i386_002dSyntax" accesskey="u" rel="up">i386-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-12"></a> +<h4 class="subsubsection">9.16.3.2 Special Characters</h4> + +<a name="index-line-comment-character_002c-i386"></a> +<a name="index-i386-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ appearing anywhere on a line indicates the +start of a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<p>If the <samp>--divide</samp> command-line option has not been specified +then the ‘<samp>/</samp>’ character appearing anywhere on a line also +introduces a line comment. +</p> +<a name="index-line-separator_002c-i386"></a> +<a name="index-statement-separator_002c-i386"></a> +<a name="index-i386-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="i386_002dMnemonics"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dRegs" accesskey="n" rel="next">i386-Regs</a>, Previous: <a href="#i386_002dSyntax" accesskey="p" rel="previous">i386-Syntax</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="i386_002dMnemonics-1"></a> +<h4 class="subsection">9.16.4 i386-Mnemonics</h4> +<a name="Instruction-Naming"></a> +<h4 class="subsubsection">9.16.4.1 Instruction Naming</h4> + +<a name="index-i386-instruction-naming"></a> +<a name="index-instruction-naming_002c-i386"></a> +<a name="index-x86_002d64-instruction-naming"></a> +<a name="index-instruction-naming_002c-x86_002d64"></a> + +<p>Instruction mnemonics are suffixed with one character modifiers which +specify the size of operands. The letters ‘<samp>b</samp>’, ‘<samp>w</samp>’, ‘<samp>l</samp>’ +and ‘<samp>q</samp>’ specify byte, word, long and quadruple word operands. If +no suffix is specified by an instruction then <code>as</code> tries to +fill in the missing suffix based on the destination register operand +(the last one by convention). Thus, ‘<samp>mov %ax, %bx</samp>’ is equivalent +to ‘<samp>movw %ax, %bx</samp>’; also, ‘<samp>mov $1, %bx</samp>’ is equivalent to +‘<samp>movw $1, bx</samp>’. Note that this is incompatible with the AT&T Unix +assembler which assumes that a missing mnemonic suffix implies long +operand size. (This incompatibility does not affect compiler output +since compilers always explicitly specify the mnemonic suffix.) +</p> +<p>When there is no sizing suffix and no (suitable) register operands to +deduce the size of memory operands, with a few exceptions and where long +operand size is possible in the first place, operand size will default +to long in 32- and 64-bit modes. Similarly it will default to short in +16-bit mode. Noteworthy exceptions are +</p> +<ul> +<li> Instructions with an implicit on-stack operand as well as branches, +which default to quad in 64-bit mode. + +</li><li> Sign- and zero-extending moves, which default to byte size source +operands. + +</li><li> Floating point insns with integer operands, which default to short (for +perhaps historical reasons). + +</li><li> CRC32 with a 64-bit destination, which defaults to a quad source +operand. + +</li></ul> + +<a name="index-encoding-options_002c-i386"></a> +<a name="index-encoding-options_002c-x86_002d64"></a> + +<p>Different encoding options can be specified via pseudo prefixes: +</p> +<ul> +<li> ‘<samp>{disp8}</samp>’ – prefer 8-bit displacement. + +</li><li> ‘<samp>{disp32}</samp>’ – prefer 32-bit displacement. + +</li><li> ‘<samp>{disp16}</samp>’ – prefer 16-bit displacement. + +</li><li> ‘<samp>{load}</samp>’ – prefer load-form instruction. + +</li><li> ‘<samp>{store}</samp>’ – prefer store-form instruction. + +</li><li> ‘<samp>{vex}</samp>’ – encode with VEX prefix. + +</li><li> ‘<samp>{vex3}</samp>’ – encode with 3-byte VEX prefix. + +</li><li> ‘<samp>{evex}</samp>’ – encode with EVEX prefix. + +</li><li> ‘<samp>{rex}</samp>’ – prefer REX prefix for integer and legacy vector +instructions (x86-64 only). Note that this differs from the ‘<samp>rex</samp>’ +prefix which generates REX prefix unconditionally. + +</li><li> ‘<samp>{nooptimize}</samp>’ – disable instruction size optimization. +</li></ul> + +<p>Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix +by default. The pseudo ‘<samp>{vex}</samp>’ prefix can be used to encode +mnemonics of Intel VNNI/IFMA instructions with the VEX prefix. +</p> +<a name="index-conversion-instructions_002c-i386"></a> +<a name="index-i386-conversion-instructions"></a> +<a name="index-conversion-instructions_002c-x86_002d64"></a> +<a name="index-x86_002d64-conversion-instructions"></a> +<p>The Intel-syntax conversion instructions +</p> +<ul> +<li> ‘<samp>cbw</samp>’ — sign-extend byte in ‘<samp>%al</samp>’ to word in ‘<samp>%ax</samp>’, + +</li><li> ‘<samp>cwde</samp>’ — sign-extend word in ‘<samp>%ax</samp>’ to long in ‘<samp>%eax</samp>’, + +</li><li> ‘<samp>cwd</samp>’ — sign-extend word in ‘<samp>%ax</samp>’ to long in ‘<samp>%dx:%ax</samp>’, + +</li><li> ‘<samp>cdq</samp>’ — sign-extend dword in ‘<samp>%eax</samp>’ to quad in ‘<samp>%edx:%eax</samp>’, + +</li><li> ‘<samp>cdqe</samp>’ — sign-extend dword in ‘<samp>%eax</samp>’ to quad in ‘<samp>%rax</samp>’ +(x86-64 only), + +</li><li> ‘<samp>cqo</samp>’ — sign-extend quad in ‘<samp>%rax</samp>’ to octuple in +‘<samp>%rdx:%rax</samp>’ (x86-64 only), +</li></ul> + +<p>are called ‘<samp>cbtw</samp>’, ‘<samp>cwtl</samp>’, ‘<samp>cwtd</samp>’, ‘<samp>cltd</samp>’, ‘<samp>cltq</samp>’, and +‘<samp>cqto</samp>’ in AT&T naming. <code>as</code> accepts either naming for these +instructions. +</p> +<a name="index-extension-instructions_002c-i386"></a> +<a name="index-i386-extension-instructions"></a> +<a name="index-extension-instructions_002c-x86_002d64"></a> +<a name="index-x86_002d64-extension-instructions"></a> +<p>The Intel-syntax extension instructions +</p> +<ul> +<li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg16</samp>’. + +</li><li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg32</samp>’. + +</li><li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg64</samp>’ +(x86-64 only). + +</li><li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg16/mem16</samp>’ to ‘<samp>reg32</samp>’ + +</li><li> ‘<samp>movsx</samp>’ — sign-extend ‘<samp>reg16/mem16</samp>’ to ‘<samp>reg64</samp>’ +(x86-64 only). + +</li><li> ‘<samp>movsxd</samp>’ — sign-extend ‘<samp>reg32/mem32</samp>’ to ‘<samp>reg64</samp>’ +(x86-64 only). + +</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg16</samp>’. + +</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg32</samp>’. + +</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg8/mem8</samp>’ to ‘<samp>reg64</samp>’ +(x86-64 only). + +</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg16/mem16</samp>’ to ‘<samp>reg32</samp>’ + +</li><li> ‘<samp>movzx</samp>’ — zero-extend ‘<samp>reg16/mem16</samp>’ to ‘<samp>reg64</samp>’ +(x86-64 only). +</li></ul> + +<p>are called ‘<samp>movsbw/movsxb/movsx</samp>’, ‘<samp>movsbl/movsxb/movsx</samp>’, +‘<samp>movsbq/movsxb/movsx</samp>’, ‘<samp>movswl/movsxw</samp>’, ‘<samp>movswq/movsxw</samp>’, +‘<samp>movslq/movsxl</samp>’, ‘<samp>movzbw/movzxb/movzx</samp>’, +‘<samp>movzbl/movzxb/movzx</samp>’, ‘<samp>movzbq/movzxb/movzx</samp>’, +‘<samp>movzwl/movzxw</samp>’ and ‘<samp>movzwq/movzxw</samp>’ in AT&T syntax. +</p> +<a name="index-jump-instructions_002c-i386"></a> +<a name="index-call-instructions_002c-i386"></a> +<a name="index-jump-instructions_002c-x86_002d64"></a> +<a name="index-call-instructions_002c-x86_002d64"></a> +<p>Far call/jump instructions are ‘<samp>lcall</samp>’ and ‘<samp>ljmp</samp>’ in +AT&T syntax, but are ‘<samp>call far</samp>’ and ‘<samp>jump far</samp>’ in Intel +convention. +</p> +<a name="AT_0026T-Mnemonic-versus-Intel-Mnemonic"></a> +<h4 class="subsubsection">9.16.4.2 AT&T Mnemonic versus Intel Mnemonic</h4> + +<a name="index-i386-mnemonic-compatibility"></a> +<a name="index-mnemonic-compatibility_002c-i386"></a> + +<p><code>as</code> supports assembly using Intel mnemonic. +<code>.intel_mnemonic</code> selects Intel mnemonic with Intel syntax, and +<code>.att_mnemonic</code> switches back to the usual AT&T mnemonic with AT&T +syntax for compatibility with the output of <code>gcc</code>. +Several x87 instructions, ‘<samp>fadd</samp>’, ‘<samp>fdiv</samp>’, ‘<samp>fdivp</samp>’, +‘<samp>fdivr</samp>’, ‘<samp>fdivrp</samp>’, ‘<samp>fmul</samp>’, ‘<samp>fsub</samp>’, ‘<samp>fsubp</samp>’, +‘<samp>fsubr</samp>’ and ‘<samp>fsubrp</samp>’, are implemented in AT&T System V/386 +assembler with different mnemonics from those in Intel IA32 specification. +<code>gcc</code> generates those instructions with AT&T mnemonic. +</p> +<ul> +<li> ‘<samp>movslq</samp>’ with AT&T mnemonic only accepts 64-bit destination +register. ‘<samp>movsxd</samp>’ should be used to encode 16-bit or 32-bit +destination register with both AT&T and Intel mnemonics. +</li></ul> + +<hr> +<a name="i386_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dPrefixes" accesskey="n" rel="next">i386-Prefixes</a>, Previous: <a href="#i386_002dMnemonics" accesskey="p" rel="previous">i386-Mnemonics</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Naming"></a> +<h4 class="subsection">9.16.5 Register Naming</h4> + +<a name="index-i386-registers"></a> +<a name="index-registers_002c-i386"></a> +<a name="index-x86_002d64-registers"></a> +<a name="index-registers_002c-x86_002d64"></a> +<p>Register operands are always prefixed with ‘<samp>%</samp>’. The 80386 registers +consist of +</p> +<ul> +<li> the 8 32-bit registers ‘<samp>%eax</samp>’ (the accumulator), ‘<samp>%ebx</samp>’, +‘<samp>%ecx</samp>’, ‘<samp>%edx</samp>’, ‘<samp>%edi</samp>’, ‘<samp>%esi</samp>’, ‘<samp>%ebp</samp>’ (the +frame pointer), and ‘<samp>%esp</samp>’ (the stack pointer). + +</li><li> the 8 16-bit low-ends of these: ‘<samp>%ax</samp>’, ‘<samp>%bx</samp>’, ‘<samp>%cx</samp>’, +‘<samp>%dx</samp>’, ‘<samp>%di</samp>’, ‘<samp>%si</samp>’, ‘<samp>%bp</samp>’, and ‘<samp>%sp</samp>’. + +</li><li> the 8 8-bit registers: ‘<samp>%ah</samp>’, ‘<samp>%al</samp>’, ‘<samp>%bh</samp>’, +‘<samp>%bl</samp>’, ‘<samp>%ch</samp>’, ‘<samp>%cl</samp>’, ‘<samp>%dh</samp>’, and ‘<samp>%dl</samp>’ (These +are the high-bytes and low-bytes of ‘<samp>%ax</samp>’, ‘<samp>%bx</samp>’, +‘<samp>%cx</samp>’, and ‘<samp>%dx</samp>’) + +</li><li> the 6 section registers ‘<samp>%cs</samp>’ (code section), ‘<samp>%ds</samp>’ +(data section), ‘<samp>%ss</samp>’ (stack section), ‘<samp>%es</samp>’, ‘<samp>%fs</samp>’, +and ‘<samp>%gs</samp>’. + +</li><li> the 5 processor control registers ‘<samp>%cr0</samp>’, ‘<samp>%cr2</samp>’, +‘<samp>%cr3</samp>’, ‘<samp>%cr4</samp>’, and ‘<samp>%cr8</samp>’. + +</li><li> the 6 debug registers ‘<samp>%db0</samp>’, ‘<samp>%db1</samp>’, ‘<samp>%db2</samp>’, +‘<samp>%db3</samp>’, ‘<samp>%db6</samp>’, and ‘<samp>%db7</samp>’. + +</li><li> the 2 test registers ‘<samp>%tr6</samp>’ and ‘<samp>%tr7</samp>’. + +</li><li> the 8 floating point register stack ‘<samp>%st</samp>’ or equivalently +‘<samp>%st(0)</samp>’, ‘<samp>%st(1)</samp>’, ‘<samp>%st(2)</samp>’, ‘<samp>%st(3)</samp>’, +‘<samp>%st(4)</samp>’, ‘<samp>%st(5)</samp>’, ‘<samp>%st(6)</samp>’, and ‘<samp>%st(7)</samp>’. +These registers are overloaded by 8 MMX registers ‘<samp>%mm0</samp>’, +‘<samp>%mm1</samp>’, ‘<samp>%mm2</samp>’, ‘<samp>%mm3</samp>’, ‘<samp>%mm4</samp>’, ‘<samp>%mm5</samp>’, +‘<samp>%mm6</samp>’ and ‘<samp>%mm7</samp>’. + +</li><li> the 8 128-bit SSE registers registers ‘<samp>%xmm0</samp>’, ‘<samp>%xmm1</samp>’, ‘<samp>%xmm2</samp>’, +‘<samp>%xmm3</samp>’, ‘<samp>%xmm4</samp>’, ‘<samp>%xmm5</samp>’, ‘<samp>%xmm6</samp>’ and ‘<samp>%xmm7</samp>’. +</li></ul> + +<p>The AMD x86-64 architecture extends the register set by: +</p> +<ul> +<li> enhancing the 8 32-bit registers to 64-bit: ‘<samp>%rax</samp>’ (the +accumulator), ‘<samp>%rbx</samp>’, ‘<samp>%rcx</samp>’, ‘<samp>%rdx</samp>’, ‘<samp>%rdi</samp>’, +‘<samp>%rsi</samp>’, ‘<samp>%rbp</samp>’ (the frame pointer), ‘<samp>%rsp</samp>’ (the stack +pointer) + +</li><li> the 8 extended registers ‘<samp>%r8</samp>’–‘<samp>%r15</samp>’. + +</li><li> the 8 32-bit low ends of the extended registers: ‘<samp>%r8d</samp>’–‘<samp>%r15d</samp>’. + +</li><li> the 8 16-bit low ends of the extended registers: ‘<samp>%r8w</samp>’–‘<samp>%r15w</samp>’. + +</li><li> the 8 8-bit low ends of the extended registers: ‘<samp>%r8b</samp>’–‘<samp>%r15b</samp>’. + +</li><li> the 4 8-bit registers: ‘<samp>%sil</samp>’, ‘<samp>%dil</samp>’, ‘<samp>%bpl</samp>’, ‘<samp>%spl</samp>’. + +</li><li> the 8 debug registers: ‘<samp>%db8</samp>’–‘<samp>%db15</samp>’. + +</li><li> the 8 128-bit SSE registers: ‘<samp>%xmm8</samp>’–‘<samp>%xmm15</samp>’. +</li></ul> + +<p>With the AVX extensions more registers were made available: +</p> +<ul> +<li> the 16 256-bit SSE ‘<samp>%ymm0</samp>’–‘<samp>%ymm15</samp>’ (only the first 8 +available in 32-bit mode). The bottom 128 bits are overlaid with the +‘<samp>xmm0</samp>’–‘<samp>xmm15</samp>’ registers. + +</li></ul> + +<p>The AVX512 extensions added the following registers: +</p> +<ul> +<li> the 32 512-bit registers ‘<samp>%zmm0</samp>’–‘<samp>%zmm31</samp>’ (only the first 8 +available in 32-bit mode). The bottom 128 bits are overlaid with the +‘<samp>%xmm0</samp>’–‘<samp>%xmm31</samp>’ registers and the first 256 bits are +overlaid with the ‘<samp>%ymm0</samp>’–‘<samp>%ymm31</samp>’ registers. + +</li><li> the 8 mask registers ‘<samp>%k0</samp>’–‘<samp>%k7</samp>’. + +</li></ul> + +<hr> +<a name="i386_002dPrefixes"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dMemory" accesskey="n" rel="next">i386-Memory</a>, Previous: <a href="#i386_002dRegs" accesskey="p" rel="previous">i386-Regs</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-Prefixes"></a> +<h4 class="subsection">9.16.6 Instruction Prefixes</h4> + +<a name="index-i386-instruction-prefixes"></a> +<a name="index-instruction-prefixes_002c-i386"></a> +<a name="index-prefixes_002c-i386"></a> +<p>Instruction prefixes are used to modify the following instruction. They +are used to repeat string instructions, to provide section overrides, to +perform bus lock operations, and to change operand and address sizes. +(Most instructions that normally operate on 32-bit operands will use +16-bit operands if the instruction has an “operand size” prefix.) +Instruction prefixes are best written on the same line as the instruction +they act upon. For example, the ‘<samp>scas</samp>’ (scan string) instruction is +repeated with: +</p> +<div class="smallexample"> +<pre class="smallexample"> repne scas %es:(%edi),%al +</pre></div> + +<p>You may also place prefixes on the lines immediately preceding the +instruction, but this circumvents checks that <code>as</code> does +with prefixes, and will not work with all prefixes. +</p> +<p>Here is a list of instruction prefixes: +</p> +<a name="index-section-override-prefixes_002c-i386"></a> +<ul> +<li> Section override prefixes ‘<samp>cs</samp>’, ‘<samp>ds</samp>’, ‘<samp>ss</samp>’, ‘<samp>es</samp>’, +‘<samp>fs</samp>’, ‘<samp>gs</samp>’. These are automatically added by specifying +using the <var>section</var>:<var>memory-operand</var> form for memory references. + +</li><li> <a name="index-size-prefixes_002c-i386"></a> +Operand/Address size prefixes ‘<samp>data16</samp>’ and ‘<samp>addr16</samp>’ +change 32-bit operands/addresses into 16-bit operands/addresses, +while ‘<samp>data32</samp>’ and ‘<samp>addr32</samp>’ change 16-bit ones (in a +<code>.code16</code> section) into 32-bit operands/addresses. These prefixes +<em>must</em> appear on the same line of code as the instruction they +modify. For example, in a 16-bit <code>.code16</code> section, you might +write: + +<div class="smallexample"> +<pre class="smallexample"> addr32 jmpl *(%ebx) +</pre></div> + +</li><li> <a name="index-bus-lock-prefixes_002c-i386"></a> +<a name="index-inhibiting-interrupts_002c-i386"></a> +The bus lock prefix ‘<samp>lock</samp>’ inhibits interrupts during execution of +the instruction it precedes. (This is only valid with certain +instructions; see a 80386 manual for details). + +</li><li> <a name="index-coprocessor-wait_002c-i386"></a> +The wait for coprocessor prefix ‘<samp>wait</samp>’ waits for the coprocessor to +complete the current instruction. This should never be needed for the +80386/80387 combination. + +</li><li> <a name="index-repeat-prefixes_002c-i386"></a> +The ‘<samp>rep</samp>’, ‘<samp>repe</samp>’, and ‘<samp>repne</samp>’ prefixes are added +to string instructions to make them repeat ‘<samp>%ecx</samp>’ times (‘<samp>%cx</samp>’ +times if the current address size is 16-bits). +</li><li> <a name="index-REX-prefixes_002c-i386"></a> +The ‘<samp>rex</samp>’ family of prefixes is used by x86-64 to encode +extensions to i386 instruction set. The ‘<samp>rex</samp>’ prefix has four +bits — an operand size overwrite (<code>64</code>) used to change operand size +from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the +register set. + +<p>You may write the ‘<samp>rex</samp>’ prefixes directly. The ‘<samp>rex64xyz</samp>’ +instruction emits ‘<samp>rex</samp>’ prefix with all the bits set. By omitting +the <code>64</code>, <code>x</code>, <code>y</code> or <code>z</code> you may write other +prefixes as well. Normally, there is no need to write the prefixes +explicitly, since gas will automatically generate them based on the +instruction operands. +</p></li></ul> + +<hr> +<a name="i386_002dMemory"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dJumps" accesskey="n" rel="next">i386-Jumps</a>, Previous: <a href="#i386_002dPrefixes" accesskey="p" rel="previous">i386-Prefixes</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Memory-References"></a> +<h4 class="subsection">9.16.7 Memory References</h4> + +<a name="index-i386-memory-references"></a> +<a name="index-memory-references_002c-i386"></a> +<a name="index-x86_002d64-memory-references"></a> +<a name="index-memory-references_002c-x86_002d64"></a> +<p>An Intel syntax indirect memory reference of the form +</p> +<div class="smallexample"> +<pre class="smallexample"><var>section</var>:[<var>base</var> + <var>index</var>*<var>scale</var> + <var>disp</var>] +</pre></div> + +<p>is translated into the AT&T syntax +</p> +<div class="smallexample"> +<pre class="smallexample"><var>section</var>:<var>disp</var>(<var>base</var>, <var>index</var>, <var>scale</var>) +</pre></div> + +<p>where <var>base</var> and <var>index</var> are the optional 32-bit base and +index registers, <var>disp</var> is the optional displacement, and +<var>scale</var>, taking the values 1, 2, 4, and 8, multiplies <var>index</var> +to calculate the address of the operand. If no <var>scale</var> is +specified, <var>scale</var> is taken to be 1. <var>section</var> specifies the +optional section register for the memory operand, and may override the +default section register (see a 80386 manual for section register +defaults). Note that section overrides in AT&T syntax <em>must</em> +be preceded by a ‘<samp>%</samp>’. If you specify a section override which +coincides with the default section register, <code>as</code> does <em>not</em> +output any section register override prefixes to assemble the given +instruction. Thus, section overrides can be specified to emphasize which +section register is used for a given memory operand. +</p> +<p>Here are some examples of Intel and AT&T style memory references: +</p> +<dl compact="compact"> +<dt>AT&T: ‘<samp>-4(%ebp)</samp>’, Intel: ‘<samp>[ebp - 4]</samp>’</dt> +<dd><p><var>base</var> is ‘<samp>%ebp</samp>’; <var>disp</var> is ‘<samp>-4</samp>’. <var>section</var> is +missing, and the default section is used (‘<samp>%ss</samp>’ for addressing with +‘<samp>%ebp</samp>’ as the base register). <var>index</var>, <var>scale</var> are both missing. +</p> +</dd> +<dt>AT&T: ‘<samp>foo(,%eax,4)</samp>’, Intel: ‘<samp>[foo + eax*4]</samp>’</dt> +<dd><p><var>index</var> is ‘<samp>%eax</samp>’ (scaled by a <var>scale</var> 4); <var>disp</var> is +‘<samp>foo</samp>’. All other fields are missing. The section register here +defaults to ‘<samp>%ds</samp>’. +</p> +</dd> +<dt>AT&T: ‘<samp>foo(,1)</samp>’; Intel ‘<samp>[foo]</samp>’</dt> +<dd><p>This uses the value pointed to by ‘<samp>foo</samp>’ as a memory operand. +Note that <var>base</var> and <var>index</var> are both missing, but there is only +<em>one</em> ‘<samp>,</samp>’. This is a syntactic exception. +</p> +</dd> +<dt>AT&T: ‘<samp>%gs:foo</samp>’; Intel ‘<samp>gs:foo</samp>’</dt> +<dd><p>This selects the contents of the variable ‘<samp>foo</samp>’ with section +register <var>section</var> being ‘<samp>%gs</samp>’. +</p></dd> +</dl> + +<p>Absolute (as opposed to PC relative) call and jump operands must be +prefixed with ‘<samp>*</samp>’. If no ‘<samp>*</samp>’ is specified, <code>as</code> +always chooses PC relative addressing for jump/call labels. +</p> +<p>Any instruction that has a memory operand, but no register operand, +<em>must</em> specify its size (byte, word, long, or quadruple) with an +instruction mnemonic suffix (‘<samp>b</samp>’, ‘<samp>w</samp>’, ‘<samp>l</samp>’ or ‘<samp>q</samp>’, +respectively). +</p> +<p>The x86-64 architecture adds an RIP (instruction pointer relative) +addressing. This addressing mode is specified by using ‘<samp>rip</samp>’ as a +base register. Only constant offsets are valid. For example: +</p> +<dl compact="compact"> +<dt>AT&T: ‘<samp>1234(%rip)</samp>’, Intel: ‘<samp>[rip + 1234]</samp>’</dt> +<dd><p>Points to the address 1234 bytes past the end of the current +instruction. +</p> +</dd> +<dt>AT&T: ‘<samp>symbol(%rip)</samp>’, Intel: ‘<samp>[rip + symbol]</samp>’</dt> +<dd><p>Points to the <code>symbol</code> in RIP relative way, this is shorter than +the default absolute addressing. +</p></dd> +</dl> + +<p>Other addressing modes remain unchanged in x86-64 architecture, except +registers used are 64-bit instead of 32-bit. +</p> +<hr> +<a name="i386_002dJumps"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dFloat" accesskey="n" rel="next">i386-Float</a>, Previous: <a href="#i386_002dMemory" accesskey="p" rel="previous">i386-Memory</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Handling-of-Jump-Instructions"></a> +<h4 class="subsection">9.16.8 Handling of Jump Instructions</h4> + +<a name="index-jump-optimization_002c-i386"></a> +<a name="index-i386-jump-optimization"></a> +<a name="index-jump-optimization_002c-x86_002d64"></a> +<a name="index-x86_002d64-jump-optimization"></a> +<p>Jump instructions are always optimized to use the smallest possible +displacements. This is accomplished by using byte (8-bit) displacement +jumps whenever the target is sufficiently close. If a byte displacement +is insufficient a long displacement is used. We do not support +word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump +instruction with the ‘<samp>data16</samp>’ instruction prefix), since the 80386 +insists upon masking ‘<samp>%eip</samp>’ to 16 bits after the word displacement +is added. (See also see <a href="#i386_002dArch">i386-Arch</a>) +</p> +<p>Note that the ‘<samp>jcxz</samp>’, ‘<samp>jecxz</samp>’, ‘<samp>loop</samp>’, ‘<samp>loopz</samp>’, +‘<samp>loope</samp>’, ‘<samp>loopnz</samp>’ and ‘<samp>loopne</samp>’ instructions only come in byte +displacements, so that if you use these instructions (<code>gcc</code> does +not use them) you may get an error message (and incorrect code). The AT&T +80386 assembler tries to get around this problem by expanding ‘<samp>jcxz foo</samp>’ +to +</p> +<div class="smallexample"> +<pre class="smallexample"> jcxz cx_zero + jmp cx_nonzero +cx_zero: jmp foo +cx_nonzero: +</pre></div> + +<hr> +<a name="i386_002dFloat"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dSIMD" accesskey="n" rel="next">i386-SIMD</a>, Previous: <a href="#i386_002dJumps" accesskey="p" rel="previous">i386-Jumps</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-7"></a> +<h4 class="subsection">9.16.9 Floating Point</h4> + +<a name="index-i386-floating-point"></a> +<a name="index-floating-point_002c-i386"></a> +<a name="index-x86_002d64-floating-point"></a> +<a name="index-floating-point_002c-x86_002d64"></a> +<p>All 80387 floating point types except packed BCD are supported. +(BCD support may be added without much difficulty). These data +types are 16-, 32-, and 64- bit integers, and single (32-bit), +double (64-bit), and extended (80-bit) precision floating point. +Each supported type has an instruction mnemonic suffix and a constructor +associated with it. Instruction mnemonic suffixes specify the operand’s +data type. Constructors build these data types into memory. +</p> +<a name="index-float-directive_002c-i386"></a> +<a name="index-single-directive_002c-i386"></a> +<a name="index-double-directive_002c-i386"></a> +<a name="index-tfloat-directive_002c-i386"></a> +<a name="index-hfloat-directive_002c-i386"></a> +<a name="index-bfloat16-directive_002c-i386"></a> +<a name="index-float-directive_002c-x86_002d64"></a> +<a name="index-single-directive_002c-x86_002d64"></a> +<a name="index-double-directive_002c-x86_002d64"></a> +<a name="index-tfloat-directive_002c-x86_002d64"></a> +<a name="index-hfloat-directive_002c-x86_002d64"></a> +<a name="index-bfloat16-directive_002c-x86_002d64"></a> +<ul> +<li> Floating point constructors are ‘<samp>.float</samp>’ or ‘<samp>.single</samp>’, +‘<samp>.double</samp>’, ‘<samp>.tfloat</samp>’, ‘<samp>.hfloat</samp>’, and ‘<samp>.bfloat16</samp>’ for 32-, +64-, 80-, and 16-bit (two flavors) formats respectively. The former three +correspond to instruction mnemonic suffixes ‘<samp>s</samp>’, ‘<samp>l</samp>’, and ‘<samp>t</samp>’. +‘<samp>t</samp>’ stands for 80-bit (ten byte) real. The 80387 only supports this +format via the ‘<samp>fldt</samp>’ (load 80-bit real to stack top) and ‘<samp>fstpt</samp>’ +(store 80-bit real and pop stack) instructions. + +</li><li> <a name="index-word-directive_002c-i386"></a> +<a name="index-long-directive_002c-i386"></a> +<a name="index-int-directive_002c-i386"></a> +<a name="index-quad-directive_002c-i386"></a> +<a name="index-word-directive_002c-x86_002d64"></a> +<a name="index-long-directive_002c-x86_002d64"></a> +<a name="index-int-directive_002c-x86_002d64"></a> +<a name="index-quad-directive_002c-x86_002d64"></a> +Integer constructors are ‘<samp>.word</samp>’, ‘<samp>.long</samp>’ or ‘<samp>.int</samp>’, and +‘<samp>.quad</samp>’ for the 16-, 32-, and 64-bit integer formats. The +corresponding instruction mnemonic suffixes are ‘<samp>s</samp>’ (short), +‘<samp>l</samp>’ (long), and ‘<samp>q</samp>’ (quad). As with the 80-bit real format, +the 64-bit ‘<samp>q</samp>’ format is only present in the ‘<samp>fildq</samp>’ (load +quad integer to stack top) and ‘<samp>fistpq</samp>’ (store quad integer and pop +stack) instructions. +</li></ul> + +<p>Register to register operations should not use instruction mnemonic suffixes. +‘<samp>fstl %st, %st(1)</samp>’ will give a warning, and be assembled as if you +wrote ‘<samp>fst %st, %st(1)</samp>’, since all register to register operations +use 80-bit floating point operands. (Contrast this with ‘<samp>fstl %st, mem</samp>’, +which converts ‘<samp>%st</samp>’ from 80-bit to 64-bit floating point format, +then stores the result in the 4 byte location ‘<samp>mem</samp>’) +</p> +<hr> +<a name="i386_002dSIMD"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dLWP" accesskey="n" rel="next">i386-LWP</a>, Previous: <a href="#i386_002dFloat" accesskey="p" rel="previous">i386-Float</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Intel_0027s-MMX-and-AMD_0027s-3DNow_0021-SIMD-Operations"></a> +<h4 class="subsection">9.16.10 Intel’s MMX and AMD’s 3DNow! SIMD Operations</h4> + +<a name="index-MMX_002c-i386"></a> +<a name="index-3DNow_0021_002c-i386"></a> +<a name="index-SIMD_002c-i386"></a> +<a name="index-MMX_002c-x86_002d64"></a> +<a name="index-3DNow_0021_002c-x86_002d64"></a> +<a name="index-SIMD_002c-x86_002d64"></a> + +<p><code>as</code> supports Intel’s MMX instruction set (SIMD +instructions for integer data), available on Intel’s Pentium MMX +processors and Pentium II processors, AMD’s K6 and K6-2 processors, +Cyrix’ M2 processor, and probably others. It also supports AMD’s 3DNow! +instruction set (SIMD instructions for 32-bit floating point data) +available on AMD’s K6-2 processor and possibly others in the future. +</p> +<p>Currently, <code>as</code> does not support Intel’s floating point +SIMD, Katmai (KNI). +</p> +<p>The eight 64-bit MMX operands, also used by 3DNow!, are called ‘<samp>%mm0</samp>’, +‘<samp>%mm1</samp>’, ... ‘<samp>%mm7</samp>’. They contain eight 8-bit integers, four +16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit +floating point values. The MMX registers cannot be used at the same time +as the floating point stack. +</p> +<p>See Intel and AMD documentation, keeping in mind that the operand order in +instructions is reversed from the Intel syntax. +</p> +<hr> +<a name="i386_002dLWP"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dBMI" accesskey="n" rel="next">i386-BMI</a>, Previous: <a href="#i386_002dSIMD" accesskey="p" rel="previous">i386-SIMD</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="AMD_0027s-Lightweight-Profiling-Instructions"></a> +<h4 class="subsection">9.16.11 AMD’s Lightweight Profiling Instructions</h4> + +<a name="index-LWP_002c-i386"></a> +<a name="index-LWP_002c-x86_002d64"></a> + +<p><code>as</code> supports AMD’s Lightweight Profiling (LWP) +instruction set, available on AMD’s Family 15h (Orochi) processors. +</p> +<p>LWP enables applications to collect and manage performance data, and +react to performance events. The collection of performance data +requires no context switches. LWP runs in the context of a thread and +so several counters can be used independently across multiple threads. +LWP can be used in both 64-bit and legacy 32-bit modes. +</p> +<p>For detailed information on the LWP instruction set, see the +<cite>AMD Lightweight Profiling Specification</cite> available at +<a href="http://developer.amd.com/cpu/LWP">Lightweight Profiling Specification</a>. +</p> +<hr> +<a name="i386_002dBMI"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dTBM" accesskey="n" rel="next">i386-TBM</a>, Previous: <a href="#i386_002dLWP" accesskey="p" rel="previous">i386-LWP</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Bit-Manipulation-Instructions"></a> +<h4 class="subsection">9.16.12 Bit Manipulation Instructions</h4> + +<a name="index-BMI_002c-i386"></a> +<a name="index-BMI_002c-x86_002d64"></a> + +<p><code>as</code> supports the Bit Manipulation (BMI) instruction set. +</p> +<p>BMI instructions provide several instructions implementing individual +bit manipulation operations such as isolation, masking, setting, or +resetting. +</p> + +<hr> +<a name="i386_002dTBM"></a> +<div class="header"> +<p> +Next: <a href="#i386_002d16bit" accesskey="n" rel="next">i386-16bit</a>, Previous: <a href="#i386_002dBMI" accesskey="p" rel="previous">i386-BMI</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="AMD_0027s-Trailing-Bit-Manipulation-Instructions"></a> +<h4 class="subsection">9.16.13 AMD’s Trailing Bit Manipulation Instructions</h4> + +<a name="index-TBM_002c-i386"></a> +<a name="index-TBM_002c-x86_002d64"></a> + +<p><code>as</code> supports AMD’s Trailing Bit Manipulation (TBM) +instruction set, available on AMD’s BDVER2 processors (Trinity and +Viperfish). +</p> +<p>TBM instructions provide instructions implementing individual bit +manipulation operations such as isolating, masking, setting, resetting, +complementing, and operations on trailing zeros and ones. +</p> + +<hr> +<a name="i386_002d16bit"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dArch" accesskey="n" rel="next">i386-Arch</a>, Previous: <a href="#i386_002dTBM" accesskey="p" rel="previous">i386-TBM</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Writing-16_002dbit-Code"></a> +<h4 class="subsection">9.16.14 Writing 16-bit Code</h4> + +<a name="index-i386-16_002dbit-code"></a> +<a name="index-16_002dbit-code_002c-i386"></a> +<a name="index-real_002dmode-code_002c-i386"></a> +<a name="index-code16gcc-directive_002c-i386"></a> +<a name="index-code16-directive_002c-i386"></a> +<a name="index-code32-directive_002c-i386"></a> +<a name="index-code64-directive_002c-i386"></a> +<a name="index-code64-directive_002c-x86_002d64"></a> +<p>While <code>as</code> normally writes only “pure” 32-bit i386 code +or 64-bit x86-64 code depending on the default configuration, +it also supports writing code to run in real mode or in 16-bit protected +mode code segments. To do this, put a ‘<samp>.code16</samp>’ or +‘<samp>.code16gcc</samp>’ directive before the assembly language instructions to +be run in 16-bit mode. You can switch <code>as</code> to writing +32-bit code with the ‘<samp>.code32</samp>’ directive or 64-bit code with the +‘<samp>.code64</samp>’ directive. +</p> +<p>‘<samp>.code16gcc</samp>’ provides experimental support for generating 16-bit +code from gcc, and differs from ‘<samp>.code16</samp>’ in that ‘<samp>call</samp>’, +‘<samp>ret</samp>’, ‘<samp>enter</samp>’, ‘<samp>leave</samp>’, ‘<samp>push</samp>’, ‘<samp>pop</samp>’, +‘<samp>pusha</samp>’, ‘<samp>popa</samp>’, ‘<samp>pushf</samp>’, and ‘<samp>popf</samp>’ instructions +default to 32-bit size. This is so that the stack pointer is +manipulated in the same way over function calls, allowing access to +function parameters at the same stack offsets as in 32-bit mode. +‘<samp>.code16gcc</samp>’ also automatically adds address size prefixes where +necessary to use the 32-bit addressing modes that gcc generates. +</p> +<p>The code which <code>as</code> generates in 16-bit mode will not +necessarily run on a 16-bit pre-80386 processor. To write code that +runs on such a processor, you must refrain from using <em>any</em> 32-bit +constructs which require <code>as</code> to output address or operand +size prefixes. +</p> +<p>Note that writing 16-bit code instructions by explicitly specifying a +prefix or an instruction mnemonic suffix within a 32-bit code section +generates different machine instructions than those generated for a +16-bit code segment. In a 32-bit code section, the following code +generates the machine opcode bytes ‘<samp>66 6a 04</samp>’, which pushes the +value ‘<samp>4</samp>’ onto the stack, decrementing ‘<samp>%esp</samp>’ by 2. +</p> +<div class="smallexample"> +<pre class="smallexample"> pushw $4 +</pre></div> + +<p>The same code in a 16-bit code section would generate the machine +opcode bytes ‘<samp>6a 04</samp>’ (i.e., without the operand size prefix), which +is correct since the processor default operand size is assumed to be 16 +bits in a 16-bit code section. +</p> +<hr> +<a name="i386_002dArch"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dISA" accesskey="n" rel="next">i386-ISA</a>, Previous: <a href="#i386_002d16bit" accesskey="p" rel="previous">i386-16bit</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Specifying-CPU-Architecture"></a> +<h4 class="subsection">9.16.15 Specifying CPU Architecture</h4> + +<a name="index-arch-directive_002c-i386"></a> +<a name="index-i386-arch-directive"></a> +<a name="index-arch-directive_002c-x86_002d64"></a> +<a name="index-x86_002d64-arch-directive"></a> + +<p><code>as</code> may be told to assemble for a particular CPU +(sub-)architecture with the <code>.arch <var>cpu_type</var></code> directive. This +directive enables a warning when gas detects an instruction that is not +supported on the CPU specified. The choices for <var>cpu_type</var> are: +</p> +<table> +<tr><td width="20%">‘<samp>default</samp>’</td><td width="20%">‘<samp>push</samp>’</td><td width="20%">‘<samp>pop</samp>’</td></tr> +<tr><td width="20%">‘<samp>i8086</samp>’</td><td width="20%">‘<samp>i186</samp>’</td><td width="20%">‘<samp>i286</samp>’</td><td width="20%">‘<samp>i386</samp>’</td></tr> +<tr><td width="20%">‘<samp>i486</samp>’</td><td width="20%">‘<samp>i586</samp>’</td><td width="20%">‘<samp>i686</samp>’</td><td width="20%">‘<samp>pentium</samp>’</td></tr> +<tr><td width="20%">‘<samp>pentiumpro</samp>’</td><td width="20%">‘<samp>pentiumii</samp>’</td><td width="20%">‘<samp>pentiumiii</samp>’</td><td width="20%">‘<samp>pentium4</samp>’</td></tr> +<tr><td width="20%">‘<samp>prescott</samp>’</td><td width="20%">‘<samp>nocona</samp>’</td><td width="20%">‘<samp>core</samp>’</td><td width="20%">‘<samp>core2</samp>’</td></tr> +<tr><td width="20%">‘<samp>corei7</samp>’</td><td width="20%">‘<samp>iamcu</samp>’</td></tr> +<tr><td width="20%">‘<samp>k6</samp>’</td><td width="20%">‘<samp>k6_2</samp>’</td><td width="20%">‘<samp>athlon</samp>’</td><td width="20%">‘<samp>k8</samp>’</td></tr> +<tr><td width="20%">‘<samp>amdfam10</samp>’</td><td width="20%">‘<samp>bdver1</samp>’</td><td width="20%">‘<samp>bdver2</samp>’</td><td width="20%">‘<samp>bdver3</samp>’</td></tr> +<tr><td width="20%">‘<samp>bdver4</samp>’</td><td width="20%">‘<samp>znver1</samp>’</td><td width="20%">‘<samp>znver2</samp>’</td><td width="20%">‘<samp>znver3</samp>’</td></tr> +<tr><td width="20%">‘<samp>znver4</samp>’</td><td width="20%">‘<samp>btver1</samp>’</td><td width="20%">‘<samp>btver2</samp>’</td><td width="20%">‘<samp>generic32</samp>’</td></tr> +<tr><td width="20%">‘<samp>generic64</samp>’</td><td width="20%">‘<samp>.cmov</samp>’</td><td width="20%">‘<samp>.fxsr</samp>’</td><td width="20%">‘<samp>.mmx</samp>’</td></tr> +<tr><td width="20%">‘<samp>.sse</samp>’</td><td width="20%">‘<samp>.sse2</samp>’</td><td width="20%">‘<samp>.sse3</samp>’</td><td width="20%">‘<samp>.sse4a</samp>’</td></tr> +<tr><td width="20%">‘<samp>.ssse3</samp>’</td><td width="20%">‘<samp>.sse4.1</samp>’</td><td width="20%">‘<samp>.sse4.2</samp>’</td><td width="20%">‘<samp>.sse4</samp>’</td></tr> +<tr><td width="20%">‘<samp>.avx</samp>’</td><td width="20%">‘<samp>.vmx</samp>’</td><td width="20%">‘<samp>.smx</samp>’</td><td width="20%">‘<samp>.ept</samp>’</td></tr> +<tr><td width="20%">‘<samp>.clflush</samp>’</td><td width="20%">‘<samp>.movbe</samp>’</td><td width="20%">‘<samp>.xsave</samp>’</td><td width="20%">‘<samp>.xsaveopt</samp>’</td></tr> +<tr><td width="20%">‘<samp>.aes</samp>’</td><td width="20%">‘<samp>.pclmul</samp>’</td><td width="20%">‘<samp>.fma</samp>’</td><td width="20%">‘<samp>.fsgsbase</samp>’</td></tr> +<tr><td width="20%">‘<samp>.rdrnd</samp>’</td><td width="20%">‘<samp>.f16c</samp>’</td><td width="20%">‘<samp>.avx2</samp>’</td><td width="20%">‘<samp>.bmi2</samp>’</td></tr> +<tr><td width="20%">‘<samp>.lzcnt</samp>’</td><td width="20%">‘<samp>.popcnt</samp>’</td><td width="20%">‘<samp>.invpcid</samp>’</td><td width="20%">‘<samp>.vmfunc</samp>’</td></tr> +<tr><td width="20%">‘<samp>.monitor</samp>’</td><td width="20%">‘<samp>.hle</samp>’</td><td width="20%">‘<samp>.rtm</samp>’</td><td width="20%">‘<samp>.tsx</samp>’</td></tr> +<tr><td width="20%">‘<samp>.lahf_sahf</samp>’</td><td width="20%">‘<samp>.adx</samp>’</td><td width="20%">‘<samp>.rdseed</samp>’</td><td width="20%">‘<samp>.prfchw</samp>’</td></tr> +<tr><td width="20%">‘<samp>.smap</samp>’</td><td width="20%">‘<samp>.mpx</samp>’</td><td width="20%">‘<samp>.sha</samp>’</td><td width="20%">‘<samp>.prefetchwt1</samp>’</td></tr> +<tr><td width="20%">‘<samp>.clflushopt</samp>’</td><td width="20%">‘<samp>.xsavec</samp>’</td><td width="20%">‘<samp>.xsaves</samp>’</td><td width="20%">‘<samp>.se1</samp>’</td></tr> +<tr><td width="20%">‘<samp>.avx512f</samp>’</td><td width="20%">‘<samp>.avx512cd</samp>’</td><td width="20%">‘<samp>.avx512er</samp>’</td><td width="20%">‘<samp>.avx512pf</samp>’</td></tr> +<tr><td width="20%">‘<samp>.avx512vl</samp>’</td><td width="20%">‘<samp>.avx512bw</samp>’</td><td width="20%">‘<samp>.avx512dq</samp>’</td><td width="20%">‘<samp>.avx512ifma</samp>’</td></tr> +<tr><td width="20%">‘<samp>.avx512vbmi</samp>’</td><td width="20%">‘<samp>.avx512_4fmaps</samp>’</td><td width="20%">‘<samp>.avx512_4vnniw</samp>’</td></tr> +<tr><td width="20%">‘<samp>.avx512_vpopcntdq</samp>’</td><td width="20%">‘<samp>.avx512_vbmi2</samp>’</td><td width="20%">‘<samp>.avx512_vnni</samp>’</td></tr> +<tr><td width="20%">‘<samp>.avx512_bitalg</samp>’</td><td width="20%">‘<samp>.avx512_bf16</samp>’</td><td width="20%">‘<samp>.avx512_vp2intersect</samp>’</td></tr> +<tr><td width="20%">‘<samp>.tdx</samp>’</td><td width="20%">‘<samp>.avx_vnni</samp>’</td><td width="20%">‘<samp>.avx512_fp16</samp>’</td></tr> +<tr><td width="20%">‘<samp>.clwb</samp>’</td><td width="20%">‘<samp>.rdpid</samp>’</td><td width="20%">‘<samp>.ptwrite</samp>’</td><td width="20%">‘<samp>.ibt</samp>’</td></tr> +<tr><td width="20%">‘<samp>.prefetchi</samp>’</td><td width="20%">‘<samp>.avx_ifma</samp>’</td><td width="20%">‘<samp>.avx_vnni_int8</samp>’</td></tr> +<tr><td width="20%">‘<samp>.cmpccxadd</samp>’</td><td width="20%">‘<samp>.wrmsrns</samp>’</td><td width="20%">‘<samp>.msrlist</samp>’</td></tr> +<tr><td width="20%">‘<samp>.avx_ne_convert</samp>’</td><td width="20%">‘<samp>.rao_int</samp>’</td></tr> +<tr><td width="20%">‘<samp>.fred</samp>’</td><td width="20%">‘<samp>.lkgs</samp>’</td></tr> +<tr><td width="20%">‘<samp>.wbnoinvd</samp>’</td><td width="20%">‘<samp>.pconfig</samp>’</td><td width="20%">‘<samp>.waitpkg</samp>’</td><td width="20%">‘<samp>.cldemote</samp>’</td></tr> +<tr><td width="20%">‘<samp>.shstk</samp>’</td><td width="20%">‘<samp>.gfni</samp>’</td><td width="20%">‘<samp>.vaes</samp>’</td><td width="20%">‘<samp>.vpclmulqdq</samp>’</td></tr> +<tr><td width="20%">‘<samp>.movdiri</samp>’</td><td width="20%">‘<samp>.movdir64b</samp>’</td><td width="20%">‘<samp>.enqcmd</samp>’</td><td width="20%">‘<samp>.tsxldtrk</samp>’</td></tr> +<tr><td width="20%">‘<samp>.amx_int8</samp>’</td><td width="20%">‘<samp>.amx_bf16</samp>’</td><td width="20%">‘<samp>.amx_fp16</samp>’</td></tr> +<tr><td width="20%">‘<samp>.amx_complex</samp>’</td><td width="20%">‘<samp>.amx_tile</samp>’</td></tr> +<tr><td width="20%">‘<samp>.kl</samp>’</td><td width="20%">‘<samp>.widekl</samp>’</td><td width="20%">‘<samp>.uintr</samp>’</td><td width="20%">‘<samp>.hreset</samp>’</td></tr> +<tr><td width="20%">‘<samp>.3dnow</samp>’</td><td width="20%">‘<samp>.3dnowa</samp>’</td><td width="20%">‘<samp>.sse4a</samp>’</td><td width="20%">‘<samp>.sse5</samp>’</td></tr> +<tr><td width="20%">‘<samp>.syscall</samp>’</td><td width="20%">‘<samp>.rdtscp</samp>’</td><td width="20%">‘<samp>.svme</samp>’</td></tr> +<tr><td width="20%">‘<samp>.lwp</samp>’</td><td width="20%">‘<samp>.fma4</samp>’</td><td width="20%">‘<samp>.xop</samp>’</td><td width="20%">‘<samp>.cx16</samp>’</td></tr> +<tr><td width="20%">‘<samp>.padlock</samp>’</td><td width="20%">‘<samp>.clzero</samp>’</td><td width="20%">‘<samp>.mwaitx</samp>’</td><td width="20%">‘<samp>.rdpru</samp>’</td></tr> +<tr><td width="20%">‘<samp>.mcommit</samp>’</td><td width="20%">‘<samp>.sev_es</samp>’</td><td width="20%">‘<samp>.snp</samp>’</td><td width="20%">‘<samp>.invlpgb</samp>’</td></tr> +<tr><td width="20%">‘<samp>.tlbsync</samp>’</td></tr> +</table> + +<p>Apart from the warning, there are only two other effects on +<code>as</code> operation; Firstly, if you specify a CPU other than +‘<samp>i486</samp>’, then shift by one instructions such as ‘<samp>sarl $1, %eax</samp>’ +will automatically use a two byte opcode sequence. The larger three +byte opcode sequence is used on the 486 (and when no architecture is +specified) because it executes faster on the 486. Note that you can +explicitly request the two byte opcode by writing ‘<samp>sarl %eax</samp>’. +Secondly, if you specify ‘<samp>i8086</samp>’, ‘<samp>i186</samp>’, or ‘<samp>i286</samp>’, +<em>and</em> ‘<samp>.code16</samp>’ or ‘<samp>.code16gcc</samp>’ then byte offset +conditional jumps will be promoted when necessary to a two instruction +sequence consisting of a conditional jump of the opposite sense around +an unconditional jump to the target. +</p> +<p>Note that the sub-architecture specifiers (starting with a dot) can be prefixed +with <code>no</code> to revoke the respective (and any dependent) functionality. +</p> +<p>Following the CPU architecture (but not a sub-architecture, which are those +starting with a dot), you may specify ‘<samp>jumps</samp>’ or ‘<samp>nojumps</samp>’ to +control automatic promotion of conditional jumps. ‘<samp>jumps</samp>’ is the +default, and enables jump promotion; All external jumps will be of the long +variety, and file-local jumps will be promoted as necessary. +(see <a href="#i386_002dJumps">i386-Jumps</a>) ‘<samp>nojumps</samp>’ leaves external conditional jumps as +byte offset jumps, and warns about file-local conditional jumps that +<code>as</code> promotes. +Unconditional jumps are treated as for ‘<samp>jumps</samp>’. +</p> +<p>For example +</p> +<div class="smallexample"> +<pre class="smallexample"> .arch i8086,nojumps +</pre></div> + +<hr> +<a name="i386_002dISA"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dBugs" accesskey="n" rel="next">i386-Bugs</a>, Previous: <a href="#i386_002dArch" accesskey="p" rel="previous">i386-Arch</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="AMD64-ISA-vs_002e-Intel64-ISA"></a> +<h4 class="subsection">9.16.16 AMD64 ISA vs. Intel64 ISA</h4> + +<p>There are some discrepancies between AMD64 and Intel64 ISAs. +</p> +<ul> +<li> For ‘<samp>movsxd</samp>’ with 16-bit destination register, AMD64 +supports 32-bit source operand and Intel64 supports 16-bit source +operand. + +</li><li> For far branches (with explicit memory operand), both ISAs support +32- and 16-bit operand size. Intel64 additionally supports 64-bit +operand size, encoded as ‘<samp>ljmpq</samp>’ and ‘<samp>lcallq</samp>’ in AT&T syntax +and with an explicit ‘<samp>tbyte ptr</samp>’ operand size specifier in Intel +syntax. + +</li><li> ‘<samp>lfs</samp>’, ‘<samp>lgs</samp>’, and ‘<samp>lss</samp>’ similarly allow for 16- +and 32-bit operand size (32- and 48-bit memory operand) in both ISAs, +while Intel64 additionally supports 64-bit operand sise (80-bit memory +operands). + +</li></ul> + +<hr> +<a name="i386_002dBugs"></a> +<div class="header"> +<p> +Next: <a href="#i386_002dNotes" accesskey="n" rel="next">i386-Notes</a>, Previous: <a href="#i386_002dISA" accesskey="p" rel="previous">i386-ISA</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="AT_0026T-Syntax-bugs"></a> +<h4 class="subsection">9.16.17 AT&T Syntax bugs</h4> + +<p>The UnixWare assembler, and probably other AT&T derived ix86 Unix +assemblers, generate floating point instructions with reversed source +and destination registers in certain cases. Unfortunately, gcc and +possibly many other programs use this reversed syntax, so we’re stuck +with it. +</p> +<p>For example +</p> +<div class="smallexample"> +<pre class="smallexample"> fsub %st,%st(3) +</pre></div> +<p>results in ‘<samp>%st(3)</samp>’ being updated to ‘<samp>%st - %st(3)</samp>’ rather +than the expected ‘<samp>%st(3) - %st</samp>’. This happens with all the +non-commutative arithmetic floating point operations with two register +operands where the source register is ‘<samp>%st</samp>’ and the destination +register is ‘<samp>%st(i)</samp>’. +</p> +<hr> +<a name="i386_002dNotes"></a> +<div class="header"> +<p> +Previous: <a href="#i386_002dBugs" accesskey="p" rel="previous">i386-Bugs</a>, Up: <a href="#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Notes-2"></a> +<h4 class="subsection">9.16.18 Notes</h4> + +<a name="index-i386-mul_002c-imul-instructions"></a> +<a name="index-mul-instruction_002c-i386"></a> +<a name="index-imul-instruction_002c-i386"></a> +<a name="index-mul-instruction_002c-x86_002d64"></a> +<a name="index-imul-instruction_002c-x86_002d64"></a> +<p>There is some trickery concerning the ‘<samp>mul</samp>’ and ‘<samp>imul</samp>’ +instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding +multiplies (base opcode ‘<samp>0xf6</samp>’; extension 4 for ‘<samp>mul</samp>’ and 5 +for ‘<samp>imul</samp>’) can be output only in the one operand form. Thus, +‘<samp>imul %ebx, %eax</samp>’ does <em>not</em> select the expanding multiply; +the expanding multiply would clobber the ‘<samp>%edx</samp>’ register, and this +would confuse <code>gcc</code> output. Use ‘<samp>imul %ebx</samp>’ to get the +64-bit product in ‘<samp>%edx:%eax</samp>’. +</p> +<p>We have added a two operand form of ‘<samp>imul</samp>’ when the first operand +is an immediate mode expression and the second operand is a register. +This is just a shorthand, so that, multiplying ‘<samp>%eax</samp>’ by 69, for +example, can be done with ‘<samp>imul $69, %eax</samp>’ rather than ‘<samp>imul +$69, %eax, %eax</samp>’. +</p> + + +<hr> +<a name="IA_002d64_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#IP2K_002dDependent" accesskey="n" rel="next">IP2K-Dependent</a>, Previous: <a href="#i386_002dDependent" accesskey="p" rel="previous">i386-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="IA_002d64-Dependent-Features"></a> +<h3 class="section">9.17 IA-64 Dependent Features</h3> + + +<a name="index-IA_002d64-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#IA_002d64-Options" accesskey="1">IA-64 Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#IA_002d64-Syntax" accesskey="2">IA-64 Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#IA_002d64-Opcodes" accesskey="3">IA-64 Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="IA_002d64-Options"></a> +<div class="header"> +<p> +Next: <a href="#IA_002d64-Syntax" accesskey="n" rel="next">IA-64 Syntax</a>, Up: <a href="#IA_002d64_002dDependent" accesskey="u" rel="up">IA-64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-12"></a> +<h4 class="subsection">9.17.1 Options</h4> +<a name="index-IA_002d64-options"></a> +<a name="index-options-for-IA_002d64"></a> + +<dl compact="compact"> +<dd><a name="index-_002dmconstant_002dgp-command_002dline-option_002c-IA_002d64"></a> + +</dd> +<dt><samp>-mconstant-gp</samp></dt> +<dd><p>This option instructs the assembler to mark the resulting object file +as using the “constant GP” model. With this model, it is assumed +that the entire program uses a single global pointer (GP) value. Note +that this option does not in any fashion affect the machine code +emitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP +flag in the ELF file header. +</p> +</dd> +<dt><samp>-mauto-pic</samp></dt> +<dd><p>This option instructs the assembler to mark the resulting object file +as using the “constant GP without function descriptor” data model. +This model is like the “constant GP” model, except that it +additionally does away with function descriptors. What this means is +that the address of a function refers directly to the function’s code +entry-point. Normally, such an address would refer to a function +descriptor, which contains both the code entry-point and the GP-value +needed by the function. Note that this option does not in any fashion +affect the machine code emitted by the assembler. All it does is +turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. +</p> +</dd> +<dt><samp>-milp32</samp></dt> +<dt><samp>-milp64</samp></dt> +<dt><samp>-mlp64</samp></dt> +<dt><samp>-mp64</samp></dt> +<dd><p>These options select the data model. The assembler defaults to <code>-mlp64</code> +(LP64 data model). +</p> +</dd> +<dt><samp>-mle</samp></dt> +<dt><samp>-mbe</samp></dt> +<dd><p>These options select the byte order. The <code>-mle</code> option selects little-endian +byte order (default) and <code>-mbe</code> selects big-endian byte order. Note that +IA-64 machine code always uses little-endian byte order. +</p> +</dd> +<dt><samp>-mtune=itanium1</samp></dt> +<dt><samp>-mtune=itanium2</samp></dt> +<dd><p>Tune for a particular IA-64 CPU, <var>itanium1</var> or <var>itanium2</var>. The +default is <var>itanium2</var>. +</p> +</dd> +<dt><samp>-munwind-check=warning</samp></dt> +<dt><samp>-munwind-check=error</samp></dt> +<dd><p>These options control what the assembler will do when performing +consistency checks on unwind directives. <code>-munwind-check=warning</code> +will make the assembler issue a warning when an unwind directive check +fails. This is the default. <code>-munwind-check=error</code> will make the +assembler issue an error when an unwind directive check fails. +</p> +</dd> +<dt><samp>-mhint.b=ok</samp></dt> +<dt><samp>-mhint.b=warning</samp></dt> +<dt><samp>-mhint.b=error</samp></dt> +<dd><p>These options control what the assembler will do when the ‘<samp>hint.b</samp>’ +instruction is used. <code>-mhint.b=ok</code> will make the assembler accept +‘<samp>hint.b</samp>’. <code>-mint.b=warning</code> will make the assembler issue a +warning when ‘<samp>hint.b</samp>’ is used. <code>-mhint.b=error</code> will make +the assembler treat ‘<samp>hint.b</samp>’ as an error, which is the default. +</p> +</dd> +<dt><samp>-x</samp></dt> +<dt><samp>-xexplicit</samp></dt> +<dd><p>These options turn on dependency violation checking. +</p> +</dd> +<dt><samp>-xauto</samp></dt> +<dd><p>This option instructs the assembler to automatically insert stop bits where necessary +to remove dependency violations. This is the default mode. +</p> +</dd> +<dt><samp>-xnone</samp></dt> +<dd><p>This option turns off dependency violation checking. +</p> +</dd> +<dt><samp>-xdebug</samp></dt> +<dd><p>This turns on debug output intended to help tracking down bugs in the dependency +violation checker. +</p> +</dd> +<dt><samp>-xdebugn</samp></dt> +<dd><p>This is a shortcut for -xnone -xdebug. +</p> +</dd> +<dt><samp>-xdebugx</samp></dt> +<dd><p>This is a shortcut for -xexplicit -xdebug. +</p> +</dd> +</dl> + +<a name="index-IA_002d64-Syntax"></a> +<hr> +<a name="IA_002d64-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#IA_002d64-Opcodes" accesskey="n" rel="next">IA-64 Opcodes</a>, Previous: <a href="#IA_002d64-Options" accesskey="p" rel="previous">IA-64 Options</a>, Up: <a href="#IA_002d64_002dDependent" accesskey="u" rel="up">IA-64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-15"></a> +<h4 class="subsection">9.17.2 Syntax</h4> +<p>The assembler syntax closely follows the IA-64 Assembly Language +Reference Guide. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#IA_002d64_002dChars" accesskey="1">IA-64-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#IA_002d64_002dRegs" accesskey="2">IA-64-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#IA_002d64_002dBits" accesskey="3">IA-64-Bits</a>:</td><td> </td><td align="left" valign="top">Bit Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#IA_002d64_002dRelocs" accesskey="4">IA-64-Relocs</a>:</td><td> </td><td align="left" valign="top">Relocations +</td></tr> +</table> + +<hr> +<a name="IA_002d64_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#IA_002d64_002dRegs" accesskey="n" rel="next">IA-64-Regs</a>, Up: <a href="#IA_002d64-Syntax" accesskey="u" rel="up">IA-64 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-13"></a> +<h4 class="subsubsection">9.17.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-IA_002d64"></a> +<a name="index-IA_002d64-line-comment-character"></a> +<p>‘<samp>//</samp>’ is the line comment token. +</p> +<a name="index-line-separator_002c-IA_002d64"></a> +<a name="index-statement-separator_002c-IA_002d64"></a> +<a name="index-IA_002d64-line-separator"></a> +<p>‘<samp>;</samp>’ can be used instead of a newline to separate statements. +</p> +<hr> +<a name="IA_002d64_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#IA_002d64_002dBits" accesskey="n" rel="next">IA-64-Bits</a>, Previous: <a href="#IA_002d64_002dChars" accesskey="p" rel="previous">IA-64-Chars</a>, Up: <a href="#IA_002d64-Syntax" accesskey="u" rel="up">IA-64 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-9"></a> +<h4 class="subsubsection">9.17.2.2 Register Names</h4> +<a name="index-IA_002d64-registers"></a> +<a name="index-register-names_002c-IA_002d64"></a> + +<p>The 128 integer registers are referred to as ‘<samp>r<var>n</var></samp>’. +The 128 floating-point registers are referred to as ‘<samp>f<var>n</var></samp>’. +The 128 application registers are referred to as ‘<samp>ar<var>n</var></samp>’. +The 128 control registers are referred to as ‘<samp>cr<var>n</var></samp>’. +The 64 one-bit predicate registers are referred to as ‘<samp>p<var>n</var></samp>’. +The 8 branch registers are referred to as ‘<samp>b<var>n</var></samp>’. +In addition, the assembler defines a number of aliases: +‘<samp>gp</samp>’ (‘<samp>r1</samp>’), ‘<samp>sp</samp>’ (‘<samp>r12</samp>’), ‘<samp>rp</samp>’ (‘<samp>b0</samp>’), +‘<samp>ret0</samp>’ (‘<samp>r8</samp>’), ‘<samp>ret1</samp>’ (‘<samp>r9</samp>’), ‘<samp>ret2</samp>’ (‘<samp>r10</samp>’), +‘<samp>ret3</samp>’ (‘<samp>r9</samp>’), ‘<samp>farg<var>n</var></samp>’ (‘<samp>f8+<var>n</var></samp>’), and +‘<samp>fret<var>n</var></samp>’ (‘<samp>f8+<var>n</var></samp>’). +</p> +<p>For convenience, the assembler also defines aliases for all named application +and control registers. For example, ‘<samp>ar.bsp</samp>’ refers to the register +backing store pointer (‘<samp>ar17</samp>’). Similarly, ‘<samp>cr.eoi</samp>’ refers to +the end-of-interrupt register (‘<samp>cr67</samp>’). +</p> +<hr> +<a name="IA_002d64_002dBits"></a> +<div class="header"> +<p> +Next: <a href="#IA_002d64_002dRelocs" accesskey="n" rel="next">IA-64-Relocs</a>, Previous: <a href="#IA_002d64_002dRegs" accesskey="p" rel="previous">IA-64-Regs</a>, Up: <a href="#IA_002d64-Syntax" accesskey="u" rel="up">IA-64 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="IA_002d64-Processor_002dStatus_002dRegister-_0028PSR_0029-Bit-Names"></a> +<h4 class="subsubsection">9.17.2.3 IA-64 Processor-Status-Register (PSR) Bit Names</h4> +<a name="index-IA_002d64-Processor_002dstatus_002dRegister-bit-names"></a> +<a name="index-PSR-bits"></a> +<a name="index-bit-names_002c-IA_002d64"></a> + +<p>The assembler defines bit masks for each of the bits in the IA-64 +processor status register. For example, ‘<samp>psr.ic</samp>’ corresponds to +a value of 0x2000. These masks are primarily intended for use with +the ‘<samp>ssm</samp>’/‘<samp>sum</samp>’ and ‘<samp>rsm</samp>’/‘<samp>rum</samp>’ +instructions, but they can be used anywhere else where an integer +constant is expected. +</p> +<hr> +<a name="IA_002d64_002dRelocs"></a> +<div class="header"> +<p> +Previous: <a href="#IA_002d64_002dBits" accesskey="p" rel="previous">IA-64-Bits</a>, Up: <a href="#IA_002d64-Syntax" accesskey="u" rel="up">IA-64 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Relocations-2"></a> +<h4 class="subsubsection">9.17.2.4 Relocations</h4> +<a name="index-IA_002d64-relocations"></a> + +<p>In addition to the standard IA-64 relocations, the following relocations are +implemented by <code>as</code>: +</p> +<dl compact="compact"> +<dt><code>@slotcount(<var>V</var>)</code></dt> +<dd><p>Convert the address offset <var>V</var> into a slot count. This pseudo +function is available only on VMS. The expression <var>V</var> must be +known at assembly time: it can’t reference undefined symbols or symbols in +different sections. +</p></dd> +</dl> + +<hr> +<a name="IA_002d64-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#IA_002d64-Syntax" accesskey="p" rel="previous">IA-64 Syntax</a>, Up: <a href="#IA_002d64_002dDependent" accesskey="u" rel="up">IA-64-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-10"></a> +<h4 class="subsection">9.17.3 Opcodes</h4> +<p>For detailed information on the IA-64 machine instruction set, see the +<a href="http://developer.intel.com/design/itanium/arch_spec.htm">IA-64 Architecture Handbook</a>. +</p> +<hr> +<a name="IP2K_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#LM32_002dDependent" accesskey="n" rel="next">LM32-Dependent</a>, Previous: <a href="#IA_002d64_002dDependent" accesskey="p" rel="previous">IA-64-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="IP2K-Dependent-Features"></a> +<h3 class="section">9.18 IP2K Dependent Features</h3> + +<a name="index-IP2K-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#IP2K_002dOpts" accesskey="1">IP2K-Opts</a>:</td><td> </td><td align="left" valign="top">IP2K Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#IP2K_002dSyntax" accesskey="2">IP2K-Syntax</a>:</td><td> </td><td align="left" valign="top">IP2K Syntax +</td></tr> +</table> + +<hr> +<a name="IP2K_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#IP2K_002dSyntax" accesskey="n" rel="next">IP2K-Syntax</a>, Up: <a href="#IP2K_002dDependent" accesskey="u" rel="up">IP2K-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="IP2K-Options"></a> +<h4 class="subsection">9.18.1 IP2K Options</h4> + +<a name="index-options_002c-IP2K"></a> +<a name="index-IP2K-options"></a> + +<p>The Ubicom IP2K version of <code>as</code> has a few machine +dependent options: +</p> +<dl compact="compact"> +<dt><code>-mip2022ext</code></dt> +<dd><a name="index-_002dmip2022ext-option_002c-IP2022"></a> +<a name="index-architecture-options_002c-IP2022"></a> +<a name="index-IP2K-architecture-options"></a> +<p><code>as</code> can assemble the extended IP2022 instructions, but +it will only do so if this is specifically allowed via this command +line option. +</p> +</dd> +<dt><code>-mip2022</code></dt> +<dd><a name="index-_002dmip2022-option_002c-IP2K"></a> +<a name="index-architecture-options_002c-IP2K"></a> +<a name="index-IP2K-architecture-options-1"></a> +<p>This option restores the assembler’s default behaviour of not +permitting the extended IP2022 instructions to be assembled. +</p> +</dd> +</dl> + +<hr> +<a name="IP2K_002dSyntax"></a> +<div class="header"> +<p> +Previous: <a href="#IP2K_002dOpts" accesskey="p" rel="previous">IP2K-Opts</a>, Up: <a href="#IP2K_002dDependent" accesskey="u" rel="up">IP2K-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="IP2K-Syntax"></a> +<h4 class="subsection">9.18.2 IP2K Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#IP2K_002dChars" accesskey="1">IP2K-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="IP2K_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#IP2K_002dSyntax" accesskey="u" rel="up">IP2K-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-14"></a> +<h4 class="subsubsection">9.18.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-IP2K"></a> +<a name="index-IP2K-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ on a line indicates the start of a comment +that extends to the end of the current line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line, the whole line +is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-IP2K"></a> +<a name="index-statement-separator_002c-IP2K"></a> +<a name="index-IP2K-line-separator"></a> +<p>The IP2K assembler does not currently support a line separator +character. +</p> + +<hr> +<a name="LM32_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#M32C_002dDependent" accesskey="n" rel="next">M32C-Dependent</a>, Previous: <a href="#IP2K_002dDependent" accesskey="p" rel="previous">IP2K-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="LM32-Dependent-Features"></a> +<h3 class="section">9.19 LM32 Dependent Features</h3> + + +<a name="index-LM32-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#LM32-Options" accesskey="1">LM32 Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#LM32-Syntax" accesskey="2">LM32 Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#LM32-Opcodes" accesskey="3">LM32 Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="LM32-Options"></a> +<div class="header"> +<p> +Next: <a href="#LM32-Syntax" accesskey="n" rel="next">LM32 Syntax</a>, Up: <a href="#LM32_002dDependent" accesskey="u" rel="up">LM32-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-13"></a> +<h4 class="subsection">9.19.1 Options</h4> +<a name="index-LM32-options-_0028none_0029"></a> +<a name="index-options-for-LM32-_0028none_0029"></a> + +<dl compact="compact"> +<dd> +<a name="index-_002dmmultiply_002denabled-command_002dline-option_002c-LM32"></a> +</dd> +<dt><code>-mmultiply-enabled</code></dt> +<dd><p>Enable multiply instructions. +</p> +<a name="index-_002dmdivide_002denabled-command_002dline-option_002c-LM32"></a> +</dd> +<dt><code>-mdivide-enabled</code></dt> +<dd><p>Enable divide instructions. +</p> +<a name="index-_002dmbarrel_002dshift_002denabled-command_002dline-option_002c-LM32"></a> +</dd> +<dt><code>-mbarrel-shift-enabled</code></dt> +<dd><p>Enable barrel-shift instructions. +</p> +<a name="index-_002dmsign_002dextend_002denabled-command_002dline-option_002c-LM32"></a> +</dd> +<dt><code>-msign-extend-enabled</code></dt> +<dd><p>Enable sign extend instructions. +</p> +<a name="index-_002dmuser_002denabled-command_002dline-option_002c-LM32"></a> +</dd> +<dt><code>-muser-enabled</code></dt> +<dd><p>Enable user defined instructions. +</p> +<a name="index-_002dmicache_002denabled-command_002dline-option_002c-LM32"></a> +</dd> +<dt><code>-micache-enabled</code></dt> +<dd><p>Enable instruction cache related CSRs. +</p> +<a name="index-_002dmdcache_002denabled-command_002dline-option_002c-LM32"></a> +</dd> +<dt><code>-mdcache-enabled</code></dt> +<dd><p>Enable data cache related CSRs. +</p> +<a name="index-_002dmbreak_002denabled-command_002dline-option_002c-LM32"></a> +</dd> +<dt><code>-mbreak-enabled</code></dt> +<dd><p>Enable break instructions. +</p> +<a name="index-_002dmall_002denabled-command_002dline-option_002c-LM32"></a> +</dd> +<dt><code>-mall-enabled</code></dt> +<dd><p>Enable all instructions and CSRs. +</p> +</dd> +</dl> + + +<hr> +<a name="LM32-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#LM32-Opcodes" accesskey="n" rel="next">LM32 Opcodes</a>, Previous: <a href="#LM32-Options" accesskey="p" rel="previous">LM32 Options</a>, Up: <a href="#LM32_002dDependent" accesskey="u" rel="up">LM32-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-16"></a> +<h4 class="subsection">9.19.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#LM32_002dRegs" accesskey="1">LM32-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#LM32_002dModifiers" accesskey="2">LM32-Modifiers</a>:</td><td> </td><td align="left" valign="top">Relocatable Expression Modifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#LM32_002dChars" accesskey="3">LM32-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="LM32_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#LM32_002dModifiers" accesskey="n" rel="next">LM32-Modifiers</a>, Up: <a href="#LM32-Syntax" accesskey="u" rel="up">LM32 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-10"></a> +<h4 class="subsubsection">9.19.2.1 Register Names</h4> + +<a name="index-LM32-register-names"></a> +<a name="index-register-names_002c-LM32"></a> + +<p>LM32 has 32 x 32-bit general purpose registers ‘<samp>r0</samp>’, +‘<samp>r1</samp>’, ... ‘<samp>r31</samp>’. +</p> +<p>The following aliases are defined: ‘<samp>gp</samp>’ - ‘<samp>r26</samp>’, +‘<samp>fp</samp>’ - ‘<samp>r27</samp>’, ‘<samp>sp</samp>’ - ‘<samp>r28</samp>’, +‘<samp>ra</samp>’ - ‘<samp>r29</samp>’, ‘<samp>ea</samp>’ - ‘<samp>r30</samp>’, +‘<samp>ba</samp>’ - ‘<samp>r31</samp>’. +</p> +<p>LM32 has the following Control and Status Registers (CSRs). +</p> +<dl compact="compact"> +<dt><code>IE</code></dt> +<dd><p>Interrupt enable. +</p></dd> +<dt><code>IM</code></dt> +<dd><p>Interrupt mask. +</p></dd> +<dt><code>IP</code></dt> +<dd><p>Interrupt pending. +</p></dd> +<dt><code>ICC</code></dt> +<dd><p>Instruction cache control. +</p></dd> +<dt><code>DCC</code></dt> +<dd><p>Data cache control. +</p></dd> +<dt><code>CC</code></dt> +<dd><p>Cycle counter. +</p></dd> +<dt><code>CFG</code></dt> +<dd><p>Configuration. +</p></dd> +<dt><code>EBA</code></dt> +<dd><p>Exception base address. +</p></dd> +<dt><code>DC</code></dt> +<dd><p>Debug control. +</p></dd> +<dt><code>DEBA</code></dt> +<dd><p>Debug exception base address. +</p></dd> +<dt><code>JTX</code></dt> +<dd><p>JTAG transmit. +</p></dd> +<dt><code>JRX</code></dt> +<dd><p>JTAG receive. +</p></dd> +<dt><code>BP0</code></dt> +<dd><p>Breakpoint 0. +</p></dd> +<dt><code>BP1</code></dt> +<dd><p>Breakpoint 1. +</p></dd> +<dt><code>BP2</code></dt> +<dd><p>Breakpoint 2. +</p></dd> +<dt><code>BP3</code></dt> +<dd><p>Breakpoint 3. +</p></dd> +<dt><code>WP0</code></dt> +<dd><p>Watchpoint 0. +</p></dd> +<dt><code>WP1</code></dt> +<dd><p>Watchpoint 1. +</p></dd> +<dt><code>WP2</code></dt> +<dd><p>Watchpoint 2. +</p></dd> +<dt><code>WP3</code></dt> +<dd><p>Watchpoint 3. +</p></dd> +</dl> + +<hr> +<a name="LM32_002dModifiers"></a> +<div class="header"> +<p> +Next: <a href="#LM32_002dChars" accesskey="n" rel="next">LM32-Chars</a>, Previous: <a href="#LM32_002dRegs" accesskey="p" rel="previous">LM32-Regs</a>, Up: <a href="#LM32-Syntax" accesskey="u" rel="up">LM32 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Relocatable-Expression-Modifiers-1"></a> +<h4 class="subsubsection">9.19.2.2 Relocatable Expression Modifiers</h4> + +<a name="index-LM32-modifiers"></a> +<a name="index-syntax_002c-LM32"></a> + +<p>The assembler supports several modifiers when using relocatable addresses +in LM32 instruction operands. The general syntax is the following: +</p> +<div class="smallexample"> +<pre class="smallexample">modifier(relocatable-expression) +</pre></div> + +<dl compact="compact"> +<dd><a name="index-symbol-modifiers-1"></a> + +</dd> +<dt><code>lo</code></dt> +<dd> +<p>This modifier allows you to use bits 0 through 15 of +an address expression as 16 bit relocatable expression. +</p> +</dd> +<dt><code>hi</code></dt> +<dd> +<p>This modifier allows you to use bits 16 through 23 of an address expression +as 16 bit relocatable expression. +</p> +<p>For example +</p> +<div class="smallexample"> +<pre class="smallexample">ori r4, r4, lo(sym+10) +orhi r4, r4, hi(sym+10) +</pre></div> + +</dd> +<dt><code>gp</code></dt> +<dd> +<p>This modified creates a 16-bit relocatable expression that is +the offset of the symbol from the global pointer. +</p> +<div class="smallexample"> +<pre class="smallexample">mva r4, gp(sym) +</pre></div> + +</dd> +<dt><code>got</code></dt> +<dd> +<p>This modifier places a symbol in the GOT and creates a 16-bit +relocatable expression that is the offset into the GOT of this +symbol. +</p> +<div class="smallexample"> +<pre class="smallexample">lw r4, (gp+got(sym)) +</pre></div> + +</dd> +<dt><code>gotofflo16</code></dt> +<dd> +<p>This modifier allows you to use the bits 0 through 15 of an +address which is an offset from the GOT. +</p> +</dd> +<dt><code>gotoffhi16</code></dt> +<dd> +<p>This modifier allows you to use the bits 16 through 31 of an +address which is an offset from the GOT. +</p> +<div class="smallexample"> +<pre class="smallexample">orhi r4, r4, gotoffhi16(lsym) +addi r4, r4, gotofflo16(lsym) +</pre></div> + +</dd> +</dl> + +<hr> +<a name="LM32_002dChars"></a> +<div class="header"> +<p> +Previous: <a href="#LM32_002dModifiers" accesskey="p" rel="previous">LM32-Modifiers</a>, Up: <a href="#LM32-Syntax" accesskey="u" rel="up">LM32 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-15"></a> +<h4 class="subsubsection">9.19.2.3 Special Characters</h4> + +<a name="index-line-comment-character_002c-LM32"></a> +<a name="index-LM32-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ on a line indicates the start of a comment +that extends to the end of the current line. Note that if a line +starts with a ‘<samp>#</samp>’ character then it can also be a logical line +number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-LM32"></a> +<a name="index-statement-separator_002c-LM32"></a> +<a name="index-LM32-line-separator"></a> +<p>A semicolon (‘<samp>;</samp>’) can be used to separate multiple statements on +the same line. +</p> +<hr> +<a name="LM32-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#LM32-Syntax" accesskey="p" rel="previous">LM32 Syntax</a>, Up: <a href="#LM32_002dDependent" accesskey="u" rel="up">LM32-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-11"></a> +<h4 class="subsection">9.19.3 Opcodes</h4> + +<a name="index-LM32-opcode-summary"></a> +<a name="index-opcode-summary_002c-LM32"></a> +<a name="index-mnemonics_002c-LM32"></a> +<a name="index-instruction-summary_002c-LM32"></a> +<p>For detailed information on the LM32 machine instruction set, see +<a href="http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/">http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/</a>. +</p> +<p><code>as</code> implements all the standard LM32 opcodes. +</p> + +<hr> +<a name="M32C_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#M32R_002dDependent" accesskey="n" rel="next">M32R-Dependent</a>, Previous: <a href="#LM32_002dDependent" accesskey="p" rel="previous">LM32-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M32C-Dependent-Features"></a> +<h3 class="section">9.20 M32C Dependent Features</h3> + +<a name="index-M32C-support"></a> + +<p><code>as</code> can assemble code for several different members of +the Renesas M32C family. Normally the default is to assemble code for +the M16C microprocessor. The <code>-m32c</code> option may be used to +change the default to the M32C microprocessor. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#M32C_002dOpts" accesskey="1">M32C-Opts</a>:</td><td> </td><td align="left" valign="top">M32C Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#M32C_002dSyntax" accesskey="2">M32C-Syntax</a>:</td><td> </td><td align="left" valign="top">M32C Syntax +</td></tr> +</table> + +<hr> +<a name="M32C_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#M32C_002dSyntax" accesskey="n" rel="next">M32C-Syntax</a>, Up: <a href="#M32C_002dDependent" accesskey="u" rel="up">M32C-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M32C-Options"></a> +<h4 class="subsection">9.20.1 M32C Options</h4> + +<a name="index-options_002c-M32C"></a> +<a name="index-M32C-options"></a> + +<p>The Renesas M32C version of <code>as</code> has these +machine-dependent options: +</p> +<dl compact="compact"> +<dt><code>-m32c</code></dt> +<dd><a name="index-_002dm32c-option_002c-M32C"></a> +<a name="index-architecture-options_002c-M32C"></a> +<a name="index-M32C-architecture-option"></a> +<p>Assemble M32C instructions. +</p> +</dd> +<dt><code>-m16c</code></dt> +<dd><a name="index-_002dm16c-option_002c-M16C"></a> +<a name="index-architecture-options_002c-M16C"></a> +<a name="index-M16C-architecture-option"></a> +<p>Assemble M16C instructions (default). +</p> +</dd> +<dt><code>-relax</code></dt> +<dd><p>Enable support for link-time relaxations. +</p> +</dd> +<dt><code>-h-tick-hex</code></dt> +<dd><p>Support H’00 style hex constants in addition to 0x00 style. +</p> + +</dd> +</dl> + +<hr> +<a name="M32C_002dSyntax"></a> +<div class="header"> +<p> +Previous: <a href="#M32C_002dOpts" accesskey="p" rel="previous">M32C-Opts</a>, Up: <a href="#M32C_002dDependent" accesskey="u" rel="up">M32C-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M32C-Syntax"></a> +<h4 class="subsection">9.20.2 M32C Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#M32C_002dModifiers" accesskey="1">M32C-Modifiers</a>:</td><td> </td><td align="left" valign="top">Symbolic Operand Modifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#M32C_002dChars" accesskey="2">M32C-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="M32C_002dModifiers"></a> +<div class="header"> +<p> +Next: <a href="#M32C_002dChars" accesskey="n" rel="next">M32C-Chars</a>, Up: <a href="#M32C_002dSyntax" accesskey="u" rel="up">M32C-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbolic-Operand-Modifiers"></a> +<h4 class="subsubsection">9.20.2.1 Symbolic Operand Modifiers</h4> + +<a name="index-M32C-modifiers"></a> +<a name="index-modifiers_002c-M32C"></a> + +<p>The assembler supports several modifiers when using symbol addresses +in M32C instruction operands. The general syntax is the following: +</p> +<div class="smallexample"> +<pre class="smallexample">%modifier(symbol) +</pre></div> + +<dl compact="compact"> +<dd><a name="index-symbol-modifiers-2"></a> + +</dd> +<dt><code>%dsp8</code></dt> +<dt><code>%dsp16</code></dt> +<dd> +<p>These modifiers override the assembler’s assumptions about how big a +symbol’s address is. Normally, when it sees an operand like +‘<samp>sym[a0]</samp>’ it assumes ‘<samp>sym</samp>’ may require the widest +displacement field (16 bits for ‘<samp>-m16c</samp>’, 24 bits for +‘<samp>-m32c</samp>’). These modifiers tell it to assume the address will fit +in an 8 or 16 bit (respectively) unsigned displacement. Note that, of +course, if it doesn’t actually fit you will get linker errors. Example: +</p> +<div class="smallexample"> +<pre class="smallexample">mov.w %dsp8(sym)[a0],r1 +mov.b #0,%dsp8(sym)[a0] +</pre></div> + +</dd> +<dt><code>%hi8</code></dt> +<dd> +<p>This modifier allows you to load bits 16 through 23 of a 24 bit +address into an 8 bit register. This is useful with, for example, the +M16C ‘<samp>smovf</samp>’ instruction, which expects a 20 bit address in +‘<samp>r1h</samp>’ and ‘<samp>a0</samp>’. Example: +</p> +<div class="smallexample"> +<pre class="smallexample">mov.b #%hi8(sym),r1h +mov.w #%lo16(sym),a0 +smovf.b +</pre></div> + +</dd> +<dt><code>%lo16</code></dt> +<dd> +<p>Likewise, this modifier allows you to load bits 0 through 15 of a 24 +bit address into a 16 bit register. +</p> +</dd> +<dt><code>%hi16</code></dt> +<dd> +<p>This modifier allows you to load bits 16 through 31 of a 32 bit +address into a 16 bit register. While the M32C family only has 24 +bits of address space, it does support addresses in pairs of 16 bit +registers (like ‘<samp>a1a0</samp>’ for the ‘<samp>lde</samp>’ instruction). This +modifier is for loading the upper half in such cases. Example: +</p> +<div class="smallexample"> +<pre class="smallexample">mov.w #%hi16(sym),a1 +mov.w #%lo16(sym),a0 +… +lde.w [a1a0],r1 +</pre></div> + +</dd> +</dl> + +<hr> +<a name="M32C_002dChars"></a> +<div class="header"> +<p> +Previous: <a href="#M32C_002dModifiers" accesskey="p" rel="previous">M32C-Modifiers</a>, Up: <a href="#M32C_002dSyntax" accesskey="u" rel="up">M32C-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-16"></a> +<h4 class="subsubsection">9.20.2.2 Special Characters</h4> + +<a name="index-line-comment-character_002c-M32C"></a> +<a name="index-M32C-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ character on a line indicates the start of +a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line, the whole line +is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a +preprocessor control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-M32C"></a> +<a name="index-statement-separator_002c-M32C"></a> +<a name="index-M32C-line-separator"></a> +<p>The ‘<samp>|</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="M32R_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#M68K_002dDependent" accesskey="n" rel="next">M68K-Dependent</a>, Previous: <a href="#M32C_002dDependent" accesskey="p" rel="previous">M32C-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M32R-Dependent-Features"></a> +<h3 class="section">9.21 M32R Dependent Features</h3> + +<a name="index-M32R-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#M32R_002dOpts" accesskey="1">M32R-Opts</a>:</td><td> </td><td align="left" valign="top">M32R Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#M32R_002dDirectives" accesskey="2">M32R-Directives</a>:</td><td> </td><td align="left" valign="top">M32R Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#M32R_002dWarnings" accesskey="3">M32R-Warnings</a>:</td><td> </td><td align="left" valign="top">M32R Warnings +</td></tr> +</table> + +<hr> +<a name="M32R_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#M32R_002dDirectives" accesskey="n" rel="next">M32R-Directives</a>, Up: <a href="#M32R_002dDependent" accesskey="u" rel="up">M32R-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M32R-Options"></a> +<h4 class="subsection">9.21.1 M32R Options</h4> + +<a name="index-options_002c-M32R"></a> +<a name="index-M32R-options"></a> + +<p>The Renesas M32R version of <code>as</code> has a few machine +dependent options: +</p> +<dl compact="compact"> +<dt><code>-m32rx</code></dt> +<dd><a name="index-_002dm32rx-option_002c-M32RX"></a> +<a name="index-architecture-options_002c-M32RX"></a> +<a name="index-M32R-architecture-options"></a> +<p><code>as</code> can assemble code for several different members of the +Renesas M32R family. Normally the default is to assemble code for +the M32R microprocessor. This option may be used to change the default +to the M32RX microprocessor, which adds some more instructions to the +basic M32R instruction set, and some additional parameters to some of +the original instructions. +</p> +</dd> +<dt><code>-m32r2</code></dt> +<dd><a name="index-_002dm32rx-option_002c-M32R2"></a> +<a name="index-architecture-options_002c-M32R2"></a> +<a name="index-M32R-architecture-options-1"></a> +<p>This option changes the target processor to the M32R2 +microprocessor. +</p> +</dd> +<dt><code>-m32r</code></dt> +<dd><a name="index-_002dm32r-option_002c-M32R"></a> +<a name="index-architecture-options_002c-M32R"></a> +<a name="index-M32R-architecture-options-2"></a> +<p>This option can be used to restore the assembler’s default behaviour of +assembling for the M32R microprocessor. This can be useful if the +default has been changed by a previous command-line option. +</p> +</dd> +<dt><code>-little</code></dt> +<dd><a name="index-_002dlittle-option_002c-M32R"></a> +<p>This option tells the assembler to produce little-endian code and +data. The default is dependent upon how the toolchain was +configured. +</p> +</dd> +<dt><code>-EL</code></dt> +<dd><a name="index-_002dEL-option_002c-M32R"></a> +<p>This is a synonym for <em>-little</em>. +</p> +</dd> +<dt><code>-big</code></dt> +<dd><a name="index-_002dbig-option_002c-M32R"></a> +<p>This option tells the assembler to produce big-endian code and +data. +</p> +</dd> +<dt><code>-EB</code></dt> +<dd><a name="index-_002dEB-option_002c-M32R"></a> +<p>This is a synonym for <em>-big</em>. +</p> +</dd> +<dt><code>-KPIC</code></dt> +<dd><a name="index-_002dKPIC-option_002c-M32R"></a> +<a name="index-PIC-code-generation-for-M32R"></a> +<p>This option specifies that the output of the assembler should be +marked as position-independent code (PIC). +</p> +</dd> +<dt><code>-parallel</code></dt> +<dd><a name="index-_002dparallel-option_002c-M32RX"></a> +<p>This option tells the assembler to attempts to combine two sequential +instructions into a single, parallel instruction, where it is legal to +do so. +</p> +</dd> +<dt><code>-no-parallel</code></dt> +<dd><a name="index-_002dno_002dparallel-option_002c-M32RX"></a> +<p>This option disables a previously enabled <em>-parallel</em> option. +</p> +</dd> +<dt><code>-no-bitinst</code></dt> +<dd><a name="index-_002dno_002dbitinst_002c-M32R2"></a> +<p>This option disables the support for the extended bit-field +instructions provided by the M32R2. If this support needs to be +re-enabled the <em>-bitinst</em> switch can be used to restore it. +</p> +</dd> +<dt><code>-O</code></dt> +<dd><a name="index-_002dO-option_002c-M32RX"></a> +<p>This option tells the assembler to attempt to optimize the +instructions that it produces. This includes filling delay slots and +converting sequential instructions into parallel ones. This option +implies <em>-parallel</em>. +</p> +</dd> +<dt><code>-warn-explicit-parallel-conflicts</code></dt> +<dd><a name="index-_002dwarn_002dexplicit_002dparallel_002dconflicts-option_002c-M32RX"></a> +<p>Instructs <code>as</code> to produce warning messages when +questionable parallel instructions are encountered. This option is +enabled by default, but <code>gcc</code> disables it when it invokes +<code>as</code> directly. Questionable instructions are those whose +behaviour would be different if they were executed sequentially. For +example the code fragment ‘<samp>mv r1, r2 || mv r3, r1</samp>’ produces a +different result from ‘<samp>mv r1, r2 \n mv r3, r1</samp>’ since the former +moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 +and r3. +</p> +</dd> +<dt><code>-Wp</code></dt> +<dd><a name="index-_002dWp-option_002c-M32RX"></a> +<p>This is a shorter synonym for the <em>-warn-explicit-parallel-conflicts</em> +option. +</p> +</dd> +<dt><code>-no-warn-explicit-parallel-conflicts</code></dt> +<dd><a name="index-_002dno_002dwarn_002dexplicit_002dparallel_002dconflicts-option_002c-M32RX"></a> +<p>Instructs <code>as</code> not to produce warning messages when +questionable parallel instructions are encountered. +</p> +</dd> +<dt><code>-Wnp</code></dt> +<dd><a name="index-_002dWnp-option_002c-M32RX"></a> +<p>This is a shorter synonym for the <em>-no-warn-explicit-parallel-conflicts</em> +option. +</p> +</dd> +<dt><code>-ignore-parallel-conflicts</code></dt> +<dd><a name="index-_002dignore_002dparallel_002dconflicts-option_002c-M32RX"></a> +<p>This option tells the assembler’s to stop checking parallel +instructions for constraint violations. This ability is provided for +hardware vendors testing chip designs and should not be used under +normal circumstances. +</p> +</dd> +<dt><code>-no-ignore-parallel-conflicts</code></dt> +<dd><a name="index-_002dno_002dignore_002dparallel_002dconflicts-option_002c-M32RX"></a> +<p>This option restores the assembler’s default behaviour of checking +parallel instructions to detect constraint violations. +</p> +</dd> +<dt><code>-Ip</code></dt> +<dd><a name="index-_002dIp-option_002c-M32RX"></a> +<p>This is a shorter synonym for the <em>-ignore-parallel-conflicts</em> +option. +</p> +</dd> +<dt><code>-nIp</code></dt> +<dd><a name="index-_002dnIp-option_002c-M32RX"></a> +<p>This is a shorter synonym for the <em>-no-ignore-parallel-conflicts</em> +option. +</p> +</dd> +<dt><code>-warn-unmatched-high</code></dt> +<dd><a name="index-_002dwarn_002dunmatched_002dhigh-option_002c-M32R"></a> +<p>This option tells the assembler to produce a warning message if a +<code>.high</code> pseudo op is encountered without a matching <code>.low</code> +pseudo op. The presence of such an unmatched pseudo op usually +indicates a programming error. +</p> +</dd> +<dt><code>-no-warn-unmatched-high</code></dt> +<dd><a name="index-_002dno_002dwarn_002dunmatched_002dhigh-option_002c-M32R"></a> +<p>Disables a previously enabled <em>-warn-unmatched-high</em> option. +</p> +</dd> +<dt><code>-Wuh</code></dt> +<dd><a name="index-_002dWuh-option_002c-M32RX"></a> +<p>This is a shorter synonym for the <em>-warn-unmatched-high</em> option. +</p> +</dd> +<dt><code>-Wnuh</code></dt> +<dd><a name="index-_002dWnuh-option_002c-M32RX"></a> +<p>This is a shorter synonym for the <em>-no-warn-unmatched-high</em> option. +</p> +</dd> +</dl> + +<hr> +<a name="M32R_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#M32R_002dWarnings" accesskey="n" rel="next">M32R-Warnings</a>, Previous: <a href="#M32R_002dOpts" accesskey="p" rel="previous">M32R-Opts</a>, Up: <a href="#M32R_002dDependent" accesskey="u" rel="up">M32R-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M32R-Directives"></a> +<h4 class="subsection">9.21.2 M32R Directives</h4> +<a name="index-directives_002c-M32R"></a> +<a name="index-M32R-directives"></a> + +<p>The Renesas M32R version of <code>as</code> has a few architecture +specific directives: +</p> +<dl compact="compact"> +<dd> +<a name="index-low-directive_002c-M32R"></a> +</dd> +<dt><code>low <var>expression</var></code></dt> +<dd><p>The <code>low</code> directive computes the value of its expression and +places the lower 16-bits of the result into the immediate-field of the +instruction. For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 + add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred +</pre></div> + +</dd> +<dt><code>high <var>expression</var></code></dt> +<dd><a name="index-high-directive_002c-M32R"></a> +<p>The <code>high</code> directive computes the value of its expression and +places the upper 16-bits of the result into the immediate-field of the +instruction. For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> seth r0, #high(0x12345678) ; compute r0 = 0x12340000 + seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred +</pre></div> + +</dd> +<dt><code>shigh <var>expression</var></code></dt> +<dd><a name="index-shigh-directive_002c-M32R"></a> +<p>The <code>shigh</code> directive is very similar to the <code>high</code> +directive. It also computes the value of its expression and places +the upper 16-bits of the result into the immediate-field of the +instruction. The difference is that <code>shigh</code> also checks to see +if the lower 16-bits could be interpreted as a signed number, and if +so it assumes that a borrow will occur from the upper-16 bits. To +compensate for this the <code>shigh</code> directive pre-biases the upper +16 bit value by adding one to it. For example: +</p> +<p>For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 + seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 +</pre></div> + +<p>In the second example the lower 16-bits are 0x8000. If these are +treated as a signed value and sign extended to 32-bits then the value +becomes 0xffff8000. If this value is then added to 0x00010000 then +the result is 0x00008000. +</p> +<p>This behaviour is to allow for the different semantics of the +<code>or3</code> and <code>add3</code> instructions. The <code>or3</code> instruction +treats its 16-bit immediate argument as unsigned whereas the +<code>add3</code> treats its 16-bit immediate as a signed value. So for +example: +</p> +<div class="smallexample"> +<pre class="smallexample"> seth r0, #shigh(0x00008000) + add3 r0, r0, #low(0x00008000) +</pre></div> + +<p>Produces the correct result in r0, whereas: +</p> +<div class="smallexample"> +<pre class="smallexample"> seth r0, #shigh(0x00008000) + or3 r0, r0, #low(0x00008000) +</pre></div> + +<p>Stores 0xffff8000 into r0. +</p> +<p>Note - the <code>shigh</code> directive does not know where in the assembly +source code the lower 16-bits of the value are going set, so it cannot +check to make sure that an <code>or3</code> instruction is being used rather +than an <code>add3</code> instruction. It is up to the programmer to make +sure that correct directives are used. +</p> +<a name="index-_002em32r-directive_002c-M32R"></a> +</dd> +<dt><code>.m32r</code></dt> +<dd><p>The directive performs a similar thing as the <em>-m32r</em> command +line option. It tells the assembler to only accept M32R instructions +from now on. An instructions from later M32R architectures are +refused. +</p> +<a name="index-_002em32rx-directive_002c-M32RX"></a> +</dd> +<dt><code>.m32rx</code></dt> +<dd><p>The directive performs a similar thing as the <em>-m32rx</em> command +line option. It tells the assembler to start accepting the extra +instructions in the M32RX ISA as well as the ordinary M32R ISA. +</p> +<a name="index-_002em32r2-directive_002c-M32R2"></a> +</dd> +<dt><code>.m32r2</code></dt> +<dd><p>The directive performs a similar thing as the <em>-m32r2</em> command +line option. It tells the assembler to start accepting the extra +instructions in the M32R2 ISA as well as the ordinary M32R ISA. +</p> +<a name="index-_002elittle-directive_002c-M32RX"></a> +</dd> +<dt><code>.little</code></dt> +<dd><p>The directive performs a similar thing as the <em>-little</em> command +line option. It tells the assembler to start producing little-endian +code and data. This option should be used with care as producing +mixed-endian binary files is fraught with danger. +</p> +<a name="index-_002ebig-directive_002c-M32RX"></a> +</dd> +<dt><code>.big</code></dt> +<dd><p>The directive performs a similar thing as the <em>-big</em> command +line option. It tells the assembler to start producing big-endian +code and data. This option should be used with care as producing +mixed-endian binary files is fraught with danger. +</p> +</dd> +</dl> + +<hr> +<a name="M32R_002dWarnings"></a> +<div class="header"> +<p> +Previous: <a href="#M32R_002dDirectives" accesskey="p" rel="previous">M32R-Directives</a>, Up: <a href="#M32R_002dDependent" accesskey="u" rel="up">M32R-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M32R-Warnings"></a> +<h4 class="subsection">9.21.3 M32R Warnings</h4> + +<a name="index-warnings_002c-M32R"></a> +<a name="index-M32R-warnings"></a> + +<p>There are several warning and error messages that can be produced by +<code>as</code> which are specific to the M32R: +</p> +<dl compact="compact"> +<dt><code>output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?</code></dt> +<dd><p>This message is only produced if warnings for explicit parallel +conflicts have been enabled. It indicates that the assembler has +encountered a parallel instruction in which the destination register of +the left hand instruction is used as an input register in the right hand +instruction. For example in this code fragment +‘<samp>mv r1, r2 || neg r3, r1</samp>’ register r1 is the destination of the +move instruction and the input to the neg instruction. +</p> +</dd> +<dt><code>output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?</code></dt> +<dd><p>This message is only produced if warnings for explicit parallel +conflicts have been enabled. It indicates that the assembler has +encountered a parallel instruction in which the destination register of +the right hand instruction is used as an input register in the left hand +instruction. For example in this code fragment +‘<samp>mv r1, r2 || neg r2, r3</samp>’ register r2 is the destination of the +neg instruction and the input to the move instruction. +</p> +</dd> +<dt><code>instruction ‘<samp>...</samp>’ is for the M32RX only</code></dt> +<dd><p>This message is produced when the assembler encounters an instruction +which is only supported by the M32Rx processor, and the ‘<samp>-m32rx</samp>’ +command-line flag has not been specified to allow assembly of such +instructions. +</p> +</dd> +<dt><code>unknown instruction ‘<samp>...</samp>’</code></dt> +<dd><p>This message is produced when the assembler encounters an instruction +which it does not recognize. +</p> +</dd> +<dt><code>only the NOP instruction can be issued in parallel on the m32r</code></dt> +<dd><p>This message is produced when the assembler encounters a parallel +instruction which does not involve a NOP instruction and the +‘<samp>-m32rx</samp>’ command-line flag has not been specified. Only the M32Rx +processor is able to execute two instructions in parallel. +</p> +</dd> +<dt><code>instruction ‘<samp>...</samp>’ cannot be executed in parallel.</code></dt> +<dd><p>This message is produced when the assembler encounters a parallel +instruction which is made up of one or two instructions which cannot be +executed in parallel. +</p> +</dd> +<dt><code>Instructions share the same execution pipeline</code></dt> +<dd><p>This message is produced when the assembler encounters a parallel +instruction whose components both use the same execution pipeline. +</p> +</dd> +<dt><code>Instructions write to the same destination register.</code></dt> +<dd><p>This message is produced when the assembler encounters a parallel +instruction where both components attempt to modify the same register. +For example these code fragments will produce this message: +‘<samp>mv r1, r2 || neg r1, r3</samp>’ +‘<samp>jl r0 || mv r14, r1</samp>’ +‘<samp>st r2, @-r1 || mv r1, r3</samp>’ +‘<samp>mv r1, r2 || ld r0, @r1+</samp>’ +‘<samp>cmp r1, r2 || addx r3, r4</samp>’ (Both write to the condition bit) +</p> +</dd> +</dl> + +<hr> +<a name="M68K_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#M68HC11_002dDependent" accesskey="n" rel="next">M68HC11-Dependent</a>, Previous: <a href="#M32R_002dDependent" accesskey="p" rel="previous">M32R-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M680x0-Dependent-Features"></a> +<h3 class="section">9.22 M680x0 Dependent Features</h3> + +<a name="index-M680x0-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#M68K_002dOpts" accesskey="1">M68K-Opts</a>:</td><td> </td><td align="left" valign="top">M680x0 Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68K_002dSyntax" accesskey="2">M68K-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68K_002dMoto_002dSyntax" accesskey="3">M68K-Moto-Syntax</a>:</td><td> </td><td align="left" valign="top">Motorola Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68K_002dFloat" accesskey="4">M68K-Float</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68K_002dDirectives" accesskey="5">M68K-Directives</a>:</td><td> </td><td align="left" valign="top">680x0 Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68K_002dopcodes" accesskey="6">M68K-opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="M68K_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#M68K_002dSyntax" accesskey="n" rel="next">M68K-Syntax</a>, Up: <a href="#M68K_002dDependent" accesskey="u" rel="up">M68K-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M680x0-Options"></a> +<h4 class="subsection">9.22.1 M680x0 Options</h4> + +<a name="index-options_002c-M680x0"></a> +<a name="index-M680x0-options"></a> +<p>The Motorola 680x0 version of <code>as</code> has a few machine +dependent options: +</p> +<dl compact="compact"> +<dd> +<a name="index-_002dmarch_003d-command_002dline-option_002c-M680x0"></a> +</dd> +<dt>‘<samp>-march=<var>architecture</var></samp>’</dt> +<dd><p>This option specifies a target architecture. The following +architectures are recognized: +<code>68000</code>, +<code>68010</code>, +<code>68020</code>, +<code>68030</code>, +<code>68040</code>, +<code>68060</code>, +<code>cpu32</code>, +<code>isaa</code>, +<code>isaaplus</code>, +<code>isab</code>, +<code>isac</code> and +<code>cfv4e</code>. +</p> + +<a name="index-_002dmcpu_003d-command_002dline-option_002c-M680x0"></a> +</dd> +<dt>‘<samp>-mcpu=<var>cpu</var></samp>’</dt> +<dd><p>This option specifies a target cpu. When used in conjunction with the +<samp>-march</samp> option, the cpu must be within the specified +architecture. Also, the generic features of the architecture are used +for instruction generation, rather than those of the specific chip. +</p> +<a name="index-_002dm_005bno_002d_005d68851-command_002dline-option_002c-M680x0"></a> +<a name="index-_002dm_005bno_002d_005d68881-command_002dline-option_002c-M680x0"></a> +<a name="index-_002dm_005bno_002d_005ddiv-command_002dline-option_002c-M680x0"></a> +<a name="index-_002dm_005bno_002d_005dusp-command_002dline-option_002c-M680x0"></a> +<a name="index-_002dm_005bno_002d_005dfloat-command_002dline-option_002c-M680x0"></a> +<a name="index-_002dm_005bno_002d_005dmac-command_002dline-option_002c-M680x0"></a> +<a name="index-_002dm_005bno_002d_005demac-command_002dline-option_002c-M680x0"></a> +</dd> +<dt>‘<samp>-m[no-]68851</samp>’</dt> +<dt>‘<samp>-m[no-]68881</samp>’</dt> +<dt>‘<samp>-m[no-]div</samp>’</dt> +<dt>‘<samp>-m[no-]usp</samp>’</dt> +<dt>‘<samp>-m[no-]float</samp>’</dt> +<dt>‘<samp>-m[no-]mac</samp>’</dt> +<dt>‘<samp>-m[no-]emac</samp>’</dt> +<dd> +<p>Enable or disable various architecture specific features. If a chip +or architecture by default supports an option (for instance +<samp>-march=isaaplus</samp> includes the <samp>-mdiv</samp> option), +explicitly disabling the option will override the default. +</p> +<a name="index-_002dl-option_002c-M680x0"></a> +</dd> +<dt>‘<samp>-l</samp>’</dt> +<dd><p>You can use the ‘<samp>-l</samp>’ option to shorten the size of references to undefined +symbols. If you do not use the ‘<samp>-l</samp>’ option, references to undefined +symbols are wide enough for a full <code>long</code> (32 bits). (Since +<code>as</code> cannot know where these symbols end up, <code>as</code> can +only allocate space for the linker to fill in later. Since <code>as</code> +does not know how far away these symbols are, it allocates as much space as it +can.) If you use this option, the references are only one word wide (16 bits). +This may be useful if you want the object file to be as small as possible, and +you know that the relevant symbols are always less than 17 bits away. +</p> +<a name="index-_002d_002dregister_002dprefix_002doptional-option_002c-M680x0"></a> +</dd> +<dt>‘<samp>--register-prefix-optional</samp>’</dt> +<dd><p>For some configurations, especially those where the compiler normally +does not prepend an underscore to the names of user variables, the +assembler requires a ‘<samp>%</samp>’ before any use of a register name. This +is intended to let the assembler distinguish between C variables and +functions named ‘<samp>a0</samp>’ through ‘<samp>a7</samp>’, and so on. The ‘<samp>%</samp>’ is +always accepted, but is not required for certain configurations, notably +‘<samp>sun3</samp>’. The ‘<samp>--register-prefix-optional</samp>’ option may be used +to permit omitting the ‘<samp>%</samp>’ even for configurations for which it is +normally required. If this is done, it will generally be impossible to +refer to C variables and functions with the same names as register +names. +</p> +<a name="index-_002d_002dbitwise_002dor-option_002c-M680x0"></a> +</dd> +<dt>‘<samp>--bitwise-or</samp>’</dt> +<dd><p>Normally the character ‘<samp>|</samp>’ is treated as a comment character, which +means that it can not be used in expressions. The ‘<samp>--bitwise-or</samp>’ +option turns ‘<samp>|</samp>’ into a normal character. In this mode, you must +either use C style comments, or start comments with a ‘<samp>#</samp>’ character +at the beginning of a line. +</p> +<a name="index-_002d_002dbase_002dsize_002ddefault_002d16"></a> +<a name="index-_002d_002dbase_002dsize_002ddefault_002d32"></a> +</dd> +<dt>‘<samp>--base-size-default-16 --base-size-default-32</samp>’</dt> +<dd><p>If you use an addressing mode with a base register without specifying +the size, <code>as</code> will normally use the full 32 bit value. +For example, the addressing mode ‘<samp>%a0@(%d0)</samp>’ is equivalent to +‘<samp>%a0@(%d0:l)</samp>’. You may use the ‘<samp>--base-size-default-16</samp>’ +option to tell <code>as</code> to default to using the 16 bit value. +In this case, ‘<samp>%a0@(%d0)</samp>’ is equivalent to ‘<samp>%a0@(%d0:w)</samp>’. +You may use the ‘<samp>--base-size-default-32</samp>’ option to restore the +default behaviour. +</p> +<a name="index-_002d_002ddisp_002dsize_002ddefault_002d16"></a> +<a name="index-_002d_002ddisp_002dsize_002ddefault_002d32"></a> +</dd> +<dt>‘<samp>--disp-size-default-16 --disp-size-default-32</samp>’</dt> +<dd><p>If you use an addressing mode with a displacement, and the value of the +displacement is not known, <code>as</code> will normally assume that +the value is 32 bits. For example, if the symbol ‘<samp>disp</samp>’ has not +been defined, <code>as</code> will assemble the addressing mode +‘<samp>%a0@(disp,%d0)</samp>’ as though ‘<samp>disp</samp>’ is a 32 bit value. You may +use the ‘<samp>--disp-size-default-16</samp>’ option to tell <code>as</code> +to instead assume that the displacement is 16 bits. In this case, +<code>as</code> will assemble ‘<samp>%a0@(disp,%d0)</samp>’ as though +‘<samp>disp</samp>’ is a 16 bit value. You may use the +‘<samp>--disp-size-default-32</samp>’ option to restore the default behaviour. +</p> +<a name="index-_002d_002dpcrel"></a> +</dd> +<dt>‘<samp>--pcrel</samp>’</dt> +<dd><p>Always keep branches PC-relative. In the M680x0 architecture all branches +are defined as PC-relative. However, on some processors they are limited +to word displacements maximum. When <code>as</code> needs a long branch +that is not available, it normally emits an absolute jump instead. This +option disables this substitution. When this option is given and no long +branches are available, only word branches will be emitted. An error +message will be generated if a word branch cannot reach its target. This +option has no effect on 68020 and other processors that have long branches. +see <a href="#M68K_002dBranch">Branch Improvement</a>. +</p> +<a name="index-_002dm68000-and-related-options"></a> +<a name="index-architecture-options_002c-M680x0"></a> +<a name="index-M680x0-architecture-options"></a> +</dd> +<dt>‘<samp>-m68000</samp>’</dt> +<dd><p><code>as</code> can assemble code for several different members of the +Motorola 680x0 family. The default depends upon how <code>as</code> +was configured when it was built; normally, the default is to assemble +code for the 68020 microprocessor. The following options may be used to +change the default. These options control which instructions and +addressing modes are permitted. The members of the 680x0 family are +very similar. For detailed information about the differences, see the +Motorola manuals. +</p> +<dl compact="compact"> +<dt>‘<samp>-m68000</samp>’</dt> +<dt>‘<samp>-m68ec000</samp>’</dt> +<dt>‘<samp>-m68hc000</samp>’</dt> +<dt>‘<samp>-m68hc001</samp>’</dt> +<dt>‘<samp>-m68008</samp>’</dt> +<dt>‘<samp>-m68302</samp>’</dt> +<dt>‘<samp>-m68306</samp>’</dt> +<dt>‘<samp>-m68307</samp>’</dt> +<dt>‘<samp>-m68322</samp>’</dt> +<dt>‘<samp>-m68356</samp>’</dt> +<dd><p>Assemble for the 68000. ‘<samp>-m68008</samp>’, ‘<samp>-m68302</samp>’, and so on are synonyms +for ‘<samp>-m68000</samp>’, since the chips are the same from the point of view +of the assembler. +</p> +</dd> +<dt>‘<samp>-m68010</samp>’</dt> +<dd><p>Assemble for the 68010. +</p> +</dd> +<dt>‘<samp>-m68020</samp>’</dt> +<dt>‘<samp>-m68ec020</samp>’</dt> +<dd><p>Assemble for the 68020. This is normally the default. +</p> +</dd> +<dt>‘<samp>-m68030</samp>’</dt> +<dt>‘<samp>-m68ec030</samp>’</dt> +<dd><p>Assemble for the 68030. +</p> +</dd> +<dt>‘<samp>-m68040</samp>’</dt> +<dt>‘<samp>-m68ec040</samp>’</dt> +<dd><p>Assemble for the 68040. +</p> +</dd> +<dt>‘<samp>-m68060</samp>’</dt> +<dt>‘<samp>-m68ec060</samp>’</dt> +<dd><p>Assemble for the 68060. +</p> +</dd> +<dt>‘<samp>-mcpu32</samp>’</dt> +<dt>‘<samp>-m68330</samp>’</dt> +<dt>‘<samp>-m68331</samp>’</dt> +<dt>‘<samp>-m68332</samp>’</dt> +<dt>‘<samp>-m68333</samp>’</dt> +<dt>‘<samp>-m68334</samp>’</dt> +<dt>‘<samp>-m68336</samp>’</dt> +<dt>‘<samp>-m68340</samp>’</dt> +<dt>‘<samp>-m68341</samp>’</dt> +<dt>‘<samp>-m68349</samp>’</dt> +<dt>‘<samp>-m68360</samp>’</dt> +<dd><p>Assemble for the CPU32 family of chips. +</p> +</dd> +<dt>‘<samp>-m5200</samp>’</dt> +<dt>‘<samp>-m5202</samp>’</dt> +<dt>‘<samp>-m5204</samp>’</dt> +<dt>‘<samp>-m5206</samp>’</dt> +<dt>‘<samp>-m5206e</samp>’</dt> +<dt>‘<samp>-m521x</samp>’</dt> +<dt>‘<samp>-m5249</samp>’</dt> +<dt>‘<samp>-m528x</samp>’</dt> +<dt>‘<samp>-m5307</samp>’</dt> +<dt>‘<samp>-m5407</samp>’</dt> +<dt>‘<samp>-m547x</samp>’</dt> +<dt>‘<samp>-m548x</samp>’</dt> +<dt>‘<samp>-mcfv4</samp>’</dt> +<dt>‘<samp>-mcfv4e</samp>’</dt> +<dd><p>Assemble for the ColdFire family of chips. +</p> +</dd> +<dt>‘<samp>-m68881</samp>’</dt> +<dt>‘<samp>-m68882</samp>’</dt> +<dd><p>Assemble 68881 floating point instructions. This is the default for the +68020, 68030, and the CPU32. The 68040 and 68060 always support +floating point instructions. +</p> +</dd> +<dt>‘<samp>-mno-68881</samp>’</dt> +<dd><p>Do not assemble 68881 floating point instructions. This is the default +for 68000 and the 68010. The 68040 and 68060 always support floating +point instructions, even if this option is used. +</p> +</dd> +<dt>‘<samp>-m68851</samp>’</dt> +<dd><p>Assemble 68851 MMU instructions. This is the default for the 68020, +68030, and 68060. The 68040 accepts a somewhat different set of MMU +instructions; ‘<samp>-m68851</samp>’ and ‘<samp>-m68040</samp>’ should not be used +together. +</p> +</dd> +<dt>‘<samp>-mno-68851</samp>’</dt> +<dd><p>Do not assemble 68851 MMU instructions. This is the default for the +68000, 68010, and the CPU32. The 68040 accepts a somewhat different set +of MMU instructions. +</p></dd> +</dl> +</dd> +</dl> + +<hr> +<a name="M68K_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#M68K_002dMoto_002dSyntax" accesskey="n" rel="next">M68K-Moto-Syntax</a>, Previous: <a href="#M68K_002dOpts" accesskey="p" rel="previous">M68K-Opts</a>, Up: <a href="#M68K_002dDependent" accesskey="u" rel="up">M68K-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-17"></a> +<h4 class="subsection">9.22.2 Syntax</h4> + +<a name="index-MIT"></a> +<p>This syntax for the Motorola 680x0 was developed at <small>MIT</small>. +</p> +<a name="index-M680x0-syntax"></a> +<a name="index-syntax_002c-M680x0"></a> +<a name="index-M680x0-size-modifiers"></a> +<a name="index-size-modifiers_002c-M680x0"></a> +<p>The 680x0 version of <code>as</code> uses instructions names and +syntax compatible with the Sun assembler. Intervening periods are +ignored; for example, ‘<samp>movl</samp>’ is equivalent to ‘<samp>mov.l</samp>’. +</p> +<p>In the following table <var>apc</var> stands for any of the address registers +(‘<samp>%a0</samp>’ through ‘<samp>%a7</samp>’), the program counter (‘<samp>%pc</samp>’), the +zero-address relative to the program counter (‘<samp>%zpc</samp>’), a suppressed +address register (‘<samp>%za0</samp>’ through ‘<samp>%za7</samp>’), or it may be omitted +entirely. The use of <var>size</var> means one of ‘<samp>w</samp>’ or ‘<samp>l</samp>’, and +it may be omitted, along with the leading colon, unless a scale is also +specified. The use of <var>scale</var> means one of ‘<samp>1</samp>’, ‘<samp>2</samp>’, +‘<samp>4</samp>’, or ‘<samp>8</samp>’, and it may always be omitted along with the +leading colon. +</p> +<a name="index-M680x0-addressing-modes"></a> +<a name="index-addressing-modes_002c-M680x0"></a> +<p>The following addressing modes are understood: +</p><dl compact="compact"> +<dt><em>Immediate</em></dt> +<dd><p>‘<samp>#<var>number</var></samp>’ +</p> +</dd> +<dt><em>Data Register</em></dt> +<dd><p>‘<samp>%d0</samp>’ through ‘<samp>%d7</samp>’ +</p> +</dd> +<dt><em>Address Register</em></dt> +<dd><p>‘<samp>%a0</samp>’ through ‘<samp>%a7</samp>’<br> +‘<samp>%a7</samp>’ is also known as ‘<samp>%sp</samp>’, i.e., the Stack Pointer. <code>%a6</code> +is also known as ‘<samp>%fp</samp>’, the Frame Pointer. +</p> +</dd> +<dt><em>Address Register Indirect</em></dt> +<dd><p>‘<samp>%a0@</samp>’ through ‘<samp>%a7@</samp>’ +</p> +</dd> +<dt><em>Address Register Postincrement</em></dt> +<dd><p>‘<samp>%a0@+</samp>’ through ‘<samp>%a7@+</samp>’ +</p> +</dd> +<dt><em>Address Register Predecrement</em></dt> +<dd><p>‘<samp>%a0@-</samp>’ through ‘<samp>%a7@-</samp>’ +</p> +</dd> +<dt><em>Indirect Plus Offset</em></dt> +<dd><p>‘<samp><var>apc</var>@(<var>number</var>)</samp>’ +</p> +</dd> +<dt><em>Index</em></dt> +<dd><p>‘<samp><var>apc</var>@(<var>number</var>,<var>register</var>:<var>size</var>:<var>scale</var>)</samp>’ +</p> +<p>The <var>number</var> may be omitted. +</p> +</dd> +<dt><em>Postindex</em></dt> +<dd><p>‘<samp><var>apc</var>@(<var>number</var>)@(<var>onumber</var>,<var>register</var>:<var>size</var>:<var>scale</var>)</samp>’ +</p> +<p>The <var>onumber</var> or the <var>register</var>, but not both, may be omitted. +</p> +</dd> +<dt><em>Preindex</em></dt> +<dd><p>‘<samp><var>apc</var>@(<var>number</var>,<var>register</var>:<var>size</var>:<var>scale</var>)@(<var>onumber</var>)</samp>’ +</p> +<p>The <var>number</var> may be omitted. Omitting the <var>register</var> produces +the Postindex addressing mode. +</p> +</dd> +<dt><em>Absolute</em></dt> +<dd><p>‘<samp><var>symbol</var></samp>’, or ‘<samp><var>digits</var></samp>’, optionally followed by +‘<samp>:b</samp>’, ‘<samp>:w</samp>’, or ‘<samp>:l</samp>’. +</p></dd> +</dl> + +<hr> +<a name="M68K_002dMoto_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#M68K_002dFloat" accesskey="n" rel="next">M68K-Float</a>, Previous: <a href="#M68K_002dSyntax" accesskey="p" rel="previous">M68K-Syntax</a>, Up: <a href="#M68K_002dDependent" accesskey="u" rel="up">M68K-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Motorola-Syntax"></a> +<h4 class="subsection">9.22.3 Motorola Syntax</h4> + +<a name="index-Motorola-syntax-for-the-680x0"></a> +<a name="index-alternate-syntax-for-the-680x0"></a> + +<p>The standard Motorola syntax for this chip differs from the syntax +already discussed (see <a href="#M68K_002dSyntax">Syntax</a>). <code>as</code> can +accept Motorola syntax for operands, even if <small>MIT</small> syntax is used for +other operands in the same instruction. The two kinds of syntax are +fully compatible. +</p> +<p>In the following table <var>apc</var> stands for any of the address registers +(‘<samp>%a0</samp>’ through ‘<samp>%a7</samp>’), the program counter (‘<samp>%pc</samp>’), the +zero-address relative to the program counter (‘<samp>%zpc</samp>’), or a +suppressed address register (‘<samp>%za0</samp>’ through ‘<samp>%za7</samp>’). The use +of <var>size</var> means one of ‘<samp>w</samp>’ or ‘<samp>l</samp>’, and it may always be +omitted along with the leading dot. The use of <var>scale</var> means one of +‘<samp>1</samp>’, ‘<samp>2</samp>’, ‘<samp>4</samp>’, or ‘<samp>8</samp>’, and it may always be omitted +along with the leading asterisk. +</p> +<p>The following additional addressing modes are understood: +</p> +<dl compact="compact"> +<dt><em>Address Register Indirect</em></dt> +<dd><p>‘<samp>(%a0)</samp>’ through ‘<samp>(%a7)</samp>’<br> +‘<samp>%a7</samp>’ is also known as ‘<samp>%sp</samp>’, i.e., the Stack Pointer. <code>%a6</code> +is also known as ‘<samp>%fp</samp>’, the Frame Pointer. +</p> +</dd> +<dt><em>Address Register Postincrement</em></dt> +<dd><p>‘<samp>(%a0)+</samp>’ through ‘<samp>(%a7)+</samp>’ +</p> +</dd> +<dt><em>Address Register Predecrement</em></dt> +<dd><p>‘<samp>-(%a0)</samp>’ through ‘<samp>-(%a7)</samp>’ +</p> +</dd> +<dt><em>Indirect Plus Offset</em></dt> +<dd><p>‘<samp><var>number</var>(<var>%a0</var>)</samp>’ through ‘<samp><var>number</var>(<var>%a7</var>)</samp>’, +or ‘<samp><var>number</var>(<var>%pc</var>)</samp>’. +</p> +<p>The <var>number</var> may also appear within the parentheses, as in +‘<samp>(<var>number</var>,<var>%a0</var>)</samp>’. When used with the <var>pc</var>, the +<var>number</var> may be omitted (with an address register, omitting the +<var>number</var> produces Address Register Indirect mode). +</p> +</dd> +<dt><em>Index</em></dt> +<dd><p>‘<samp><var>number</var>(<var>apc</var>,<var>register</var>.<var>size</var>*<var>scale</var>)</samp>’ +</p> +<p>The <var>number</var> may be omitted, or it may appear within the +parentheses. The <var>apc</var> may be omitted. The <var>register</var> and the +<var>apc</var> may appear in either order. If both <var>apc</var> and +<var>register</var> are address registers, and the <var>size</var> and <var>scale</var> +are omitted, then the first register is taken as the base register, and +the second as the index register. +</p> +</dd> +<dt><em>Postindex</em></dt> +<dd><p>‘<samp>([<var>number</var>,<var>apc</var>],<var>register</var>.<var>size</var>*<var>scale</var>,<var>onumber</var>)</samp>’ +</p> +<p>The <var>onumber</var>, or the <var>register</var>, or both, may be omitted. +Either the <var>number</var> or the <var>apc</var> may be omitted, but not both. +</p> +</dd> +<dt><em>Preindex</em></dt> +<dd><p>‘<samp>([<var>number</var>,<var>apc</var>,<var>register</var>.<var>size</var>*<var>scale</var>],<var>onumber</var>)</samp>’ +</p> +<p>The <var>number</var>, or the <var>apc</var>, or the <var>register</var>, or any two of +them, may be omitted. The <var>onumber</var> may be omitted. The +<var>register</var> and the <var>apc</var> may appear in either order. If both +<var>apc</var> and <var>register</var> are address registers, and the <var>size</var> +and <var>scale</var> are omitted, then the first register is taken as the +base register, and the second as the index register. +</p></dd> +</dl> + +<hr> +<a name="M68K_002dFloat"></a> +<div class="header"> +<p> +Next: <a href="#M68K_002dDirectives" accesskey="n" rel="next">M68K-Directives</a>, Previous: <a href="#M68K_002dMoto_002dSyntax" accesskey="p" rel="previous">M68K-Moto-Syntax</a>, Up: <a href="#M68K_002dDependent" accesskey="u" rel="up">M68K-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-8"></a> +<h4 class="subsection">9.22.4 Floating Point</h4> + +<a name="index-floating-point_002c-M680x0"></a> +<a name="index-M680x0-floating-point"></a> +<p>Packed decimal (P) format floating literals are not supported. +Feel free to add the code! +</p> +<p>The floating point formats generated by directives are these. +</p> +<dl compact="compact"> +<dd><a name="index-float-directive_002c-M680x0"></a> +</dd> +<dt><code>.float</code></dt> +<dd><p><code>Single</code> precision floating point constants. +</p> +<a name="index-double-directive_002c-M680x0"></a> +</dd> +<dt><code>.double</code></dt> +<dd><p><code>Double</code> precision floating point constants. +</p> +<a name="index-extend-directive-M680x0"></a> +<a name="index-ldouble-directive-M680x0"></a> +</dd> +<dt><code>.extend</code></dt> +<dt><code>.ldouble</code></dt> +<dd><p><code>Extended</code> precision (<code>long double</code>) floating point constants. +</p></dd> +</dl> + +<hr> +<a name="M68K_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#M68K_002dopcodes" accesskey="n" rel="next">M68K-opcodes</a>, Previous: <a href="#M68K_002dFloat" accesskey="p" rel="previous">M68K-Float</a>, Up: <a href="#M68K_002dDependent" accesskey="u" rel="up">M68K-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="g_t680x0-Machine-Directives"></a> +<h4 class="subsection">9.22.5 680x0 Machine Directives</h4> + +<a name="index-M680x0-directives"></a> +<a name="index-directives_002c-M680x0"></a> +<p>In order to be compatible with the Sun assembler the 680x0 assembler +understands the following directives. +</p> +<dl compact="compact"> +<dd><a name="index-data1-directive_002c-M680x0"></a> +</dd> +<dt><code>.data1</code></dt> +<dd><p>This directive is identical to a <code>.data 1</code> directive. +</p> +<a name="index-data2-directive_002c-M680x0"></a> +</dd> +<dt><code>.data2</code></dt> +<dd><p>This directive is identical to a <code>.data 2</code> directive. +</p> +<a name="index-even-directive_002c-M680x0"></a> +</dd> +<dt><code>.even</code></dt> +<dd><p>This directive is a special case of the <code>.align</code> directive; it +aligns the output to an even byte boundary. +</p> +<a name="index-skip-directive_002c-M680x0"></a> +</dd> +<dt><code>.skip</code></dt> +<dd><p>This directive is identical to a <code>.space</code> directive. +</p> +<a name="index-arch-directive_002c-M680x0"></a> +</dd> +<dt><code>.arch <var>name</var></code></dt> +<dd><p>Select the target architecture and extension features. Valid values +for <var>name</var> are the same as for the <samp>-march</samp> command-line +option. This directive cannot be specified after +any instructions have been assembled. If it is given multiple times, +or in conjunction with the <samp>-march</samp> option, all uses must be for +the same architecture and extension set. +</p> +<a name="index-cpu-directive_002c-M680x0"></a> +</dd> +<dt><code>.cpu <var>name</var></code></dt> +<dd><p>Select the target cpu. Valid values +for <var>name</var> are the same as for the <samp>-mcpu</samp> command-line +option. This directive cannot be specified after +any instructions have been assembled. If it is given multiple times, +or in conjunction with the <samp>-mopt</samp> option, all uses must be for +the same cpu. +</p> +</dd> +</dl> + +<hr> +<a name="M68K_002dopcodes"></a> +<div class="header"> +<p> +Previous: <a href="#M68K_002dDirectives" accesskey="p" rel="previous">M68K-Directives</a>, Up: <a href="#M68K_002dDependent" accesskey="u" rel="up">M68K-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-12"></a> +<h4 class="subsection">9.22.6 Opcodes</h4> + +<a name="index-M680x0-opcodes"></a> +<a name="index-opcodes_002c-M680x0"></a> +<a name="index-instruction-set_002c-M680x0"></a> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#M68K_002dBranch" accesskey="1">M68K-Branch</a>:</td><td> </td><td align="left" valign="top">Branch Improvement +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68K_002dChars" accesskey="2">M68K-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="M68K_002dBranch"></a> +<div class="header"> +<p> +Next: <a href="#M68K_002dChars" accesskey="n" rel="next">M68K-Chars</a>, Up: <a href="#M68K_002dopcodes" accesskey="u" rel="up">M68K-opcodes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Branch-Improvement"></a> +<h4 class="subsubsection">9.22.6.1 Branch Improvement</h4> + +<a name="index-pseudo_002dopcodes_002c-M680x0"></a> +<a name="index-M680x0-pseudo_002dopcodes"></a> +<a name="index-branch-improvement_002c-M680x0"></a> +<a name="index-M680x0-branch-improvement"></a> +<p>Certain pseudo opcodes are permitted for branch instructions. +They expand to the shortest branch instruction that reach the +target. Generally these mnemonics are made by substituting ‘<samp>j</samp>’ for +‘<samp>b</samp>’ at the start of a Motorola mnemonic. +</p> +<p>The following table summarizes the pseudo-operations. A <code>*</code> flags +cases that are more fully described after the table: +</p> +<div class="smallexample"> +<pre class="smallexample"> Displacement + +------------------------------------------------------------ + | 68020 68000/10, not PC-relative OK +Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** + +------------------------------------------------------------ + jbsr |bsrs bsrw bsrl jsr + jra |bras braw bral jmp +* jXX |bXXs bXXw bXXl bNXs;jmp +* dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp + fjXX | N/A fbXXw fbXXl N/A + +XX: condition +NX: negative of condition XX + +</pre></div> +<div align="center"><code>*</code>—see full description below +</div><div align="center"><code>**</code>—this expansion mode is disallowed by ‘<samp>--pcrel</samp>’ +</div> +<dl compact="compact"> +<dt><code>jbsr</code></dt> +<dt><code>jra</code></dt> +<dd><p>These are the simplest jump pseudo-operations; they always map to one +particular machine instruction, depending on the displacement to the +branch target. This instruction will be a byte or word branch is that +is sufficient. Otherwise, a long branch will be emitted if available. +If no long branches are available and the ‘<samp>--pcrel</samp>’ option is not +given, an absolute long jump will be emitted instead. If no long +branches are available, the ‘<samp>--pcrel</samp>’ option is given, and a word +branch cannot reach the target, an error message is generated. +</p> +<p>In addition to standard branch operands, <code>as</code> allows these +pseudo-operations to have all operands that are allowed for jsr and jmp, +substituting these instructions if the operand given is not valid for a +branch instruction. +</p> +</dd> +<dt><code>j<var>XX</var></code></dt> +<dd><p>Here, ‘<samp>j<var>XX</var></samp>’ stands for an entire family of pseudo-operations, +where <var>XX</var> is a conditional branch or condition-code test. The full +list of pseudo-ops in this family is: +</p><div class="smallexample"> +<pre class="smallexample"> jhi jls jcc jcs jne jeq jvc + jvs jpl jmi jge jlt jgt jle +</pre></div> + +<p>Usually, each of these pseudo-operations expands to a single branch +instruction. However, if a word branch is not sufficient, no long branches +are available, and the ‘<samp>--pcrel</samp>’ option is not given, <code>as</code> +issues a longer code fragment in terms of <var>NX</var>, the opposite condition +to <var>XX</var>. For example, under these conditions: +</p><div class="smallexample"> +<pre class="smallexample"> j<var>XX</var> foo +</pre></div> +<p>gives +</p><div class="smallexample"> +<pre class="smallexample"> b<var>NX</var>s oof + jmp foo + oof: +</pre></div> + +</dd> +<dt><code>db<var>XX</var></code></dt> +<dd><p>The full family of pseudo-operations covered here is +</p><div class="smallexample"> +<pre class="smallexample"> dbhi dbls dbcc dbcs dbne dbeq dbvc + dbvs dbpl dbmi dbge dblt dbgt dble + dbf dbra dbt +</pre></div> + +<p>Motorola ‘<samp>db<var>XX</var></samp>’ instructions allow word displacements only. When +a word displacement is sufficient, each of these pseudo-operations expands +to the corresponding Motorola instruction. When a word displacement is not +sufficient and long branches are available, when the source reads +‘<samp>db<var>XX</var> foo</samp>’, <code>as</code> emits +</p><div class="smallexample"> +<pre class="smallexample"> db<var>XX</var> oo1 + bras oo2 + oo1:bral foo + oo2: +</pre></div> + +<p>If, however, long branches are not available and the ‘<samp>--pcrel</samp>’ option is +not given, <code>as</code> emits +</p><div class="smallexample"> +<pre class="smallexample"> db<var>XX</var> oo1 + bras oo2 + oo1:jmp foo + oo2: +</pre></div> + +</dd> +<dt><code>fj<var>XX</var></code></dt> +<dd><p>This family includes +</p><div class="smallexample"> +<pre class="smallexample"> fjne fjeq fjge fjlt fjgt fjle fjf + fjt fjgl fjgle fjnge fjngl fjngle fjngt + fjnle fjnlt fjoge fjogl fjogt fjole fjolt + fjor fjseq fjsf fjsne fjst fjueq fjuge + fjugt fjule fjult fjun +</pre></div> + +<p>Each of these pseudo-operations always expands to a single Motorola +coprocessor branch instruction, word or long. All Motorola coprocessor +branch instructions allow both word and long displacements. +</p> +</dd> +</dl> + +<hr> +<a name="M68K_002dChars"></a> +<div class="header"> +<p> +Previous: <a href="#M68K_002dBranch" accesskey="p" rel="previous">M68K-Branch</a>, Up: <a href="#M68K_002dopcodes" accesskey="u" rel="up">M68K-opcodes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-17"></a> +<h4 class="subsubsection">9.22.6.2 Special Characters</h4> + +<a name="index-special-characters_002c-M680x0"></a> + +<a name="index-M680x0-line-comment-character"></a> +<a name="index-line-comment-character_002c-M680x0"></a> +<a name="index-comments_002c-M680x0"></a> +<p>Line comments are introduced by the ‘<samp>|</samp>’ character appearing +anywhere on a line, unless the <samp>--bitwise-or</samp> command-line option +has been specified. +</p> +<p>An asterisk (‘<samp>*</samp>’) as the first character on a line marks the +start of a line comment as well. +</p> +<a name="index-M680x0-immediate-character"></a> +<a name="index-immediate-character_002c-M680x0"></a> + +<p>A hash character (‘<samp>#</samp>’) as the first character on a line also +marks the start of a line comment, but in this case it could also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). If the hash character +appears elsewhere on a line it is used to introduce an immediate +value. (This is for compatibility with Sun’s assembler). +</p> +<a name="index-M680x0-line-separator"></a> +<a name="index-line-separator_002c-M680x0"></a> + +<p>Multiple statements on the same line can appear if they are separated +by the ‘<samp>;</samp>’ character. +</p> +<hr> +<a name="M68HC11_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#S12Z_002dDependent" accesskey="n" rel="next">S12Z-Dependent</a>, Previous: <a href="#M68K_002dDependent" accesskey="p" rel="previous">M68K-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M68HC11-and-M68HC12-Dependent-Features"></a> +<h3 class="section">9.23 M68HC11 and M68HC12 Dependent Features</h3> + +<a name="index-M68HC11-and-M68HC12-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#M68HC11_002dOpts" accesskey="1">M68HC11-Opts</a>:</td><td> </td><td align="left" valign="top">M68HC11 and M68HC12 Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68HC11_002dSyntax" accesskey="2">M68HC11-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68HC11_002dModifiers" accesskey="3">M68HC11-Modifiers</a>:</td><td> </td><td align="left" valign="top">Symbolic Operand Modifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68HC11_002dDirectives" accesskey="4">M68HC11-Directives</a>:</td><td> </td><td align="left" valign="top">Assembler Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68HC11_002dFloat" accesskey="5">M68HC11-Float</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#M68HC11_002dopcodes" accesskey="6">M68HC11-opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="M68HC11_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#M68HC11_002dSyntax" accesskey="n" rel="next">M68HC11-Syntax</a>, Up: <a href="#M68HC11_002dDependent" accesskey="u" rel="up">M68HC11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="M68HC11-and-M68HC12-Options"></a> +<h4 class="subsection">9.23.1 M68HC11 and M68HC12 Options</h4> + +<a name="index-options_002c-M68HC11"></a> +<a name="index-M68HC11-options"></a> +<p>The Motorola 68HC11 and 68HC12 version of <code>as</code> have a few machine +dependent options. +</p> +<dl compact="compact"> +<dd> +<a name="index-_002dm68hc11"></a> +</dd> +<dt><code>-m68hc11</code></dt> +<dd><p>This option switches the assembler into the M68HC11 mode. In this mode, +the assembler only accepts 68HC11 operands and mnemonics. It produces +code for the 68HC11. +</p> +<a name="index-_002dm68hc12"></a> +</dd> +<dt><code>-m68hc12</code></dt> +<dd><p>This option switches the assembler into the M68HC12 mode. In this mode, +the assembler also accepts 68HC12 operands and mnemonics. It produces +code for the 68HC12. A few 68HC11 instructions are replaced by +some 68HC12 instructions as recommended by Motorola specifications. +</p> +<a name="index-_002dm68hcs12"></a> +</dd> +<dt><code>-m68hcs12</code></dt> +<dd><p>This option switches the assembler into the M68HCS12 mode. This mode is +similar to ‘<samp>-m68hc12</samp>’ but specifies to assemble for the 68HCS12 +series. The only difference is on the assembling of the ‘<samp>movb</samp>’ +and ‘<samp>movw</samp>’ instruction when a PC-relative operand is used. +</p> +<a name="index-_002dmm9s12x"></a> +</dd> +<dt><code>-mm9s12x</code></dt> +<dd><p>This option switches the assembler into the M9S12X mode. This mode is +similar to ‘<samp>-m68hc12</samp>’ but specifies to assemble for the S12X +series which is a superset of the HCS12. +</p> +<a name="index-_002dmm9s12xg"></a> +</dd> +<dt><code>-mm9s12xg</code></dt> +<dd><p>This option switches the assembler into the XGATE mode for the RISC +co-processor featured on some S12X-family chips. +</p> +<a name="index-_002d_002dxgate_002dramoffset"></a> +</dd> +<dt><code>--xgate-ramoffset</code></dt> +<dd><p>This option instructs the linker to offset RAM addresses from S12X address +space into XGATE address space. +</p> +<a name="index-_002dmshort"></a> +</dd> +<dt><code>-mshort</code></dt> +<dd><p>This option controls the ABI and indicates to use a 16-bit integer ABI. +It has no effect on the assembled instructions. +This is the default. +</p> +<a name="index-_002dmlong"></a> +</dd> +<dt><code>-mlong</code></dt> +<dd><p>This option controls the ABI and indicates to use a 32-bit integer ABI. +</p> +<a name="index-_002dmshort_002ddouble"></a> +</dd> +<dt><code>-mshort-double</code></dt> +<dd><p>This option controls the ABI and indicates to use a 32-bit float ABI. +This is the default. +</p> +<a name="index-_002dmlong_002ddouble"></a> +</dd> +<dt><code>-mlong-double</code></dt> +<dd><p>This option controls the ABI and indicates to use a 64-bit float ABI. +</p> +<a name="index-_002d_002dstrict_002ddirect_002dmode"></a> +</dd> +<dt><code>--strict-direct-mode</code></dt> +<dd><p>You can use the ‘<samp>--strict-direct-mode</samp>’ option to disable +the automatic translation of direct page mode addressing into +extended mode when the instruction does not support direct mode. +For example, the ‘<samp>clr</samp>’ instruction does not support direct page +mode addressing. When it is used with the direct page mode, +<code>as</code> will ignore it and generate an absolute addressing. +This option prevents <code>as</code> from doing this, and the wrong +usage of the direct page mode will raise an error. +</p> +<a name="index-_002d_002dshort_002dbranches"></a> +</dd> +<dt><code>--short-branches</code></dt> +<dd><p>The ‘<samp>--short-branches</samp>’ option turns off the translation of +relative branches into absolute branches when the branch offset is +out of range. By default <code>as</code> transforms the relative +branch (‘<samp>bsr</samp>’, ‘<samp>bgt</samp>’, ‘<samp>bge</samp>’, ‘<samp>beq</samp>’, ‘<samp>bne</samp>’, +‘<samp>ble</samp>’, ‘<samp>blt</samp>’, ‘<samp>bhi</samp>’, ‘<samp>bcc</samp>’, ‘<samp>bls</samp>’, +‘<samp>bcs</samp>’, ‘<samp>bmi</samp>’, ‘<samp>bvs</samp>’, ‘<samp>bvs</samp>’, ‘<samp>bra</samp>’) into +an absolute branch when the offset is out of the -128 .. 127 range. +In that case, the ‘<samp>bsr</samp>’ instruction is translated into a +‘<samp>jsr</samp>’, the ‘<samp>bra</samp>’ instruction is translated into a +‘<samp>jmp</samp>’ and the conditional branches instructions are inverted and +followed by a ‘<samp>jmp</samp>’. This option disables these translations +and <code>as</code> will generate an error if a relative branch +is out of range. This option does not affect the optimization +associated to the ‘<samp>jbra</samp>’, ‘<samp>jbsr</samp>’ and ‘<samp>jbXX</samp>’ pseudo opcodes. +</p> +<a name="index-_002d_002dforce_002dlong_002dbranches"></a> +</dd> +<dt><code>--force-long-branches</code></dt> +<dd><p>The ‘<samp>--force-long-branches</samp>’ option forces the translation of +relative branches into absolute branches. This option does not affect +the optimization associated to the ‘<samp>jbra</samp>’, ‘<samp>jbsr</samp>’ and +‘<samp>jbXX</samp>’ pseudo opcodes. +</p> +<a name="index-_002d_002dprint_002dinsn_002dsyntax"></a> +</dd> +<dt><code>--print-insn-syntax</code></dt> +<dd><p>You can use the ‘<samp>--print-insn-syntax</samp>’ option to obtain the +syntax description of the instruction when an error is detected. +</p> +<a name="index-_002d_002dprint_002dopcodes"></a> +</dd> +<dt><code>--print-opcodes</code></dt> +<dd><p>The ‘<samp>--print-opcodes</samp>’ option prints the list of all the +instructions with their syntax. The first item of each line +represents the instruction name and the rest of the line indicates +the possible operands for that instruction. The list is printed +in alphabetical order. Once the list is printed <code>as</code> +exits. +</p> +<a name="index-_002d_002dgenerate_002dexample"></a> +</dd> +<dt><code>--generate-example</code></dt> +<dd><p>The ‘<samp>--generate-example</samp>’ option is similar to ‘<samp>--print-opcodes</samp>’ +but it generates an example for each instruction instead. +</p></dd> +</dl> + +<hr> +<a name="M68HC11_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#M68HC11_002dModifiers" accesskey="n" rel="next">M68HC11-Modifiers</a>, Previous: <a href="#M68HC11_002dOpts" accesskey="p" rel="previous">M68HC11-Opts</a>, Up: <a href="#M68HC11_002dDependent" accesskey="u" rel="up">M68HC11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-18"></a> +<h4 class="subsection">9.23.2 Syntax</h4> + +<a name="index-M68HC11-syntax"></a> +<a name="index-syntax_002c-M68HC11"></a> + +<p>In the M68HC11 syntax, the instruction name comes first and it may +be followed by one or several operands (up to three). Operands are +separated by comma (‘<samp>,</samp>’). In the normal mode, +<code>as</code> will complain if too many operands are specified for +a given instruction. In the MRI mode (turned on with ‘<samp>-M</samp>’ option), +it will treat them as comments. Example: +</p> +<div class="smallexample"> +<pre class="smallexample">inx +lda #23 +bset 2,x #4 +brclr *bot #8 foo +</pre></div> + +<a name="index-line-comment-character_002c-M68HC11"></a> +<a name="index-M68HC11-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ character or a ‘<samp>!</samp>’ character anywhere +on a line indicates the start of a comment that extends to the end of +that line. +</p> +<p>A ‘<samp>*</samp>’ or a ‘<samp>#</samp>’ character at the start of a line also +introduces a line comment, but these characters do not work elsewhere +on the line. If the first character of the line is a ‘<samp>#</samp>’ then as +well as starting a comment, the line could also be logical line number +directive (see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-M68HC11"></a> +<a name="index-statement-separator_002c-M68HC11"></a> +<a name="index-M68HC11-line-separator"></a> +<p>The M68HC11 assembler does not currently support a line separator +character. +</p> +<a name="index-M68HC11-addressing-modes"></a> +<a name="index-addressing-modes_002c-M68HC11"></a> +<p>The following addressing modes are understood for 68HC11 and 68HC12: +</p><dl compact="compact"> +<dt><em>Immediate</em></dt> +<dd><p>‘<samp>#<var>number</var></samp>’ +</p> +</dd> +<dt><em>Address Register</em></dt> +<dd><p>‘<samp><var>number</var>,X</samp>’, ‘<samp><var>number</var>,Y</samp>’ +</p> +<p>The <var>number</var> may be omitted in which case 0 is assumed. +</p> +</dd> +<dt><em>Direct Addressing mode</em></dt> +<dd><p>‘<samp>*<var>symbol</var></samp>’, or ‘<samp>*<var>digits</var></samp>’ +</p> +</dd> +<dt><em>Absolute</em></dt> +<dd><p>‘<samp><var>symbol</var></samp>’, or ‘<samp><var>digits</var></samp>’ +</p></dd> +</dl> + +<p>The M68HC12 has other more complex addressing modes. All of them +are supported and they are represented below: +</p> +<dl compact="compact"> +<dt><em>Constant Offset Indexed Addressing Mode</em></dt> +<dd><p>‘<samp><var>number</var>,<var>reg</var></samp>’ +</p> +<p>The <var>number</var> may be omitted in which case 0 is assumed. +The register can be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, ‘<samp>SP</samp>’ or +‘<samp>PC</samp>’. The assembler will use the smaller post-byte definition +according to the constant value (5-bit constant offset, 9-bit constant +offset or 16-bit constant offset). If the constant is not known by +the assembler it will use the 16-bit constant offset post-byte and the value +will be resolved at link time. +</p> +</dd> +<dt><em>Offset Indexed Indirect</em></dt> +<dd><p>‘<samp>[<var>number</var>,<var>reg</var>]</samp>’ +</p> +<p>The register can be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, ‘<samp>SP</samp>’ or ‘<samp>PC</samp>’. +</p> +</dd> +<dt><em>Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement</em></dt> +<dd><p>‘<samp><var>number</var>,-<var>reg</var></samp>’ +‘<samp><var>number</var>,+<var>reg</var></samp>’ +‘<samp><var>number</var>,<var>reg</var>-</samp>’ +‘<samp><var>number</var>,<var>reg</var>+</samp>’ +</p> +<p>The number must be in the range ‘<samp>-8</samp>’..‘<samp>+8</samp>’ and must not be 0. +The register can be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, ‘<samp>SP</samp>’ or ‘<samp>PC</samp>’. +</p> +</dd> +<dt><em>Accumulator Offset</em></dt> +<dd><p>‘<samp><var>acc</var>,<var>reg</var></samp>’ +</p> +<p>The accumulator register can be either ‘<samp>A</samp>’, ‘<samp>B</samp>’ or ‘<samp>D</samp>’. +The register can be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, ‘<samp>SP</samp>’ or ‘<samp>PC</samp>’. +</p> +</dd> +<dt><em>Accumulator D offset indexed-indirect</em></dt> +<dd><p>‘<samp>[D,<var>reg</var>]</samp>’ +</p> +<p>The register can be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, ‘<samp>SP</samp>’ or ‘<samp>PC</samp>’. +</p> +</dd> +</dl> + +<p>For example: +</p> +<div class="smallexample"> +<pre class="smallexample">ldab 1024,sp +ldd [10,x] +orab 3,+x +stab -2,y- +ldx a,pc +sty [d,sp] +</pre></div> + + +<hr> +<a name="M68HC11_002dModifiers"></a> +<div class="header"> +<p> +Next: <a href="#M68HC11_002dDirectives" accesskey="n" rel="next">M68HC11-Directives</a>, Previous: <a href="#M68HC11_002dSyntax" accesskey="p" rel="previous">M68HC11-Syntax</a>, Up: <a href="#M68HC11_002dDependent" accesskey="u" rel="up">M68HC11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbolic-Operand-Modifiers-1"></a> +<h4 class="subsection">9.23.3 Symbolic Operand Modifiers</h4> + +<a name="index-M68HC11-modifiers"></a> +<a name="index-syntax_002c-M68HC11-1"></a> + +<p>The assembler supports several modifiers when using symbol addresses +in 68HC11 and 68HC12 instruction operands. The general syntax is +the following: +</p> +<div class="smallexample"> +<pre class="smallexample">%modifier(symbol) +</pre></div> + +<dl compact="compact"> +<dd><a name="index-symbol-modifiers-3"></a> +</dd> +<dt><code>%addr</code></dt> +<dd><p>This modifier indicates to the assembler and linker to use +the 16-bit physical address corresponding to the symbol. This is intended +to be used on memory window systems to map a symbol in the memory bank window. +If the symbol is in a memory expansion part, the physical address +corresponds to the symbol address within the memory bank window. +If the symbol is not in a memory expansion part, this is the symbol address +(using or not using the %addr modifier has no effect in that case). +</p> +</dd> +<dt><code>%page</code></dt> +<dd><p>This modifier indicates to use the memory page number corresponding +to the symbol. If the symbol is in a memory expansion part, its page +number is computed by the linker as a number used to map the page containing +the symbol in the memory bank window. If the symbol is not in a memory +expansion part, the page number is 0. +</p> +</dd> +<dt><code>%hi</code></dt> +<dd><p>This modifier indicates to use the 8-bit high part of the physical +address of the symbol. +</p> +</dd> +<dt><code>%lo</code></dt> +<dd><p>This modifier indicates to use the 8-bit low part of the physical +address of the symbol. +</p> +</dd> +</dl> + +<p>For example a 68HC12 call to a function ‘<samp>foo_example</samp>’ stored in memory +expansion part could be written as follows: +</p> +<div class="smallexample"> +<pre class="smallexample">call %addr(foo_example),%page(foo_example) +</pre></div> + +<p>and this is equivalent to +</p> +<div class="smallexample"> +<pre class="smallexample">call foo_example +</pre></div> + +<p>And for 68HC11 it could be written as follows: +</p> +<div class="smallexample"> +<pre class="smallexample">ldab #%page(foo_example) +stab _page_switch +jsr %addr(foo_example) +</pre></div> + +<hr> +<a name="M68HC11_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#M68HC11_002dFloat" accesskey="n" rel="next">M68HC11-Float</a>, Previous: <a href="#M68HC11_002dModifiers" accesskey="p" rel="previous">M68HC11-Modifiers</a>, Up: <a href="#M68HC11_002dDependent" accesskey="u" rel="up">M68HC11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives-2"></a> +<h4 class="subsection">9.23.4 Assembler Directives</h4> + +<a name="index-assembler-directives_002c-M68HC11"></a> +<a name="index-assembler-directives_002c-M68HC12"></a> +<a name="index-M68HC11-assembler-directives"></a> +<a name="index-M68HC12-assembler-directives"></a> + +<p>The 68HC11 and 68HC12 version of <code>as</code> have the following +specific assembler directives: +</p> +<dl compact="compact"> +<dt><code>.relax</code></dt> +<dd><a name="index-assembler-directive-_002erelax_002c-M68HC11"></a> +<a name="index-M68HC11-assembler-directive-_002erelax"></a> +<p>The relax directive is used by the ‘<samp>GNU Compiler</samp>’ to emit a specific +relocation to mark a group of instructions for linker relaxation. +The sequence of instructions within the group must be known to the linker +so that relaxation can be performed. +</p> +</dd> +<dt><code>.mode [mshort|mlong|mshort-double|mlong-double]</code></dt> +<dd><a name="index-assembler-directive-_002emode_002c-M68HC11"></a> +<a name="index-M68HC11-assembler-directive-_002emode"></a> +<p>This directive specifies the ABI. It overrides the ‘<samp>-mshort</samp>’, +‘<samp>-mlong</samp>’, ‘<samp>-mshort-double</samp>’ and ‘<samp>-mlong-double</samp>’ options. +</p> +</dd> +<dt><code>.far <var>symbol</var></code></dt> +<dd><a name="index-assembler-directive-_002efar_002c-M68HC11"></a> +<a name="index-M68HC11-assembler-directive-_002efar"></a> +<p>This directive marks the symbol as a ‘<samp>far</samp>’ symbol meaning that it +uses a ‘<samp>call/rtc</samp>’ calling convention as opposed to ‘<samp>jsr/rts</samp>’. +During a final link, the linker will identify references to the ‘<samp>far</samp>’ +symbol and will verify the proper calling convention. +</p> +</dd> +<dt><code>.interrupt <var>symbol</var></code></dt> +<dd><a name="index-assembler-directive-_002einterrupt_002c-M68HC11"></a> +<a name="index-M68HC11-assembler-directive-_002einterrupt"></a> +<p>This directive marks the symbol as an interrupt entry point. +This information is then used by the debugger to correctly unwind the +frame across interrupts. +</p> +</dd> +<dt><code>.xrefb <var>symbol</var></code></dt> +<dd><a name="index-assembler-directive-_002exrefb_002c-M68HC11"></a> +<a name="index-M68HC11-assembler-directive-_002exrefb"></a> +<p>This directive is defined for compatibility with the +‘<samp>Specification for Motorola 8 and 16-Bit Assembly Language Input +Standard</samp>’ and is ignored. +</p> +</dd> +</dl> + +<hr> +<a name="M68HC11_002dFloat"></a> +<div class="header"> +<p> +Next: <a href="#M68HC11_002dopcodes" accesskey="n" rel="next">M68HC11-opcodes</a>, Previous: <a href="#M68HC11_002dDirectives" accesskey="p" rel="previous">M68HC11-Directives</a>, Up: <a href="#M68HC11_002dDependent" accesskey="u" rel="up">M68HC11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-9"></a> +<h4 class="subsection">9.23.5 Floating Point</h4> + +<a name="index-floating-point_002c-M68HC11"></a> +<a name="index-M68HC11-floating-point"></a> +<p>Packed decimal (P) format floating literals are not supported. +Feel free to add the code! +</p> +<p>The floating point formats generated by directives are these. +</p> +<dl compact="compact"> +<dd><a name="index-float-directive_002c-M68HC11"></a> +</dd> +<dt><code>.float</code></dt> +<dd><p><code>Single</code> precision floating point constants. +</p> +<a name="index-double-directive_002c-M68HC11"></a> +</dd> +<dt><code>.double</code></dt> +<dd><p><code>Double</code> precision floating point constants. +</p> +<a name="index-extend-directive-M68HC11"></a> +<a name="index-ldouble-directive-M68HC11"></a> +</dd> +<dt><code>.extend</code></dt> +<dt><code>.ldouble</code></dt> +<dd><p><code>Extended</code> precision (<code>long double</code>) floating point constants. +</p></dd> +</dl> + +<hr> +<a name="M68HC11_002dopcodes"></a> +<div class="header"> +<p> +Previous: <a href="#M68HC11_002dFloat" accesskey="p" rel="previous">M68HC11-Float</a>, Up: <a href="#M68HC11_002dDependent" accesskey="u" rel="up">M68HC11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-13"></a> +<h4 class="subsection">9.23.6 Opcodes</h4> + +<a name="index-M68HC11-opcodes"></a> +<a name="index-opcodes_002c-M68HC11"></a> +<a name="index-instruction-set_002c-M68HC11"></a> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#M68HC11_002dBranch" accesskey="1">M68HC11-Branch</a>:</td><td> </td><td align="left" valign="top">Branch Improvement +</td></tr> +</table> + +<hr> +<a name="M68HC11_002dBranch"></a> +<div class="header"> +<p> +Up: <a href="#M68HC11_002dopcodes" accesskey="u" rel="up">M68HC11-opcodes</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Branch-Improvement-1"></a> +<h4 class="subsubsection">9.23.6.1 Branch Improvement</h4> + +<a name="index-pseudo_002dopcodes_002c-M68HC11"></a> +<a name="index-M68HC11-pseudo_002dopcodes"></a> +<a name="index-branch-improvement_002c-M68HC11"></a> +<a name="index-M68HC11-branch-improvement"></a> + +<p>Certain pseudo opcodes are permitted for branch instructions. +They expand to the shortest branch instruction that reach the +target. Generally these mnemonics are made by prepending ‘<samp>j</samp>’ to +the start of Motorola mnemonic. These pseudo opcodes are not affected +by the ‘<samp>--short-branches</samp>’ or ‘<samp>--force-long-branches</samp>’ options. +</p> +<p>The following table summarizes the pseudo-operations. +</p> +<div class="smallexample"> +<pre class="smallexample"> Displacement Width + +-------------------------------------------------------------+ + | Options | + | --short-branches --force-long-branches | + +--------------------------+----------------------------------+ + Op |BYTE WORD | BYTE WORD | + +--------------------------+----------------------------------+ + bsr | bsr <pc-rel> <error> | jsr <abs> | + bra | bra <pc-rel> <error> | jmp <abs> | +jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | +jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | + bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | +jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | + | jmp <abs> | | + +--------------------------+----------------------------------+ +XX: condition +NX: negative of condition XX + +</pre></div> + +<dl compact="compact"> +<dt><code>jbsr</code></dt> +<dt><code>jbra</code></dt> +<dd><p>These are the simplest jump pseudo-operations; they always map to one +particular machine instruction, depending on the displacement to the +branch target. +</p> +</dd> +<dt><code>jb<var>XX</var></code></dt> +<dd><p>Here, ‘<samp>jb<var>XX</var></samp>’ stands for an entire family of pseudo-operations, +where <var>XX</var> is a conditional branch or condition-code test. The full +list of pseudo-ops in this family is: +</p><div class="smallexample"> +<pre class="smallexample"> jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo + jbcs jbne jblt jble jbls jbvc jbmi +</pre></div> + +<p>For the cases of non-PC relative displacements and long displacements, +<code>as</code> issues a longer code fragment in terms of +<var>NX</var>, the opposite condition to <var>XX</var>. For example, for the +non-PC relative case: +</p><div class="smallexample"> +<pre class="smallexample"> jb<var>XX</var> foo +</pre></div> +<p>gives +</p><div class="smallexample"> +<pre class="smallexample"> b<var>NX</var>s oof + jmp foo + oof: +</pre></div> + +</dd> +</dl> + + + +<hr> +<a name="S12Z_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Meta_002dDependent" accesskey="n" rel="next">Meta-Dependent</a>, Previous: <a href="#M68HC11_002dDependent" accesskey="p" rel="previous">M68HC11-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="S12Z-Dependent-Features"></a> +<h3 class="section">9.24 S12Z Dependent Features</h3> + +<p>The Freescale S12Z version of <code>as</code> has a few machine +dependent features. +</p> +<a name="index-S12Z-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#S12Z-Options" accesskey="1">S12Z Options</a>:</td><td> </td><td align="left" valign="top">S12Z Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#S12Z-Syntax" accesskey="2">S12Z Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +</table> + +<hr> +<a name="S12Z-Options"></a> +<div class="header"> +<p> +Next: <a href="#S12Z-Syntax" accesskey="n" rel="next">S12Z Syntax</a>, Up: <a href="#S12Z_002dDependent" accesskey="u" rel="up">S12Z-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="S12Z-Options-1"></a> +<h4 class="subsection">9.24.1 S12Z Options</h4> + +<a name="index-options_002c-S12Z"></a> +<a name="index-S12Z-options"></a> + +<p>The S12Z version of <code>as</code> recognizes the following options: +</p> +<dl compact="compact"> +<dt>‘<samp>-mreg-prefix=<var>prefix</var></samp>’</dt> +<dd><a name="index-_002dmreg_002dprefix_003dprefix-option_002c-reg_002dprefix"></a> +<p>You can use the ‘<samp>-mreg-prefix=<var>pfx</var></samp>’ option to indicate +that the assembler should expect all register names to be prefixed with the +string <var>pfx</var>. +</p> +<p>For an explanation of what this means and why it might be needed, +see <a href="#S12Z-Register-Notation">S12Z Register Notation</a>. +</p> + +</dd> +<dt>‘<samp>-mdollar-hex</samp>’</dt> +<dd><a name="index-_002dmdollar_002dhex-option_002c-dollar_002dhex"></a> +<a name="index-hexadecimal-prefix_002c-S12Z"></a> +<p>The ‘<samp>-mdollar-hex</samp>’ option affects the way that literal hexadecimal constants +are represented. When this option is specified, the assembler will consider +the ‘<samp>$</samp>’ character as the start of a hexadecimal integer constant. Without +this option, the standard value of ‘<samp>0x</samp>’ is expected. +</p> +<p>If you use this option, then you cannot have symbol names starting with ‘<samp>$</samp>’. +‘<samp>-mdollar-hex</samp>’ is implied if the ‘<samp>--traditional-format</samp>’ +(see <a href="#traditional_002dformat">traditional-format</a>) is used. +</p></dd> +</dl> + +<hr> +<a name="S12Z-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#S12Z-Options" accesskey="p" rel="previous">S12Z Options</a>, Up: <a href="#S12Z_002dDependent" accesskey="u" rel="up">S12Z-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-19"></a> +<h4 class="subsection">9.24.2 Syntax</h4> + + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#S12Z-Syntax-Overview" accesskey="1">S12Z Syntax Overview</a>:</td><td> </td><td align="left" valign="top">General description +</td></tr> +<tr><td align="left" valign="top">• <a href="#S12Z-Addressing-Modes" accesskey="2">S12Z Addressing Modes</a>:</td><td> </td><td align="left" valign="top">Operands and their semantics +</td></tr> +<tr><td align="left" valign="top">• <a href="#S12Z-Register-Notation" accesskey="3">S12Z Register Notation</a>:</td><td> </td><td align="left" valign="top">How to refer to registers +</td></tr> +</table> + + +<a name="index-S12Z-syntax"></a> +<a name="index-syntax_002c-S12Z"></a> + +<hr> +<a name="S12Z-Syntax-Overview"></a> +<div class="header"> +<p> +Next: <a href="#S12Z-Addressing-Modes" accesskey="n" rel="next">S12Z Addressing Modes</a>, Up: <a href="#S12Z-Syntax" accesskey="u" rel="up">S12Z Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Overview-2"></a> +<h4 class="subsubsection">9.24.2.1 Overview</h4> + +<p>In the S12Z syntax, the instruction name comes first and it may +be followed by one, or by several operands. +In most cases the maximum number of operands is three. +Operands are separated by a comma (‘<samp>,</samp>’). +A comma however does not act as a separator if it appears within parentheses +(‘<samp>()</samp>’) or within square brackets (‘<samp>[]</samp>’). +<code>as</code> will complain if too many, too few or inappropriate operands +are specified for a given instruction. +</p> +<p>Some instructions accept and (in certain situations require) a suffix +indicating the size of the operand. +The suffix is separated from the instruction name by a period (‘<samp>.</samp>’) +and may be one of ‘<samp>b</samp>’, ‘<samp>w</samp>’, ‘<samp>p</samp>’ or ‘<samp>l</samp>’ indicating +‘byte’ (a single byte), ‘word’ (2 bytes), ‘pointer’ (3 bytes) or ‘long’ (4 bytes) +respectively. +</p> +<p>Example: +</p> +<div class="smallexample"> +<pre class="smallexample"> bset.b 0xA98, #5 + mov.b #6, 0x2409 + ld d0, #4 + mov.l (d0, x), 0x2409 + inc d0 + cmp d0, #12 + blt *-4 + lea x, 0x2409 + st y, (1, x) +</pre></div> + +<a name="index-line-comment-character_002c-S12Z"></a> +<p>The presence of a ‘<samp>;</samp>’ character anywhere +on a line indicates the start of a comment that extends to the end of +that line. +</p> +<p>A ‘<samp>*</samp>’ or a ‘<samp>#</samp>’ character at the start of a line also +introduces a line comment, but these characters do not work elsewhere +on the line. If the first character of the line is a ‘<samp>#</samp>’ then as +well as starting a comment, the line could also be logical line number +directive (see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-S12Z"></a> +<a name="index-statement-separator_002c-S12Z"></a> +<a name="index-S12Z-line-separator"></a> +<p>The S12Z assembler does not currently support a line separator +character. +</p> + +<hr> +<a name="S12Z-Addressing-Modes"></a> +<div class="header"> +<p> +Next: <a href="#S12Z-Register-Notation" accesskey="n" rel="next">S12Z Register Notation</a>, Previous: <a href="#S12Z-Syntax-Overview" accesskey="p" rel="previous">S12Z Syntax Overview</a>, Up: <a href="#S12Z-Syntax" accesskey="u" rel="up">S12Z Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Addressing-Modes-3"></a> +<h4 class="subsubsection">9.24.2.2 Addressing Modes</h4> +<a name="index-S12Z-addressing-modes"></a> +<a name="index-addressing-modes_002c-S12Z"></a> + +<p>The following addressing modes are understood for the S12Z. +</p><dl compact="compact"> +<dt><em>Immediate</em></dt> +<dd><p>‘<samp>#<var>number</var></samp>’ +</p> +</dd> +<dt><em>Immediate Bit Field</em></dt> +<dd><p>‘<samp>#<var>width</var>:<var>offset</var></samp>’ +</p> +<p>Bit field instructions in the immediate mode require the width and offset to +be specified. +The <var>width</var> parameter specifies the number of bits in the field. +It should be a number in the range [1,32]. +<var>Offset</var> determines the position within the field where the operation +should start. +It should be a number in the range [0,31]. +</p> +</dd> +<dt><em>Relative</em></dt> +<dd><p>‘<samp>*<var>symbol</var></samp>’, or ‘<samp>*[+-]<var>digits</var></samp>’ +</p> +<p>Program counter relative addresses have a width of 15 bits. +Thus, they must be within the range [-32768, 32767]. +</p> +</dd> +<dt><em>Register</em></dt> +<dd><p>‘<samp><var>reg</var></samp>’ +</p> +<a name="index-register-names_002c-S12Z"></a> +<p>Some instructions accept a register as an operand. +In general, <var>reg</var> may be a +data register (‘<samp>D0</samp>’, ‘<samp>D1</samp>’ … ‘<samp>D7</samp>’), +the ‘<samp>X</samp>’ register or the ‘<samp>Y</samp>’ register. +</p> +<p>A few instructions accept as an argument the stack pointer +register (‘<samp>S</samp>’), and/or the program counter (‘<samp>P</samp>’). +</p> +<p>Some very special instructions accept arguments which refer to the +condition code register. For these arguments the syntax is +‘<samp>CCR</samp>’, ‘<samp>CCH</samp>’ or ‘<samp>CCL</samp>’ which refer to the complete +condition code register, the condition code register high byte +and the condition code register low byte respectively. +</p> + +</dd> +<dt><em>Absolute Direct</em></dt> +<dd><p>‘<samp><var>symbol</var></samp>’, or ‘<samp><var>digits</var></samp>’ +</p> +</dd> +<dt><em>Absolute Indirect</em></dt> +<dd><p>‘<samp>[<var>symbol</var></samp>’, or ‘<samp><var>digits</var>]</samp>’ +</p> + +</dd> +<dt><em>Constant Offset Indexed</em></dt> +<dd><p>‘<samp>(<var>number</var>,<var>reg</var>)</samp>’ +</p> +<p><var>Reg</var> may be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, ‘<samp>S</samp>’ or +‘<samp>P</samp>’ or one of the data registers ‘<samp>D0</samp>’, ‘<samp>D1</samp>’ … +‘<samp>D7</samp>’. +If any of the registers ‘<samp>D2</samp>’ … ‘<samp>D5</samp>’ are specified, then the +register value is treated as a signed value. +Otherwise it is treated as unsigned. +<var>Number</var> may be any integer in the range [-8388608,8388607]. +</p> +</dd> +<dt><em>Offset Indexed Indirect</em></dt> +<dd><p>‘<samp>[<var>number</var>,<var>reg</var>]</samp>’ +</p> +<p><var>Reg</var> may be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, ‘<samp>S</samp>’ or +‘<samp>P</samp>’. +<var>Number</var> may be any integer in the range [-8388608,8388607]. +</p> +</dd> +<dt><em>Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement</em></dt> +<dd><p>‘<samp>-<var>reg</var></samp>’, +‘<samp>+<var>reg</var></samp>’, +‘<samp><var>reg</var>-</samp>’ or +‘<samp><var>reg</var>+</samp>’ +</p> +<p>This addressing mode is typically used to access a value at an address, +and simultaneously to increment/decrement the register pointing to that +address. +Thus <var>reg</var> may be any of the 24 bit registers ‘<samp>X</samp>’, ‘<samp>Y</samp>’, or +‘<samp>S</samp>’. +Pre-increment and post-decrement are not available for +register ‘<samp>S</samp>’ (only post-increment and pre-decrement are available). +</p> +</dd> +<dt><em>Register Offset Direct</em></dt> +<dd><p>‘<samp>(<var>data-reg</var>,<var>reg</var>)</samp>’ +</p> +<p><var>Reg</var> can be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, or ‘<samp>S</samp>’. +<var>Data-reg</var> +must be one of the data registers ‘<samp>D0</samp>’, ‘<samp>D1</samp>’ … ‘<samp>D7</samp>’. +If any of the registers ‘<samp>D2</samp>’ … ‘<samp>D5</samp>’ are specified, then +the register value is treated as a signed value. +Otherwise it is treated as unsigned. +</p> +</dd> +<dt><em>Register Offset Indirect</em></dt> +<dd><p>‘<samp>[<var>data-reg</var>,<var>reg</var>]</samp>’ +</p> +<p><var>Reg</var> can be either ‘<samp>X</samp>’ or ‘<samp>Y</samp>’. +<var>Data-reg</var> +must be one of the data registers ‘<samp>D0</samp>’, ‘<samp>D1</samp>’ … ‘<samp>D7</samp>’. +If any of the registers ‘<samp>D2</samp>’ … ‘<samp>D5</samp>’ are specified, then +the register value is treated as a signed value. +Otherwise it is treated as unsigned. +</p></dd> +</dl> + +<p>For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> trap #197 ;; Immediate mode + bra *+49 ;; Relative mode + bra .L0 ;; ditto + jmp 0xFE0034 ;; Absolute direct mode + jmp [0xFD0012] ;; Absolute indirect mode + inc.b (4,x) ;; Constant offset indexed mode + jsr (45, d0) ;; ditto + dec.w [4,y] ;; Constant offset indexed indirect mode + clr.p (-s) ;; Pre-decrement mode + neg.l (d0, s) ;; Register offset direct mode + com.b [d1, x] ;; Register offset indirect mode + psh cch ;; Register mode +</pre></div> + +<hr> +<a name="S12Z-Register-Notation"></a> +<div class="header"> +<p> +Previous: <a href="#S12Z-Addressing-Modes" accesskey="p" rel="previous">S12Z Addressing Modes</a>, Up: <a href="#S12Z-Syntax" accesskey="u" rel="up">S12Z Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Notation"></a> +<h4 class="subsubsection">9.24.2.3 Register Notation</h4> + +<a name="index-register-notation_002c-S12Z"></a> +<p>Without a register prefix (see <a href="#S12Z-Options">S12Z Options</a>), S12Z assembler code is expected in the traditional +format like this: +</p><div class="smallexample"> +<pre class="smallexample">lea s, (-2,s) +st d2, (0,s) +ld x, symbol +tfr d2, d6 +cmp d6, #1532 +</pre></div> + +<p>However, if <code>as</code> is started with (for example) ‘<samp>-mreg-prefix=%</samp>’ +then all register names must be prefixed with ‘<samp>%</samp>’ as follows: +</p><div class="smallexample"> +<pre class="smallexample">lea %s, (-2,%s) +st %d2, (0,%s) +ld %x, symbol +tfr %d2, %d6 +cmp %d6, #1532 +</pre></div> + +<p>The register prefix feature is intended to be used by compilers +to avoid ambiguity between symbols and register names. +Consider the following assembler instruction: +</p><div class="smallexample"> +<pre class="smallexample">st d0, d1 +</pre></div> +<p>The destination operand of this instruction could either refer to the register +‘<samp>D1</samp>’, or it could refer to the symbol named “d1”. +If the latter is intended then <code>as</code> must be invoked with +‘<samp>-mreg-prefix=<var>pfx</var></samp>’ and the code written as +</p><div class="smallexample"> +<pre class="smallexample">st <var>pfx</var>d0, d1 +</pre></div> +<p>where <var>pfx</var> is the chosen register prefix. +For this reason, compiler back-ends should choose a register prefix which +cannot be confused with a symbol name. +</p> + +<hr> +<a name="Meta_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#MicroBlaze_002dDependent" accesskey="n" rel="next">MicroBlaze-Dependent</a>, Previous: <a href="#S12Z_002dDependent" accesskey="p" rel="previous">S12Z-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Meta-Dependent-Features"></a> +<h3 class="section">9.25 Meta Dependent Features</h3> + +<a name="index-Meta-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Meta-Options" accesskey="1">Meta Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#Meta-Syntax" accesskey="2">Meta Syntax</a>:</td><td> </td><td align="left" valign="top">Meta Assembler Syntax +</td></tr> +</table> + +<hr> +<a name="Meta-Options"></a> +<div class="header"> +<p> +Next: <a href="#Meta-Syntax" accesskey="n" rel="next">Meta Syntax</a>, Up: <a href="#Meta_002dDependent" accesskey="u" rel="up">Meta-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-14"></a> +<h4 class="subsection">9.25.1 Options</h4> + +<a name="index-options-for-Meta"></a> +<a name="index-Meta-options"></a> +<a name="index-architectures_002c-Meta"></a> +<a name="index-Meta-architectures"></a> + +<p>The Imagination Technologies Meta architecture is implemented in a +number of versions, with each new version adding new features such as +instructions and registers. For precise details of what instructions +each core supports, please see the chip’s technical reference manual. +</p> +<p>The following table lists all available Meta options. +</p> +<dl compact="compact"> +<dt><code>-mcpu=metac11</code></dt> +<dd><p>Generate code for Meta 1.1. +</p> +</dd> +<dt><code>-mcpu=metac12</code></dt> +<dd><p>Generate code for Meta 1.2. +</p> +</dd> +<dt><code>-mcpu=metac21</code></dt> +<dd><p>Generate code for Meta 2.1. +</p> +</dd> +<dt><code>-mfpu=metac21</code></dt> +<dd><p>Allow code to use FPU hardware of Meta 2.1. +</p> +</dd> +</dl> + +<hr> +<a name="Meta-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#Meta-Options" accesskey="p" rel="previous">Meta Options</a>, Up: <a href="#Meta_002dDependent" accesskey="u" rel="up">Meta-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-20"></a> +<h4 class="subsection">9.25.2 Syntax</h4> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Meta_002dChars" accesskey="1">Meta-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#Meta_002dRegs" accesskey="2">Meta-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +</table> + +<hr> +<a name="Meta_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#Meta_002dRegs" accesskey="n" rel="next">Meta-Regs</a>, Up: <a href="#Meta-Syntax" accesskey="u" rel="up">Meta Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-18"></a> +<h4 class="subsubsection">9.25.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-Meta"></a> +<a name="index-Meta-line-comment-character"></a> +<p>‘<samp>!</samp>’ is the line comment character. +</p> +<a name="index-line-separator_002c-Meta"></a> +<a name="index-statement-separator_002c-Meta"></a> +<a name="index-Meta-line-separator"></a> +<p>You can use ‘<samp>;</samp>’ instead of a newline to separate statements. +</p> +<a name="index-symbol-names_002c-_0024-in-2"></a> +<a name="index-_0024-in-symbol-names-2"></a> +<p>Since ‘<samp>$</samp>’ has no special meaning, you may use it in symbol names. +</p> +<hr> +<a name="Meta_002dRegs"></a> +<div class="header"> +<p> +Previous: <a href="#Meta_002dChars" accesskey="p" rel="previous">Meta-Chars</a>, Up: <a href="#Meta-Syntax" accesskey="u" rel="up">Meta Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-11"></a> +<h4 class="subsubsection">9.25.2.2 Register Names</h4> + +<a name="index-Meta-registers"></a> +<a name="index-registers_002c-Meta"></a> +<p>Registers can be specified either using their mnemonic names, such as +‘<samp>D0Re0</samp>’, or using the unit plus register number separated by a ‘<samp>.</samp>’, +such as ‘<samp>D0.0</samp>’. +</p> +<hr> +<a name="MicroBlaze_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#MIPS_002dDependent" accesskey="n" rel="next">MIPS-Dependent</a>, Previous: <a href="#Meta_002dDependent" accesskey="p" rel="previous">Meta-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="MicroBlaze-Dependent-Features"></a> +<h3 class="section">9.26 MicroBlaze Dependent Features</h3> + +<a name="index-MicroBlaze-architectures"></a> +<p>The Xilinx MicroBlaze processor family includes several variants, all using +the same core instruction set. This chapter covers features of the <small>GNU</small> +assembler that are specific to the MicroBlaze architecture. For details about +the MicroBlaze instruction set, please see the <cite>MicroBlaze Processor +Reference Guide (UG081)</cite> available at www.xilinx.com. +</p> +<a name="index-MicroBlaze-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#MicroBlaze-Directives" accesskey="1">MicroBlaze Directives</a>:</td><td> </td><td align="left" valign="top">Directives for MicroBlaze Processors. +</td></tr> +<tr><td align="left" valign="top">• <a href="#MicroBlaze-Syntax" accesskey="2">MicroBlaze Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax for the MicroBlaze +</td></tr> +</table> + +<hr> +<a name="MicroBlaze-Directives"></a> +<div class="header"> +<p> +Next: <a href="#MicroBlaze-Syntax" accesskey="n" rel="next">MicroBlaze Syntax</a>, Up: <a href="#MicroBlaze_002dDependent" accesskey="u" rel="up">MicroBlaze-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-1"></a> +<h4 class="subsection">9.26.1 Directives</h4> +<a name="index-MicroBlaze-directives"></a> +<p>A number of assembler directives are available for MicroBlaze. +</p> +<dl compact="compact"> +<dt><code>.data8 <var>expression</var>,...</code></dt> +<dd><p>This directive is an alias for <code>.byte</code>. Each expression is assembled +into an eight-bit value. +</p> +</dd> +<dt><code>.data16 <var>expression</var>,...</code></dt> +<dd><p>This directive is an alias for <code>.hword</code>. Each expression is assembled +into an 16-bit value. +</p> +</dd> +<dt><code>.data32 <var>expression</var>,...</code></dt> +<dd><p>This directive is an alias for <code>.word</code>. Each expression is assembled +into an 32-bit value. +</p> +</dd> +<dt><code>.ent <var>name</var>[,<var>label</var>]</code></dt> +<dd><p>This directive is an alias for <code>.func</code> denoting the start of function +<var>name</var> at (optional) <var>label</var>. +</p> +</dd> +<dt><code>.end <var>name</var>[,<var>label</var>]</code></dt> +<dd><p>This directive is an alias for <code>.endfunc</code> denoting the end of function +<var>name</var>. +</p> +</dd> +<dt><code>.gpword <var>label</var>,...</code></dt> +<dd><p>This directive is an alias for <code>.rva</code>. The resolved address of <var>label</var> +is stored in the data section. +</p> +</dd> +<dt><code>.weakext <var>label</var></code></dt> +<dd><p>Declare that <var>label</var> is a weak external symbol. +</p> +</dd> +<dt><code>.rodata</code></dt> +<dd><p>Switch to .rodata section. Equivalent to <code>.section .rodata</code> +</p> +</dd> +<dt><code>.sdata2</code></dt> +<dd><p>Switch to .sdata2 section. Equivalent to <code>.section .sdata2</code> +</p> +</dd> +<dt><code>.sdata</code></dt> +<dd><p>Switch to .sdata section. Equivalent to <code>.section .sdata</code> +</p> +</dd> +<dt><code>.bss</code></dt> +<dd><p>Switch to .bss section. Equivalent to <code>.section .bss</code> +</p> +</dd> +<dt><code>.sbss</code></dt> +<dd><p>Switch to .sbss section. Equivalent to <code>.section .sbss</code> +</p></dd> +</dl> + +<hr> +<a name="MicroBlaze-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#MicroBlaze-Directives" accesskey="p" rel="previous">MicroBlaze Directives</a>, Up: <a href="#MicroBlaze_002dDependent" accesskey="u" rel="up">MicroBlaze-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-for-the-MicroBlaze"></a> +<h4 class="subsection">9.26.2 Syntax for the MicroBlaze</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#MicroBlaze_002dChars" accesskey="1">MicroBlaze-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="MicroBlaze_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#MicroBlaze-Syntax" accesskey="u" rel="up">MicroBlaze Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-19"></a> +<h4 class="subsubsection">9.26.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-MicroBlaze"></a> +<a name="index-MicroBlaze-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ on a line indicates the start of a comment +that extends to the end of the current line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line, the whole line +is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a +preprocessor control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-MicroBlaze"></a> +<a name="index-statement-separator_002c-MicroBlaze"></a> +<a name="index-MicroBlaze-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="MIPS_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#MMIX_002dDependent" accesskey="n" rel="next">MMIX-Dependent</a>, Previous: <a href="#MicroBlaze_002dDependent" accesskey="p" rel="previous">MicroBlaze-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="MIPS-Dependent-Features"></a> +<h3 class="section">9.27 MIPS Dependent Features</h3> + +<a name="index-MIPS-processor"></a> +<p><small>GNU</small> <code>as</code> for MIPS architectures supports several +different MIPS processors, and MIPS ISA levels I through V, MIPS32, +and MIPS64. For information about the MIPS instruction set, see +<cite>MIPS RISC Architecture</cite>, by Kane and Heindrich (Prentice-Hall). +For an overview of MIPS assembly conventions, see “Appendix D: +Assembly Language Programming” in the same work. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#MIPS-Options" accesskey="1">MIPS Options</a>:</td><td> </td><td align="left" valign="top">Assembler options +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-Macros" accesskey="2">MIPS Macros</a>:</td><td> </td><td align="left" valign="top">High-level assembly macros +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-Symbol-Sizes" accesskey="3">MIPS Symbol Sizes</a>:</td><td> </td><td align="left" valign="top">Directives to override the size of symbols +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-Small-Data" accesskey="4">MIPS Small Data</a>:</td><td> </td><td align="left" valign="top">Controlling the use of small data accesses +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-ISA" accesskey="5">MIPS ISA</a>:</td><td> </td><td align="left" valign="top">Directives to override the ISA level +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-assembly-options" accesskey="6">MIPS assembly options</a>:</td><td> </td><td align="left" valign="top">Directives to control code generation +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-autoextend" accesskey="7">MIPS autoextend</a>:</td><td> </td><td align="left" valign="top">Directives for extending MIPS 16 bit instructions +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-insn" accesskey="8">MIPS insn</a>:</td><td> </td><td align="left" valign="top">Directive to mark data as an instruction +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-FP-ABIs" accesskey="9">MIPS FP ABIs</a>:</td><td> </td><td align="left" valign="top">Marking which FP ABI is in use +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-NaN-Encodings">MIPS NaN Encodings</a>:</td><td> </td><td align="left" valign="top">Directives to record which NaN encoding is being used +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-Option-Stack">MIPS Option Stack</a>:</td><td> </td><td align="left" valign="top">Directives to save and restore options +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a>:</td><td> </td><td align="left" valign="top">Directives to control + generation of MIPS ASE instructions +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-Floating_002dPoint">MIPS Floating-Point</a>:</td><td> </td><td align="left" valign="top">Directives to override floating-point options +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-Syntax">MIPS Syntax</a>:</td><td> </td><td align="left" valign="top">MIPS specific syntactical considerations +</td></tr> +</table> + +<hr> +<a name="MIPS-Options"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-Macros" accesskey="n" rel="next">MIPS Macros</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-options"></a> +<h4 class="subsection">9.27.1 Assembler options</h4> + +<p>The MIPS configurations of <small>GNU</small> <code>as</code> support these +special options: +</p> +<dl compact="compact"> +<dd><a name="index-_002dG-option-_0028MIPS_0029"></a> +</dd> +<dt><code>-G <var>num</var></code></dt> +<dd><p>Set the “small data” limit to <var>n</var> bytes. The default limit is 8 bytes. +See <a href="#MIPS-Small-Data">Controlling the use of small data accesses</a>. +</p> +<a name="index-_002dEB-option-_0028MIPS_0029"></a> +<a name="index-_002dEL-option-_0028MIPS_0029"></a> +<a name="index-MIPS-big_002dendian-output"></a> +<a name="index-MIPS-little_002dendian-output"></a> +<a name="index-big_002dendian-output_002c-MIPS"></a> +<a name="index-little_002dendian-output_002c-MIPS"></a> +</dd> +<dt><code>-EB</code></dt> +<dt><code>-EL</code></dt> +<dd><p>Any MIPS configuration of <code>as</code> can select big-endian or +little-endian output at run time (unlike the other <small>GNU</small> development +tools, which must be configured for one or the other). Use ‘<samp>-EB</samp>’ +to select big-endian output, and ‘<samp>-EL</samp>’ for little-endian. +</p> +</dd> +<dt><code>-KPIC</code></dt> +<dd><a name="index-PIC-selection_002c-MIPS"></a> +<a name="index-_002dKPIC-option_002c-MIPS"></a> +<p>Generate SVR4-style PIC. This option tells the assembler to generate +SVR4-style position-independent macro expansions. It also tells the +assembler to mark the output file as PIC. +</p> +</dd> +<dt><code>-mvxworks-pic</code></dt> +<dd><a name="index-_002dmvxworks_002dpic-option_002c-MIPS"></a> +<p>Generate VxWorks PIC. This option tells the assembler to generate +VxWorks-style position-independent macro expansions. +</p> +<a name="index-MIPS-architecture-options"></a> +</dd> +<dt><code>-mips1</code></dt> +<dt><code>-mips2</code></dt> +<dt><code>-mips3</code></dt> +<dt><code>-mips4</code></dt> +<dt><code>-mips5</code></dt> +<dt><code>-mips32</code></dt> +<dt><code>-mips32r2</code></dt> +<dt><code>-mips32r3</code></dt> +<dt><code>-mips32r5</code></dt> +<dt><code>-mips32r6</code></dt> +<dt><code>-mips64</code></dt> +<dt><code>-mips64r2</code></dt> +<dt><code>-mips64r3</code></dt> +<dt><code>-mips64r5</code></dt> +<dt><code>-mips64r6</code></dt> +<dd><p>Generate code for a particular MIPS Instruction Set Architecture level. +‘<samp>-mips1</samp>’ corresponds to the R2000 and R3000 processors, +‘<samp>-mips2</samp>’ to the R6000 processor, ‘<samp>-mips3</samp>’ to the +R4000 processor, and ‘<samp>-mips4</samp>’ to the R8000 and R10000 processors. +‘<samp>-mips5</samp>’, ‘<samp>-mips32</samp>’, ‘<samp>-mips32r2</samp>’, ‘<samp>-mips32r3</samp>’, +‘<samp>-mips32r5</samp>’, ‘<samp>-mips32r6</samp>’, ‘<samp>-mips64</samp>’, ‘<samp>-mips64r2</samp>’, +‘<samp>-mips64r3</samp>’, ‘<samp>-mips64r5</samp>’, and ‘<samp>-mips64r6</samp>’ correspond to +generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 +Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 +Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, +respectively. You can also switch instruction sets during the assembly; +see <a href="#MIPS-ISA">Directives to override the ISA level</a>. +</p> +</dd> +<dt><code>-mgp32</code></dt> +<dt><code>-mfp32</code></dt> +<dd><p>Some macros have different expansions for 32-bit and 64-bit registers. +The register sizes are normally inferred from the ISA and ABI, but these +flags force a certain group of registers to be treated as 32 bits wide at +all times. ‘<samp>-mgp32</samp>’ controls the size of general-purpose registers +and ‘<samp>-mfp32</samp>’ controls the size of floating-point registers. +</p> +<p>The <code>.set gp=32</code> and <code>.set fp=32</code> directives allow the size +of registers to be changed for parts of an object. The default value is +restored by <code>.set gp=default</code> and <code>.set fp=default</code>. +</p> +<p>On some MIPS variants there is a 32-bit mode flag; when this flag is +set, 64-bit instructions generate a trap. Also, some 32-bit OSes only +save the 32-bit registers on a context switch, so it is essential never +to use the 64-bit registers. +</p> +</dd> +<dt><code>-mgp64</code></dt> +<dt><code>-mfp64</code></dt> +<dd><p>Assume that 64-bit registers are available. This is provided in the +interests of symmetry with ‘<samp>-mgp32</samp>’ and ‘<samp>-mfp32</samp>’. +</p> +<p>The <code>.set gp=64</code> and <code>.set fp=64</code> directives allow the size +of registers to be changed for parts of an object. The default value is +restored by <code>.set gp=default</code> and <code>.set fp=default</code>. +</p> +</dd> +<dt><code>-mfpxx</code></dt> +<dd><p>Make no assumptions about whether 32-bit or 64-bit floating-point +registers are available. This is provided to support having modules +compatible with either ‘<samp>-mfp32</samp>’ or ‘<samp>-mfp64</samp>’. This option can +only be used with MIPS II and above. +</p> +<p>The <code>.set fp=xx</code> directive allows a part of an object to be marked +as not making assumptions about 32-bit or 64-bit FP registers. The +default value is restored by <code>.set fp=default</code>. +</p> +</dd> +<dt><code>-modd-spreg</code></dt> +<dt><code>-mno-odd-spreg</code></dt> +<dd><p>Enable use of floating-point operations on odd-numbered single-precision +registers when supported by the ISA. ‘<samp>-mfpxx</samp>’ implies +‘<samp>-mno-odd-spreg</samp>’, otherwise the default is ‘<samp>-modd-spreg</samp>’ +</p> +</dd> +<dt><code>-mips16</code></dt> +<dt><code>-no-mips16</code></dt> +<dd><p>Generate code for the MIPS 16 processor. This is equivalent to putting +<code>.module mips16</code> at the start of the assembly file. ‘<samp>-no-mips16</samp>’ +turns off this option. +</p> +</dd> +<dt><code>-mmips16e2</code></dt> +<dt><code>-mno-mips16e2</code></dt> +<dd><p>Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent +to putting <code>.module mips16e2</code> at the start of the assembly file. +‘<samp>-mno-mips16e2</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mmicromips</code></dt> +<dt><code>-mno-micromips</code></dt> +<dd><p>Generate code for the microMIPS processor. This is equivalent to putting +<code>.module micromips</code> at the start of the assembly file. +‘<samp>-mno-micromips</samp>’ turns off this option. This is equivalent to putting +<code>.module nomicromips</code> at the start of the assembly file. +</p> +</dd> +<dt><code>-msmartmips</code></dt> +<dt><code>-mno-smartmips</code></dt> +<dd><p>Enables the SmartMIPS extensions to the MIPS32 instruction set, which +provides a number of new instructions which target smartcard and +cryptographic applications. This is equivalent to putting +<code>.module smartmips</code> at the start of the assembly file. +‘<samp>-mno-smartmips</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mips3d</code></dt> +<dt><code>-no-mips3d</code></dt> +<dd><p>Generate code for the MIPS-3D Application Specific Extension. +This tells the assembler to accept MIPS-3D instructions. +‘<samp>-no-mips3d</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mdmx</code></dt> +<dt><code>-no-mdmx</code></dt> +<dd><p>Generate code for the MDMX Application Specific Extension. +This tells the assembler to accept MDMX instructions. +‘<samp>-no-mdmx</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mdsp</code></dt> +<dt><code>-mno-dsp</code></dt> +<dd><p>Generate code for the DSP Release 1 Application Specific Extension. +This tells the assembler to accept DSP Release 1 instructions. +‘<samp>-mno-dsp</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mdspr2</code></dt> +<dt><code>-mno-dspr2</code></dt> +<dd><p>Generate code for the DSP Release 2 Application Specific Extension. +This option implies ‘<samp>-mdsp</samp>’. +This tells the assembler to accept DSP Release 2 instructions. +‘<samp>-mno-dspr2</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mdspr3</code></dt> +<dt><code>-mno-dspr3</code></dt> +<dd><p>Generate code for the DSP Release 3 Application Specific Extension. +This option implies ‘<samp>-mdsp</samp>’ and ‘<samp>-mdspr2</samp>’. +This tells the assembler to accept DSP Release 3 instructions. +‘<samp>-mno-dspr3</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mmt</code></dt> +<dt><code>-mno-mt</code></dt> +<dd><p>Generate code for the MT Application Specific Extension. +This tells the assembler to accept MT instructions. +‘<samp>-mno-mt</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mmcu</code></dt> +<dt><code>-mno-mcu</code></dt> +<dd><p>Generate code for the MCU Application Specific Extension. +This tells the assembler to accept MCU instructions. +‘<samp>-mno-mcu</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mmsa</code></dt> +<dt><code>-mno-msa</code></dt> +<dd><p>Generate code for the MIPS SIMD Architecture Extension. +This tells the assembler to accept MSA instructions. +‘<samp>-mno-msa</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mxpa</code></dt> +<dt><code>-mno-xpa</code></dt> +<dd><p>Generate code for the MIPS eXtended Physical Address (XPA) Extension. +This tells the assembler to accept XPA instructions. +‘<samp>-mno-xpa</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mvirt</code></dt> +<dt><code>-mno-virt</code></dt> +<dd><p>Generate code for the Virtualization Application Specific Extension. +This tells the assembler to accept Virtualization instructions. +‘<samp>-mno-virt</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mcrc</code></dt> +<dt><code>-mno-crc</code></dt> +<dd><p>Generate code for the cyclic redundancy check (CRC) Application Specific +Extension. This tells the assembler to accept CRC instructions. +‘<samp>-mno-crc</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mginv</code></dt> +<dt><code>-mno-ginv</code></dt> +<dd><p>Generate code for the Global INValidate (GINV) Application Specific +Extension. This tells the assembler to accept GINV instructions. +‘<samp>-mno-ginv</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mloongson-mmi</code></dt> +<dt><code>-mno-loongson-mmi</code></dt> +<dd><p>Generate code for the Loongson MultiMedia extensions Instructions (MMI) +Application Specific Extension. This tells the assembler to accept MMI +instructions. +‘<samp>-mno-loongson-mmi</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mloongson-cam</code></dt> +<dt><code>-mno-loongson-cam</code></dt> +<dd><p>Generate code for the Loongson Content Address Memory (CAM) +Application Specific Extension. This tells the assembler to accept CAM +instructions. +‘<samp>-mno-loongson-cam</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mloongson-ext</code></dt> +<dt><code>-mno-loongson-ext</code></dt> +<dd><p>Generate code for the Loongson EXTensions (EXT) instructions +Application Specific Extension. This tells the assembler to accept EXT +instructions. +‘<samp>-mno-loongson-ext</samp>’ turns off this option. +</p> +</dd> +<dt><code>-mloongson-ext2</code></dt> +<dt><code>-mno-loongson-ext2</code></dt> +<dd><p>Generate code for the Loongson EXTensions R2 (EXT2) instructions +Application Specific Extension. This tells the assembler to accept EXT2 +instructions. +‘<samp>-mno-loongson-ext2</samp>’ turns off this option. +</p> +</dd> +<dt><code>-minsn32</code></dt> +<dt><code>-mno-insn32</code></dt> +<dd><p>Only use 32-bit instruction encodings when generating code for the +microMIPS processor. This option inhibits the use of any 16-bit +instructions. This is equivalent to putting <code>.set insn32</code> at +the start of the assembly file. ‘<samp>-mno-insn32</samp>’ turns off this +option. This is equivalent to putting <code>.set noinsn32</code> at the +start of the assembly file. By default ‘<samp>-mno-insn32</samp>’ is +selected, allowing all instructions to be used. +</p> +</dd> +<dt><code>-mfix7000</code></dt> +<dt><code>-mno-fix7000</code></dt> +<dd><p>Cause nops to be inserted if the read of the destination register +of an mfhi or mflo instruction occurs in the following two instructions. +</p> +</dd> +<dt><code>-mfix-rm7000</code></dt> +<dt><code>-mno-fix-rm7000</code></dt> +<dd><p>Cause nops to be inserted if a dmult or dmultu instruction is +followed by a load instruction. +</p> +</dd> +<dt><code>-mfix-loongson2f-jump</code></dt> +<dt><code>-mno-fix-loongson2f-jump</code></dt> +<dd><p>Eliminate instruction fetch from outside 256M region to work around the +Loongson2F ‘<samp>jump</samp>’ instructions. Without it, under extreme cases, +the kernel may crash. The issue has been solved in latest processor +batches, but this fix has no side effect to them. +</p> +</dd> +<dt><code>-mfix-loongson2f-nop</code></dt> +<dt><code>-mno-fix-loongson2f-nop</code></dt> +<dd><p>Replace nops by <code>or at,at,zero</code> to work around the Loongson2F +‘<samp>nop</samp>’ errata. Without it, under extreme cases, the CPU might +deadlock. The issue has been solved in later Loongson2F batches, but +this fix has no side effect to them. +</p> +</dd> +<dt><code>-mfix-loongson3-llsc</code></dt> +<dt><code>-mno-fix-loongson3-llsc</code></dt> +<dd><p>Insert ‘<samp>sync</samp>’ before ‘<samp>ll</samp>’ and ‘<samp>lld</samp>’ to work around +Loongson3 LLSC errata. Without it, under extrame cases, the CPU might +deadlock. The default can be controlled by the +<samp>--enable-mips-fix-loongson3-llsc=[yes|no]</samp> configure option. +</p> +</dd> +<dt><code>-mfix-vr4120</code></dt> +<dt><code>-mno-fix-vr4120</code></dt> +<dd><p>Insert nops to work around certain VR4120 errata. This option is +intended to be used on GCC-generated code: it is not designed to catch +all problems in hand-written assembler code. +</p> +</dd> +<dt><code>-mfix-vr4130</code></dt> +<dt><code>-mno-fix-vr4130</code></dt> +<dd><p>Insert nops to work around the VR4130 ‘<samp>mflo</samp>’/‘<samp>mfhi</samp>’ errata. +</p> +</dd> +<dt><code>-mfix-24k</code></dt> +<dt><code>-mno-fix-24k</code></dt> +<dd><p>Insert nops to work around the 24K ‘<samp>eret</samp>’/‘<samp>deret</samp>’ errata. +</p> +</dd> +<dt><code>-mfix-cn63xxp1</code></dt> +<dt><code>-mno-fix-cn63xxp1</code></dt> +<dd><p>Replace <code>pref</code> hints 0 - 4 and 6 - 24 with hint 28 to work around +certain CN63XXP1 errata. +</p> +</dd> +<dt><code>-mfix-r5900</code></dt> +<dt><code>-mno-fix-r5900</code></dt> +<dd><p>Do not attempt to schedule the preceding instruction into the delay slot +of a branch instruction placed at the end of a short loop of six +instructions or fewer and always schedule a <code>nop</code> instruction there +instead. The short loop bug under certain conditions causes loops to +execute only once or twice, due to a hardware bug in the R5900 chip. +</p> +</dd> +<dt><code>-m4010</code></dt> +<dt><code>-no-m4010</code></dt> +<dd><p>Generate code for the LSI R4010 chip. This tells the assembler to +accept the R4010-specific instructions (‘<samp>addciu</samp>’, ‘<samp>ffc</samp>’, +etc.), and to not schedule ‘<samp>nop</samp>’ instructions around accesses to +the ‘<samp>HI</samp>’ and ‘<samp>LO</samp>’ registers. ‘<samp>-no-m4010</samp>’ turns off this +option. +</p> +</dd> +<dt><code>-m4650</code></dt> +<dt><code>-no-m4650</code></dt> +<dd><p>Generate code for the MIPS R4650 chip. This tells the assembler to accept +the ‘<samp>mad</samp>’ and ‘<samp>madu</samp>’ instruction, and to not schedule ‘<samp>nop</samp>’ +instructions around accesses to the ‘<samp>HI</samp>’ and ‘<samp>LO</samp>’ registers. +‘<samp>-no-m4650</samp>’ turns off this option. +</p> +</dd> +<dt><code>-m3900</code></dt> +<dt><code>-no-m3900</code></dt> +<dt><code>-m4100</code></dt> +<dt><code>-no-m4100</code></dt> +<dd><p>For each option ‘<samp>-m<var>nnnn</var></samp>’, generate code for the MIPS +R<var>nnnn</var> chip. This tells the assembler to accept instructions +specific to that chip, and to schedule for that chip’s hazards. +</p> +</dd> +<dt><code>-march=<var>cpu</var></code></dt> +<dd><p>Generate code for a particular MIPS CPU. It is exactly equivalent to +‘<samp>-m<var>cpu</var></samp>’, except that there are more value of <var>cpu</var> +understood. Valid <var>cpu</var> value are: +</p> +<blockquote> +<p>2000, +3000, +3900, +4000, +4010, +4100, +4111, +vr4120, +vr4130, +vr4181, +4300, +4400, +4600, +4650, +5000, +rm5200, +rm5230, +rm5231, +rm5261, +rm5721, +vr5400, +vr5500, +6000, +rm7000, +8000, +rm9000, +10000, +12000, +14000, +16000, +4kc, +4km, +4kp, +4ksc, +4kec, +4kem, +4kep, +4ksd, +m4k, +m4kp, +m14k, +m14kc, +m14ke, +m14kec, +24kc, +24kf2_1, +24kf, +24kf1_1, +24kec, +24kef2_1, +24kef, +24kef1_1, +34kc, +34kf2_1, +34kf, +34kf1_1, +34kn, +74kc, +74kf2_1, +74kf, +74kf1_1, +74kf3_2, +1004kc, +1004kf2_1, +1004kf, +1004kf1_1, +interaptiv, +interaptiv-mr2, +m5100, +m5101, +p5600, +5kc, +5kf, +20kc, +25kf, +sb1, +sb1a, +i6400, +i6500, +p6600, +loongson2e, +loongson2f, +gs464, +gs464e, +gs264e, +octeon, +octeon+, +octeon2, +octeon3, +xlr, +xlp +</p></blockquote> + +<p>For compatibility reasons, ‘<samp><var>n</var>x</samp>’ and ‘<samp><var>b</var>fx</samp>’ are +accepted as synonyms for ‘<samp><var>n</var>f1_1</samp>’. These values are +deprecated. +</p> +</dd> +<dt><code>-mtune=<var>cpu</var></code></dt> +<dd><p>Schedule and tune for a particular MIPS CPU. Valid <var>cpu</var> values are +identical to ‘<samp>-march=<var>cpu</var></samp>’. +</p> +</dd> +<dt><code>-mabi=<var>abi</var></code></dt> +<dd><p>Record which ABI the source code uses. The recognized arguments +are: ‘<samp>32</samp>’, ‘<samp>n32</samp>’, ‘<samp>o64</samp>’, ‘<samp>64</samp>’ and ‘<samp>eabi</samp>’. +</p> +</dd> +<dt><code>-msym32</code></dt> +<dt><code>-mno-sym32</code></dt> +<dd><a name="index-_002dmsym32"></a> +<a name="index-_002dmno_002dsym32"></a> +<p>Equivalent to adding <code>.set sym32</code> or <code>.set nosym32</code> to +the beginning of the assembler input. See <a href="#MIPS-Symbol-Sizes">MIPS Symbol Sizes</a>. +</p> +<a name="index-_002dnocpp-ignored-_0028MIPS_0029"></a> +</dd> +<dt><code>-nocpp</code></dt> +<dd><p>This option is ignored. It is accepted for command-line compatibility with +other assemblers, which use it to turn off C style preprocessing. With +<small>GNU</small> <code>as</code>, there is no need for ‘<samp>-nocpp</samp>’, because the +<small>GNU</small> assembler itself never runs the C preprocessor. +</p> +</dd> +<dt><code>-msoft-float</code></dt> +<dt><code>-mhard-float</code></dt> +<dd><p>Disable or enable floating-point instructions. Note that by default +floating-point instructions are always allowed even with CPU targets +that don’t have support for these instructions. +</p> +</dd> +<dt><code>-msingle-float</code></dt> +<dt><code>-mdouble-float</code></dt> +<dd><p>Disable or enable double-precision floating-point operations. Note +that by default double-precision floating-point operations are always +allowed even with CPU targets that don’t have support for these +operations. +</p> +</dd> +<dt><code>--construct-floats</code></dt> +<dt><code>--no-construct-floats</code></dt> +<dd><p>The <code>--no-construct-floats</code> option disables the construction of +double width floating point constants by loading the two halves of the +value into the two single width floating point registers that make up +the double width register. This feature is useful if the processor +support the FR bit in its status register, and this bit is known (by +the programmer) to be set. This bit prevents the aliasing of the double +width register by the single width registers. +</p> +<p>By default <code>--construct-floats</code> is selected, allowing construction +of these floating point constants. +</p> +</dd> +<dt><code>--relax-branch</code></dt> +<dt><code>--no-relax-branch</code></dt> +<dd><p>The ‘<samp>--relax-branch</samp>’ option enables the relaxation of out-of-range +branches. Any branches whose target cannot be reached directly are +converted to a small instruction sequence including an inverse-condition +branch to the physically next instruction, and a jump to the original +target is inserted between the two instructions. In PIC code the jump +will involve further instructions for address calculation. +</p> +<p>The <code>BC1ANY2F</code>, <code>BC1ANY2T</code>, <code>BC1ANY4F</code>, <code>BC1ANY4T</code>, +<code>BPOSGE32</code> and <code>BPOSGE64</code> instructions are excluded from +relaxation, because they have no complementing counterparts. They could +be relaxed with the use of a longer sequence involving another branch, +however this has not been implemented and if their target turns out of +reach, they produce an error even if branch relaxation is enabled. +</p> +<p>Also no MIPS16 branches are ever relaxed. +</p> +<p>By default ‘<samp>--no-relax-branch</samp>’ is selected, causing any out-of-range +branches to produce an error. +</p> +</dd> +<dt><code>-mignore-branch-isa</code></dt> +<dt><code>-mno-ignore-branch-isa</code></dt> +<dd><p>Ignore branch checks for invalid transitions between ISA modes. +</p> +<p>The semantics of branches does not provide for an ISA mode switch, so in +most cases the ISA mode a branch has been encoded for has to be the same +as the ISA mode of the branch’s target label. If the ISA modes do not +match, then such a branch, if taken, will cause the ISA mode to remain +unchanged and instructions that follow will be executed in the wrong ISA +mode causing the program to misbehave or crash. +</p> +<p>In the case of the <code>BAL</code> instruction it may be possible to relax +it to an equivalent <code>JALX</code> instruction so that the ISA mode is +switched at the run time as required. For other branches no relaxation +is possible and therefore GAS has checks implemented that verify in +branch assembly that the two ISA modes match, and report an error +otherwise so that the problem with code can be diagnosed at the assembly +time rather than at the run time. +</p> +<p>However some assembly code, including generated code produced by some +versions of GCC, may incorrectly include branches to data labels, which +appear to require a mode switch but are either dead or immediately +followed by valid instructions encoded for the same ISA the branch has +been encoded for. While not strictly correct at the source level such +code will execute as intended, so to help with these cases +‘<samp>-mignore-branch-isa</samp>’ is supported which disables ISA mode checks +for branches. +</p> +<p>By default ‘<samp>-mno-ignore-branch-isa</samp>’ is selected, causing any invalid +branch requiring a transition between ISA modes to produce an error. +</p> +<a name="index-_002dmnan_003d-command_002dline-option_002c-MIPS"></a> +</dd> +<dt><code>-mnan=<var>encoding</var></code></dt> +<dd><p>This option indicates whether the source code uses the IEEE 2008 +NaN encoding (<samp>-mnan=2008</samp>) or the original MIPS encoding +(<samp>-mnan=legacy</samp>). It is equivalent to adding a <code>.nan</code> +directive to the beginning of the source file. See <a href="#MIPS-NaN-Encodings">MIPS NaN Encodings</a>. +</p> +<p><samp>-mnan=legacy</samp> is the default if no <samp>-mnan</samp> option or +<code>.nan</code> directive is used. +</p> +</dd> +<dt><code>--trap</code></dt> +<dt><code>--no-break</code></dt> +<dd><p><code>as</code> automatically macro expands certain division and +multiplication instructions to check for overflow and division by zero. This +option causes <code>as</code> to generate code to take a trap exception +rather than a break exception when an error is detected. The trap instructions +are only supported at Instruction Set Architecture level 2 and higher. +</p> +</dd> +<dt><code>--break</code></dt> +<dt><code>--no-trap</code></dt> +<dd><p>Generate code to take a break exception rather than a trap exception when an +error is detected. This is the default. +</p> +</dd> +<dt><code>-mpdr</code></dt> +<dt><code>-mno-pdr</code></dt> +<dd><p>Control generation of <code>.pdr</code> sections. Off by default on IRIX, on +elsewhere. +</p> +</dd> +<dt><code>-mshared</code></dt> +<dt><code>-mno-shared</code></dt> +<dd><p>When generating code using the Unix calling conventions (selected by +‘<samp>-KPIC</samp>’ or ‘<samp>-mcall_shared</samp>’), gas will normally generate code +which can go into a shared library. The ‘<samp>-mno-shared</samp>’ option +tells gas to generate code which uses the calling convention, but can +not go into a shared library. The resulting code is slightly more +efficient. This option only affects the handling of the +‘<samp>.cpload</samp>’ and ‘<samp>.cpsetup</samp>’ pseudo-ops. +</p></dd> +</dl> + +<hr> +<a name="MIPS-Macros"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-Symbol-Sizes" accesskey="n" rel="next">MIPS Symbol Sizes</a>, Previous: <a href="#MIPS-Options" accesskey="p" rel="previous">MIPS Options</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="High_002dlevel-assembly-macros"></a> +<h4 class="subsection">9.27.2 High-level assembly macros</h4> + +<p>MIPS assemblers have traditionally provided a wider range of +instructions than the MIPS architecture itself. These extra +instructions are usually referred to as “macro” instructions +<a name="DOCF2" href="#FOOT2"><sup>2</sup></a>. +</p> +<p>Some MIPS macro instructions extend an underlying architectural instruction +while others are entirely new. An example of the former type is <code>and</code>, +which allows the third operand to be either a register or an arbitrary +immediate value. Examples of the latter type include <code>bgt</code>, which +branches to the third operand when the first operand is greater than +the second operand, and <code>ulh</code>, which implements an unaligned +2-byte load. +</p> +<p>One of the most common extensions provided by macros is to expand +memory offsets to the full address range (32 or 64 bits) and to allow +symbolic offsets such as ‘<samp>my_data + 4</samp>’ to be used in place of +integer constants. For example, the architectural instruction +<code>lbu</code> allows only a signed 16-bit offset, whereas the macro +<code>lbu</code> allows code such as ‘<samp>lbu $4,array+32769($5)</samp>’. +The implementation of these symbolic offsets depends on several factors, +such as whether the assembler is generating SVR4-style PIC (selected by +<samp>-KPIC</samp>, see <a href="#MIPS-Options">Assembler options</a>), the size of symbols +(see <a href="#MIPS-Symbol-Sizes">Directives to override the size of symbols</a>), +and the small data limit (see <a href="#MIPS-Small-Data">Controlling the use +of small data accesses</a>). +</p> +<a name="index-_002eset-macro"></a> +<a name="index-_002eset-nomacro"></a> +<p>Sometimes it is undesirable to have one assembly instruction expand +to several machine instructions. The directive <code>.set nomacro</code> +tells the assembler to warn when this happens. <code>.set macro</code> +restores the default behavior. +</p> +<a name="index-at-register_002c-MIPS"></a> +<a name="index-_002eset-at_003dreg"></a> +<p>Some macro instructions need a temporary register to store intermediate +results. This register is usually <code>$1</code>, also known as <code>$at</code>, +but it can be changed to any core register <var>reg</var> using +<code>.set at=<var>reg</var></code>. Note that <code>$at</code> always refers +to <code>$1</code> regardless of which register is being used as the +temporary register. +</p> +<a name="index-_002eset-at"></a> +<a name="index-_002eset-noat"></a> +<p>Implicit uses of the temporary register in macros could interfere with +explicit uses in the assembly code. The assembler therefore warns +whenever it sees an explicit use of the temporary register. The directive +<code>.set noat</code> silences this warning while <code>.set at</code> restores +the default behavior. It is safe to use <code>.set noat</code> while +<code>.set nomacro</code> is in effect since single-instruction macros +never need a temporary register. +</p> +<p>Note that while the <small>GNU</small> assembler provides these macros for compatibility, +it does not make any attempt to optimize them with the surrounding code. +</p> +<hr> +<a name="MIPS-Symbol-Sizes"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-Small-Data" accesskey="n" rel="next">MIPS Small Data</a>, Previous: <a href="#MIPS-Macros" accesskey="p" rel="previous">MIPS Macros</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-to-override-the-size-of-symbols"></a> +<h4 class="subsection">9.27.3 Directives to override the size of symbols</h4> + +<a name="index-_002eset-sym32"></a> +<a name="index-_002eset-nosym32"></a> +<p>The n64 ABI allows symbols to have any 64-bit value. Although this +provides a great deal of flexibility, it means that some macros have +much longer expansions than their 32-bit counterparts. For example, +the non-PIC expansion of ‘<samp>dla $4,sym</samp>’ is usually: +</p> +<div class="smallexample"> +<pre class="smallexample">lui $4,%highest(sym) +lui $1,%hi(sym) +daddiu $4,$4,%higher(sym) +daddiu $1,$1,%lo(sym) +dsll32 $4,$4,0 +daddu $4,$4,$1 +</pre></div> + +<p>whereas the 32-bit expansion is simply: +</p> +<div class="smallexample"> +<pre class="smallexample">lui $4,%hi(sym) +daddiu $4,$4,%lo(sym) +</pre></div> + +<p>n64 code is sometimes constructed in such a way that all symbolic +constants are known to have 32-bit values, and in such cases, it’s +preferable to use the 32-bit expansion instead of the 64-bit +expansion. +</p> +<p>You can use the <code>.set sym32</code> directive to tell the assembler +that, from this point on, all expressions of the form +‘<samp><var>symbol</var></samp>’ or ‘<samp><var>symbol</var> + <var>offset</var></samp>’ +have 32-bit values. For example: +</p> +<div class="smallexample"> +<pre class="smallexample">.set sym32 +dla $4,sym +lw $4,sym+16 +sw $4,sym+0x8000($4) +</pre></div> + +<p>will cause the assembler to treat ‘<samp>sym</samp>’, <code>sym+16</code> and +<code>sym+0x8000</code> as 32-bit values. The handling of non-symbolic +addresses is not affected. +</p> +<p>The directive <code>.set nosym32</code> ends a <code>.set sym32</code> block and +reverts to the normal behavior. It is also possible to change the +symbol size using the command-line options <samp>-msym32</samp> and +<samp>-mno-sym32</samp>. +</p> +<p>These options and directives are always accepted, but at present, +they have no effect for anything other than n64. +</p> +<hr> +<a name="MIPS-Small-Data"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-ISA" accesskey="n" rel="next">MIPS ISA</a>, Previous: <a href="#MIPS-Symbol-Sizes" accesskey="p" rel="previous">MIPS Symbol Sizes</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Controlling-the-use-of-small-data-accesses"></a> +<h4 class="subsection">9.27.4 Controlling the use of small data accesses</h4> + +<a name="index-small-data_002c-MIPS"></a> +<a name="index-gp-register_002c-MIPS"></a> +<p>It often takes several instructions to load the address of a symbol. +For example, when ‘<samp>addr</samp>’ is a 32-bit symbol, the non-PIC expansion +of ‘<samp>dla $4,addr</samp>’ is usually: +</p> +<div class="smallexample"> +<pre class="smallexample">lui $4,%hi(addr) +daddiu $4,$4,%lo(addr) +</pre></div> + +<p>The sequence is much longer when ‘<samp>addr</samp>’ is a 64-bit symbol. +See <a href="#MIPS-Symbol-Sizes">Directives to override the size of symbols</a>. +</p> +<p>In order to cut down on this overhead, most embedded MIPS systems +set aside a 64-kilobyte “small data” area and guarantee that all +data of size <var>n</var> and smaller will be placed in that area. +The limit <var>n</var> is passed to both the assembler and the linker +using the command-line option <samp>-G <var>n</var></samp>, see <a href="#MIPS-Options">Assembler options</a>. Note that the same value of <var>n</var> must be used +when linking and when assembling all input files to the link; any +inconsistency could cause a relocation overflow error. +</p> +<p>The size of an object in the <code>.bss</code> section is set by the +<code>.comm</code> or <code>.lcomm</code> directive that defines it. The size of +an external object may be set with the <code>.extern</code> directive. For +example, ‘<samp>.extern sym,4</samp>’ declares that the object at <code>sym</code> +is 4 bytes in length, while leaving <code>sym</code> otherwise undefined. +</p> +<p>When no <samp>-G</samp> option is given, the default limit is 8 bytes. +The option <samp>-G 0</samp> prevents any data from being automatically +classified as small. +</p> +<p>It is also possible to mark specific objects as small by putting them +in the special sections <code>.sdata</code> and <code>.sbss</code>, which are +“small” counterparts of <code>.data</code> and <code>.bss</code> respectively. +The toolchain will treat such data as small regardless of the +<samp>-G</samp> setting. +</p> +<p>On startup, systems that support a small data area are expected to +initialize register <code>$28</code>, also known as <code>$gp</code>, in such a +way that small data can be accessed using a 16-bit offset from that +register. For example, when ‘<samp>addr</samp>’ is small data, +the ‘<samp>dla $4,addr</samp>’ instruction above is equivalent to: +</p> +<div class="smallexample"> +<pre class="smallexample">daddiu $4,$28,%gp_rel(addr) +</pre></div> + +<p>Small data is not supported for SVR4-style PIC. +</p> +<hr> +<a name="MIPS-ISA"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-assembly-options" accesskey="n" rel="next">MIPS assembly options</a>, Previous: <a href="#MIPS-Small-Data" accesskey="p" rel="previous">MIPS Small Data</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-to-override-the-ISA-level"></a> +<h4 class="subsection">9.27.5 Directives to override the ISA level</h4> + +<a name="index-MIPS-ISA-override"></a> +<a name="index-_002eset-mipsn"></a> +<p><small>GNU</small> <code>as</code> supports an additional directive to change +the MIPS Instruction Set Architecture level on the fly: <code>.set +mips<var>n</var></code>. <var>n</var> should be a number from 0 to 5, or 32, 32r2, 32r3, +32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. +The values other than 0 make the assembler accept instructions +for the corresponding ISA level, from that point on in the +assembly. <code>.set mips<var>n</var></code> affects not only which instructions +are permitted, but also how certain macros are expanded. <code>.set +mips0</code> restores the ISA level to its original level: either the +level you selected with command-line options, or the default for your +configuration. You can use this feature to permit specific MIPS III +instructions while assembling in 32 bit mode. Use this directive with +care! +</p> +<a name="index-MIPS-CPU-override"></a> +<a name="index-_002eset-arch_003dcpu"></a> +<p>The <code>.set arch=<var>cpu</var></code> directive provides even finer control. +It changes the effective CPU target and allows the assembler to use +instructions specific to a particular CPU. All CPUs supported by the +‘<samp>-march</samp>’ command-line option are also selectable by this directive. +The original value is restored by <code>.set arch=default</code>. +</p> +<p>The directive <code>.set mips16</code> puts the assembler into MIPS 16 mode, +in which it will assemble instructions for the MIPS 16 processor. Use +<code>.set nomips16</code> to return to normal 32 bit mode. +</p> +<p>Traditional MIPS assemblers do not support this directive. +</p> +<p>The directive <code>.set micromips</code> puts the assembler into microMIPS mode, +in which it will assemble instructions for the microMIPS processor. Use +<code>.set nomicromips</code> to return to normal 32 bit mode. +</p> +<p>Traditional MIPS assemblers do not support this directive. +</p> +<hr> +<a name="MIPS-assembly-options"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-autoextend" accesskey="n" rel="next">MIPS autoextend</a>, Previous: <a href="#MIPS-ISA" accesskey="p" rel="previous">MIPS ISA</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-to-control-code-generation"></a> +<h4 class="subsection">9.27.6 Directives to control code generation</h4> + +<a name="index-MIPS-directives-to-override-command_002dline-options"></a> +<a name="index-_002emodule"></a> +<p>The <code>.module</code> directive allows command-line options to be set directly +from assembly. The format of the directive matches the <code>.set</code> +directive but only those options which are relevant to a whole module are +supported. The effect of a <code>.module</code> directive is the same as the +corresponding command-line option. Where <code>.set</code> directives support +returning to a default then the <code>.module</code> directives do not as they +define the defaults. +</p> +<p>These module-level directives must appear first in assembly. +</p> +<p>Traditional MIPS assemblers do not support this directive. +</p> +<a name="index-MIPS-32_002dbit-microMIPS-instruction-generation-override"></a> +<a name="index-_002eset-insn32"></a> +<a name="index-_002eset-noinsn32"></a> +<p>The directive <code>.set insn32</code> makes the assembler only use 32-bit +instruction encodings when generating code for the microMIPS processor. +This directive inhibits the use of any 16-bit instructions from that +point on in the assembly. The <code>.set noinsn32</code> directive allows +16-bit instructions to be accepted. +</p> +<p>Traditional MIPS assemblers do not support this directive. +</p> +<hr> +<a name="MIPS-autoextend"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-insn" accesskey="n" rel="next">MIPS insn</a>, Previous: <a href="#MIPS-assembly-options" accesskey="p" rel="previous">MIPS assembly options</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-for-extending-MIPS-16-bit-instructions"></a> +<h4 class="subsection">9.27.7 Directives for extending MIPS 16 bit instructions</h4> + +<a name="index-_002eset-autoextend"></a> +<a name="index-_002eset-noautoextend"></a> +<p>By default, MIPS 16 instructions are automatically extended to 32 bits +when necessary. The directive <code>.set noautoextend</code> will turn this +off. When <code>.set noautoextend</code> is in effect, any 32 bit instruction +must be explicitly extended with the <code>.e</code> modifier (e.g., +<code>li.e $4,1000</code>). The directive <code>.set autoextend</code> may be used +to once again automatically extend instructions when necessary. +</p> +<p>This directive is only meaningful when in MIPS 16 mode. Traditional +MIPS assemblers do not support this directive. +</p> +<hr> +<a name="MIPS-insn"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-FP-ABIs" accesskey="n" rel="next">MIPS FP ABIs</a>, Previous: <a href="#MIPS-autoextend" accesskey="p" rel="previous">MIPS autoextend</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directive-to-mark-data-as-an-instruction"></a> +<h4 class="subsection">9.27.8 Directive to mark data as an instruction</h4> + +<a name="index-_002einsn"></a> +<p>The <code>.insn</code> directive tells <code>as</code> that the following +data is actually instructions. This makes a difference in MIPS 16 and +microMIPS modes: when loading the address of a label which precedes +instructions, <code>as</code> automatically adds 1 to the value, so +that jumping to the loaded address will do the right thing. +</p> +<a name="index-_002eglobal"></a> +<p>The <code>.global</code> and <code>.globl</code> directives supported by +<code>as</code> will by default mark the symbol as pointing to a +region of data not code. This means that, for example, any +instructions following such a symbol will not be disassembled by +<code>objdump</code> as it will regard them as data. To change this +behavior an optional section name can be placed after the symbol name +in the <code>.global</code> directive. If this section exists and is known +to be a code section, then the symbol will be marked as pointing at +code not data. Ie the syntax for the directive is: +</p> +<p><code>.global <var>symbol</var>[ <var>section</var>][, <var>symbol</var>[ <var>section</var>]] ...</code>, +</p> +<p>Here is a short example: +</p> +<div class="example"> +<pre class="example"> .global foo .text, bar, baz .data +foo: + nop +bar: + .word 0x0 +baz: + .word 0x1 + +</pre></div> + +<hr> +<a name="MIPS-FP-ABIs"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-NaN-Encodings" accesskey="n" rel="next">MIPS NaN Encodings</a>, Previous: <a href="#MIPS-insn" accesskey="p" rel="previous">MIPS insn</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-to-control-the-FP-ABI"></a> +<h4 class="subsection">9.27.9 Directives to control the FP ABI</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#MIPS-FP-ABI-History" accesskey="1">MIPS FP ABI History</a>:</td><td> </td><td align="left" valign="top">History of FP ABIs +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-FP-ABI-Variants" accesskey="2">MIPS FP ABI Variants</a>:</td><td> </td><td align="left" valign="top">Supported FP ABIs +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-FP-ABI-Selection" accesskey="3">MIPS FP ABI Selection</a>:</td><td> </td><td align="left" valign="top">Automatic selection of FP ABI +</td></tr> +<tr><td align="left" valign="top">• <a href="#MIPS-FP-ABI-Compatibility" accesskey="4">MIPS FP ABI Compatibility</a>:</td><td> </td><td align="left" valign="top">Linking different FP ABI variants +</td></tr> +</table> + +<hr> +<a name="MIPS-FP-ABI-History"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-FP-ABI-Variants" accesskey="n" rel="next">MIPS FP ABI Variants</a>, Up: <a href="#MIPS-FP-ABIs" accesskey="u" rel="up">MIPS FP ABIs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="History-of-FP-ABIs"></a> +<h4 class="subsubsection">9.27.9.1 History of FP ABIs</h4> +<a name="index-_002egnu_005fattribute-4_002c-n-directive_002c-MIPS"></a> +<a name="index-_002egnu_005fattribute-Tag_005fGNU_005fMIPS_005fABI_005fFP_002c-n-directive_002c-MIPS"></a> +<p>The MIPS ABIs support a variety of different floating-point extensions +where calling-convention and register sizes vary for floating-point data. +The extensions exist to support a wide variety of optional architecture +features. The resulting ABI variants are generally incompatible with each +other and must be tracked carefully. +</p> +<p>Traditionally the use of an explicit <code>.gnu_attribute 4, <var>n</var></code> +directive is used to indicate which ABI is in use by a specific module. +It was then left to the user to ensure that command-line options and the +selected ABI were compatible with some potential for inconsistencies. +</p> +<hr> +<a name="MIPS-FP-ABI-Variants"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-FP-ABI-Selection" accesskey="n" rel="next">MIPS FP ABI Selection</a>, Previous: <a href="#MIPS-FP-ABI-History" accesskey="p" rel="previous">MIPS FP ABI History</a>, Up: <a href="#MIPS-FP-ABIs" accesskey="u" rel="up">MIPS FP ABIs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Supported-FP-ABIs"></a> +<h4 class="subsubsection">9.27.9.2 Supported FP ABIs</h4> +<p>The supported floating-point ABI variants are: +</p> +<dl compact="compact"> +<dt><code>0 - No floating-point</code></dt> +<dd><p>This variant is used to indicate that floating-point is not used within +the module at all and therefore has no impact on the ABI. This is the +default. +</p> +</dd> +<dt><code>1 - Double-precision</code></dt> +<dd><p>This variant indicates that double-precision support is used. For 64-bit +ABIs this means that 64-bit wide floating-point registers are required. +For 32-bit ABIs this means that 32-bit wide floating-point registers are +required and double-precision operations use pairs of registers. +</p> +</dd> +<dt><code>2 - Single-precision</code></dt> +<dd><p>This variant indicates that single-precision support is used. Double +precision operations will be supported via soft-float routines. +</p> +</dd> +<dt><code>3 - Soft-float</code></dt> +<dd><p>This variant indicates that although floating-point support is used all +operations are emulated in software. This means the ABI is modified to +pass all floating-point data in general-purpose registers. +</p> +</dd> +<dt><code>4 - Deprecated</code></dt> +<dd><p>This variant existed as an initial attempt at supporting 64-bit wide +floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been +superseded by 5, 6 and 7. +</p> +</dd> +<dt><code>5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU</code></dt> +<dd><p>This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module has been designed to operate correctly with either +32-bit wide or 64-bit wide floating-point registers. Double-precision +support is used. Only O32 currently supports this variant and requires +a minimum architecture of MIPS II. +</p> +</dd> +<dt><code>6 - Double-precision 32-bit FPU, 64-bit FPU</code></dt> +<dd><p>This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. Only O32 currently supports this +variant and requires a minimum architecture of MIPS32r2. +</p> +</dd> +<dt><code>7 - Double-precision compat 32-bit FPU, 64-bit FPU</code></dt> +<dd><p>This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. This differs from the previous ABI +as it restricts use of odd-numbered single-precision registers. Only +O32 currently supports this variant and requires a minimum architecture +of MIPS32r2. +</p></dd> +</dl> + +<hr> +<a name="MIPS-FP-ABI-Selection"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-FP-ABI-Compatibility" accesskey="n" rel="next">MIPS FP ABI Compatibility</a>, Previous: <a href="#MIPS-FP-ABI-Variants" accesskey="p" rel="previous">MIPS FP ABI Variants</a>, Up: <a href="#MIPS-FP-ABIs" accesskey="u" rel="up">MIPS FP ABIs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Automatic-selection-of-FP-ABI"></a> +<h4 class="subsubsection">9.27.9.3 Automatic selection of FP ABI</h4> +<a name="index-_002emodule-fp_003dnn-directive_002c-MIPS"></a> +<p>In order to simplify and add safety to the process of selecting the +correct floating-point ABI, the assembler will automatically infer the +correct <code>.gnu_attribute 4, <var>n</var></code> directive based on command-line +options and <code>.module</code> overrides. Where an explicit +<code>.gnu_attribute 4, <var>n</var></code> directive has been seen then a warning +will be raised if it does not match an inferred setting. +</p> +<p>The floating-point ABI is inferred as follows. If ‘<samp>-msoft-float</samp>’ +has been used the module will be marked as soft-float. If +‘<samp>-msingle-float</samp>’ has been used then the module will be marked as +single-precision. The remaining ABIs are then selected based +on the FP register width. Double-precision is selected if the width +of GP and FP registers match and the special double-precision variants +for 32-bit ABIs are then selected depending on ‘<samp>-mfpxx</samp>’, +‘<samp>-mfp64</samp>’ and ‘<samp>-mno-odd-spreg</samp>’. +</p> +<hr> +<a name="MIPS-FP-ABI-Compatibility"></a> +<div class="header"> +<p> +Previous: <a href="#MIPS-FP-ABI-Selection" accesskey="p" rel="previous">MIPS FP ABI Selection</a>, Up: <a href="#MIPS-FP-ABIs" accesskey="u" rel="up">MIPS FP ABIs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Linking-different-FP-ABI-variants"></a> +<h4 class="subsubsection">9.27.9.4 Linking different FP ABI variants</h4> +<p>Modules using the default FP ABI (no floating-point) can be linked with +any other (singular) FP ABI variant. +</p> +<p>Special compatibility support exists for O32 with the four +double-precision FP ABI variants. The ‘<samp>-mfpxx</samp>’ FP ABI is specifically +designed to be compatible with the standard double-precision ABI and the +‘<samp>-mfp64</samp>’ FP ABIs. This makes it desirable for O32 modules to be +built as ‘<samp>-mfpxx</samp>’ to ensure the maximum compatibility with other +modules produced for more specific needs. The only FP ABIs which cannot +be linked together are the standard double-precision ABI and the full +‘<samp>-mfp64</samp>’ ABI with ‘<samp>-modd-spreg</samp>’. +</p> +<hr> +<a name="MIPS-NaN-Encodings"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-Option-Stack" accesskey="n" rel="next">MIPS Option Stack</a>, Previous: <a href="#MIPS-FP-ABIs" accesskey="p" rel="previous">MIPS FP ABIs</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-to-record-which-NaN-encoding-is-being-used"></a> +<h4 class="subsection">9.27.10 Directives to record which NaN encoding is being used</h4> + +<a name="index-MIPS-IEEE-754-NaN-data-encoding-selection"></a> +<a name="index-_002enan-directive_002c-MIPS"></a> +<p>The IEEE 754 floating-point standard defines two types of not-a-number +(NaN) data: “signalling” NaNs and “quiet” NaNs. The original version +of the standard did not specify how these two types should be +distinguished. Most implementations followed the i387 model, in which +the first bit of the significand is set for quiet NaNs and clear for +signalling NaNs. However, the original MIPS implementation assigned the +opposite meaning to the bit, so that it was set for signalling NaNs and +clear for quiet NaNs. +</p> +<p>The 2008 revision of the standard formally suggested the i387 choice +and as from Sep 2012 the current release of the MIPS architecture +therefore optionally supports that form. Code that uses one NaN encoding +would usually be incompatible with code that uses the other NaN encoding, +so MIPS ELF objects have a flag (<code>EF_MIPS_NAN2008</code>) to record which +encoding is being used. +</p> +<p>Assembly files can use the <code>.nan</code> directive to select between the +two encodings. ‘<samp>.nan 2008</samp>’ says that the assembly file uses the +IEEE 754-2008 encoding while ‘<samp>.nan legacy</samp>’ says that the file uses +the original MIPS encoding. If several <code>.nan</code> directives are given, +the final setting is the one that is used. +</p> +<p>The command-line options <samp>-mnan=legacy</samp> and <samp>-mnan=2008</samp> +can be used instead of ‘<samp>.nan legacy</samp>’ and ‘<samp>.nan 2008</samp>’ +respectively. However, any <code>.nan</code> directive overrides the +command-line setting. +</p> +<p>‘<samp>.nan legacy</samp>’ is the default if no <code>.nan</code> directive or +<samp>-mnan</samp> option is given. +</p> +<p>Note that <small>GNU</small> <code>as</code> does not produce NaNs itself and +therefore these directives do not affect code generation. They simply +control the setting of the <code>EF_MIPS_NAN2008</code> flag. +</p> +<p>Traditional MIPS assemblers do not support these directives. +</p> +<hr> +<a name="MIPS-Option-Stack"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-ASE-Instruction-Generation-Overrides" accesskey="n" rel="next">MIPS ASE Instruction Generation Overrides</a>, Previous: <a href="#MIPS-NaN-Encodings" accesskey="p" rel="previous">MIPS NaN Encodings</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-to-save-and-restore-options"></a> +<h4 class="subsection">9.27.11 Directives to save and restore options</h4> + +<a name="index-MIPS-option-stack"></a> +<a name="index-_002eset-push"></a> +<a name="index-_002eset-pop"></a> +<p>The directives <code>.set push</code> and <code>.set pop</code> may be used to save +and restore the current settings for all the options which are +controlled by <code>.set</code>. The <code>.set push</code> directive saves the +current settings on a stack. The <code>.set pop</code> directive pops the +stack and restores the settings. +</p> +<p>These directives can be useful inside an macro which must change an +option such as the ISA level or instruction reordering but does not want +to change the state of the code which invoked the macro. +</p> +<p>Traditional MIPS assemblers do not support these directives. +</p> +<hr> +<a name="MIPS-ASE-Instruction-Generation-Overrides"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-Floating_002dPoint" accesskey="n" rel="next">MIPS Floating-Point</a>, Previous: <a href="#MIPS-Option-Stack" accesskey="p" rel="previous">MIPS Option Stack</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-to-control-generation-of-MIPS-ASE-instructions"></a> +<h4 class="subsection">9.27.12 Directives to control generation of MIPS ASE instructions</h4> + +<a name="index-MIPS-MIPS_002d3D-instruction-generation-override"></a> +<a name="index-_002eset-mips3d"></a> +<a name="index-_002eset-nomips3d"></a> +<p>The directive <code>.set mips3d</code> makes the assembler accept instructions +from the MIPS-3D Application Specific Extension from that point on +in the assembly. The <code>.set nomips3d</code> directive prevents MIPS-3D +instructions from being accepted. +</p> +<a name="index-SmartMIPS-instruction-generation-override"></a> +<a name="index-_002eset-smartmips"></a> +<a name="index-_002eset-nosmartmips"></a> +<p>The directive <code>.set smartmips</code> makes the assembler accept +instructions from the SmartMIPS Application Specific Extension to the +MIPS32 ISA from that point on in the assembly. The +<code>.set nosmartmips</code> directive prevents SmartMIPS instructions from +being accepted. +</p> +<a name="index-MIPS-MDMX-instruction-generation-override"></a> +<a name="index-_002eset-mdmx"></a> +<a name="index-_002eset-nomdmx"></a> +<p>The directive <code>.set mdmx</code> makes the assembler accept instructions +from the MDMX Application Specific Extension from that point on +in the assembly. The <code>.set nomdmx</code> directive prevents MDMX +instructions from being accepted. +</p> +<a name="index-MIPS-DSP-Release-1-instruction-generation-override"></a> +<a name="index-_002eset-dsp"></a> +<a name="index-_002eset-nodsp"></a> +<p>The directive <code>.set dsp</code> makes the assembler accept instructions +from the DSP Release 1 Application Specific Extension from that point +on in the assembly. The <code>.set nodsp</code> directive prevents DSP +Release 1 instructions from being accepted. +</p> +<a name="index-MIPS-DSP-Release-2-instruction-generation-override"></a> +<a name="index-_002eset-dspr2"></a> +<a name="index-_002eset-nodspr2"></a> +<p>The directive <code>.set dspr2</code> makes the assembler accept instructions +from the DSP Release 2 Application Specific Extension from that point +on in the assembly. This directive implies <code>.set dsp</code>. The +<code>.set nodspr2</code> directive prevents DSP Release 2 instructions from +being accepted. +</p> +<a name="index-MIPS-DSP-Release-3-instruction-generation-override"></a> +<a name="index-_002eset-dspr3"></a> +<a name="index-_002eset-nodspr3"></a> +<p>The directive <code>.set dspr3</code> makes the assembler accept instructions +from the DSP Release 3 Application Specific Extension from that point +on in the assembly. This directive implies <code>.set dsp</code> and +<code>.set dspr2</code>. The <code>.set nodspr3</code> directive prevents DSP +Release 3 instructions from being accepted. +</p> +<a name="index-MIPS-MT-instruction-generation-override"></a> +<a name="index-_002eset-mt"></a> +<a name="index-_002eset-nomt"></a> +<p>The directive <code>.set mt</code> makes the assembler accept instructions +from the MT Application Specific Extension from that point on +in the assembly. The <code>.set nomt</code> directive prevents MT +instructions from being accepted. +</p> +<a name="index-MIPS-MCU-instruction-generation-override"></a> +<a name="index-_002eset-mcu"></a> +<a name="index-_002eset-nomcu"></a> +<p>The directive <code>.set mcu</code> makes the assembler accept instructions +from the MCU Application Specific Extension from that point on +in the assembly. The <code>.set nomcu</code> directive prevents MCU +instructions from being accepted. +</p> +<a name="index-MIPS-SIMD-Architecture-instruction-generation-override"></a> +<a name="index-_002eset-msa"></a> +<a name="index-_002eset-nomsa"></a> +<p>The directive <code>.set msa</code> makes the assembler accept instructions +from the MIPS SIMD Architecture Extension from that point on +in the assembly. The <code>.set nomsa</code> directive prevents MSA +instructions from being accepted. +</p> +<a name="index-Virtualization-instruction-generation-override"></a> +<a name="index-_002eset-virt"></a> +<a name="index-_002eset-novirt"></a> +<p>The directive <code>.set virt</code> makes the assembler accept instructions +from the Virtualization Application Specific Extension from that point +on in the assembly. The <code>.set novirt</code> directive prevents Virtualization +instructions from being accepted. +</p> +<a name="index-MIPS-eXtended-Physical-Address-_0028XPA_0029-instruction-generation-override"></a> +<a name="index-_002eset-xpa"></a> +<a name="index-_002eset-noxpa"></a> +<p>The directive <code>.set xpa</code> makes the assembler accept instructions +from the XPA Extension from that point on in the assembly. The +<code>.set noxpa</code> directive prevents XPA instructions from being accepted. +</p> +<a name="index-MIPS16e2-instruction-generation-override"></a> +<a name="index-_002eset-mips16e2"></a> +<a name="index-_002eset-nomips16e2"></a> +<p>The directive <code>.set mips16e2</code> makes the assembler accept instructions +from the MIPS16e2 Application Specific Extension from that point on in the +assembly, whenever in MIPS16 mode. The <code>.set nomips16e2</code> directive +prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. Neither +directive affects the state of MIPS16 mode being active itself which has +separate controls. +</p> +<a name="index-MIPS-cyclic-redundancy-check-_0028CRC_0029-instruction-generation-override"></a> +<a name="index-_002eset-crc"></a> +<a name="index-_002eset-nocrc"></a> +<p>The directive <code>.set crc</code> makes the assembler accept instructions +from the CRC Extension from that point on in the assembly. The +<code>.set nocrc</code> directive prevents CRC instructions from being accepted. +</p> +<a name="index-MIPS-Global-INValidate-_0028GINV_0029-instruction-generation-override"></a> +<a name="index-_002eset-ginv"></a> +<a name="index-_002eset-noginv"></a> +<p>The directive <code>.set ginv</code> makes the assembler accept instructions +from the GINV Extension from that point on in the assembly. The +<code>.set noginv</code> directive prevents GINV instructions from being accepted. +</p> +<a name="index-Loongson-MultiMedia-extensions-Instructions-_0028MMI_0029-generation-override"></a> +<a name="index-_002eset-loongson_002dmmi"></a> +<a name="index-_002eset-noloongson_002dmmi"></a> +<p>The directive <code>.set loongson-mmi</code> makes the assembler accept +instructions from the MMI Extension from that point on in the assembly. +The <code>.set noloongson-mmi</code> directive prevents MMI instructions from +being accepted. +</p> +<a name="index-Loongson-Content-Address-Memory-_0028CAM_0029-generation-override"></a> +<a name="index-_002eset-loongson_002dcam"></a> +<a name="index-_002eset-noloongson_002dcam"></a> +<p>The directive <code>.set loongson-cam</code> makes the assembler accept +instructions from the Loongson CAM from that point on in the assembly. +The <code>.set noloongson-cam</code> directive prevents Loongson CAM instructions +from being accepted. +</p> +<a name="index-Loongson-EXTensions-_0028EXT_0029-instructions-generation-override"></a> +<a name="index-_002eset-loongson_002dext"></a> +<a name="index-_002eset-noloongson_002dext"></a> +<p>The directive <code>.set loongson-ext</code> makes the assembler accept +instructions from the Loongson EXT from that point on in the assembly. +The <code>.set noloongson-ext</code> directive prevents Loongson EXT instructions +from being accepted. +</p> +<a name="index-Loongson-EXTensions-R2-_0028EXT2_0029-instructions-generation-override"></a> +<a name="index-_002eset-loongson_002dext2"></a> +<a name="index-_002eset-noloongson_002dext2"></a> +<p>The directive <code>.set loongson-ext2</code> makes the assembler accept +instructions from the Loongson EXT2 from that point on in the assembly. +This directive implies <code>.set loognson-ext</code>. +The <code>.set noloongson-ext2</code> directive prevents Loongson EXT2 instructions +from being accepted. +</p> +<p>Traditional MIPS assemblers do not support these directives. +</p> +<hr> +<a name="MIPS-Floating_002dPoint"></a> +<div class="header"> +<p> +Next: <a href="#MIPS-Syntax" accesskey="n" rel="next">MIPS Syntax</a>, Previous: <a href="#MIPS-ASE-Instruction-Generation-Overrides" accesskey="p" rel="previous">MIPS ASE Instruction Generation Overrides</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-to-override-floating_002dpoint-options"></a> +<h4 class="subsection">9.27.13 Directives to override floating-point options</h4> + +<a name="index-Disable-floating_002dpoint-instructions"></a> +<a name="index-_002eset-softfloat"></a> +<a name="index-_002eset-hardfloat"></a> +<p>The directives <code>.set softfloat</code> and <code>.set hardfloat</code> provide +finer control of disabling and enabling float-point instructions. +These directives always override the default (that hard-float +instructions are accepted) or the command-line options +(‘<samp>-msoft-float</samp>’ and ‘<samp>-mhard-float</samp>’). +</p> +<a name="index-Disable-single_002dprecision-floating_002dpoint-operations"></a> +<a name="index-_002eset-singlefloat"></a> +<a name="index-_002eset-doublefloat"></a> +<p>The directives <code>.set singlefloat</code> and <code>.set doublefloat</code> +provide finer control of disabling and enabling double-precision +float-point operations. These directives always override the default +(that double-precision operations are accepted) or the command-line +options (‘<samp>-msingle-float</samp>’ and ‘<samp>-mdouble-float</samp>’). +</p> +<p>Traditional MIPS assemblers do not support these directives. +</p> +<hr> +<a name="MIPS-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#MIPS-Floating_002dPoint" accesskey="p" rel="previous">MIPS Floating-Point</a>, Up: <a href="#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntactical-considerations-for-the-MIPS-assembler"></a> +<h4 class="subsection">9.27.14 Syntactical considerations for the MIPS assembler</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#MIPS_002dChars" accesskey="1">MIPS-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="MIPS_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#MIPS-Syntax" accesskey="u" rel="up">MIPS Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-20"></a> +<h4 class="subsubsection">9.27.14.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-MIPS"></a> +<a name="index-MIPS-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ on a line indicates the start of a comment +that extends to the end of the current line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line, the whole line +is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a +preprocessor control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-MIPS"></a> +<a name="index-statement-separator_002c-MIPS"></a> +<a name="index-MIPS-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="MMIX_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#MSP430_002dDependent" accesskey="n" rel="next">MSP430-Dependent</a>, Previous: <a href="#MIPS_002dDependent" accesskey="p" rel="previous">MIPS-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="MMIX-Dependent-Features"></a> +<h3 class="section">9.28 MMIX Dependent Features</h3> + +<a name="index-MMIX-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#MMIX_002dOpts" accesskey="1">MMIX-Opts</a>:</td><td> </td><td align="left" valign="top">Command-line Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#MMIX_002dExpand" accesskey="2">MMIX-Expand</a>:</td><td> </td><td align="left" valign="top">Instruction expansion +</td></tr> +<tr><td align="left" valign="top">• <a href="#MMIX_002dSyntax" accesskey="3">MMIX-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#MMIX_002dmmixal" accesskey="4">MMIX-mmixal</a>:</td><td> </td><td align="left" valign="top">Differences to <code>mmixal</code> syntax and semantics +</td></tr> +</table> + +<hr> +<a name="MMIX_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#MMIX_002dExpand" accesskey="n" rel="next">MMIX-Expand</a>, Up: <a href="#MMIX_002dDependent" accesskey="u" rel="up">MMIX-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Command_002dline-Options-1"></a> +<h4 class="subsection">9.28.1 Command-line Options</h4> + +<a name="index-options_002c-MMIX"></a> +<a name="index-MMIX-options"></a> +<p>The MMIX version of <code>as</code> has some machine-dependent options. +</p> +<a name="index-_002d_002dfixed_002dspecial_002dregister_002dnames-command_002dline-option_002c-MMIX"></a> +<p>When ‘<samp>--fixed-special-register-names</samp>’ is specified, only the register +names specified in <a href="#MMIX_002dRegs">MMIX-Regs</a> are recognized in the instructions +<code>PUT</code> and <code>GET</code>. +</p> +<a name="index-_002d_002dglobalize_002dsymbols-command_002dline-option_002c-MMIX"></a> +<p>You can use the ‘<samp>--globalize-symbols</samp>’ to make all symbols global. +This option is useful when splitting up a <code>mmixal</code> program into +several files. +</p> +<a name="index-_002d_002dgnu_002dsyntax-command_002dline-option_002c-MMIX"></a> +<p>The ‘<samp>--gnu-syntax</samp>’ turns off most syntax compatibility with +<code>mmixal</code>. Its usability is currently doubtful. +</p> +<a name="index-_002d_002drelax-command_002dline-option_002c-MMIX"></a> +<p>The ‘<samp>--relax</samp>’ option is not fully supported, but will eventually make +the object file prepared for linker relaxation. +</p> +<a name="index-_002d_002dno_002dpredefined_002dsyms-command_002dline-option_002c-MMIX"></a> +<p>If you want to avoid inadvertently calling a predefined symbol and would +rather get an error, for example when using <code>as</code> with a +compiler or other machine-generated code, specify +‘<samp>--no-predefined-syms</samp>’. This turns off built-in predefined +definitions of all such symbols, including rounding-mode symbols, segment +symbols, ‘<samp>BIT</samp>’ symbols, and <code>TRAP</code> symbols used in <code>mmix</code> +“system calls”. It also turns off predefined special-register names, +except when used in <code>PUT</code> and <code>GET</code> instructions. +</p> +<a name="index-_002d_002dno_002dexpand-command_002dline-option_002c-MMIX"></a> +<p>By default, some instructions are expanded to fit the size of the operand +or an external symbol (see <a href="#MMIX_002dExpand">MMIX-Expand</a>). By passing +‘<samp>--no-expand</samp>’, no such expansion will be done, instead causing errors +at link time if the operand does not fit. +</p> +<a name="index-_002d_002dno_002dmerge_002dgregs-command_002dline-option_002c-MMIX"></a> +<p>The <code>mmixal</code> documentation (see <a href="#mmixsite">mmixsite</a>) specifies that global +registers allocated with the ‘<samp>GREG</samp>’ directive (see <a href="#MMIX_002dgreg">MMIX-greg</a>) and +initialized to the same non-zero value, will refer to the same global +register. This isn’t strictly enforceable in <code>as</code> since the +final addresses aren’t known until link-time, but it will do an effort +unless the ‘<samp>--no-merge-gregs</samp>’ option is specified. (Register merging +isn’t yet implemented in <code>ld</code>.) +</p> +<a name="index-_002dx-command_002dline-option_002c-MMIX"></a> +<p><code>as</code> will warn every time it expands an instruction to fit an +operand unless the option ‘<samp>-x</samp>’ is specified. It is believed that +this behaviour is more useful than just mimicking <code>mmixal</code>’s +behaviour, in which instructions are only expanded if the ‘<samp>-x</samp>’ option +is specified, and assembly fails otherwise, when an instruction needs to +be expanded. It needs to be kept in mind that <code>mmixal</code> is both an +assembler and linker, while <code>as</code> will expand instructions +that at link stage can be contracted. (Though linker relaxation isn’t yet +implemented in <code>ld</code>.) The option ‘<samp>-x</samp>’ also implies +‘<samp>--linker-allocated-gregs</samp>’. +</p> +<a name="index-_002d_002dno_002dpushj_002dstubs-command_002dline-option_002c-MMIX"></a> +<a name="index-_002d_002dno_002dstubs-command_002dline-option_002c-MMIX"></a> +<p>If instruction expansion is enabled, <code>as</code> can expand a +‘<samp>PUSHJ</samp>’ instruction into a series of instructions. The shortest +expansion is to not expand it, but just mark the call as redirectable to a +stub, which <code>ld</code> creates at link-time, but only if the +original ‘<samp>PUSHJ</samp>’ instruction is found not to reach the target. The +stub consists of the necessary instructions to form a jump to the target. +This happens if <code>as</code> can assert that the ‘<samp>PUSHJ</samp>’ +instruction can reach such a stub. The option ‘<samp>--no-pushj-stubs</samp>’ +disables this shorter expansion, and the longer series of instructions is +then created at assembly-time. The option ‘<samp>--no-stubs</samp>’ is a synonym, +intended for compatibility with future releases, where generation of stubs +for other instructions may be implemented. +</p> +<a name="index-_002d_002dlinker_002dallocated_002dgregs-command_002dline-option_002c-MMIX"></a> +<p>Usually a two-operand-expression (see <a href="#GREG_002dbase">GREG-base</a>) without a matching +‘<samp>GREG</samp>’ directive is treated as an error by <code>as</code>. When +the option ‘<samp>--linker-allocated-gregs</samp>’ is in effect, they are instead +passed through to the linker, which will allocate as many global registers +as is needed. +</p> +<hr> +<a name="MMIX_002dExpand"></a> +<div class="header"> +<p> +Next: <a href="#MMIX_002dSyntax" accesskey="n" rel="next">MMIX-Syntax</a>, Previous: <a href="#MMIX_002dOpts" accesskey="p" rel="previous">MMIX-Opts</a>, Up: <a href="#MMIX_002dDependent" accesskey="u" rel="up">MMIX-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-expansion-1"></a> +<h4 class="subsection">9.28.2 Instruction expansion</h4> + +<a name="index-instruction-expansion_002c-MMIX"></a> +<p>When <code>as</code> encounters an instruction with an operand that is +either not known or does not fit the operand size of the instruction, +<code>as</code> (and <code>ld</code>) will expand the instruction into +a sequence of instructions semantically equivalent to the operand fitting +the instruction. Expansion will take place for the following +instructions: +</p> +<dl compact="compact"> +<dt>‘<samp>GETA</samp>’</dt> +<dd><p>Expands to a sequence of four instructions: <code>SETL</code>, <code>INCML</code>, +<code>INCMH</code> and <code>INCH</code>. The operand must be a multiple of four. +</p></dd> +<dt>Conditional branches</dt> +<dd><p>A branch instruction is turned into a branch with the complemented +condition and prediction bit over five instructions; four instructions +setting <code>$255</code> to the operand value, which like with <code>GETA</code> must +be a multiple of four, and a final <code>GO $255,$255,0</code>. +</p></dd> +<dt>‘<samp>PUSHJ</samp>’</dt> +<dd><p>Similar to expansion for conditional branches; four instructions set +<code>$255</code> to the operand value, followed by a <code>PUSHGO $255,$255,0</code>. +</p></dd> +<dt>‘<samp>JMP</samp>’</dt> +<dd><p>Similar to conditional branches and <code>PUSHJ</code>. The final instruction +is <code>GO $255,$255,0</code>. +</p></dd> +</dl> + +<p>The linker <code>ld</code> is expected to shrink these expansions for +code assembled with ‘<samp>--relax</samp>’ (though not currently implemented). +</p> +<hr> +<a name="MMIX_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#MMIX_002dmmixal" accesskey="n" rel="next">MMIX-mmixal</a>, Previous: <a href="#MMIX_002dExpand" accesskey="p" rel="previous">MMIX-Expand</a>, Up: <a href="#MMIX_002dDependent" accesskey="u" rel="up">MMIX-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-21"></a> +<h4 class="subsection">9.28.3 Syntax</h4> + +<p>The assembly syntax is supposed to be upward compatible with that +described in Sections 1.3 and 1.4 of ‘<samp>The Art of Computer +Programming, Volume 1</samp>’. Draft versions of those chapters as well as other +MMIX information is located at +<a name="mmixsite"></a><a href="http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html">http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html</a>. +Most code examples from the mmixal package located there should work +unmodified when assembled and linked as single files, with a few +noteworthy exceptions (see <a href="#MMIX_002dmmixal">MMIX-mmixal</a>). +</p> +<p>Before an instruction is emitted, the current location is aligned to the +next four-byte boundary. If a label is defined at the beginning of the +line, its value will be the aligned value. +</p> +<p>In addition to the traditional hex-prefix ‘<samp>0x</samp>’, a hexadecimal number +can also be specified by the prefix character ‘<samp>#</samp>’. +</p> +<p>After all operands to an MMIX instruction or directive have been +specified, the rest of the line is ignored, treated as a comment. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#MMIX_002dChars" accesskey="1">MMIX-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#MMIX_002dSymbols" accesskey="2">MMIX-Symbols</a>:</td><td> </td><td align="left" valign="top">Symbols +</td></tr> +<tr><td align="left" valign="top">• <a href="#MMIX_002dRegs" accesskey="3">MMIX-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#MMIX_002dPseudos" accesskey="4">MMIX-Pseudos</a>:</td><td> </td><td align="left" valign="top">Assembler Directives +</td></tr> +</table> + +<hr> +<a name="MMIX_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#MMIX_002dSymbols" accesskey="n" rel="next">MMIX-Symbols</a>, Up: <a href="#MMIX_002dSyntax" accesskey="u" rel="up">MMIX-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-21"></a> +<h4 class="subsubsection">9.28.3.1 Special Characters</h4> +<a name="index-line-comment-characters_002c-MMIX"></a> +<a name="index-MMIX-line-comment-characters"></a> + +<p>The characters ‘<samp>*</samp>’ and ‘<samp>#</samp>’ are line comment characters; each +start a comment at the beginning of a line, but only at the beginning of a +line. A ‘<samp>#</samp>’ prefixes a hexadecimal number if found elsewhere on a +line. If a ‘<samp>#</samp>’ appears at the start of a line the whole line is +treated as a comment, but the line can also act as a logical line +number directive (see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +<p>Two other characters, ‘<samp>%</samp>’ and ‘<samp>!</samp>’, each start a comment anywhere +on the line. Thus you can’t use the ‘<samp>modulus</samp>’ and ‘<samp>not</samp>’ +operators in expressions normally associated with these two characters. +</p> +<p>A ‘<samp>;</samp>’ is a line separator, treated as a new-line, so separate +instructions can be specified on a single line. +</p> +<hr> +<a name="MMIX_002dSymbols"></a> +<div class="header"> +<p> +Next: <a href="#MMIX_002dRegs" accesskey="n" rel="next">MMIX-Regs</a>, Previous: <a href="#MMIX_002dChars" accesskey="p" rel="previous">MMIX-Chars</a>, Up: <a href="#MMIX_002dSyntax" accesskey="u" rel="up">MMIX-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbols-4"></a> +<h4 class="subsubsection">9.28.3.2 Symbols</h4> +<p>The character ‘<samp>:</samp>’ is permitted in identifiers. There are two +exceptions to it being treated as any other symbol character: if a symbol +begins with ‘<samp>:</samp>’, it means that the symbol is in the global namespace +and that the current prefix should not be prepended to that symbol +(see <a href="#MMIX_002dprefix">MMIX-prefix</a>). The ‘<samp>:</samp>’ is then not considered part of the +symbol. For a symbol in the label position (first on a line), a ‘<samp>:</samp>’ +at the end of a symbol is silently stripped off. A label is permitted, +but not required, to be followed by a ‘<samp>:</samp>’, as with many other +assembly formats. +</p> +<p>The character ‘<samp>@</samp>’ in an expression, is a synonym for ‘<samp>.</samp>’, the +current location. +</p> +<p>In addition to the common forward and backward local symbol formats +(see <a href="#Symbol-Names">Symbol Names</a>), they can be specified with upper-case ‘<samp>B</samp>’ and +‘<samp>F</samp>’, as in ‘<samp>8B</samp>’ and ‘<samp>9F</samp>’. A local label defined for the +current position is written with a ‘<samp>H</samp>’ appended to the number: +</p><div class="smallexample"> +<pre class="smallexample">3H LDB $0,$1,2 +</pre></div> +<p>This and traditional local-label formats cannot be mixed: a label must be +defined and referred to using the same format. +</p> +<p>There’s a minor caveat: just as for the ordinary local symbols, the local +symbols are translated into ordinary symbols using control characters are +to hide the ordinal number of the symbol. Unfortunately, these symbols +are not translated back in error messages. Thus you may see confusing +error messages when local symbols are used. Control characters +‘<samp>\003</samp>’ (control-C) and ‘<samp>\004</samp>’ (control-D) are used for the +MMIX-specific local-symbol syntax. +</p> +<p>The symbol ‘<samp>Main</samp>’ is handled specially; it is always global. +</p> +<p>By defining the symbols ‘<samp>__.MMIX.start..text</samp>’ and +‘<samp>__.MMIX.start..data</samp>’, the address of respectively the ‘<samp>.text</samp>’ +and ‘<samp>.data</samp>’ segments of the final program can be defined, though when +linking more than one object file, the code or data in the object file +containing the symbol is not guaranteed to be start at that position; just +the final executable. See <a href="#MMIX_002dloc">MMIX-loc</a>. +</p> +<hr> +<a name="MMIX_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#MMIX_002dPseudos" accesskey="n" rel="next">MMIX-Pseudos</a>, Previous: <a href="#MMIX_002dSymbols" accesskey="p" rel="previous">MMIX-Symbols</a>, Up: <a href="#MMIX_002dSyntax" accesskey="u" rel="up">MMIX-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-names-1"></a> +<h4 class="subsubsection">9.28.3.3 Register names</h4> +<a name="index-register-names_002c-MMIX"></a> +<a name="index-MMIX-register-names"></a> + +<p>Local and global registers are specified as ‘<samp>$0</samp>’ to ‘<samp>$255</samp>’. +The recognized special register names are ‘<samp>rJ</samp>’, ‘<samp>rA</samp>’, ‘<samp>rB</samp>’, +‘<samp>rC</samp>’, ‘<samp>rD</samp>’, ‘<samp>rE</samp>’, ‘<samp>rF</samp>’, ‘<samp>rG</samp>’, ‘<samp>rH</samp>’, +‘<samp>rI</samp>’, ‘<samp>rK</samp>’, ‘<samp>rL</samp>’, ‘<samp>rM</samp>’, ‘<samp>rN</samp>’, ‘<samp>rO</samp>’, +‘<samp>rP</samp>’, ‘<samp>rQ</samp>’, ‘<samp>rR</samp>’, ‘<samp>rS</samp>’, ‘<samp>rT</samp>’, ‘<samp>rU</samp>’, +‘<samp>rV</samp>’, ‘<samp>rW</samp>’, ‘<samp>rX</samp>’, ‘<samp>rY</samp>’, ‘<samp>rZ</samp>’, ‘<samp>rBB</samp>’, +‘<samp>rTT</samp>’, ‘<samp>rWW</samp>’, ‘<samp>rXX</samp>’, ‘<samp>rYY</samp>’ and ‘<samp>rZZ</samp>’. A leading +‘<samp>:</samp>’ is optional for special register names. +</p> +<p>Local and global symbols can be equated to register names and used in +place of ordinary registers. +</p> +<p>Similarly for special registers, local and global symbols can be used. +Also, symbols equated from numbers and constant expressions are allowed in +place of a special register, except when either of the options +<code>--no-predefined-syms</code> and <code>--fixed-special-register-names</code> are +specified. Then only the special register names above are allowed for the +instructions having a special register operand; <code>GET</code> and <code>PUT</code>. +</p> +<hr> +<a name="MMIX_002dPseudos"></a> +<div class="header"> +<p> +Previous: <a href="#MMIX_002dRegs" accesskey="p" rel="previous">MMIX-Regs</a>, Up: <a href="#MMIX_002dSyntax" accesskey="u" rel="up">MMIX-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives-3"></a> +<h4 class="subsubsection">9.28.3.4 Assembler Directives</h4> +<a name="index-assembler-directives_002c-MMIX"></a> +<a name="index-pseudo_002dops_002c-MMIX"></a> +<a name="index-MMIX-assembler-directives"></a> +<a name="index-MMIX-pseudo_002dops"></a> + +<dl compact="compact"> +<dt><code>LOC</code></dt> +<dd><a name="index-assembler-directive-LOC_002c-MMIX"></a> +<a name="index-pseudo_002dop-LOC_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-LOC"></a> +<a name="index-MMIX-pseudo_002dop-LOC"></a> + +<a name="MMIX_002dloc"></a><p>The <code>LOC</code> directive sets the current location to the value of the +operand field, which may include changing sections. If the operand is a +constant, the section is set to either <code>.data</code> if the value is +<code>0x2000000000000000</code> or larger, else it is set to <code>.text</code>. +Within a section, the current location may only be changed to +monotonically higher addresses. A LOC expression must be a previously +defined symbol or a “pure” constant. +</p> +<p>An example, which sets the label <var>prev</var> to the current location, and +updates the current location to eight bytes forward: +</p><div class="smallexample"> +<pre class="smallexample">prev LOC @+8 +</pre></div> + +<p>When a LOC has a constant as its operand, a symbol +<code>__.MMIX.start..text</code> or <code>__.MMIX.start..data</code> is defined +depending on the address as mentioned above. Each such symbol is +interpreted as special by the linker, locating the section at that +address. Note that if multiple files are linked, the first object file +with that section will be mapped to that address (not necessarily the file +with the LOC definition). +</p> +</dd> +<dt><code>LOCAL</code></dt> +<dd><a name="index-assembler-directive-LOCAL_002c-MMIX"></a> +<a name="index-pseudo_002dop-LOCAL_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-LOCAL"></a> +<a name="index-MMIX-pseudo_002dop-LOCAL"></a> + +<a name="MMIX_002dlocal"></a><p>Example: +</p><div class="smallexample"> +<pre class="smallexample"> LOCAL external_symbol + LOCAL 42 + .local asymbol +</pre></div> + +<p>This directive-operation generates a link-time assertion that the operand +does not correspond to a global register. The operand is an expression +that at link-time resolves to a register symbol or a number. A number is +treated as the register having that number. There is one restriction on +the use of this directive: the pseudo-directive must be placed in a +section with contents, code or data. +</p> +</dd> +<dt><code>IS</code></dt> +<dd><a name="index-assembler-directive-IS_002c-MMIX"></a> +<a name="index-pseudo_002dop-IS_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-IS"></a> +<a name="index-MMIX-pseudo_002dop-IS"></a> + +<a name="MMIX_002dis"></a><p>The <code>IS</code> directive: +</p><div class="smallexample"> +<pre class="smallexample">asymbol IS an_expression +</pre></div> +<p>sets the symbol ‘<samp>asymbol</samp>’ to ‘<samp>an_expression</samp>’. A symbol may not +be set more than once using this directive. Local labels may be set using +this directive, for example: +</p><div class="smallexample"> +<pre class="smallexample">5H IS @+4 +</pre></div> + +</dd> +<dt><code>GREG</code></dt> +<dd><a name="index-assembler-directive-GREG_002c-MMIX"></a> +<a name="index-pseudo_002dop-GREG_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-GREG"></a> +<a name="index-MMIX-pseudo_002dop-GREG"></a> + +<a name="MMIX_002dgreg"></a><p>This directive reserves a global register, gives it an initial value and +optionally gives it a symbolic name. Some examples: +</p> +<div class="smallexample"> +<pre class="smallexample">areg GREG +breg GREG data_value + GREG data_buffer + .greg creg, another_data_value +</pre></div> + +<p>The symbolic register name can be used in place of a (non-special) +register. If a value isn’t provided, it defaults to zero. Unless the +option ‘<samp>--no-merge-gregs</samp>’ is specified, non-zero registers allocated +with this directive may be eliminated by <code>as</code>; another +register with the same value used in its place. +Any of the instructions +‘<samp>CSWAP</samp>’, +‘<samp>GO</samp>’, +‘<samp>LDA</samp>’, +‘<samp>LDBU</samp>’, +‘<samp>LDB</samp>’, +‘<samp>LDHT</samp>’, +‘<samp>LDOU</samp>’, +‘<samp>LDO</samp>’, +‘<samp>LDSF</samp>’, +‘<samp>LDTU</samp>’, +‘<samp>LDT</samp>’, +‘<samp>LDUNC</samp>’, +‘<samp>LDVTS</samp>’, +‘<samp>LDWU</samp>’, +‘<samp>LDW</samp>’, +‘<samp>PREGO</samp>’, +‘<samp>PRELD</samp>’, +‘<samp>PREST</samp>’, +‘<samp>PUSHGO</samp>’, +‘<samp>STBU</samp>’, +‘<samp>STB</samp>’, +‘<samp>STCO</samp>’, +‘<samp>STHT</samp>’, +‘<samp>STOU</samp>’, +‘<samp>STSF</samp>’, +‘<samp>STTU</samp>’, +‘<samp>STT</samp>’, +‘<samp>STUNC</samp>’, +‘<samp>SYNCD</samp>’, +‘<samp>SYNCID</samp>’, +can have a value nearby <a name="GREG_002dbase"></a>an initial value in place of its +second and third operands. Here, “nearby” is defined as within the +range 0…255 from the initial value of such an allocated register. +</p> +<div class="smallexample"> +<pre class="smallexample">buffer1 BYTE 0,0,0,0,0 +buffer2 BYTE 0,0,0,0,0 + … + GREG buffer1 + LDOU $42,buffer2 +</pre></div> +<p>In the example above, the ‘<samp>Y</samp>’ field of the <code>LDOUI</code> instruction +(LDOU with a constant Z) will be replaced with the global register +allocated for ‘<samp>buffer1</samp>’, and the ‘<samp>Z</samp>’ field will have the value +5, the offset from ‘<samp>buffer1</samp>’ to ‘<samp>buffer2</samp>’. The result is +equivalent to this code: +</p><div class="smallexample"> +<pre class="smallexample">buffer1 BYTE 0,0,0,0,0 +buffer2 BYTE 0,0,0,0,0 + … +tmpreg GREG buffer1 + LDOU $42,tmpreg,(buffer2-buffer1) +</pre></div> + +<p>Global registers allocated with this directive are allocated in order +higher-to-lower within a file. Other than that, the exact order of +register allocation and elimination is undefined. For example, the order +is undefined when more than one file with such directives are linked +together. With the options ‘<samp>-x</samp>’ and ‘<samp>--linker-allocated-gregs</samp>’, +‘<samp>GREG</samp>’ directives for two-operand cases like the one mentioned above +can be omitted. Sufficient global registers will then be allocated by the +linker. +</p> +</dd> +<dt><code>BYTE</code></dt> +<dd><a name="index-assembler-directive-BYTE_002c-MMIX"></a> +<a name="index-pseudo_002dop-BYTE_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-BYTE"></a> +<a name="index-MMIX-pseudo_002dop-BYTE"></a> + +<a name="MMIX_002dbyte"></a><p>The ‘<samp>BYTE</samp>’ directive takes a series of operands separated by a comma. +If an operand is a string (see <a href="#Strings">Strings</a>), each character of that string +is emitted as a byte. Other operands must be constant expressions without +forward references, in the range 0…255. If you need operands having +expressions with forward references, use ‘<samp>.byte</samp>’ (see <a href="#Byte">Byte</a>). An +operand can be omitted, defaulting to a zero value. +</p> +</dd> +<dt><code>WYDE</code></dt> +<dt><code>TETRA</code></dt> +<dt><code>OCTA</code></dt> +<dd><a name="index-assembler-directive-WYDE_002c-MMIX"></a> +<a name="index-pseudo_002dop-WYDE_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-WYDE"></a> +<a name="index-MMIX-pseudo_002dop-WYDE"></a> +<a name="index-assembler-directive-TETRA_002c-MMIX"></a> +<a name="index-pseudo_002dop-TETRA_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-TETRA"></a> +<a name="index-MMIX-pseudo_002dop-TETRA"></a> +<a name="index-assembler-directive-OCTA_002c-MMIX"></a> +<a name="index-pseudo_002dop-OCTA_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-OCTA"></a> +<a name="index-MMIX-pseudo_002dop-OCTA"></a> + +<a name="MMIX_002dconstants"></a><p>The directives ‘<samp>WYDE</samp>’, ‘<samp>TETRA</samp>’ and ‘<samp>OCTA</samp>’ emit constants of +two, four and eight bytes size respectively. Before anything else happens +for the directive, the current location is aligned to the respective +constant-size boundary. If a label is defined at the beginning of the +line, its value will be that after the alignment. A single operand can be +omitted, defaulting to a zero value emitted for the directive. Operands +can be expressed as strings (see <a href="#Strings">Strings</a>), in which case each +character in the string is emitted as a separate constant of the size +indicated by the directive. +</p> +</dd> +<dt><code>PREFIX</code></dt> +<dd><a name="index-assembler-directive-PREFIX_002c-MMIX"></a> +<a name="index-pseudo_002dop-PREFIX_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-PREFIX"></a> +<a name="index-MMIX-pseudo_002dop-PREFIX"></a> + +<a name="MMIX_002dprefix"></a><p>The ‘<samp>PREFIX</samp>’ directive sets a symbol name prefix to be prepended to +all symbols (except local symbols, see <a href="#MMIX_002dSymbols">MMIX-Symbols</a>), that are not +prefixed with ‘<samp>:</samp>’, until the next ‘<samp>PREFIX</samp>’ directive. Such +prefixes accumulate. For example, +</p><div class="smallexample"> +<pre class="smallexample"> PREFIX a + PREFIX b +c IS 0 +</pre></div> +<p>defines a symbol ‘<samp>abc</samp>’ with the value 0. +</p> +</dd> +<dt><code>BSPEC</code></dt> +<dt><code>ESPEC</code></dt> +<dd><a name="index-assembler-directive-BSPEC_002c-MMIX"></a> +<a name="index-pseudo_002dop-BSPEC_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-BSPEC"></a> +<a name="index-MMIX-pseudo_002dop-BSPEC"></a> +<a name="index-assembler-directive-ESPEC_002c-MMIX"></a> +<a name="index-pseudo_002dop-ESPEC_002c-MMIX"></a> +<a name="index-MMIX-assembler-directive-ESPEC"></a> +<a name="index-MMIX-pseudo_002dop-ESPEC"></a> + +<a name="MMIX_002dspec"></a><p>A pair of ‘<samp>BSPEC</samp>’ and ‘<samp>ESPEC</samp>’ directives delimit a section of +special contents (without specified semantics). Example: +</p><div class="smallexample"> +<pre class="smallexample"> BSPEC 42 + TETRA 1,2,3 + ESPEC +</pre></div> +<p>The single operand to ‘<samp>BSPEC</samp>’ must be number in the range +0…255. The ‘<samp>BSPEC</samp>’ number 80 is used by the GNU binutils +implementation. +</p></dd> +</dl> + +<hr> +<a name="MMIX_002dmmixal"></a> +<div class="header"> +<p> +Previous: <a href="#MMIX_002dSyntax" accesskey="p" rel="previous">MMIX-Syntax</a>, Up: <a href="#MMIX_002dDependent" accesskey="u" rel="up">MMIX-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Differences-to-mmixal"></a> +<h4 class="subsection">9.28.4 Differences to <code>mmixal</code></h4> +<a name="index-mmixal-differences"></a> +<a name="index-differences_002c-mmixal"></a> + +<p>The binutils <code>as</code> and <code>ld</code> combination has a few +differences in function compared to <code>mmixal</code> (see <a href="#mmixsite">mmixsite</a>). +</p> +<p>The replacement of a symbol with a GREG-allocated register +(see <a href="#GREG_002dbase">GREG-base</a>) is not handled the exactly same way in +<code>as</code> as in <code>mmixal</code>. This is apparent in the +<code>mmixal</code> example file <code>inout.mms</code>, where different registers +with different offsets, eventually yielding the same address, are used in +the first instruction. This type of difference should however not affect +the function of any program unless it has specific assumptions about the +allocated register number. +</p> +<p>Line numbers (in the ‘<samp>mmo</samp>’ object format) are currently not +supported. +</p> +<p>Expression operator precedence is not that of mmixal: operator precedence +is that of the C programming language. It’s recommended to use +parentheses to explicitly specify wanted operator precedence whenever more +than one type of operators are used. +</p> +<p>The serialize unary operator <code>&</code>, the fractional division operator +‘<samp>//</samp>’, the logical not operator <code>!</code> and the modulus operator +‘<samp>%</samp>’ are not available. +</p> +<p>Symbols are not global by default, unless the option +‘<samp>--globalize-symbols</samp>’ is passed. Use the ‘<samp>.global</samp>’ directive to +globalize symbols (see <a href="#Global">Global</a>). +</p> +<p>Operand syntax is a bit stricter with <code>as</code> than +<code>mmixal</code>. For example, you can’t say <code>addu 1,2,3</code>, instead you +must write <code>addu $1,$2,3</code>. +</p> +<p>You can’t LOC to a lower address than those already visited +(i.e., “backwards”). +</p> +<p>A LOC directive must come before any emitted code. +</p> +<p>Predefined symbols are visible as file-local symbols after use. (In the +ELF file, that is—the linked mmo file has no notion of a file-local +symbol.) +</p> +<p>Some mapping of constant expressions to sections in LOC expressions is +attempted, but that functionality is easily confused and should be avoided +unless compatibility with <code>mmixal</code> is required. A LOC expression to +‘<samp>0x2000000000000000</samp>’ or higher, maps to the ‘<samp>.data</samp>’ section and +lower addresses map to the ‘<samp>.text</samp>’ section (see <a href="#MMIX_002dloc">MMIX-loc</a>). +</p> +<p>The code and data areas are each contiguous. Sparse programs with +far-away LOC directives will take up the same amount of space as a +contiguous program with zeros filled in the gaps between the LOC +directives. If you need sparse programs, you might try and get the wanted +effect with a linker script and splitting up the code parts into sections +(see <a href="#Section">Section</a>). Assembly code for this, to be compatible with +<code>mmixal</code>, would look something like: +</p><div class="smallexample"> +<pre class="smallexample"> .if 0 + LOC away_expression + .else + .section away,"ax" + .fi +</pre></div> +<p><code>as</code> will not execute the LOC directive and <code>mmixal</code> +ignores the lines with <code>.</code>. This construct can be used generally to +help compatibility. +</p> +<p>Symbols can’t be defined twice–not even to the same value. +</p> +<p>Instruction mnemonics are recognized case-insensitive, though the +‘<samp>IS</samp>’ and ‘<samp>GREG</samp>’ pseudo-operations must be specified in +upper-case characters. +</p> +<p>There’s no unicode support. +</p> +<p>The following is a list of programs in ‘<samp>mmix.tar.gz</samp>’, available at +<a href="http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html">http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html</a>, last +checked with the version dated 2001-08-25 (md5sum +c393470cfc86fac040487d22d2bf0172) that assemble with <code>mmixal</code> but do +not assemble with <code>as</code>: +</p> +<dl compact="compact"> +<dt><code>silly.mms</code></dt> +<dd><p>LOC to a previous address. +</p></dd> +<dt><code>sim.mms</code></dt> +<dd><p>Redefines symbol ‘<samp>Done</samp>’. +</p></dd> +<dt><code>test.mms</code></dt> +<dd><p>Uses the serial operator ‘<samp>&</samp>’. +</p></dd> +</dl> + +<hr> +<a name="MSP430_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#NDS32_002dDependent" accesskey="n" rel="next">NDS32-Dependent</a>, Previous: <a href="#MMIX_002dDependent" accesskey="p" rel="previous">MMIX-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="MSP-430-Dependent-Features"></a> +<h3 class="section">9.29 MSP 430 Dependent Features</h3> + +<a name="index-MSP-430-support"></a> +<a name="index-430-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#MSP430-Options" accesskey="1">MSP430 Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#MSP430-Syntax" accesskey="2">MSP430 Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#MSP430-Floating-Point" accesskey="3">MSP430 Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#MSP430-Directives" accesskey="4">MSP430 Directives</a>:</td><td> </td><td align="left" valign="top">MSP 430 Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#MSP430-Opcodes" accesskey="5">MSP430 Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +<tr><td align="left" valign="top">• <a href="#MSP430-Profiling-Capability" accesskey="6">MSP430 Profiling Capability</a>:</td><td> </td><td align="left" valign="top">Profiling Capability +</td></tr> +</table> + +<hr> +<a name="MSP430-Options"></a> +<div class="header"> +<p> +Next: <a href="#MSP430-Syntax" accesskey="n" rel="next">MSP430 Syntax</a>, Up: <a href="#MSP430_002dDependent" accesskey="u" rel="up">MSP430-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-15"></a> +<h4 class="subsection">9.29.1 Options</h4> +<a name="index-MSP-430-options-_0028none_0029"></a> +<a name="index-options-for-MSP430-_0028none_0029"></a> +<dl compact="compact"> +<dt><code>-mmcu</code></dt> +<dd><p>selects the mcu architecture. If the architecture is 430Xv2 then this +also enables NOP generation unless the <samp>-mN</samp> is also specified. +</p> +</dd> +<dt><code>-mcpu</code></dt> +<dd><p>selects the cpu architecture. If the architecture is 430Xv2 then this +also enables NOP generation unless the <samp>-mN</samp> is also specified. +</p> +</dd> +<dt><code>-msilicon-errata=<var>name</var>[,<var>name</var>…]</code></dt> +<dd><p>Implements a fixup for named silicon errata. Multiple silicon errata +can be specified by multiple uses of the <samp>-msilicon-errata</samp> +option and/or by including the errata names, separated by commas, on +an individual <samp>-msilicon-errata</samp> option. Errata names +currently recognised by the assembler are: +</p> +<dl compact="compact"> +<dt><code>cpu4</code></dt> +<dd><p><code>PUSH #4</code> and <samp>PUSH #8</samp> need longer encodings on the +MSP430. This option is enabled by default, and cannot be disabled. +</p></dd> +<dt><code>cpu8</code></dt> +<dd><p>Do not set the <code>SP</code> to an odd value. +</p></dd> +<dt><code>cpu11</code></dt> +<dd><p>Do not update the <code>SR</code> and the <code>PC</code> in the same instruction. +</p></dd> +<dt><code>cpu12</code></dt> +<dd><p>Do not use the <code>PC</code> in a <code>CMP</code> or <code>BIT</code> instruction. +</p></dd> +<dt><code>cpu13</code></dt> +<dd><p>Do not use an arithmetic instruction to modify the <code>SR</code>. +</p></dd> +<dt><code>cpu19</code></dt> +<dd><p>Insert <code>NOP</code> after <code>CPUOFF</code>. +</p></dd> +</dl> + +</dd> +<dt><code>-msilicon-errata-warn=<var>name</var>[,<var>name</var>…]</code></dt> +<dd><p>Like the <samp>-msilicon-errata</samp> option except that instead of +fixing the specified errata, a warning message is issued instead. +This option can be used alongside <samp>-msilicon-errata</samp> to +generate messages whenever a problem is fixed, or on its own in order +to inspect code for potential problems. +</p> +</dd> +<dt><code>-mP</code></dt> +<dd><p>enables polymorph instructions handler. +</p> +</dd> +<dt><code>-mQ</code></dt> +<dd><p>enables relaxation at assembly time. DANGEROUS! +</p> +</dd> +<dt><code>-ml</code></dt> +<dd><p>indicates that the input uses the large code model. +</p> +</dd> +<dt><code>-mn</code></dt> +<dd><p>enables the generation of a NOP instruction following any instruction +that might change the interrupts enabled/disabled state. The +pipelined nature of the MSP430 core means that any instruction that +changes the interrupt state (<code>EINT</code>, <code>DINT</code>, <code>BIC #8, +SR</code>, <code>BIS #8, SR</code> or <code>MOV.W <>, SR</code>) must be +followed by a NOP instruction in order to ensure the correct +processing of interrupts. By default it is up to the programmer to +supply these NOP instructions, but this command-line option enables +the automatic insertion by the assembler, if they are missing. +</p> +</dd> +<dt><code>-mN</code></dt> +<dd><p>disables the generation of a NOP instruction following any instruction +that might change the interrupts enabled/disabled state. This is the +default behaviour. +</p> +</dd> +<dt><code>-my</code></dt> +<dd><p>tells the assembler to generate a warning message if a NOP does not +immediately follow an instruction that enables or disables +interrupts. This is the default. +</p> +<p>Note that this option can be stacked with the <samp>-mn</samp> option so +that the assembler will both warn about missing NOP instructions and +then insert them automatically. +</p> +</dd> +<dt><code>-mY</code></dt> +<dd><p>disables warnings about missing NOP instructions. +</p> +</dd> +<dt><code>-md</code></dt> +<dd><p>mark the object file as one that requires data to copied from ROM to +RAM at execution startup. Disabled by default. +</p> +</dd> +<dt><code>-mdata-region=<var>region</var></code></dt> +<dd><p>Select the region data will be placed in. +Region placement is performed by the compiler and linker. The only effect this +option will have on the assembler is that if <var>upper</var> or <var>either</var> is +selected, then the symbols to initialise high data and bss will be defined. +Valid <var>region</var> values are: +</p><dl compact="compact"> +<dt><code>none</code></dt> +<dt><code>lower</code></dt> +<dt><code>upper</code></dt> +<dt><code>either</code></dt> +</dl> + +</dd> +</dl> + +<hr> +<a name="MSP430-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#MSP430-Floating-Point" accesskey="n" rel="next">MSP430 Floating Point</a>, Previous: <a href="#MSP430-Options" accesskey="p" rel="previous">MSP430 Options</a>, Up: <a href="#MSP430_002dDependent" accesskey="u" rel="up">MSP430-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-22"></a> +<h4 class="subsection">9.29.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#MSP430_002dMacros" accesskey="1">MSP430-Macros</a>:</td><td> </td><td align="left" valign="top">Macros +</td></tr> +<tr><td align="left" valign="top">• <a href="#MSP430_002dChars" accesskey="2">MSP430-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#MSP430_002dRegs" accesskey="3">MSP430-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#MSP430_002dExt" accesskey="4">MSP430-Ext</a>:</td><td> </td><td align="left" valign="top">Assembler Extensions +</td></tr> +</table> + +<hr> +<a name="MSP430_002dMacros"></a> +<div class="header"> +<p> +Next: <a href="#MSP430_002dChars" accesskey="n" rel="next">MSP430-Chars</a>, Up: <a href="#MSP430-Syntax" accesskey="u" rel="up">MSP430 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Macros"></a> +<h4 class="subsubsection">9.29.2.1 Macros</h4> + +<a name="index-Macros_002c-MSP-430"></a> +<a name="index-MSP-430-macros"></a> +<p>The macro syntax used on the MSP 430 is like that described in the MSP +430 Family Assembler Specification. Normal <code>as</code> +macros should still work. +</p> +<p>Additional built-in macros are: +</p> +<dl compact="compact"> +<dt><code>llo(exp)</code></dt> +<dd><p>Extracts least significant word from 32-bit expression ’exp’. +</p> +</dd> +<dt><code>lhi(exp)</code></dt> +<dd><p>Extracts most significant word from 32-bit expression ’exp’. +</p> +</dd> +<dt><code>hlo(exp)</code></dt> +<dd><p>Extracts 3rd word from 64-bit expression ’exp’. +</p> +</dd> +<dt><code>hhi(exp)</code></dt> +<dd><p>Extracts 4rd word from 64-bit expression ’exp’. +</p> +</dd> +</dl> + +<p>They normally being used as an immediate source operand. +</p><div class="smallexample"> +<pre class="smallexample"> mov #llo(1), r10 ; == mov #1, r10 + mov #lhi(1), r10 ; == mov #0, r10 +</pre></div> + +<hr> +<a name="MSP430_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#MSP430_002dRegs" accesskey="n" rel="next">MSP430-Regs</a>, Previous: <a href="#MSP430_002dMacros" accesskey="p" rel="previous">MSP430-Macros</a>, Up: <a href="#MSP430-Syntax" accesskey="u" rel="up">MSP430 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-22"></a> +<h4 class="subsubsection">9.29.2.2 Special Characters</h4> + +<a name="index-line-comment-character_002c-MSP-430"></a> +<a name="index-MSP-430-line-comment-character"></a> +<p>A semicolon (‘<samp>;</samp>’) appearing anywhere on a line starts a comment +that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but it can also be a logical line number +directive (see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-MSP-430"></a> +<a name="index-statement-separator_002c-MSP-430"></a> +<a name="index-MSP-430-line-separator"></a> +<p>Multiple statements can appear on the same line provided that they are +separated by the ‘<samp>{</samp>’ character. +</p> +<a name="index-identifiers_002c-MSP-430"></a> +<a name="index-MSP-430-identifiers"></a> +<p>The character ‘<samp>$</samp>’ in jump instructions indicates current location and +implemented only for TI syntax compatibility. +</p> +<hr> +<a name="MSP430_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#MSP430_002dExt" accesskey="n" rel="next">MSP430-Ext</a>, Previous: <a href="#MSP430_002dChars" accesskey="p" rel="previous">MSP430-Chars</a>, Up: <a href="#MSP430-Syntax" accesskey="u" rel="up">MSP430 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-12"></a> +<h4 class="subsubsection">9.29.2.3 Register Names</h4> + +<a name="index-MSP-430-register-names"></a> +<a name="index-register-names_002c-MSP-430"></a> +<p>General-purpose registers are represented by predefined symbols of the +form ‘<samp>r<var>N</var></samp>’ (for global registers), where <var>N</var> represents +a number between <code>0</code> and <code>15</code>. The leading +letters may be in either upper or lower case; for example, ‘<samp>r13</samp>’ +and ‘<samp>R7</samp>’ are both valid register names. +</p> +<a name="index-special-purpose-registers_002c-MSP-430"></a> +<p>Register names ‘<samp>PC</samp>’, ‘<samp>SP</samp>’ and ‘<samp>SR</samp>’ cannot be used as register names +and will be treated as variables. Use ‘<samp>r0</samp>’, ‘<samp>r1</samp>’, and ‘<samp>r2</samp>’ instead. +</p> + +<hr> +<a name="MSP430_002dExt"></a> +<div class="header"> +<p> +Previous: <a href="#MSP430_002dRegs" accesskey="p" rel="previous">MSP430-Regs</a>, Up: <a href="#MSP430-Syntax" accesskey="u" rel="up">MSP430 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Extensions"></a> +<h4 class="subsubsection">9.29.2.4 Assembler Extensions</h4> +<a name="index-MSP430-Assembler-Extensions"></a> + +<dl compact="compact"> +<dt><code>@rN</code></dt> +<dd><p>As destination operand being treated as ‘<samp>0(rn)</samp>’ +</p> +</dd> +<dt><code>0(rN)</code></dt> +<dd><p>As source operand being treated as ‘<samp>@rn</samp>’ +</p> +</dd> +<dt><code>jCOND +N</code></dt> +<dd><p>Skips next N bytes followed by jump instruction and equivalent to +‘<samp>jCOND $+N+2</samp>’ +</p> +</dd> +</dl> + +<p>Also, there are some instructions, which cannot be found in other assemblers. +These are branch instructions, which has different opcodes upon jump distance. +They all got PC relative addressing mode. +</p> +<dl compact="compact"> +<dt><code>beq label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jeq label</samp>’ in case if jump distance +within allowed range for cpu’s jump instruction. If not, this unrolls into +a sequence of +</p><div class="smallexample"> +<pre class="smallexample"> jne $+6 + br label +</pre></div> + +</dd> +<dt><code>bne label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jne label</samp>’ or ‘<samp>jeq +4; br label</samp>’ +</p> +</dd> +<dt><code>blt label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jl label</samp>’ or ‘<samp>jge +4; br label</samp>’ +</p> +</dd> +<dt><code>bltn label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jn label</samp>’ or ‘<samp>jn +2; jmp +4; br label</samp>’ +</p> +</dd> +<dt><code>bltu label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jlo label</samp>’ or ‘<samp>jhs +2; br label</samp>’ +</p> +</dd> +<dt><code>bge label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jge label</samp>’ or ‘<samp>jl +4; br label</samp>’ +</p> +</dd> +<dt><code>bgeu label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jhs label</samp>’ or ‘<samp>jlo +4; br label</samp>’ +</p> +</dd> +<dt><code>bgt label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jeq +2; jge label</samp>’ or ‘<samp>jeq +6; jl +4; br label</samp>’ +</p> +</dd> +<dt><code>bgtu label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jeq +2; jhs label</samp>’ or ‘<samp>jeq +6; jlo +4; br label</samp>’ +</p> +</dd> +<dt><code>bleu label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jeq label; jlo label</samp>’ or ‘<samp>jeq +2; jhs +4; br label</samp>’ +</p> +</dd> +<dt><code>ble label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jeq label; jl label</samp>’ or ‘<samp>jeq +2; jge +4; br label</samp>’ +</p> +</dd> +<dt><code>jump label</code></dt> +<dd><p>A polymorph instruction which is ‘<samp>jmp label</samp>’ or ‘<samp>br label</samp>’ +</p></dd> +</dl> + + +<hr> +<a name="MSP430-Floating-Point"></a> +<div class="header"> +<p> +Next: <a href="#MSP430-Directives" accesskey="n" rel="next">MSP430 Directives</a>, Previous: <a href="#MSP430-Syntax" accesskey="p" rel="previous">MSP430 Syntax</a>, Up: <a href="#MSP430_002dDependent" accesskey="u" rel="up">MSP430-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-10"></a> +<h4 class="subsection">9.29.3 Floating Point</h4> + +<a name="index-floating-point_002c-MSP-430-_0028IEEE_0029"></a> +<a name="index-MSP-430-floating-point-_0028IEEE_0029"></a> +<p>The MSP 430 family uses <small>IEEE</small> 32-bit floating-point numbers. +</p> +<hr> +<a name="MSP430-Directives"></a> +<div class="header"> +<p> +Next: <a href="#MSP430-Opcodes" accesskey="n" rel="next">MSP430 Opcodes</a>, Previous: <a href="#MSP430-Floating-Point" accesskey="p" rel="previous">MSP430 Floating Point</a>, Up: <a href="#MSP430_002dDependent" accesskey="u" rel="up">MSP430-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="MSP-430-Machine-Directives"></a> +<h4 class="subsection">9.29.4 MSP 430 Machine Directives</h4> + +<a name="index-machine-directives_002c-MSP-430"></a> +<a name="index-MSP-430-machine-directives"></a> +<dl compact="compact"> +<dd><a name="index-file-directive_002c-MSP-430"></a> +</dd> +<dt><code>.file</code></dt> +<dd><p>This directive is ignored; it is accepted for compatibility with other +MSP 430 assemblers. +</p> +<blockquote> +<p><em>Warning:</em> in other versions of the <small>GNU</small> assembler, <code>.file</code> is +used for the directive called <code>.app-file</code> in the MSP 430 support. +</p></blockquote> + +<a name="index-line-directive_002c-MSP-430"></a> +</dd> +<dt><code>.line</code></dt> +<dd><p>This directive is ignored; it is accepted for compatibility with other +MSP 430 assemblers. +</p> +<a name="index-arch-directive_002c-MSP-430"></a> +</dd> +<dt><code>.arch</code></dt> +<dd><p>Sets the target microcontroller in the same way as the <samp>-mmcu</samp> +command-line option. +</p> +<a name="index-cpu-directive_002c-MSP-430"></a> +</dd> +<dt><code>.cpu</code></dt> +<dd><p>Sets the target architecture in the same way as the <samp>-mcpu</samp> +command-line option. +</p> +<a name="index-profiler-directive_002c-MSP-430"></a> +</dd> +<dt><code>.profiler</code></dt> +<dd><p>This directive instructs assembler to add new profile entry to the object file. +</p> +<a name="index-refsym-directive_002c-MSP-430"></a> +</dd> +<dt><code>.refsym</code></dt> +<dd><p>This directive instructs assembler to add an undefined reference to +the symbol following the directive. The maximum symbol name length is +1023 characters. No relocation is created for this symbol; it will +exist purely for pulling in object files from archives. Note that +this reloc is not sufficient to prevent garbage collection; use a +KEEP() directive in the linker file to preserve such objects. +</p> +<a name="index-mspabi_005fattribute-directive_002c-MSP430"></a> +</dd> +<dt><code>.mspabi_attribute</code></dt> +<dd><p>This directive tells the assembler what the MSPABI build attributes for this +file are. This is used for validating the command line options passed to +the assembler against the options the original source file was compiled with. +The expected format is: +‘<samp>.mspabi_attribute tag_name, tag_value</samp>’ +For example, to set the tag <code>OFBA_MSPABI_Tag_ISA</code> to <code>MSP430X</code>: +‘<samp>.mspabi_attribute 4, 2</samp>’ +</p> +<p>See the <cite>MSP430 EABI, document slaa534</cite> for the details on tag names and +values. +</p></dd> +</dl> + +<hr> +<a name="MSP430-Opcodes"></a> +<div class="header"> +<p> +Next: <a href="#MSP430-Profiling-Capability" accesskey="n" rel="next">MSP430 Profiling Capability</a>, Previous: <a href="#MSP430-Directives" accesskey="p" rel="previous">MSP430 Directives</a>, Up: <a href="#MSP430_002dDependent" accesskey="u" rel="up">MSP430-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-14"></a> +<h4 class="subsection">9.29.5 Opcodes</h4> + +<a name="index-MSP-430-opcodes"></a> +<a name="index-opcodes-for-MSP-430"></a> +<p><code>as</code> implements all the standard MSP 430 opcodes. No +additional pseudo-instructions are needed on this family. +</p> +<p>For information on the 430 machine instruction set, see <cite>MSP430 +User’s Manual, document slau049d</cite>, Texas Instrument, Inc. +</p> +<hr> +<a name="MSP430-Profiling-Capability"></a> +<div class="header"> +<p> +Previous: <a href="#MSP430-Opcodes" accesskey="p" rel="previous">MSP430 Opcodes</a>, Up: <a href="#MSP430_002dDependent" accesskey="u" rel="up">MSP430-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Profiling-Capability"></a> +<h4 class="subsection">9.29.6 Profiling Capability</h4> + +<a name="index-MSP-430-profiling-capability"></a> +<a name="index-profiling-capability-for-MSP-430"></a> +<p>It is a performance hit to use gcc’s profiling approach for this tiny target. +Even more – jtag hardware facility does not perform any profiling functions. +However we’ve got gdb’s built-in simulator where we can do anything. +</p> +<p>We define new section ‘<samp>.profiler</samp>’ which holds all profiling information. +We define new pseudo operation ‘<samp>.profiler</samp>’ which will instruct assembler to +add new profile entry to the object file. Profile should take place at the +present address. +</p> +<p>Pseudo operation format: +</p> +<p>‘<samp>.profiler flags,function_to_profile [, cycle_corrector, extra]</samp>’ +</p> + +<p>where: +</p> +<dl compact="compact"> +<dd> +<dl compact="compact"> +<dd> +<p>‘<samp>flags</samp>’ is a combination of the following characters: +</p> +</dd> +<dt><code>s</code></dt> +<dd><p>function entry +</p></dd> +<dt><code>x</code></dt> +<dd><p>function exit +</p></dd> +<dt><code>i</code></dt> +<dd><p>function is in init section +</p></dd> +<dt><code>f</code></dt> +<dd><p>function is in fini section +</p></dd> +<dt><code>l</code></dt> +<dd><p>library call +</p></dd> +<dt><code>c</code></dt> +<dd><p>libc standard call +</p></dd> +<dt><code>d</code></dt> +<dd><p>stack value demand +</p></dd> +<dt><code>I</code></dt> +<dd><p>interrupt service routine +</p></dd> +<dt><code>P</code></dt> +<dd><p>prologue start +</p></dd> +<dt><code>p</code></dt> +<dd><p>prologue end +</p></dd> +<dt><code>E</code></dt> +<dd><p>epilogue start +</p></dd> +<dt><code>e</code></dt> +<dd><p>epilogue end +</p></dd> +<dt><code>j</code></dt> +<dd><p>long jump / sjlj unwind +</p></dd> +<dt><code>a</code></dt> +<dd><p>an arbitrary code fragment +</p></dd> +<dt><code>t</code></dt> +<dd><p>extra parameter saved (a constant value like frame size) +</p></dd> +</dl> + +</dd> +<dt><code>function_to_profile</code></dt> +<dd><p>a function address +</p></dd> +<dt><code>cycle_corrector</code></dt> +<dd><p>a value which should be added to the cycle counter, zero if omitted. +</p></dd> +<dt><code>extra</code></dt> +<dd><p>any extra parameter, zero if omitted. +</p> +</dd> +</dl> + +<p>For example: +</p><div class="smallexample"> +<pre class="smallexample">.global fxx +.type fxx,@function +fxx: +.LFrameOffset_fxx=0x08 +.profiler "scdP", fxx ; function entry. + ; we also demand stack value to be saved + push r11 + push r10 + push r9 + push r8 +.profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point + ; (this is a prologue end) + ; note, that spare var filled with + ; the farme size + mov r15,r8 +... +.profiler cdE,fxx ; check stack + pop r8 + pop r9 + pop r10 + pop r11 +.profiler xcde,fxx,3 ; exit adds 3 to the cycle counter + ret ; cause 'ret' insn takes 3 cycles +</pre></div> + + +<hr> +<a name="NDS32_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#NiosII_002dDependent" accesskey="n" rel="next">NiosII-Dependent</a>, Previous: <a href="#MSP430_002dDependent" accesskey="p" rel="previous">MSP430-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="NDS32-Dependent-Features"></a> +<h3 class="section">9.30 NDS32 Dependent Features</h3> + +<a name="index-NDS32-processor"></a> +<p>The NDS32 processors family includes high-performance and low-power 32-bit +processors for high-end to low-end. <small>GNU</small> <code>as</code> for NDS32 +architectures supports NDS32 ISA version 3. For detail about NDS32 +instruction set, please see the AndeStar ISA User Manual which is available +at http://www.andestech.com/en/index/index.htm +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#NDS32-Options" accesskey="1">NDS32 Options</a>:</td><td> </td><td align="left" valign="top">Assembler options +</td></tr> +<tr><td align="left" valign="top">• <a href="#NDS32-Syntax" accesskey="2">NDS32 Syntax</a>:</td><td> </td><td align="left" valign="top">High-level assembly macros +</td></tr> +</table> + +<hr> +<a name="NDS32-Options"></a> +<div class="header"> +<p> +Next: <a href="#NDS32-Syntax" accesskey="n" rel="next">NDS32 Syntax</a>, Up: <a href="#NDS32_002dDependent" accesskey="u" rel="up">NDS32-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="NDS32-Options-1"></a> +<h4 class="subsection">9.30.1 NDS32 Options</h4> + +<a name="index-NDS32-options"></a> +<a name="index-options-for-NDS32"></a> +<p>The NDS32 configurations of <small>GNU</small> <code>as</code> support these +special options: +</p> +<dl compact="compact"> +<dt><code>-O1</code></dt> +<dd><p>Optimize for performance. +</p> +</dd> +<dt><code>-Os</code></dt> +<dd><p>Optimize for space. +</p> +</dd> +<dt><code>-EL</code></dt> +<dd><p>Produce little endian data output. +</p> +</dd> +<dt><code>-EB</code></dt> +<dd><p>Produce little endian data output. +</p> +</dd> +<dt><code>-mpic</code></dt> +<dd><p>Generate PIC. +</p> +</dd> +<dt><code>-mno-fp-as-gp-relax</code></dt> +<dd><p>Suppress fp-as-gp relaxation for this file. +</p> +</dd> +<dt><code>-mb2bb-relax</code></dt> +<dd><p>Back-to-back branch optimization. +</p> +</dd> +<dt><code>-mno-all-relax</code></dt> +<dd><p>Suppress all relaxation for this file. +</p> +</dd> +<dt><code>-march=<arch name></code></dt> +<dd><p>Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, +v3s, v2, v2j, v2f, v2s. +</p> +</dd> +<dt><code>-mbaseline=<baseline></code></dt> +<dd><p>Assemble for baseline <baseline> which could be v2, v3, v3m. +</p> +</dd> +<dt><code>-mfpu-freg=<var>FREG</var></code></dt> +<dd><p>Specify a FPU configuration. +</p><dl compact="compact"> +<dt><code>0 8 SP / 4 DP registers</code></dt> +<dt><code>1 16 SP / 8 DP registers</code></dt> +<dt><code>2 32 SP / 16 DP registers</code></dt> +<dt><code>3 32 SP / 32 DP registers</code></dt> +</dl> + +</dd> +<dt><code>-mabi=<var>abi</var></code></dt> +<dd><p>Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. +</p> +</dd> +<dt><code>-m[no-]mac</code></dt> +<dd><p>Enable/Disable Multiply instructions support. +</p> +</dd> +<dt><code>-m[no-]div</code></dt> +<dd><p>Enable/Disable Divide instructions support. +</p> +</dd> +<dt><code>-m[no-]16bit-ext</code></dt> +<dd><p>Enable/Disable 16-bit extension +</p> +</dd> +<dt><code>-m[no-]dx-regs</code></dt> +<dd><p>Enable/Disable d0/d1 registers +</p> +</dd> +<dt><code>-m[no-]perf-ext</code></dt> +<dd><p>Enable/Disable Performance extension +</p> +</dd> +<dt><code>-m[no-]perf2-ext</code></dt> +<dd><p>Enable/Disable Performance extension 2 +</p> +</dd> +<dt><code>-m[no-]string-ext</code></dt> +<dd><p>Enable/Disable String extension +</p> +</dd> +<dt><code>-m[no-]reduced-regs</code></dt> +<dd><p>Enable/Disable Reduced Register configuration (GPR16) option +</p> +</dd> +<dt><code>-m[no-]audio-isa-ext</code></dt> +<dd><p>Enable/Disable AUDIO ISA extension +</p> +</dd> +<dt><code>-m[no-]fpu-sp-ext</code></dt> +<dd><p>Enable/Disable FPU SP extension +</p> +</dd> +<dt><code>-m[no-]fpu-dp-ext</code></dt> +<dd><p>Enable/Disable FPU DP extension +</p> +</dd> +<dt><code>-m[no-]fpu-fma</code></dt> +<dd><p>Enable/Disable FPU fused-multiply-add instructions +</p> +</dd> +<dt><code>-mall-ext</code></dt> +<dd><p>Turn on all extensions and instructions support +</p></dd> +</dl> + +<hr> +<a name="NDS32-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#NDS32-Options" accesskey="p" rel="previous">NDS32 Options</a>, Up: <a href="#NDS32_002dDependent" accesskey="u" rel="up">NDS32-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-23"></a> +<h4 class="subsection">9.30.2 Syntax</h4> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#NDS32_002dChars" accesskey="1">NDS32-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#NDS32_002dRegs" accesskey="2">NDS32-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#NDS32_002dOps" accesskey="3">NDS32-Ops</a>:</td><td> </td><td align="left" valign="top">Pseudo Instructions +</td></tr> +</table> + +<hr> +<a name="NDS32_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#NDS32_002dRegs" accesskey="n" rel="next">NDS32-Regs</a>, Up: <a href="#NDS32-Syntax" accesskey="u" rel="up">NDS32 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-23"></a> +<h4 class="subsubsection">9.30.2.1 Special Characters</h4> + +<p>Use ‘<samp>#</samp>’ at column 1 and ‘<samp>!</samp>’ anywhere in the line except inside +quotes. +</p> +<p>Multiple instructions in a line are allowed though not recommended and +should be separated by ‘<samp>;</samp>’. +</p> +<p>Assembler is not case-sensitive in general except user defined label. +For example, ‘<samp>jral F1</samp>’ is different from ‘<samp>jral f1</samp>’ while it is +the same as ‘<samp>JRAL F1</samp>’. +</p> +<hr> +<a name="NDS32_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#NDS32_002dOps" accesskey="n" rel="next">NDS32-Ops</a>, Previous: <a href="#NDS32_002dChars" accesskey="p" rel="previous">NDS32-Chars</a>, Up: <a href="#NDS32-Syntax" accesskey="u" rel="up">NDS32 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-13"></a> +<h4 class="subsubsection">9.30.2.2 Register Names</h4> +<dl compact="compact"> +<dt><code>General purpose registers (GPR)</code></dt> +<dd><p>There are 32 32-bit general purpose registers $r0 to $r31. +</p> +</dd> +<dt><code>Accumulators d0 and d1</code></dt> +<dd><p>64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo. +</p> +</dd> +<dt><code>Assembler reserved register $ta</code></dt> +<dd><p>Register $ta ($r15) is reserved for assembler using. +</p> +</dd> +<dt><code>Operating system reserved registers $p0 and $p1</code></dt> +<dd><p>Registers $p0 ($r26) and $p1 ($r27) are used by operating system as scratch +registers. +</p> +</dd> +<dt><code>Frame pointer $fp</code></dt> +<dd><p>Register $r28 is regarded as the frame pointer. +</p> +</dd> +<dt><code>Global pointer</code></dt> +<dd><p>Register $r29 is regarded as the global pointer. +</p> +</dd> +<dt><code>Link pointer</code></dt> +<dd><p>Register $r30 is regarded as the link pointer. +</p> +</dd> +<dt><code>Stack pointer</code></dt> +<dd><p>Register $r31 is regarded as the stack pointer. +</p></dd> +</dl> + +<hr> +<a name="NDS32_002dOps"></a> +<div class="header"> +<p> +Previous: <a href="#NDS32_002dRegs" accesskey="p" rel="previous">NDS32-Regs</a>, Up: <a href="#NDS32-Syntax" accesskey="u" rel="up">NDS32 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Pseudo-Instructions-1"></a> +<h4 class="subsubsection">9.30.2.3 Pseudo Instructions</h4> +<dl compact="compact"> +<dt><code>li rt5,imm32</code></dt> +<dd><p>load 32-bit integer into register rt5. ‘<samp>sethi rt5,hi20(imm32)</samp>’ and then +‘<samp>ori rt5,reg,lo12(imm32)</samp>’. +</p> +</dd> +<dt><code>la rt5,var</code></dt> +<dd><p>Load 32-bit address of var into register rt5. ‘<samp>sethi rt5,hi20(var)</samp>’ and +then ‘<samp>ori reg,rt5,lo12(var)</samp>’ +</p> +</dd> +<dt><code>l.[bhw] rt5,var</code></dt> +<dd><p>Load value of var into register rt5. ‘<samp>sethi $ta,hi20(var)</samp>’ and then +‘<samp>l[bhw]i rt5,[$ta+lo12(var)]</samp>’ +</p> +</dd> +<dt><code>l.[bh]s rt5,var</code></dt> +<dd><p>Load value of var into register rt5. ‘<samp>sethi $ta,hi20(var)</samp>’ and then +‘<samp>l[bh]si rt5,[$ta+lo12(var)]</samp>’ +</p> +</dd> +<dt><code>l.[bhw]p rt5,var,inc</code></dt> +<dd><p>Load value of var into register rt5 and increment $ta by amount inc. +‘<samp>la $ta,var</samp>’ and then ‘<samp>l[bhw]i.bi rt5,[$ta],inc</samp>’ +</p> +</dd> +<dt><code>l.[bhw]pc rt5,inc</code></dt> +<dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc. +‘<samp>l[bhw]i.bi rt5,[$ta],inc.</samp>’ +</p> +</dd> +<dt><code>l.[bh]sp rt5,var,inc</code></dt> +<dd><p>Load value of var into register rt5 and increment $ta by amount inc. +‘<samp>la $ta,var</samp>’ and then ‘<samp>l[bh]si.bi rt5,[$ta],inc</samp>’ +</p> +</dd> +<dt><code>l.[bh]spc rt5,inc</code></dt> +<dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc. +‘<samp>l[bh]si.bi rt5,[$ta],inc.</samp>’ +</p> +</dd> +<dt><code>s.[bhw] rt5,var</code></dt> +<dd><p>Store register rt5 to var. +‘<samp>sethi $ta,hi20(var)</samp>’ and then ‘<samp>s[bhw]i rt5,[$ta+lo12(var)]</samp>’ +</p> +</dd> +<dt><code>s.[bhw]p rt5,var,inc</code></dt> +<dd><p>Store register rt5 to var and increment $ta by amount inc. +‘<samp>la $ta,var</samp>’ and then ‘<samp>s[bhw]i.bi rt5,[$ta],inc</samp>’ +</p> +</dd> +<dt><code>s.[bhw]pc rt5,inc</code></dt> +<dd><p>Continue storing register rt5 to var and increment $ta by amount inc. +‘<samp>s[bhw]i.bi rt5,[$ta],inc.</samp>’ +</p> +</dd> +<dt><code>not rt5,ra5</code></dt> +<dd><p>Alias of ‘<samp>nor rt5,ra5,ra5</samp>’. +</p> +</dd> +<dt><code>neg rt5,ra5</code></dt> +<dd><p>Alias of ‘<samp>subri rt5,ra5,0</samp>’. +</p> +</dd> +<dt><code>br rb5</code></dt> +<dd><p>Depending on how it is assembled, it is translated into ‘<samp>r5 rb5</samp>’ +or ‘<samp>jr rb5</samp>’. +</p> +</dd> +<dt><code>b label</code></dt> +<dd><p>Branch to label depending on how it is assembled, it is translated into +‘<samp>j8 label</samp>’, ‘<samp>j label</samp>’, or "‘<samp>la $ta,label</samp>’ ‘<samp>br $ta</samp>’". +</p> +</dd> +<dt><code>bral rb5</code></dt> +<dd><p>Alias of jral br5 depending on how it is assembled, it is translated +into ‘<samp>jral5 rb5</samp>’ or ‘<samp>jral rb5</samp>’. +</p> +</dd> +<dt><code>bal fname</code></dt> +<dd><p>Alias of jal fname depending on how it is assembled, it is translated into +‘<samp>jal fname</samp>’ or "‘<samp>la $ta,fname</samp>’ ‘<samp>bral $ta</samp>’". +</p> +</dd> +<dt><code>call fname</code></dt> +<dd><p>Call function fname same as ‘<samp>jal fname</samp>’. +</p> +</dd> +<dt><code>move rt5,ra5</code></dt> +<dd><p>For 16-bit, this is ‘<samp>mov55 rt5,ra5</samp>’. +For no 16-bit, this is ‘<samp>ori rt5,ra5,0</samp>’. +</p> +</dd> +<dt><code>move rt5,var</code></dt> +<dd><p>This is the same as ‘<samp>l.w rt5,var</samp>’. +</p> +</dd> +<dt><code>move rt5,imm32</code></dt> +<dd><p>This is the same as ‘<samp>li rt5,imm32</samp>’. +</p> +</dd> +<dt><code>pushm ra5,rb5</code></dt> +<dd><p>Push contents of registers from ra5 to rb5 into stack. +</p> +</dd> +<dt><code>push ra5</code></dt> +<dd><p>Push content of register ra5 into stack. (same ‘<samp>pushm ra5,ra5</samp>’). +</p> +</dd> +<dt><code>push.d var</code></dt> +<dd><p>Push value of double-word variable var into stack. +</p> +</dd> +<dt><code>push.w var</code></dt> +<dd><p>Push value of word variable var into stack. +</p> +</dd> +<dt><code>push.h var</code></dt> +<dd><p>Push value of half-word variable var into stack. +</p> +</dd> +<dt><code>push.b var</code></dt> +<dd><p>Push value of byte variable var into stack. +</p> +</dd> +<dt><code>pusha var</code></dt> +<dd><p>Push 32-bit address of variable var into stack. +</p> +</dd> +<dt><code>pushi imm32</code></dt> +<dd><p>Push 32-bit immediate value into stack. +</p> +</dd> +<dt><code>popm ra5,rb5</code></dt> +<dd><p>Pop top of stack values into registers ra5 to rb5. +</p> +</dd> +<dt><code>pop rt5</code></dt> +<dd><p>Pop top of stack value into register. (same as ‘<samp>popm rt5,rt5</samp>’.) +</p> +</dd> +<dt><code>pop.d var,ra5</code></dt> +<dd><p>Pop value of double-word variable var from stack using register ra5 +as 2nd scratch register. (1st is $ta) +</p> +</dd> +<dt><code>pop.w var,ra5</code></dt> +<dd><p>Pop value of word variable var from stack using register ra5. +</p> +</dd> +<dt><code>pop.h var,ra5</code></dt> +<dd><p>Pop value of half-word variable var from stack using register ra5. +</p> +</dd> +<dt><code>pop.b var,ra5</code></dt> +<dd><p>Pop value of byte variable var from stack using register ra5. +</p> +</dd> +</dl> + +<hr> +<a name="NiosII_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#NS32K_002dDependent" accesskey="n" rel="next">NS32K-Dependent</a>, Previous: <a href="#NDS32_002dDependent" accesskey="p" rel="previous">NDS32-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Nios-II-Dependent-Features"></a> +<h3 class="section">9.31 Nios II Dependent Features</h3> + +<a name="index-Altera-Nios-II-support"></a> +<a name="index-Nios-support"></a> +<a name="index-Nios-II-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Nios-II-Options" accesskey="1">Nios II Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#Nios-II-Syntax" accesskey="2">Nios II Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#Nios-II-Relocations" accesskey="3">Nios II Relocations</a>:</td><td> </td><td align="left" valign="top">Relocations +</td></tr> +<tr><td align="left" valign="top">• <a href="#Nios-II-Directives" accesskey="4">Nios II Directives</a>:</td><td> </td><td align="left" valign="top">Nios II Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#Nios-II-Opcodes" accesskey="5">Nios II Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="Nios-II-Options"></a> +<div class="header"> +<p> +Next: <a href="#Nios-II-Syntax" accesskey="n" rel="next">Nios II Syntax</a>, Up: <a href="#NiosII_002dDependent" accesskey="u" rel="up">NiosII-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-16"></a> +<h4 class="subsection">9.31.1 Options</h4> +<a name="index-Nios-II-options"></a> +<a name="index-options-for-Nios-II"></a> + +<dl compact="compact"> +<dd> +<a name="index-relax_002dsection-command_002dline-option_002c-Nios-II"></a> +</dd> +<dt><code>-relax-section</code></dt> +<dd><p>Replace identified out-of-range branches with PC-relative <code>jmp</code> +sequences when possible. The generated code sequences are suitable +for use in position-independent code, but there is a practical limit +on the extended branch range because of the length of the sequences. +This option is the default. +</p> +<a name="index-relax_002dall-command_002dline-option_002c-Nios-II"></a> +</dd> +<dt><code>-relax-all</code></dt> +<dd><p>Replace branch instructions not determinable to be in range +and all call instructions with <code>jmp</code> and <code>callr</code> sequences +(respectively). This option generates absolute relocations against the +target symbols and is not appropriate for position-independent code. +</p> +<a name="index-no_002drelax-command_002dline-option_002c-Nios-II"></a> +</dd> +<dt><code>-no-relax</code></dt> +<dd><p>Do not replace any branches or calls. +</p> +<a name="index-EB-command_002dline-option_002c-Nios-II"></a> +</dd> +<dt><code>-EB</code></dt> +<dd><p>Generate big-endian output. +</p> +<a name="index-EL-command_002dline-option_002c-Nios-II"></a> +</dd> +<dt><code>-EL</code></dt> +<dd><p>Generate little-endian output. This is the default. +</p> +<a name="index-march-command_002dline-option_002c-Nios-II"></a> +</dd> +<dt><code>-march=<var>architecture</var></code></dt> +<dd><p>This option specifies the target architecture. The assembler issues +an error message if an attempt is made to assemble an instruction which +will not execute on the target architecture. The following architecture +names are recognized: +<code>r1</code>, +<code>r2</code>. +The default is <code>r1</code>. +</p> +</dd> +</dl> + +<hr> +<a name="Nios-II-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#Nios-II-Relocations" accesskey="n" rel="next">Nios II Relocations</a>, Previous: <a href="#Nios-II-Options" accesskey="p" rel="previous">Nios II Options</a>, Up: <a href="#NiosII_002dDependent" accesskey="u" rel="up">NiosII-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-24"></a> +<h4 class="subsection">9.31.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Nios-II-Chars" accesskey="1">Nios II Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + + +<hr> +<a name="Nios-II-Chars"></a> +<div class="header"> +<p> +Up: <a href="#Nios-II-Syntax" accesskey="u" rel="up">Nios II Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-24"></a> +<h4 class="subsubsection">9.31.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-Nios-II"></a> +<a name="index-Nios-II-line-comment-character"></a> +<a name="index-line-separator-character_002c-Nios-II"></a> +<a name="index-Nios-II-line-separator-character"></a> +<p>‘<samp>#</samp>’ is the line comment character. +‘<samp>;</samp>’ is the line separator character. +</p> + +<hr> +<a name="Nios-II-Relocations"></a> +<div class="header"> +<p> +Next: <a href="#Nios-II-Directives" accesskey="n" rel="next">Nios II Directives</a>, Previous: <a href="#Nios-II-Syntax" accesskey="p" rel="previous">Nios II Syntax</a>, Up: <a href="#NiosII_002dDependent" accesskey="u" rel="up">NiosII-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Nios-II-Machine-Relocations"></a> +<h4 class="subsection">9.31.3 Nios II Machine Relocations</h4> + +<a name="index-machine-relocations_002c-Nios-II"></a> +<a name="index-Nios-II-machine-relocations"></a> + +<dl compact="compact"> +<dd><a name="index-hiadj-directive_002c-Nios-II"></a> +</dd> +<dt><code>%hiadj(<var>expression</var>)</code></dt> +<dd><p>Extract the upper 16 bits of <var>expression</var> and add +one if the 15th bit is set. +</p> +<p>The value of <code>%hiadj(<var>expression</var>)</code> is: +</p><div class="smallexample"> +<pre class="smallexample">((<var>expression</var> >> 16) & 0xffff) + ((<var>expression</var> >> 15) & 0x01) +</pre></div> + +<p>The <code>%hiadj</code> relocation is intended to be used with +the <code>addi</code>, <code>ld</code> or <code>st</code> instructions +along with a <code>%lo</code>, in order to load a 32-bit constant. +</p> +<div class="smallexample"> +<pre class="smallexample">movhi r2, %hiadj(symbol) +addi r2, r2, %lo(symbol) +</pre></div> + +<a name="index-hi-directive_002c-Nios-II"></a> +</dd> +<dt><code>%hi(<var>expression</var>)</code></dt> +<dd><p>Extract the upper 16 bits of <var>expression</var>. +</p> +<a name="index-lo-directive_002c-Nios-II"></a> +</dd> +<dt><code>%lo(<var>expression</var>)</code></dt> +<dd><p>Extract the lower 16 bits of <var>expression</var>. +</p> +<a name="index-gprel-directive_002c-Nios-II"></a> +</dd> +<dt><code>%gprel(<var>expression</var>)</code></dt> +<dd><p>Subtract the value of the symbol <code>_gp</code> from +<var>expression</var>. +</p> +<p>The intention of the <code>%gprel</code> relocation is +to have a fast small area of memory which only +takes a 16-bit immediate to access. +</p> +<div class="smallexample"> +<pre class="smallexample"> .section .sdata +fastint: + .int 123 + .section .text + ldw r4, %gprel(fastint)(gp) +</pre></div> + +<a name="index-call-directive_002c-Nios-II"></a> +<a name="index-call_005flo-directive_002c-Nios-II"></a> +<a name="index-call_005fhiadj-directive_002c-Nios-II"></a> +<a name="index-got-directive_002c-Nios-II"></a> +<a name="index-got_005flo-directive_002c-Nios-II"></a> +<a name="index-got_005fhiadj-directive_002c-Nios-II"></a> +<a name="index-gotoff-directive_002c-Nios-II"></a> +<a name="index-gotoff_005flo-directive_002c-Nios-II"></a> +<a name="index-gotoff_005fhiadj-directive_002c-Nios-II"></a> +<a name="index-tls_005fgd-directive_002c-Nios-II"></a> +<a name="index-tls_005fie-directive_002c-Nios-II"></a> +<a name="index-tls_005fle-directive_002c-Nios-II"></a> +<a name="index-tls_005fldm-directive_002c-Nios-II"></a> +<a name="index-tls_005fldo-directive_002c-Nios-II"></a> +</dd> +<dt><code>%call(<var>expression</var>)</code></dt> +<dt><code>%call_lo(<var>expression</var>)</code></dt> +<dt><code>%call_hiadj(<var>expression</var>)</code></dt> +<dt><code>%got(<var>expression</var>)</code></dt> +<dt><code>%got_lo(<var>expression</var>)</code></dt> +<dt><code>%got_hiadj(<var>expression</var>)</code></dt> +<dt><code>%gotoff(<var>expression</var>)</code></dt> +<dt><code>%gotoff_lo(<var>expression</var>)</code></dt> +<dt><code>%gotoff_hiadj(<var>expression</var>)</code></dt> +<dt><code>%tls_gd(<var>expression</var>)</code></dt> +<dt><code>%tls_ie(<var>expression</var>)</code></dt> +<dt><code>%tls_le(<var>expression</var>)</code></dt> +<dt><code>%tls_ldm(<var>expression</var>)</code></dt> +<dt><code>%tls_ldo(<var>expression</var>)</code></dt> +<dd> +<p>These relocations support the ABI for Linux Systems documented in the +<cite>Nios II Processor Reference Handbook</cite>. +</p></dd> +</dl> + + +<hr> +<a name="Nios-II-Directives"></a> +<div class="header"> +<p> +Next: <a href="#Nios-II-Opcodes" accesskey="n" rel="next">Nios II Opcodes</a>, Previous: <a href="#Nios-II-Relocations" accesskey="p" rel="previous">Nios II Relocations</a>, Up: <a href="#NiosII_002dDependent" accesskey="u" rel="up">NiosII-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Nios-II-Machine-Directives"></a> +<h4 class="subsection">9.31.4 Nios II Machine Directives</h4> + +<a name="index-machine-directives_002c-Nios-II"></a> +<a name="index-Nios-II-machine-directives"></a> + +<dl compact="compact"> +<dd> +<a name="index-align-directive_002c-Nios-II"></a> +</dd> +<dt><code>.align <var>expression</var> [, <var>expression</var>]</code></dt> +<dd><p>This is the generic <code>.align</code> directive, however +this aligns to a power of two. +</p> +<a name="index-half-directive_002c-Nios-II"></a> +</dd> +<dt><code>.half <var>expression</var></code></dt> +<dd><p>Create an aligned constant 2 bytes in size. +</p> +<a name="index-word-directive_002c-Nios-II"></a> +</dd> +<dt><code>.word <var>expression</var></code></dt> +<dd><p>Create an aligned constant 4 bytes in size. +</p> +<a name="index-dword-directive_002c-Nios-II"></a> +</dd> +<dt><code>.dword <var>expression</var></code></dt> +<dd><p>Create an aligned constant 8 bytes in size. +</p> +<a name="index-2byte-directive_002c-Nios-II"></a> +</dd> +<dt><code>.2byte <var>expression</var></code></dt> +<dd><p>Create an unaligned constant 2 bytes in size. +</p> +<a name="index-4byte-directive_002c-Nios-II"></a> +</dd> +<dt><code>.4byte <var>expression</var></code></dt> +<dd><p>Create an unaligned constant 4 bytes in size. +</p> +<a name="index-8byte-directive_002c-Nios-II"></a> +</dd> +<dt><code>.8byte <var>expression</var></code></dt> +<dd><p>Create an unaligned constant 8 bytes in size. +</p> +<a name="index-16byte-directive_002c-Nios-II"></a> +</dd> +<dt><code>.16byte <var>expression</var></code></dt> +<dd><p>Create an unaligned constant 16 bytes in size. +</p> +<a name="index-set-noat-directive_002c-Nios-II"></a> +</dd> +<dt><code>.set noat</code></dt> +<dd><p>Allows assembly code to use <code>at</code> register without +warning. Macro or relaxation expansions +generate warnings. +</p> +<a name="index-set-at-directive_002c-Nios-II"></a> +</dd> +<dt><code>.set at</code></dt> +<dd><p>Assembly code using <code>at</code> register generates +warnings, and macro expansion and relaxation are +enabled. +</p> +<a name="index-set-nobreak-directive_002c-Nios-II"></a> +</dd> +<dt><code>.set nobreak</code></dt> +<dd><p>Allows assembly code to use <code>ba</code> and <code>bt</code> +registers without warning. +</p> +<a name="index-set-break-directive_002c-Nios-II"></a> +</dd> +<dt><code>.set break</code></dt> +<dd><p>Turns warnings back on for using <code>ba</code> and <code>bt</code> +registers. +</p> +<a name="index-set-norelax-directive_002c-Nios-II"></a> +</dd> +<dt><code>.set norelax</code></dt> +<dd><p>Do not replace any branches or calls. +</p> +<a name="index-set-relaxsection-directive_002c-Nios-II"></a> +</dd> +<dt><code>.set relaxsection</code></dt> +<dd><p>Replace identified out-of-range branches with +<code>jmp</code> sequences (default). +</p> +<a name="index-set-relaxall-directive_002c-Nios-II"></a> +</dd> +<dt><code>.set relaxsection</code></dt> +<dd><p>Replace all branch and call instructions with +<code>jmp</code> and <code>callr</code> sequences. +</p> +<a name="index-set-directive_002c-Nios-II"></a> +</dd> +<dt><code>.set …</code></dt> +<dd><p>All other <code>.set</code> are the normal use. +</p> +</dd> +</dl> + +<hr> +<a name="Nios-II-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#Nios-II-Directives" accesskey="p" rel="previous">Nios II Directives</a>, Up: <a href="#NiosII_002dDependent" accesskey="u" rel="up">NiosII-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-15"></a> +<h4 class="subsection">9.31.5 Opcodes</h4> + +<a name="index-Nios-II-opcodes"></a> +<a name="index-opcodes-for-Nios-II"></a> +<p><code>as</code> implements all the standard Nios II opcodes documented in the +<cite>Nios II Processor Reference Handbook</cite>, including the assembler +pseudo-instructions. +</p> + + +<hr> +<a name="NS32K_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#OpenRISC_002dDependent" accesskey="n" rel="next">OpenRISC-Dependent</a>, Previous: <a href="#NiosII_002dDependent" accesskey="p" rel="previous">NiosII-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="NS32K-Dependent-Features"></a> +<h3 class="section">9.32 NS32K Dependent Features</h3> + + +<a name="index-N32K-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#NS32K-Syntax" accesskey="1">NS32K Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +</table> + + +<hr> +<a name="NS32K-Syntax"></a> +<div class="header"> +<p> +Up: <a href="#NS32K_002dDependent" accesskey="u" rel="up">NS32K-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-25"></a> +<h4 class="subsection">9.32.1 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#NS32K_002dChars" accesskey="1">NS32K-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="NS32K_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#NS32K-Syntax" accesskey="u" rel="up">NS32K Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-25"></a> +<h4 class="subsubsection">9.32.1.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-NS32K"></a> +<a name="index-NS32K-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ appearing anywhere on a line indicates the +start of a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<p>If Sequent compatibility has been configured into the assembler then +the ‘<samp>|</samp>’ character appearing as the first character on a line will +also indicate the start of a line comment. +</p> +<a name="index-line-separator_002c-NS32K"></a> +<a name="index-statement-separator_002c-NS32K"></a> +<a name="index-NS32K-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="OpenRISC_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#PDP_002d11_002dDependent" accesskey="n" rel="next">PDP-11-Dependent</a>, Previous: <a href="#NS32K_002dDependent" accesskey="p" rel="previous">NS32K-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="OPENRISC-Dependent-Features"></a> +<h3 class="section">9.33 OPENRISC Dependent Features</h3> + +<a name="index-OPENRISC-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#OpenRISC_002dSyntax" accesskey="1">OpenRISC-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#OpenRISC_002dFloat" accesskey="2">OpenRISC-Float</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#OpenRISC_002dDirectives" accesskey="3">OpenRISC-Directives</a>:</td><td> </td><td align="left" valign="top">OpenRISC Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#OpenRISC_002dOpcodes" accesskey="4">OpenRISC-Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<a name="index-OPENRISC-syntax"></a> +<a name="index-syntax_002c-OPENRISC"></a> +<hr> +<a name="OpenRISC_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#OpenRISC_002dFloat" accesskey="n" rel="next">OpenRISC-Float</a>, Up: <a href="#OpenRISC_002dDependent" accesskey="u" rel="up">OpenRISC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="OpenRISC-Syntax"></a> +<h4 class="subsection">9.33.1 OpenRISC Syntax</h4> +<p>The assembler syntax follows the OpenRISC 1000 Architecture Manual. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#OpenRISC_002dChars" accesskey="1">OpenRISC-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#OpenRISC_002dRegs" accesskey="2">OpenRISC-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#OpenRISC_002dRelocs" accesskey="3">OpenRISC-Relocs</a>:</td><td> </td><td align="left" valign="top">Relocations +</td></tr> +</table> + +<hr> +<a name="OpenRISC_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#OpenRISC_002dRegs" accesskey="n" rel="next">OpenRISC-Regs</a>, Up: <a href="#OpenRISC_002dSyntax" accesskey="u" rel="up">OpenRISC-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-26"></a> +<h4 class="subsubsection">9.33.1.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-OpenRISC"></a> +<a name="index-OpenRISC-line-comment-character"></a> +<p>A ‘<samp>#</samp>’ character appearing anywhere on a line indicates the start +of a comment that extends to the end of that line. +</p> +<a name="index-line-separator_002c-OpenRISC"></a> +<a name="index-statement-separator_002c-OpenRISC"></a> +<a name="index-OpenRISC-line-separator"></a> +<p>‘<samp>;</samp>’ can be used instead of a newline to separate statements. +</p> +<hr> +<a name="OpenRISC_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#OpenRISC_002dRelocs" accesskey="n" rel="next">OpenRISC-Relocs</a>, Previous: <a href="#OpenRISC_002dChars" accesskey="p" rel="previous">OpenRISC-Chars</a>, Up: <a href="#OpenRISC_002dSyntax" accesskey="u" rel="up">OpenRISC-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-14"></a> +<h4 class="subsubsection">9.33.1.2 Register Names</h4> +<a name="index-OpenRISC-registers"></a> +<a name="index-register-names_002c-OpenRISC"></a> + +<p>The OpenRISC register file contains 32 general pupose registers. +</p> +<ul> +<li> The 32 general purpose registers are referred to as ‘<samp>r<var>n</var></samp>’. + +</li><li> The stack pointer register ‘<samp>r1</samp>’ can be referenced using the alias +‘<samp>sp</samp>’. + +</li><li> The frame pointer register ‘<samp>r2</samp>’ can be referenced using the alias +‘<samp>fp</samp>’. + +</li><li> The link register ‘<samp>r9</samp>’ can be referenced using the alias ‘<samp>lr</samp>’. +</li></ul> + +<p>Floating point operations use the same general purpose registers. The +instructions <code>lf.itof.s</code> (single precision) and <code>lf.itof.d</code> (double +precision) can be used to convert integer values to floating point. +Likewise, instructions <code>lf.ftoi.s</code> (single precision) and +<code>lf.ftoi.d</code> (double precision) can be used to convert floating point to +integer. +</p> +<p>OpenRISC also contains privileged special purpose registers (SPRs). The +SPRs are accessed using the <code>l.mfspr</code> and <code>l.mtspr</code> instructions. +</p> +<hr> +<a name="OpenRISC_002dRelocs"></a> +<div class="header"> +<p> +Previous: <a href="#OpenRISC_002dRegs" accesskey="p" rel="previous">OpenRISC-Regs</a>, Up: <a href="#OpenRISC_002dSyntax" accesskey="u" rel="up">OpenRISC-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Relocations-3"></a> +<h4 class="subsubsection">9.33.1.3 Relocations</h4> +<a name="index-OpenRISC-relocations"></a> +<a name="index-relocations_002c-OpenRISC"></a> + +<p>ELF relocations are available as defined in the OpenRISC architecture +specification. +</p> +<p><code>R_OR1K_HI_16_IN_INSN</code> is obtained using ‘<samp>hi</samp>’ and +<code>R_OR1K_LO_16_IN_INSN</code> and <code>R_OR1K_SLO16</code> are obtained using +‘<samp>lo</samp>’. For signed offsets <code>R_OR1K_AHI16</code> is obtained from +‘<samp>ha</samp>’. For example: +</p> +<div class="example"> +<pre class="example">l.movhi r5, hi(symbol) +l.ori r5, r5, lo(symbol) + +l.movhi r5, ha(symbol) +l.addi r5, r5, lo(symbol) +</pre></div> + +<p>These “high” mnemonics extract bits 31:16 of their operand, +and the “low” mnemonics extract bits 15:0 of their operand. +</p> +<p>The PC relative relocation <code>R_OR1K_GOTPC_HI16</code> can be obtained by +enclosing an operand inside of ‘<samp>gotpchi</samp>’. Likewise, the +<code>R_OR1K_GOTPC_LO16</code> relocation can be obtained using ‘<samp>gotpclo</samp>’. +These are mostly used when assembling PIC code. For example, the +standard PIC sequence on OpenRISC to get the base of the global offset +table, PC relative, into a register, can be performed as: +</p> +<div class="example"> +<pre class="example">l.jal 0x8 + l.movhi r17, gotpchi(_GLOBAL_OFFSET_TABLE_-4) +l.ori r17, r17, gotpclo(_GLOBAL_OFFSET_TABLE_+0) +l.add r17, r17, r9 +</pre></div> + +<p>Several relocations exist to allow the link editor to perform GOT data +references. The <code>R_OR1K_GOT16</code> relocation can obtained by enclosing an +operand inside of ‘<samp>got</samp>’. For example, assuming the GOT base is in +register <code>r17</code>. +</p> +<div class="example"> +<pre class="example">l.lwz r19, got(a)(r17) +l.lwz r21, 0(r19) +</pre></div> + +<p>Also, several relocations exist for local GOT references. The +<code>R_OR1K_GOTOFF_AHI16</code> relocation can obtained by enclosing an operand +inside of ‘<samp>gotoffha</samp>’. Likewise, <code>R_OR1K_GOTOFF_LO16</code> and +<code>R_OR1K_GOTOFF_SLO16</code> can be obtained by enclosing an operand inside of +‘<samp>gotofflo</samp>’. For example, assuming the GOT base is in register +<code>rl7</code>: +</p> +<div class="example"> +<pre class="example">l.movhi r19, gotoffha(symbol) +l.add r19, r19, r17 +l.lwz r19, gotofflo(symbol)(r19) +</pre></div> + +<p>The above PC relative relocations use a <code>l.jal</code> (jump) instruction +and reading of the link register to load the PC. OpenRISC also supports +page offset PC relative locations without a jump instruction using the +<code>l.adrp</code> instruction. By default the <code>l.adrp</code> instruction will +create an <code>R_OR1K_PCREL_PG21</code> relocation. +Likewise, <code>BFD_RELOC_OR1K_LO13</code> and <code>BFD_RELOC_OR1K_SLO13</code> can +be obtained by enclosing an operand inside of ‘<samp>po</samp>’. For example: +</p> +<div class="example"> +<pre class="example">l.adrp r3, symbol +l.ori r4, r3, po(symbol) +l.lbz r5, po(symbol)(r3) +l.sb po(symbol)(r3), r6 +</pre></div> + +<p>Likewise the page offset relocations can be used with GOT references. The +relocation <code>R_OR1K_GOT_PG21</code> can be obtained by enclosing an +<code>l.adrp</code> immediate operand inside of ‘<samp>got</samp>’. Likewise, +<code>R_OR1K_GOT_LO13</code> can be obtained by enclosing an operand inside of +‘<samp>gotpo</samp>’. For example to load the value of a GOT symbol into register +‘<samp>r5</samp>’ we can do: +</p> +<div class="example"> +<pre class="example">l.adrp r17, got(_GLOBAL_OFFSET_TABLE_) +l.lwz r5, gotpo(symbol)(r17) +</pre></div> + +<p>There are many relocations that can be requested for access to +thread local storage variables. All of the OpenRISC TLS mnemonics +are supported: +</p> +<ul> +<li> <code>R_OR1K_TLS_GD_HI16</code> is requested using ‘<samp>tlsgdhi</samp>’. +</li><li> <code>R_OR1K_TLS_GD_LO16</code> is requested using ‘<samp>tlsgdlo</samp>’. +</li><li> <code>R_OR1K_TLS_GD_PG21</code> is requested using ‘<samp>tldgd</samp>’. +</li><li> <code>R_OR1K_TLS_GD_LO13</code> is requested using ‘<samp>tlsgdpo</samp>’. + +</li><li> <code>R_OR1K_TLS_LDM_HI16</code> is requested using ‘<samp>tlsldmhi</samp>’. +</li><li> <code>R_OR1K_TLS_LDM_LO16</code> is requested using ‘<samp>tlsldmlo</samp>’. +</li><li> <code>R_OR1K_TLS_LDM_PG21</code> is requested using ‘<samp>tldldm</samp>’. +</li><li> <code>R_OR1K_TLS_LDM_LO13</code> is requested using ‘<samp>tlsldmpo</samp>’. + +</li><li> <code>R_OR1K_TLS_LDO_HI16</code> is requested using ‘<samp>dtpoffhi</samp>’. +</li><li> <code>R_OR1K_TLS_LDO_LO16</code> is requested using ‘<samp>dtpofflo</samp>’. + +</li><li> <code>R_OR1K_TLS_IE_HI16</code> is requested using ‘<samp>gottpoffhi</samp>’. +</li><li> <code>R_OR1K_TLS_IE_AHI16</code> is requested using ‘<samp>gottpoffha</samp>’. +</li><li> <code>R_OR1K_TLS_IE_LO16</code> is requested using ‘<samp>gottpofflo</samp>’. +</li><li> <code>R_OR1K_TLS_IE_PG21</code> is requested using ‘<samp>gottp</samp>’. +</li><li> <code>R_OR1K_TLS_IE_LO13</code> is requested using ‘<samp>gottppo</samp>’. + +</li><li> <code>R_OR1K_TLS_LE_HI16</code> is requested using ‘<samp>tpoffhi</samp>’. +</li><li> <code>R_OR1K_TLS_LE_AHI16</code> is requested using ‘<samp>tpoffha</samp>’. +</li><li> <code>R_OR1K_TLS_LE_LO16</code> is requested using ‘<samp>tpofflo</samp>’. +</li><li> <code>R_OR1K_TLS_LE_SLO16</code> also is requested using ‘<samp>tpofflo</samp>’ +depending on the instruction format. +</li></ul> + +<p>Here are some example TLS model sequences. +</p> +<p>First, General Dynamic: +</p> +<div class="example"> +<pre class="example">l.movhi r17, tlsgdhi(symbol) +l.ori r17, r17, tlsgdlo(symbol) +l.add r17, r17, r16 +l.or r3, r17, r17 +l.jal plt(__tls_get_addr) + l.nop +</pre></div> + +<p>Initial Exec: +</p> +<div class="example"> +<pre class="example">l.movhi r17, gottpoffhi(symbol) +l.add r17, r17, r16 +l.lwz r17, gottpofflo(symbol)(r17) +l.add r17, r17, r10 +l.lbs r17, 0(r17) +</pre></div> + +<p>And finally, Local Exec: +</p> +<div class="example"> +<pre class="example">l.movhi r17, tpoffha(symbol) +l.add r17, r17, r10 +l.addi r17, r17, tpofflo(symbol) +l.lbs r17, 0(r17) +</pre></div> + +<hr> +<a name="OpenRISC_002dFloat"></a> +<div class="header"> +<p> +Next: <a href="#OpenRISC_002dDirectives" accesskey="n" rel="next">OpenRISC-Directives</a>, Previous: <a href="#OpenRISC_002dSyntax" accesskey="p" rel="previous">OpenRISC-Syntax</a>, Up: <a href="#OpenRISC_002dDependent" accesskey="u" rel="up">OpenRISC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-11"></a> +<h4 class="subsection">9.33.2 Floating Point</h4> + +<a name="index-floating-point_002c-OPENRISC-_0028IEEE_0029"></a> +<a name="index-OPENRISC-floating-point-_0028IEEE_0029"></a> +<p>OpenRISC uses <small>IEEE</small> floating-point numbers. +</p> +<hr> +<a name="OpenRISC_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#OpenRISC_002dOpcodes" accesskey="n" rel="next">OpenRISC-Opcodes</a>, Previous: <a href="#OpenRISC_002dFloat" accesskey="p" rel="previous">OpenRISC-Float</a>, Up: <a href="#OpenRISC_002dDependent" accesskey="u" rel="up">OpenRISC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="OpenRISC-Machine-Directives"></a> +<h4 class="subsection">9.33.3 OpenRISC Machine Directives</h4> + +<a name="index-OPENRISC-machine-directives"></a> +<a name="index-machine-directives_002c-OPENRISC"></a> +<p>The OpenRISC version of <code>as</code> supports the following additional +machine directives: +</p> +<dl compact="compact"> +<dd><a name="index-align-directive_002c-OpenRISC"></a> +</dd> +<dt><code>.align</code></dt> +<dd><p>This must be followed by the desired alignment in bytes. +</p> +<a name="index-word-directive_002c-OpenRISC"></a> +</dd> +<dt><code>.word</code></dt> +<dd><p>On the OpenRISC, the <code>.word</code> directive produces a 32 bit value. +</p> +<a name="index-nodelay-directive_002c-OpenRISC"></a> +</dd> +<dt><code>.nodelay</code></dt> +<dd><p>On the OpenRISC, the <code>.nodelay</code> directive sets a flag in elf binaries +indicating that the binary is generated catering for no delay slots. +</p> +<a name="index-proc-directive_002c-OpenRISC"></a> +</dd> +<dt><code>.proc</code></dt> +<dd><p>This directive is ignored. Any text following it on the same +line is also ignored. +</p> +<a name="index-endproc-directive_002c-OpenRISC"></a> +</dd> +<dt><code>.endproc</code></dt> +<dd><p>This directive is ignored. Any text following it on the same +line is also ignored. +</p></dd> +</dl> + +<hr> +<a name="OpenRISC_002dOpcodes"></a> +<div class="header"> +<p> +Previous: <a href="#OpenRISC_002dDirectives" accesskey="p" rel="previous">OpenRISC-Directives</a>, Up: <a href="#OpenRISC_002dDependent" accesskey="u" rel="up">OpenRISC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-16"></a> +<h4 class="subsection">9.33.4 Opcodes</h4> + +<a name="index-OpenRISC-opcode-summary"></a> +<a name="index-opcode-summary_002c-OpenRISC"></a> +<a name="index-mnemonics_002c-OpenRISC"></a> +<a name="index-instruction-summary_002c-LM32-1"></a> +<p>For detailed information on the OpenRISC machine instruction set, see +<a href="http://www.openrisc.io/architecture/">http://www.openrisc.io/architecture/</a>. +</p> +<p><code>as</code> implements all the standard OpenRISC opcodes. +</p> +<hr> +<a name="PDP_002d11_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#PJ_002dDependent" accesskey="n" rel="next">PJ-Dependent</a>, Previous: <a href="#OpenRISC_002dDependent" accesskey="p" rel="previous">OpenRISC-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="PDP_002d11-Dependent-Features"></a> +<h3 class="section">9.34 PDP-11 Dependent Features</h3> + +<a name="index-PDP_002d11-support"></a> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#PDP_002d11_002dOptions" accesskey="1">PDP-11-Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#PDP_002d11_002dPseudos" accesskey="2">PDP-11-Pseudos</a>:</td><td> </td><td align="left" valign="top">Assembler Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#PDP_002d11_002dSyntax" accesskey="3">PDP-11-Syntax</a>:</td><td> </td><td align="left" valign="top">DEC Syntax versus BSD Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#PDP_002d11_002dMnemonics" accesskey="4">PDP-11-Mnemonics</a>:</td><td> </td><td align="left" valign="top">Instruction Naming +</td></tr> +<tr><td align="left" valign="top">• <a href="#PDP_002d11_002dSynthetic" accesskey="5">PDP-11-Synthetic</a>:</td><td> </td><td align="left" valign="top">Synthetic Instructions +</td></tr> +</table> + +<hr> +<a name="PDP_002d11_002dOptions"></a> +<div class="header"> +<p> +Next: <a href="#PDP_002d11_002dPseudos" accesskey="n" rel="next">PDP-11-Pseudos</a>, Up: <a href="#PDP_002d11_002dDependent" accesskey="u" rel="up">PDP-11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-17"></a> +<h4 class="subsection">9.34.1 Options</h4> + +<a name="index-options-for-PDP_002d11"></a> + +<p>The PDP-11 version of <code>as</code> has a rich set of machine +dependent options. +</p> +<a name="Code-Generation-Options"></a> +<h4 class="subsubsection">9.34.1.1 Code Generation Options</h4> + +<dl compact="compact"> +<dd><a name="index-_002dmpic"></a> +<a name="index-_002dmno_002dpic"></a> +</dd> +<dt><code>-mpic | -mno-pic</code></dt> +<dd><p>Generate position-independent (or position-dependent) code. +</p> +<p>The default is to generate position-independent code. +</p></dd> +</dl> + +<a name="Instruction-Set-Extension-Options"></a> +<h4 class="subsubsection">9.34.1.2 Instruction Set Extension Options</h4> + +<p>These options enables or disables the use of extensions over the base +line instruction set as introduced by the first PDP-11 CPU: the KA11. +Most options come in two variants: a <code>-m</code><var>extension</var> that +enables <var>extension</var>, and a <code>-mno-</code><var>extension</var> that disables +<var>extension</var>. +</p> +<p>The default is to enable all extensions. +</p> +<dl compact="compact"> +<dd><a name="index-_002dmall"></a> +<a name="index-_002dmall_002dextensions"></a> +</dd> +<dt><code>-mall | -mall-extensions</code></dt> +<dd><p>Enable all instruction set extensions. +</p> +<a name="index-_002dmno_002dextensions"></a> +</dd> +<dt><code>-mno-extensions</code></dt> +<dd><p>Disable all instruction set extensions. +</p> +<a name="index-_002dmcis"></a> +<a name="index-_002dmno_002dcis"></a> +</dd> +<dt><code>-mcis | -mno-cis</code></dt> +<dd><p>Enable (or disable) the use of the commercial instruction set, which +consists of these instructions: <code>ADDNI</code>, <code>ADDN</code>, <code>ADDPI</code>, +<code>ADDP</code>, <code>ASHNI</code>, <code>ASHN</code>, <code>ASHPI</code>, <code>ASHP</code>, +<code>CMPCI</code>, <code>CMPC</code>, <code>CMPNI</code>, <code>CMPN</code>, <code>CMPPI</code>, +<code>CMPP</code>, <code>CVTLNI</code>, <code>CVTLN</code>, <code>CVTLPI</code>, <code>CVTLP</code>, +<code>CVTNLI</code>, <code>CVTNL</code>, <code>CVTNPI</code>, <code>CVTNP</code>, <code>CVTPLI</code>, +<code>CVTPL</code>, <code>CVTPNI</code>, <code>CVTPN</code>, <code>DIVPI</code>, <code>DIVP</code>, +<code>L2DR</code>, <code>L3DR</code>, <code>LOCCI</code>, <code>LOCC</code>, <code>MATCI</code>, +<code>MATC</code>, <code>MOVCI</code>, <code>MOVC</code>, <code>MOVRCI</code>, <code>MOVRC</code>, +<code>MOVTCI</code>, <code>MOVTC</code>, <code>MULPI</code>, <code>MULP</code>, <code>SCANCI</code>, +<code>SCANC</code>, <code>SKPCI</code>, <code>SKPC</code>, <code>SPANCI</code>, <code>SPANC</code>, +<code>SUBNI</code>, <code>SUBN</code>, <code>SUBPI</code>, and <code>SUBP</code>. +</p> +<a name="index-_002dmcsm"></a> +<a name="index-_002dmno_002dcsm"></a> +</dd> +<dt><code>-mcsm | -mno-csm</code></dt> +<dd><p>Enable (or disable) the use of the <code>CSM</code> instruction. +</p> +<a name="index-_002dmeis"></a> +<a name="index-_002dmno_002deis"></a> +</dd> +<dt><code>-meis | -mno-eis</code></dt> +<dd><p>Enable (or disable) the use of the extended instruction set, which +consists of these instructions: <code>ASHC</code>, <code>ASH</code>, <code>DIV</code>, +<code>MARK</code>, <code>MUL</code>, <code>RTT</code>, <code>SOB</code> <code>SXT</code>, and +<code>XOR</code>. +</p> +<a name="index-_002dmfis"></a> +<a name="index-_002dmno_002dfis"></a> +<a name="index-_002dmkev11"></a> +<a name="index-_002dmkev11-1"></a> +<a name="index-_002dmno_002dkev11"></a> +</dd> +<dt><code>-mfis | -mkev11</code></dt> +<dt><code>-mno-fis | -mno-kev11</code></dt> +<dd><p>Enable (or disable) the use of the KEV11 floating-point instructions: +<code>FADD</code>, <code>FDIV</code>, <code>FMUL</code>, and <code>FSUB</code>. +</p> +<a name="index-_002dmfpp"></a> +<a name="index-_002dmno_002dfpp"></a> +<a name="index-_002dmfpu"></a> +<a name="index-_002dmno_002dfpu"></a> +<a name="index-_002dmfp_002d11"></a> +<a name="index-_002dmno_002dfp_002d11"></a> +</dd> +<dt><code>-mfpp | -mfpu | -mfp-11</code></dt> +<dt><code>-mno-fpp | -mno-fpu | -mno-fp-11</code></dt> +<dd><p>Enable (or disable) the use of FP-11 floating-point instructions: +<code>ABSF</code>, <code>ADDF</code>, <code>CFCC</code>, <code>CLRF</code>, <code>CMPF</code>, +<code>DIVF</code>, <code>LDCFF</code>, <code>LDCIF</code>, <code>LDEXP</code>, <code>LDF</code>, +<code>LDFPS</code>, <code>MODF</code>, <code>MULF</code>, <code>NEGF</code>, <code>SETD</code>, +<code>SETF</code>, <code>SETI</code>, <code>SETL</code>, <code>STCFF</code>, <code>STCFI</code>, +<code>STEXP</code>, <code>STF</code>, <code>STFPS</code>, <code>STST</code>, <code>SUBF</code>, and +<code>TSTF</code>. +</p> +<a name="index-_002dmlimited_002deis"></a> +<a name="index-_002dmno_002dlimited_002deis"></a> +</dd> +<dt><code>-mlimited-eis | -mno-limited-eis</code></dt> +<dd><p>Enable (or disable) the use of the limited extended instruction set: +<code>MARK</code>, <code>RTT</code>, <code>SOB</code>, <code>SXT</code>, and <code>XOR</code>. +</p> +<p>The -mno-limited-eis options also implies -mno-eis. +</p> +<a name="index-_002dmmfpt"></a> +<a name="index-_002dmno_002dmfpt"></a> +</dd> +<dt><code>-mmfpt | -mno-mfpt</code></dt> +<dd><p>Enable (or disable) the use of the <code>MFPT</code> instruction. +</p> +<a name="index-_002dmmutiproc"></a> +<a name="index-_002dmno_002dmutiproc"></a> +</dd> +<dt><code>-mmultiproc | -mno-multiproc</code></dt> +<dd><p>Enable (or disable) the use of multiprocessor instructions: <code>TSTSET</code> and +<code>WRTLCK</code>. +</p> +<a name="index-_002dmmxps"></a> +<a name="index-_002dmno_002dmxps"></a> +</dd> +<dt><code>-mmxps | -mno-mxps</code></dt> +<dd><p>Enable (or disable) the use of the <code>MFPS</code> and <code>MTPS</code> instructions. +</p> +<a name="index-_002dmspl"></a> +<a name="index-_002dmno_002dspl"></a> +</dd> +<dt><code>-mspl | -mno-spl</code></dt> +<dd><p>Enable (or disable) the use of the <code>SPL</code> instruction. +</p> +<a name="index-_002dmmicrocode"></a> +<a name="index-_002dmno_002dmicrocode"></a> +<p>Enable (or disable) the use of the microcode instructions: <code>LDUB</code>, +<code>MED</code>, and <code>XFC</code>. +</p></dd> +</dl> + +<a name="CPU-Model-Options"></a> +<h4 class="subsubsection">9.34.1.3 CPU Model Options</h4> + +<p>These options enable the instruction set extensions supported by a +particular CPU, and disables all other extensions. +</p> +<dl compact="compact"> +<dd><a name="index-_002dmka11"></a> +</dd> +<dt><code>-mka11</code></dt> +<dd><p>KA11 CPU. Base line instruction set only. +</p> +<a name="index-_002dmkb11"></a> +</dd> +<dt><code>-mkb11</code></dt> +<dd><p>KB11 CPU. Enable extended instruction set and <code>SPL</code>. +</p> +<a name="index-_002dmkd11a"></a> +</dd> +<dt><code>-mkd11a</code></dt> +<dd><p>KD11-A CPU. Enable limited extended instruction set. +</p> +<a name="index-_002dmkd11b"></a> +</dd> +<dt><code>-mkd11b</code></dt> +<dd><p>KD11-B CPU. Base line instruction set only. +</p> +<a name="index-_002dmkd11d"></a> +</dd> +<dt><code>-mkd11d</code></dt> +<dd><p>KD11-D CPU. Base line instruction set only. +</p> +<a name="index-_002dmkd11e"></a> +</dd> +<dt><code>-mkd11e</code></dt> +<dd><p>KD11-E CPU. Enable extended instruction set, <code>MFPS</code>, and <code>MTPS</code>. +</p> +<a name="index-_002dmkd11f"></a> +<a name="index-_002dmkd11h"></a> +<a name="index-_002dmkd11q"></a> +</dd> +<dt><code>-mkd11f | -mkd11h | -mkd11q</code></dt> +<dd><p>KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction set, +<code>MFPS</code>, and <code>MTPS</code>. +</p> +<a name="index-_002dmkd11k"></a> +</dd> +<dt><code>-mkd11k</code></dt> +<dd><p>KD11-K CPU. Enable extended instruction set, <code>LDUB</code>, <code>MED</code>, +<code>MFPS</code>, <code>MFPT</code>, <code>MTPS</code>, and <code>XFC</code>. +</p> +<a name="index-_002dmkd11z"></a> +</dd> +<dt><code>-mkd11z</code></dt> +<dd><p>KD11-Z CPU. Enable extended instruction set, <code>CSM</code>, <code>MFPS</code>, +<code>MFPT</code>, <code>MTPS</code>, and <code>SPL</code>. +</p> +<a name="index-_002dmf11"></a> +</dd> +<dt><code>-mf11</code></dt> +<dd><p>F11 CPU. Enable extended instruction set, <code>MFPS</code>, <code>MFPT</code>, and +<code>MTPS</code>. +</p> +<a name="index-_002dmj11"></a> +</dd> +<dt><code>-mj11</code></dt> +<dd><p>J11 CPU. Enable extended instruction set, <code>CSM</code>, <code>MFPS</code>, +<code>MFPT</code>, <code>MTPS</code>, <code>SPL</code>, <code>TSTSET</code>, and <code>WRTLCK</code>. +</p> +<a name="index-_002dmt11"></a> +</dd> +<dt><code>-mt11</code></dt> +<dd><p>T11 CPU. Enable limited extended instruction set, <code>MFPS</code>, and +<code>MTPS</code>. +</p></dd> +</dl> + +<a name="Machine-Model-Options"></a> +<h4 class="subsubsection">9.34.1.4 Machine Model Options</h4> + +<p>These options enable the instruction set extensions supported by a +particular machine model, and disables all other extensions. +</p> +<dl compact="compact"> +<dd><a name="index-_002dm11_002f03"></a> +</dd> +<dt><code>-m11/03</code></dt> +<dd><p>Same as <code>-mkd11f</code>. +</p> +<a name="index-_002dm11_002f04"></a> +</dd> +<dt><code>-m11/04</code></dt> +<dd><p>Same as <code>-mkd11d</code>. +</p> +<a name="index-_002dm11_002f05"></a> +<a name="index-_002dm11_002f10"></a> +</dd> +<dt><code>-m11/05 | -m11/10</code></dt> +<dd><p>Same as <code>-mkd11b</code>. +</p> +<a name="index-_002dm11_002f15"></a> +<a name="index-_002dm11_002f20"></a> +</dd> +<dt><code>-m11/15 | -m11/20</code></dt> +<dd><p>Same as <code>-mka11</code>. +</p> +<a name="index-_002dm11_002f21"></a> +</dd> +<dt><code>-m11/21</code></dt> +<dd><p>Same as <code>-mt11</code>. +</p> +<a name="index-_002dm11_002f23"></a> +<a name="index-_002dm11_002f24"></a> +</dd> +<dt><code>-m11/23 | -m11/24</code></dt> +<dd><p>Same as <code>-mf11</code>. +</p> +<a name="index-_002dm11_002f34"></a> +</dd> +<dt><code>-m11/34</code></dt> +<dd><p>Same as <code>-mkd11e</code>. +</p> +<a name="index-_002dm11_002f34a"></a> +</dd> +<dt><code>-m11/34a</code></dt> +<dd><p>Ame as <code>-mkd11e</code> <code>-mfpp</code>. +</p> +<a name="index-_002dm11_002f35"></a> +<a name="index-_002dm11_002f40"></a> +</dd> +<dt><code>-m11/35 | -m11/40</code></dt> +<dd><p>Same as <code>-mkd11a</code>. +</p> +<a name="index-_002dm11_002f44"></a> +</dd> +<dt><code>-m11/44</code></dt> +<dd><p>Same as <code>-mkd11z</code>. +</p> +<a name="index-_002dm11_002f45"></a> +<a name="index-_002dm11_002f50"></a> +<a name="index-_002dm11_002f55"></a> +<a name="index-_002dm11_002f70"></a> +</dd> +<dt><code>-m11/45 | -m11/50 | -m11/55 | -m11/70</code></dt> +<dd><p>Same as <code>-mkb11</code>. +</p> +<a name="index-_002dm11_002f53"></a> +<a name="index-_002dm11_002f73"></a> +<a name="index-_002dm11_002f83"></a> +<a name="index-_002dm11_002f84"></a> +<a name="index-_002dm11_002f93"></a> +<a name="index-_002dm11_002f94"></a> +</dd> +<dt><code>-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94</code></dt> +<dd><p>Same as <code>-mj11</code>. +</p> +<a name="index-_002dm11_002f60"></a> +</dd> +<dt><code>-m11/60</code></dt> +<dd><p>Same as <code>-mkd11k</code>. +</p></dd> +</dl> + +<hr> +<a name="PDP_002d11_002dPseudos"></a> +<div class="header"> +<p> +Next: <a href="#PDP_002d11_002dSyntax" accesskey="n" rel="next">PDP-11-Syntax</a>, Previous: <a href="#PDP_002d11_002dOptions" accesskey="p" rel="previous">PDP-11-Options</a>, Up: <a href="#PDP_002d11_002dDependent" accesskey="u" rel="up">PDP-11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives-4"></a> +<h4 class="subsection">9.34.2 Assembler Directives</h4> + +<p>The PDP-11 version of <code>as</code> has a few machine +dependent assembler directives. +</p> +<dl compact="compact"> +<dt><code>.bss</code></dt> +<dd><p>Switch to the <code>bss</code> section. +</p> +</dd> +<dt><code>.even</code></dt> +<dd><p>Align the location counter to an even number. +</p></dd> +</dl> + +<hr> +<a name="PDP_002d11_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#PDP_002d11_002dMnemonics" accesskey="n" rel="next">PDP-11-Mnemonics</a>, Previous: <a href="#PDP_002d11_002dPseudos" accesskey="p" rel="previous">PDP-11-Pseudos</a>, Up: <a href="#PDP_002d11_002dDependent" accesskey="u" rel="up">PDP-11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="PDP_002d11-Assembly-Language-Syntax"></a> +<h4 class="subsection">9.34.3 PDP-11 Assembly Language Syntax</h4> + +<a name="index-PDP_002d11-syntax"></a> + +<a name="index-DEC-syntax"></a> +<a name="index-BSD-syntax"></a> +<p><code>as</code> supports both DEC syntax and BSD syntax. The only +difference is that in DEC syntax, a <code>#</code> character is used to denote +an immediate constants, while in BSD syntax the character for this +purpose is <code>$</code>. +</p> +<a name="index-PDP_002d11-general_002dpurpose-register-syntax"></a> +<p>general-purpose registers are named <code>r0</code> through <code>r7</code>. +Mnemonic alternatives for <code>r6</code> and <code>r7</code> are <code>sp</code> and +<code>pc</code>, respectively. +</p> +<a name="index-PDP_002d11-floating_002dpoint-register-syntax"></a> +<p>Floating-point registers are named <code>ac0</code> through <code>ac3</code>, or +alternatively <code>fr0</code> through <code>fr3</code>. +</p> +<a name="index-PDP_002d11-comments"></a> +<p>Comments are started with a <code>#</code> or a <code>/</code> character, and extend +to the end of the line. (FIXME: clash with immediates?) +</p> +<a name="index-PDP_002d11-line-separator"></a> +<p>Multiple statements on the same line can be separated by the ‘<samp>;</samp>’ character. +</p> +<hr> +<a name="PDP_002d11_002dMnemonics"></a> +<div class="header"> +<p> +Next: <a href="#PDP_002d11_002dSynthetic" accesskey="n" rel="next">PDP-11-Synthetic</a>, Previous: <a href="#PDP_002d11_002dSyntax" accesskey="p" rel="previous">PDP-11-Syntax</a>, Up: <a href="#PDP_002d11_002dDependent" accesskey="u" rel="up">PDP-11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-Naming-1"></a> +<h4 class="subsection">9.34.4 Instruction Naming</h4> + +<a name="index-PDP_002d11-instruction-naming"></a> + +<p>Some instructions have alternative names. +</p> +<dl compact="compact"> +<dt><code>BCC</code></dt> +<dd><p><code>BHIS</code> +</p> +</dd> +<dt><code>BCS</code></dt> +<dd><p><code>BLO</code> +</p> +</dd> +<dt><code>L2DR</code></dt> +<dd><p><code>L2D</code> +</p> +</dd> +<dt><code>L3DR</code></dt> +<dd><p><code>L3D</code> +</p> +</dd> +<dt><code>SYS</code></dt> +<dd><p><code>TRAP</code> +</p></dd> +</dl> + +<hr> +<a name="PDP_002d11_002dSynthetic"></a> +<div class="header"> +<p> +Previous: <a href="#PDP_002d11_002dMnemonics" accesskey="p" rel="previous">PDP-11-Mnemonics</a>, Up: <a href="#PDP_002d11_002dDependent" accesskey="u" rel="up">PDP-11-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Synthetic-Instructions"></a> +<h4 class="subsection">9.34.5 Synthetic Instructions</h4> + +<p>The <code>JBR</code> and <code>J</code><var>CC</var> synthetic instructions are not +supported yet. +</p> +<hr> +<a name="PJ_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#PPC_002dDependent" accesskey="n" rel="next">PPC-Dependent</a>, Previous: <a href="#PDP_002d11_002dDependent" accesskey="p" rel="previous">PDP-11-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="picoJava-Dependent-Features"></a> +<h3 class="section">9.35 picoJava Dependent Features</h3> + +<a name="index-PJ-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#PJ-Options" accesskey="1">PJ Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#PJ-Syntax" accesskey="2">PJ Syntax</a>:</td><td> </td><td align="left" valign="top">PJ Syntax +</td></tr> +</table> + +<hr> +<a name="PJ-Options"></a> +<div class="header"> +<p> +Next: <a href="#PJ-Syntax" accesskey="n" rel="next">PJ Syntax</a>, Up: <a href="#PJ_002dDependent" accesskey="u" rel="up">PJ-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-18"></a> +<h4 class="subsection">9.35.1 Options</h4> + +<a name="index-PJ-options"></a> +<a name="index-options_002c-PJ"></a> +<p><code>as</code> has two additional command-line options for the picoJava +architecture. +</p><dl compact="compact"> +<dt><code>-ml</code></dt> +<dd><p>This option selects little endian data output. +</p> +</dd> +<dt><code>-mb</code></dt> +<dd><p>This option selects big endian data output. +</p></dd> +</dl> + +<hr> +<a name="PJ-Syntax"></a> +<div class="header"> +<p> +Previous: <a href="#PJ-Options" accesskey="p" rel="previous">PJ Options</a>, Up: <a href="#PJ_002dDependent" accesskey="u" rel="up">PJ-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="PJ-Syntax-1"></a> +<h4 class="subsection">9.35.2 PJ Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#PJ_002dChars" accesskey="1">PJ-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="PJ_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#PJ-Syntax" accesskey="u" rel="up">PJ Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-27"></a> +<h4 class="subsubsection">9.35.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-PJ"></a> +<a name="index-PJ-line-comment-character"></a> +<p>The presence of a ‘<samp>!</samp>’ or ‘<samp>/</samp>’ on a line indicates the start +of a comment that extends to the end of the current line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-PJ"></a> +<a name="index-statement-separator_002c-PJ"></a> +<a name="index-PJ-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="PPC_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#PRU_002dDependent" accesskey="n" rel="next">PRU-Dependent</a>, Previous: <a href="#PJ_002dDependent" accesskey="p" rel="previous">PJ-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="PowerPC-Dependent-Features"></a> +<h3 class="section">9.36 PowerPC Dependent Features</h3> + +<a name="index-PowerPC-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#PowerPC_002dOpts" accesskey="1">PowerPC-Opts</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#PowerPC_002dPseudo" accesskey="2">PowerPC-Pseudo</a>:</td><td> </td><td align="left" valign="top">PowerPC Assembler Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#PowerPC_002dSyntax" accesskey="3">PowerPC-Syntax</a>:</td><td> </td><td align="left" valign="top">PowerPC Syntax +</td></tr> +</table> + +<hr> +<a name="PowerPC_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#PowerPC_002dPseudo" accesskey="n" rel="next">PowerPC-Pseudo</a>, Up: <a href="#PPC_002dDependent" accesskey="u" rel="up">PPC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-19"></a> +<h4 class="subsection">9.36.1 Options</h4> + +<a name="index-options-for-PowerPC"></a> +<a name="index-PowerPC-options"></a> +<a name="index-architectures_002c-PowerPC"></a> +<a name="index-PowerPC-architectures"></a> +<p>The PowerPC chip family includes several successive levels, using the same +core instruction set, but including a few additional instructions at +each level. There are exceptions to this however. For details on what +instructions each variant supports, please see the chip’s architecture +reference manual. +</p> +<p>The following table lists all available PowerPC options. +</p> +<dl compact="compact"> +<dt><code>-a32</code></dt> +<dd><p>Generate ELF32 or XCOFF32. +</p> +</dd> +<dt><code>-a64</code></dt> +<dd><p>Generate ELF64 or XCOFF64. +</p> +</dd> +<dt><code>-K PIC</code></dt> +<dd><p>Set EF_PPC_RELOCATABLE_LIB in ELF flags. +</p> +</dd> +<dt><code>-mpwrx | -mpwr2</code></dt> +<dd><p>Generate code for POWER/2 (RIOS2). +</p> +</dd> +<dt><code>-mpwr</code></dt> +<dd><p>Generate code for POWER (RIOS1) +</p> +</dd> +<dt><code>-m601</code></dt> +<dd><p>Generate code for PowerPC 601. +</p> +</dd> +<dt><code>-mppc, -mppc32, -m603, -m604</code></dt> +<dd><p>Generate code for PowerPC 603/604. +</p> +</dd> +<dt><code>-m403, -m405</code></dt> +<dd><p>Generate code for PowerPC 403/405. +</p> +</dd> +<dt><code>-m440</code></dt> +<dd><p>Generate code for PowerPC 440. BookE and some 405 instructions. +</p> +</dd> +<dt><code>-m464</code></dt> +<dd><p>Generate code for PowerPC 464. +</p> +</dd> +<dt><code>-m476</code></dt> +<dd><p>Generate code for PowerPC 476. +</p> +</dd> +<dt><code>-m7400, -m7410, -m7450, -m7455</code></dt> +<dd><p>Generate code for PowerPC 7400/7410/7450/7455. +</p> +</dd> +<dt><code>-m750cl, -mgekko, -mbroadway</code></dt> +<dd><p>Generate code for PowerPC 750CL/Gekko/Broadway. +</p> +</dd> +<dt><code>-m821, -m850, -m860</code></dt> +<dd><p>Generate code for PowerPC 821/850/860. +</p> +</dd> +<dt><code>-mppc64, -m620</code></dt> +<dd><p>Generate code for PowerPC 620/625/630. +</p> +</dd> +<dt><code>-me200z2, -me200z4</code></dt> +<dd><p>Generate code for e200 variants, e200z2 with LSP, e200z4 with SPE. +</p> +</dd> +<dt><code>-me300</code></dt> +<dd><p>Generate code for PowerPC e300 family. +</p> +</dd> +<dt><code>-me500, -me500x2</code></dt> +<dd><p>Generate code for Motorola e500 core complex. +</p> +</dd> +<dt><code>-me500mc</code></dt> +<dd><p>Generate code for Freescale e500mc core complex. +</p> +</dd> +<dt><code>-me500mc64</code></dt> +<dd><p>Generate code for Freescale e500mc64 core complex. +</p> +</dd> +<dt><code>-me5500</code></dt> +<dd><p>Generate code for Freescale e5500 core complex. +</p> +</dd> +<dt><code>-me6500</code></dt> +<dd><p>Generate code for Freescale e6500 core complex. +</p> +</dd> +<dt><code>-mlsp</code></dt> +<dd><p>Enable LSP instructions. (Disables SPE and SPE2.) +</p> +</dd> +<dt><code>-mspe</code></dt> +<dd><p>Generate code for Motorola SPE instructions. (Disables LSP.) +</p> +</dd> +<dt><code>-mspe2</code></dt> +<dd><p>Generate code for Freescale SPE2 instructions. (Disables LSP.) +</p> +</dd> +<dt><code>-mtitan</code></dt> +<dd><p>Generate code for AppliedMicro Titan core complex. +</p> +</dd> +<dt><code>-mppc64bridge</code></dt> +<dd><p>Generate code for PowerPC 64, including bridge insns. +</p> +</dd> +<dt><code>-mbooke</code></dt> +<dd><p>Generate code for 32-bit BookE. +</p> +</dd> +<dt><code>-ma2</code></dt> +<dd><p>Generate code for A2 architecture. +</p> +</dd> +<dt><code>-maltivec</code></dt> +<dd><p>Generate code for processors with AltiVec instructions. +</p> +</dd> +<dt><code>-mvle</code></dt> +<dd><p>Generate code for Freescale PowerPC VLE instructions. +</p> +</dd> +<dt><code>-mvsx</code></dt> +<dd><p>Generate code for processors with Vector-Scalar (VSX) instructions. +</p> +</dd> +<dt><code>-mhtm</code></dt> +<dd><p>Generate code for processors with Hardware Transactional Memory instructions. +</p> +</dd> +<dt><code>-mpower4, -mpwr4</code></dt> +<dd><p>Generate code for Power4 architecture. +</p> +</dd> +<dt><code>-mpower5, -mpwr5, -mpwr5x</code></dt> +<dd><p>Generate code for Power5 architecture. +</p> +</dd> +<dt><code>-mpower6, -mpwr6</code></dt> +<dd><p>Generate code for Power6 architecture. +</p> +</dd> +<dt><code>-mpower7, -mpwr7</code></dt> +<dd><p>Generate code for Power7 architecture. +</p> +</dd> +<dt><code>-mpower8, -mpwr8</code></dt> +<dd><p>Generate code for Power8 architecture. +</p> +</dd> +<dt><code>-mpower9, -mpwr9</code></dt> +<dd><p>Generate code for Power9 architecture. +</p> +</dd> +<dt><code>-mpower10, -mpwr10</code></dt> +<dd><p>Generate code for Power10 architecture. +</p> +</dd> +<dt><code>-mfuture</code></dt> +<dd><p>Generate code for ’future’ architecture. +</p> +</dd> +<dt><code>-mcell</code></dt> +<dt><code>-mcell</code></dt> +<dd><p>Generate code for Cell Broadband Engine architecture. +</p> +</dd> +<dt><code>-mcom</code></dt> +<dd><p>Generate code Power/PowerPC common instructions. +</p> +</dd> +<dt><code>-many</code></dt> +<dd><p>Generate code for any architecture (PWR/PWRX/PPC). +</p> +</dd> +<dt><code>-mregnames</code></dt> +<dd><p>Allow symbolic names for registers. +</p> +</dd> +<dt><code>-mno-regnames</code></dt> +<dd><p>Do not allow symbolic names for registers. +</p> +</dd> +<dt><code>-mrelocatable</code></dt> +<dd><p>Support for GCC’s -mrelocatable option. +</p> +</dd> +<dt><code>-mrelocatable-lib</code></dt> +<dd><p>Support for GCC’s -mrelocatable-lib option. +</p> +</dd> +<dt><code>-memb</code></dt> +<dd><p>Set PPC_EMB bit in ELF flags. +</p> +</dd> +<dt><code>-mlittle, -mlittle-endian, -le</code></dt> +<dd><p>Generate code for a little endian machine. +</p> +</dd> +<dt><code>-mbig, -mbig-endian, -be</code></dt> +<dd><p>Generate code for a big endian machine. +</p> +</dd> +<dt><code>-msolaris</code></dt> +<dd><p>Generate code for Solaris. +</p> +</dd> +<dt><code>-mno-solaris</code></dt> +<dd><p>Do not generate code for Solaris. +</p> +</dd> +<dt><code>-nops=<var>count</var></code></dt> +<dd><p>If an alignment directive inserts more than <var>count</var> nops, put a +branch at the beginning to skip execution of the nops. +</p></dd> +</dl> + + +<hr> +<a name="PowerPC_002dPseudo"></a> +<div class="header"> +<p> +Next: <a href="#PowerPC_002dSyntax" accesskey="n" rel="next">PowerPC-Syntax</a>, Previous: <a href="#PowerPC_002dOpts" accesskey="p" rel="previous">PowerPC-Opts</a>, Up: <a href="#PPC_002dDependent" accesskey="u" rel="up">PPC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="PowerPC-Assembler-Directives"></a> +<h4 class="subsection">9.36.2 PowerPC Assembler Directives</h4> + +<a name="index-directives-for-PowerPC"></a> +<a name="index-PowerPC-directives"></a> +<p>A number of assembler directives are available for PowerPC. The +following table is far from complete. +</p> +<dl compact="compact"> +<dt><code>.machine "string"</code></dt> +<dd><p>This directive allows you to change the machine for which code is +generated. <code>"string"</code> may be any of the -m cpu selection options +(without the -m) enclosed in double quotes, <code>"push"</code>, or +<code>"pop"</code>. <code>.machine "push"</code> saves the currently selected +cpu, which may be restored with <code>.machine "pop"</code>. +</p></dd> +</dl> + +<hr> +<a name="PowerPC_002dSyntax"></a> +<div class="header"> +<p> +Previous: <a href="#PowerPC_002dPseudo" accesskey="p" rel="previous">PowerPC-Pseudo</a>, Up: <a href="#PPC_002dDependent" accesskey="u" rel="up">PPC-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="PowerPC-Syntax"></a> +<h4 class="subsection">9.36.3 PowerPC Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#PowerPC_002dChars" accesskey="1">PowerPC-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="PowerPC_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#PowerPC_002dSyntax" accesskey="u" rel="up">PowerPC-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-28"></a> +<h4 class="subsubsection">9.36.3.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-PowerPC"></a> +<a name="index-PowerPC-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ on a line indicates the start of a comment +that extends to the end of the current line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<p>If the assembler has been configured for the ppc-*-solaris* target +then the ‘<samp>!</samp>’ character also acts as a line comment character. +This can be disabled via the <samp>-mno-solaris</samp> command-line +option. +</p> +<a name="index-line-separator_002c-PowerPC"></a> +<a name="index-statement-separator_002c-PowerPC"></a> +<a name="index-PowerPC-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="PRU_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#RISC_002dV_002dDependent" accesskey="n" rel="next">RISC-V-Dependent</a>, Previous: <a href="#PPC_002dDependent" accesskey="p" rel="previous">PPC-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="PRU-Dependent-Features"></a> +<h3 class="section">9.37 PRU Dependent Features</h3> + +<a name="index-PRU-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#PRU-Options" accesskey="1">PRU Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#PRU-Syntax" accesskey="2">PRU Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#PRU-Relocations" accesskey="3">PRU Relocations</a>:</td><td> </td><td align="left" valign="top">Relocations +</td></tr> +<tr><td align="left" valign="top">• <a href="#PRU-Directives" accesskey="4">PRU Directives</a>:</td><td> </td><td align="left" valign="top">PRU Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#PRU-Opcodes" accesskey="5">PRU Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="PRU-Options"></a> +<div class="header"> +<p> +Next: <a href="#PRU-Syntax" accesskey="n" rel="next">PRU Syntax</a>, Up: <a href="#PRU_002dDependent" accesskey="u" rel="up">PRU-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-20"></a> +<h4 class="subsection">9.37.1 Options</h4> +<a name="index-PRU-options"></a> +<a name="index-options-for-PRU"></a> + +<dl compact="compact"> +<dd> +<a name="index-mlink_002drelax-command_002dline-option_002c-PRU"></a> +</dd> +<dt><code>-mlink-relax</code></dt> +<dd><p>Assume that LD would optimize LDI32 instructions by checking the upper +16 bits of the <var>expression</var>. If they are all zeros, then LD would +shorten the LDI32 instruction to a single LDI. In such case <code>as</code> +will output DIFF relocations for diff expressions. +</p> +<a name="index-mno_002dlink_002drelax-command_002dline-option_002c-PRU"></a> +</dd> +<dt><code>-mno-link-relax</code></dt> +<dd><p>Assume that LD would not optimize LDI32 instructions. As a consequence, +DIFF relocations will not be emitted. +</p> +<a name="index-mno_002dwarn_002dregname_002dlabel-command_002dline-option_002c-PRU"></a> +</dd> +<dt><code>-mno-warn-regname-label</code></dt> +<dd><p>Do not warn if a label name matches a register name. Usually assembler +programmers will want this warning to be emitted. C compilers may want +to turn this off. +</p> +</dd> +</dl> + +<hr> +<a name="PRU-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#PRU-Relocations" accesskey="n" rel="next">PRU Relocations</a>, Previous: <a href="#PRU-Options" accesskey="p" rel="previous">PRU Options</a>, Up: <a href="#PRU_002dDependent" accesskey="u" rel="up">PRU-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-26"></a> +<h4 class="subsection">9.37.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#PRU-Chars" accesskey="1">PRU Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + + +<hr> +<a name="PRU-Chars"></a> +<div class="header"> +<p> +Up: <a href="#PRU-Syntax" accesskey="u" rel="up">PRU Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-29"></a> +<h4 class="subsubsection">9.37.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-PRU"></a> +<a name="index-PRU-line-comment-character"></a> +<p>‘<samp>#</samp>’ and ‘<samp>;</samp>’ are the line comment characters. +</p> + +<hr> +<a name="PRU-Relocations"></a> +<div class="header"> +<p> +Next: <a href="#PRU-Directives" accesskey="n" rel="next">PRU Directives</a>, Previous: <a href="#PRU-Syntax" accesskey="p" rel="previous">PRU Syntax</a>, Up: <a href="#PRU_002dDependent" accesskey="u" rel="up">PRU-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="PRU-Machine-Relocations"></a> +<h4 class="subsection">9.37.3 PRU Machine Relocations</h4> + +<a name="index-machine-relocations_002c-PRU"></a> +<a name="index-PRU-machine-relocations"></a> + +<dl compact="compact"> +<dd> +<a name="index-pmem-directive_002c-PRU"></a> +</dd> +<dt><code>%pmem(<var>expression</var>)</code></dt> +<dd><p>Convert <var>expression</var> from byte-address to a +word-address. In other words, shift right by two. +</p> +</dd> +<dt><code>%label(<var>expression</var>)</code></dt> +<dd><p>Mark the given operand as a label. This is useful if you need to jump to +a label that matches a register name. +</p> +<div class="smallexample"> +<pre class="smallexample">r1: + jmp r1 ; Will jump to register R1 + jmp %label(r1) ; Will jump to label r1 +</pre></div> + +</dd> +</dl> + + +<hr> +<a name="PRU-Directives"></a> +<div class="header"> +<p> +Next: <a href="#PRU-Opcodes" accesskey="n" rel="next">PRU Opcodes</a>, Previous: <a href="#PRU-Relocations" accesskey="p" rel="previous">PRU Relocations</a>, Up: <a href="#PRU_002dDependent" accesskey="u" rel="up">PRU-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="PRU-Machine-Directives"></a> +<h4 class="subsection">9.37.4 PRU Machine Directives</h4> + +<a name="index-machine-directives_002c-PRU"></a> +<a name="index-PRU-machine-directives"></a> + +<dl compact="compact"> +<dd> +<a name="index-align-directive_002c-PRU"></a> +</dd> +<dt><code>.align <var>expression</var> [, <var>expression</var>]</code></dt> +<dd><p>This is the generic <code>.align</code> directive, however +this aligns to a power of two. +</p> +<a name="index-word-directive_002c-PRU"></a> +</dd> +<dt><code>.word <var>expression</var></code></dt> +<dd><p>Create an aligned constant 4 bytes in size. +</p> +<a name="index-dword-directive_002c-PRU"></a> +</dd> +<dt><code>.dword <var>expression</var></code></dt> +<dd><p>Create an aligned constant 8 bytes in size. +</p> +<a name="index-2byte-directive_002c-PRU"></a> +</dd> +<dt><code>.2byte <var>expression</var></code></dt> +<dd><p>Create an unaligned constant 2 bytes in size. +</p> +<a name="index-4byte-directive_002c-PRU"></a> +</dd> +<dt><code>.4byte <var>expression</var></code></dt> +<dd><p>Create an unaligned constant 4 bytes in size. +</p> +<a name="index-8byte-directive_002c-PRU"></a> +</dd> +<dt><code>.8byte <var>expression</var></code></dt> +<dd><p>Create an unaligned constant 8 bytes in size. +</p> +<a name="index-16byte-directive_002c-PRU"></a> +</dd> +<dt><code>.16byte <var>expression</var></code></dt> +<dd><p>Create an unaligned constant 16 bytes in size. +</p> +<a name="index-set-no_005fwarn_005fregname_005flabel-directive_002c-PRU"></a> +</dd> +<dt><code>.set no_warn_regname_label</code></dt> +<dd><p>Do not output warnings when a label name matches a register name. Equivalent +to passing the <code>-mno-warn-regname-label</code> command-line option. +</p> +</dd> +</dl> + +<hr> +<a name="PRU-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#PRU-Directives" accesskey="p" rel="previous">PRU Directives</a>, Up: <a href="#PRU_002dDependent" accesskey="u" rel="up">PRU-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-17"></a> +<h4 class="subsection">9.37.5 Opcodes</h4> + +<a name="index-PRU-opcodes"></a> +<a name="index-opcodes-for-PRU"></a> +<p><code>as</code> implements all the standard PRU core V3 opcodes in the +original pasm assembler. Older cores are not supported by <code>as</code>. +</p> +<p>GAS also implements the LDI32 pseudo instruction for loading a 32-bit +immediate value into a register. +</p> +<div class="smallexample"> +<pre class="smallexample"> ldi32 sp, __stack_top + ldi32 r14, 0x12345678 +</pre></div> + + +<hr> +<a name="RISC_002dV_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#RL78_002dDependent" accesskey="n" rel="next">RL78-Dependent</a>, Previous: <a href="#PRU_002dDependent" accesskey="p" rel="previous">PRU-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RISC_002dV-Dependent-Features"></a> +<h3 class="section">9.38 RISC-V Dependent Features</h3> + +<a name="index-RISC_002dV-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#RISC_002dV_002dOptions" accesskey="1">RISC-V-Options</a>:</td><td> </td><td align="left" valign="top">RISC-V Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#RISC_002dV_002dDirectives" accesskey="2">RISC-V-Directives</a>:</td><td> </td><td align="left" valign="top">RISC-V Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#RISC_002dV_002dModifiers" accesskey="3">RISC-V-Modifiers</a>:</td><td> </td><td align="left" valign="top">RISC-V Assembler Modifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#RISC_002dV_002dFloating_002dPoint" accesskey="4">RISC-V-Floating-Point</a>:</td><td> </td><td align="left" valign="top">RISC-V Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#RISC_002dV_002dFormats" accesskey="5">RISC-V-Formats</a>:</td><td> </td><td align="left" valign="top">RISC-V Instruction Formats +</td></tr> +<tr><td align="left" valign="top">• <a href="#RISC_002dV_002dATTRIBUTE" accesskey="6">RISC-V-ATTRIBUTE</a>:</td><td> </td><td align="left" valign="top">RISC-V Object Attribute +</td></tr> +<tr><td align="left" valign="top">• <a href="#RISC_002dV_002dCustomExts" accesskey="7">RISC-V-CustomExts</a>:</td><td> </td><td align="left" valign="top">RISC-V Custom (Vendor-Defined) Extensions +</td></tr> +</table> + +<hr> +<a name="RISC_002dV_002dOptions"></a> +<div class="header"> +<p> +Next: <a href="#RISC_002dV_002dDirectives" accesskey="n" rel="next">RISC-V-Directives</a>, Up: <a href="#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RISC_002dV-Options"></a> +<h4 class="subsection">9.38.1 RISC-V Options</h4> + +<p>The following table lists all available RISC-V specific options. +</p> +<dl compact="compact"> +<dd> +<a name="index-_002dfpic-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-fpic</code></dt> +<dt><code>-fPIC</code></dt> +<dd><p>Generate position-independent code +</p> +<a name="index-_002dfno_002dpic-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-fno-pic</code></dt> +<dd><p>Don’t generate position-independent code (default) +</p> +<a name="index-_002dmarch_003dISA-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-march=ISA</code></dt> +<dd><p>Select the base isa, as specified by ISA. For example -march=rv32ima. +If this option and the architecture attributes aren’t set, then assembler +will check the default configure setting –with-arch=ISA. +</p> +<a name="index-_002dmisa_002dspec_003dISAspec-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-misa-spec=ISAspec</code></dt> +<dd><p>Select the default isa spec version. If the version of ISA isn’t set +by -march, then assembler helps to set the version according to +the default chosen spec. If this option isn’t set, then assembler will +check the default configure setting –with-isa-spec=ISAspec. +</p> +<a name="index-_002dmpriv_002dspec_003dPRIVspec-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-mpriv-spec=PRIVspec</code></dt> +<dd><p>Select the privileged spec version. We can decide whether the CSR is valid or +not according to the chosen spec. If this option and the privilege attributes +aren’t set, then assembler will check the default configure setting +–with-priv-spec=PRIVspec. +</p> +<a name="index-_002dmabi_003dABI-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-mabi=ABI</code></dt> +<dd><p>Selects the ABI, which is either "ilp32" or "lp64", optionally followed +by "f", "d", or "q" to indicate single-precision, double-precision, or +quad-precision floating-point calling convention, or none to indicate +the soft-float calling convention. Also, "ilp32" can optionally be followed +by "e" to indicate the RVE ABI, which is always soft-float. +</p> +<a name="index-_002dmrelax-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-mrelax</code></dt> +<dd><p>Take advantage of linker relaxations to reduce the number of instructions +required to materialize symbol addresses. (default) +</p> +<a name="index-_002dmno_002drelax-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-mno-relax</code></dt> +<dd><p>Don’t do linker relaxations. +</p> +<a name="index-_002dmarch_002dattr-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-march-attr</code></dt> +<dd><p>Generate the default contents for the riscv elf attribute section if the +.attribute directives are not set. This section is used to record the +information that a linker or runtime loader needs to check compatibility. +This information includes ISA string, stack alignment requirement, unaligned +memory accesses, and the major, minor and revision version of privileged +specification. +</p> +<a name="index-_002dmno_002darch_002dattr-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-mno-arch-attr</code></dt> +<dd><p>Don’t generate the default riscv elf attribute section if the .attribute +directives are not set. +</p> +<a name="index-_002dmcsr_002dcheck-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-mcsr-check</code></dt> +<dd><p>Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. +The ISA-dependent CSR are only valid when the specific ISA is set. The +read-only CSR can not be written by the CSR instructions. +</p> +<a name="index-_002dmno_002dcsr_002dcheck-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-mno-csr-check</code></dt> +<dd><p>Don’t do CSR checking. +</p> +<a name="index-_002dmlittle_002dendian-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-mlittle-endian</code></dt> +<dd><p>Generate code for a little endian machine. +</p> +<a name="index-_002dmbig_002dendian-option_002c-RISC_002dV"></a> +</dd> +<dt><code>-mbig-endian</code></dt> +<dd><p>Generate code for a big endian machine. +</p></dd> +</dl> + +<hr> +<a name="RISC_002dV_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#RISC_002dV_002dModifiers" accesskey="n" rel="next">RISC-V-Modifiers</a>, Previous: <a href="#RISC_002dV_002dOptions" accesskey="p" rel="previous">RISC-V-Options</a>, Up: <a href="#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RISC_002dV-Directives"></a> +<h4 class="subsection">9.38.2 RISC-V Directives</h4> +<a name="index-machine-directives_002c-RISC_002dV"></a> +<a name="index-RISC_002dV-machine-directives"></a> + +<p>The following table lists all available RISC-V specific directives. +</p> +<dl compact="compact"> +<dd> +<a name="index-align-directive-1"></a> +</dd> +<dt><code>.align <var>size-log-2</var></code></dt> +<dd><p>Align to the given boundary, with the size given as log2 the number of bytes to +align to. +</p> +<a name="index-Data-directives"></a> +</dd> +<dt><code>.half <var>value</var></code></dt> +<dt><code>.word <var>value</var></code></dt> +<dt><code>.dword <var>value</var></code></dt> +<dd><p>Emits a half-word, word, or double-word value at the current position. +</p> +<a name="index-DTP_002drelative-data-directives"></a> +</dd> +<dt><code>.dtprelword <var>value</var></code></dt> +<dt><code>.dtpreldword <var>value</var></code></dt> +<dd><p>Emits a DTP-relative word (or double-word) at the current position. This is +meant to be used by the compiler in shared libraries for DWARF debug info for +thread local variables. +</p> +<a name="index-BSS-directive"></a> +</dd> +<dt><code>.bss</code></dt> +<dd><p>Sets the current section to the BSS section. +</p> +<a name="index-LEB128-directives"></a> +</dd> +<dt><code>.uleb128 <var>value</var></code></dt> +<dt><code>.sleb128 <var>value</var></code></dt> +<dd><p>Emits a signed or unsigned LEB128 value at the current position. This only +accepts constant expressions, because symbol addresses can change with +relaxation, and we don’t support relocations to modify LEB128 values at link +time. +</p> +<a name="index-Option-directive"></a> +<a name="index-option-directive"></a> +</dd> +<dt><code>.option <var>argument</var></code></dt> +<dd><p>Modifies RISC-V specific assembler options inline with the assembly code. +This is used when particular instruction sequences must be assembled with a +specific set of options. For example, since we relax addressing sequences to +shorter GP-relative sequences when possible the initial load of GP must not be +relaxed and should be emitted as something like +</p> +<div class="smallexample"> +<pre class="smallexample"> .option push + .option norelax + la gp, __global_pointer$ + .option pop +</pre></div> + +<p>in order to produce after linker relaxation the expected +</p> +<div class="smallexample"> +<pre class="smallexample"> auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(__global_pointer$) +</pre></div> + +<p>instead of just +</p> +<div class="smallexample"> +<pre class="smallexample"> addi gp, gp, 0 +</pre></div> + +<p>It’s not expected that options are changed in this manner during regular use, +but there are a handful of esoteric cases like the one above where users need +to disable particular features of the assembler for particular code sequences. +The complete list of option arguments is shown below: +</p> +<dl compact="compact"> +<dt><code>push</code></dt> +<dt><code>pop</code></dt> +<dd><p>Pushes or pops the current option stack. These should be used whenever +changing an option in line with assembly code in order to ensure the user’s +command-line options are respected for the bulk of the file being assembled. +</p> +</dd> +<dt><code>rvc</code></dt> +<dt><code>norvc</code></dt> +<dd><p>Enables or disables the generation of compressed instructions. Instructions +are opportunistically compressed by the RISC-V assembler when possible, but +sometimes this behavior is not desirable, especially when handling alignments. +</p> +</dd> +<dt><code>pic</code></dt> +<dt><code>nopic</code></dt> +<dd><p>Enables or disables position-independent code generation. Unless you really +know what you’re doing, this should only be at the top of a file. +</p> +</dd> +<dt><code>relax</code></dt> +<dt><code>norelax</code></dt> +<dd><p>Enables or disables relaxation. The RISC-V assembler and linker +opportunistically relax some code sequences, but sometimes this behavior is not +desirable. +</p> +</dd> +<dt><code>csr-check</code></dt> +<dt><code>no-csr-check</code></dt> +<dd><p>Enables or disables the CSR checking. +</p> +</dd> +<dt><code>arch, <var>+extension[version]</var> [,...,<var>+extension_n[version_n]</var>]</code></dt> +<dt><code>arch, <var>-extension</var> [,...,<var>-extension_n</var>]</code></dt> +<dt><code>arch, <var>=ISA</var></code></dt> +<dd><p>Enables or disables the extensions for specific code region. For example, +‘<samp>.option arch, +m2p0</samp>’ means add m extension with version 2.0, and +‘<samp>.option arch, -f, -d</samp>’ means remove extensions, f and d, from the +architecture string. Note that, ‘<samp>.option arch, +c, -c</samp>’ have the same +behavior as ‘<samp>.option rvc, norvc</samp>’. However, they are also undesirable +sometimes. Besides, ‘<samp>.option arch, -i</samp>’ is illegal, since we cannot +remove the base i extension anytime. If you want to reset the whole ISA +string, you can also use ‘<samp>.option arch, =rv32imac</samp>’ to overwrite the +previous settings. +</p></dd> +</dl> + +<a name="index-INSN-directives"></a> +</dd> +<dt><code>.insn <var>type</var>, <var>operand</var> [,...,<var>operand_n</var>]</code></dt> +<dt><code>.insn <var>insn_length</var>, <var>value</var></code></dt> +<dt><code>.insn <var>value</var></code></dt> +<dd><p>This directive permits the numeric representation of an instructions +and makes the assembler insert the operands according to one of the +instruction formats for ‘<samp>.insn</samp>’ (<a href="#RISC_002dV_002dFormats">RISC-V-Formats</a>). +For example, the instruction ‘<samp>add a0, a1, a2</samp>’ could be written as +‘<samp>.insn r 0x33, 0, 0, a0, a1, a2</samp>’. But in fact, the instruction +formats are difficult to use for some users, so most of them are using +‘<samp>.word</samp>’ to encode the instruction directly, rather than using +‘<samp>.insn</samp>’. It is fine for now, but will be wrong when the mapping +symbols are supported, since ‘<samp>.word</samp>’ will not be shown as an +instruction, it should be shown as data. Therefore, we also support +two more formats of the ‘<samp>.insn</samp>’, the instruction ‘<samp>add a0, a1, a2</samp>’ +could also be written as ‘<samp>.insn 0x4, 0xc58533</samp>’ or ‘<samp>.insn 0xc58533</samp>’. +When the <var>insn_length</var> is set, then assembler will check if the +<var>value</var> is a valid <var>insn_length</var> bytes instruction. +</p> +<a name="index-_002eattribute-directive_002c-RISC_002dV"></a> +</dd> +<dt><code>.attribute <var>tag</var>, <var>value</var></code></dt> +<dd><p>Set the object attribute <var>tag</var> to <var>value</var>. +</p> +<p>The <var>tag</var> is either an attribute number, or one of the following: +<code>Tag_RISCV_arch</code>, <code>Tag_RISCV_stack_align</code>, +<code>Tag_RISCV_unaligned_access</code>, <code>Tag_RISCV_priv_spec</code>, +<code>Tag_RISCV_priv_spec_minor</code>, <code>Tag_RISCV_priv_spec_revision</code>. +</p> +</dd> +</dl> + +<hr> +<a name="RISC_002dV_002dModifiers"></a> +<div class="header"> +<p> +Next: <a href="#RISC_002dV_002dFloating_002dPoint" accesskey="n" rel="next">RISC-V-Floating-Point</a>, Previous: <a href="#RISC_002dV_002dDirectives" accesskey="p" rel="previous">RISC-V-Directives</a>, Up: <a href="#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RISC_002dV-Assembler-Modifiers"></a> +<h4 class="subsection">9.38.3 RISC-V Assembler Modifiers</h4> + +<p>The RISC-V assembler supports following modifiers for relocatable addresses +used in RISC-V instruction operands. However, we also support some pseudo +instructions that are easier to use than these modifiers. +</p> +<dl compact="compact"> +<dt><code>%lo(<var>symbol</var>)</code></dt> +<dd><p>The low 12 bits of absolute address for <var>symbol</var>. +</p> +</dd> +<dt><code>%hi(<var>symbol</var>)</code></dt> +<dd><p>The high 20 bits of absolute address for <var>symbol</var>. This is usually +used with the %lo modifier to represent a 32-bit absolute address. +</p> +<div class="smallexample"> +<pre class="smallexample"> lui a0, %hi(<var>symbol</var>) // R_RISCV_HI20 + addi a0, a0, %lo(<var>symbol</var>) // R_RISCV_LO12_I + + lui a0, %hi(<var>symbol</var>) // R_RISCV_HI20 + load/store a0, %lo(<var>symbol</var>)(a0) // R_RISCV_LO12_I/S +</pre></div> + +</dd> +<dt><code>%pcrel_lo(<var>label</var>)</code></dt> +<dd><p>The low 12 bits of relative address between pc and <var>symbol</var>. +The <var>symbol</var> is related to the high part instruction which is marked +by <var>label</var>. +</p> +</dd> +<dt><code>%pcrel_hi(<var>symbol</var>)</code></dt> +<dd><p>The high 20 bits of relative address between pc and <var>symbol</var>. +This is usually used with the %pcrel_lo modifier to represent a +/-2GB +pc-relative range. +</p> +<div class="smallexample"> +<pre class="smallexample"><var>label</var>: + auipc a0, %pcrel_hi(<var>symbol</var>) // R_RISCV_PCREL_HI20 + addi a0, a0, %pcrel_lo(<var>label</var>) // R_RISCV_PCREL_LO12_I + +<var>label</var>: + auipc a0, %pcrel_hi(<var>symbol</var>) // R_RISCV_PCREL_HI20 + load/store a0, %pcrel_lo(<var>label</var>)(a0) // R_RISCV_PCREL_LO12_I/S +</pre></div> + +<p>Or you can use the pseudo lla/lw/sw/... instruction to do this. +</p> +<div class="smallexample"> +<pre class="smallexample"> lla a0, <var>symbol</var> +</pre></div> + +</dd> +<dt><code>%got_pcrel_hi(<var>symbol</var>)</code></dt> +<dd><p>The high 20 bits of relative address between pc and the GOT entry of +<var>symbol</var>. This is usually used with the %pcrel_lo modifier to access +the GOT entry. +</p> +<div class="smallexample"> +<pre class="smallexample"><var>label</var>: + auipc a0, %got_pcrel_hi(<var>symbol</var>) // R_RISCV_GOT_HI20 + addi a0, a0, %pcrel_lo(<var>label</var>) // R_RISCV_PCREL_LO12_I + +<var>label</var>: + auipc a0, %got_pcrel_hi(<var>symbol</var>) // R_RISCV_GOT_HI20 + load/store a0, %pcrel_lo(<var>label</var>)(a0) // R_RISCV_PCREL_LO12_I/S +</pre></div> + +<p>Also, the pseudo la instruction with PIC has similar behavior. +</p> +</dd> +<dt><code>%tprel_add(<var>symbol</var>)</code></dt> +<dd><p>This is used purely to associate the R_RISCV_TPREL_ADD relocation for +TLS relaxation. This one is only valid as the fourth operand to the normally +3 operand add instruction. +</p> +</dd> +<dt><code>%tprel_lo(<var>symbol</var>)</code></dt> +<dd><p>The low 12 bits of relative address between tp and <var>symbol</var>. +</p> +</dd> +<dt><code>%tprel_hi(<var>symbol</var>)</code></dt> +<dd><p>The high 20 bits of relative address between tp and <var>symbol</var>. This is +usually used with the %tprel_lo and %tprel_add modifiers to access the thread +local variable <var>symbol</var> in TLS Local Exec. +</p> +<div class="smallexample"> +<pre class="smallexample"> lui a5, %tprel_hi(<var>symbol</var>) // R_RISCV_TPREL_HI20 + add a5, a5, tp, %tprel_add(<var>symbol</var>) // R_RISCV_TPREL_ADD + load/store t0, %tprel_lo(<var>symbol</var>)(a5) // R_RISCV_TPREL_LO12_I/S +</pre></div> + +</dd> +<dt><code>%tls_ie_pcrel_hi(<var>symbol</var>)</code></dt> +<dd><p>The high 20 bits of relative address between pc and GOT entry. It is +usually used with the %pcrel_lo modifier to access the thread local +variable <var>symbol</var> in TLS Initial Exec. +</p> +<div class="smallexample"> +<pre class="smallexample"> la.tls.ie a5, <var>symbol</var> + add a5, a5, tp + load/store t0, 0(a5) +</pre></div> + +<p>The pseudo la.tls.ie instruction can be expended to +</p> +<div class="smallexample"> +<pre class="smallexample"><var>label</var>: + auipc a5, %tls_ie_pcrel_hi(<var>symbol</var>) // R_RISCV_TLS_GOT_HI20 + load a5, %pcrel_lo(<var>label</var>)(a5) // R_RISCV_PCREL_LO12_I +</pre></div> + +</dd> +<dt><code>%tls_gd_pcrel_hi(<var>symbol</var>)</code></dt> +<dd><p>The high 20 bits of relative address between pc and GOT entry. It is +usually used with the %pcrel_lo modifier to access the thread local variable +<var>symbol</var> in TLS Global Dynamic. +</p> +<div class="smallexample"> +<pre class="smallexample"> la.tls.gd a0, <var>symbol</var> + call __tls_get_addr@plt + mv a5, a0 + load/store t0, 0(a5) +</pre></div> + +<p>The pseudo la.tls.gd instruction can be expended to +</p> +<div class="smallexample"> +<pre class="smallexample"><var>label</var>: + auipc a0, %tls_gd_pcrel_hi(<var>symbol</var>) // R_RISCV_TLS_GD_HI20 + addi a0, a0, %pcrel_lo(<var>label</var>) // R_RISCV_PCREL_LO12_I +</pre></div> + +</dd> +</dl> + +<hr> +<a name="RISC_002dV_002dFloating_002dPoint"></a> +<div class="header"> +<p> +Next: <a href="#RISC_002dV_002dFormats" accesskey="n" rel="next">RISC-V-Formats</a>, Previous: <a href="#RISC_002dV_002dModifiers" accesskey="p" rel="previous">RISC-V-Modifiers</a>, Up: <a href="#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RISC_002dV-Floating-Point"></a> +<h4 class="subsection">9.38.4 RISC-V Floating Point</h4> +<a name="index-floating-point_002c-risc_002dv-_0028IEEE_0029"></a> +<a name="index-RISC_002dV-floating-point-_0028IEEE_0029"></a> + +<p>The RISC-V architecture uses <small>IEEE</small> floating-point numbers. +</p> +<p>The RISC-V Zfa extension includes a load-immediate instruction +for floating-point registers, which allows specifying the immediate +(from a pool of 32 predefined values defined in the specification) +as operand. +E.g. to load the value <code>0.0625</code> as single-precision FP value into +the FP register <code>ft1</code> one of the following instructions can be used: +</p> +<p>fli.s ft1, 0.0625 # dec floating-point literal + fli.s ft1, 0x1p-4 # hex floating-point literal + fli.s ft1, 0x0.8p-3 + fli.s ft1, 0x1.0p-4 + fli.s ft1, 0x2p-5 + fli.s ft1, 0x4p-6 + ... +</p> +<p>As can be seen, many valid ways exist to express a floating-point value. +This is realized by parsing the value operand using strtof() and +comparing the parsed value against built-in float-constants that +are written as hex floating-point literals. +</p> +<p>This approach works on all machines that use IEEE 754. +However, there is a chance that this fails on other machines +with the following error message: +</p> +<p>Error: improper fli value operand + Error: illegal operands ‘fli.s ft1,0.0625 +</p> +<p>The error indicates that parsing ‘<samp>0x1p-4</samp>’ and ‘<samp>0.0625</samp>’ +to single-precision floating point numbers will not result +in two equal values on that machine. +</p> +<p>If you encounter this problem, then please report it. +</p> +<hr> +<a name="RISC_002dV_002dFormats"></a> +<div class="header"> +<p> +Next: <a href="#RISC_002dV_002dATTRIBUTE" accesskey="n" rel="next">RISC-V-ATTRIBUTE</a>, Previous: <a href="#RISC_002dV_002dFloating_002dPoint" accesskey="p" rel="previous">RISC-V-Floating-Point</a>, Up: <a href="#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RISC_002dV-Instruction-Formats"></a> +<h4 class="subsection">9.38.5 RISC-V Instruction Formats</h4> +<a name="index-instruction-formats_002c-risc_002dv"></a> +<a name="index-RISC_002dV-instruction-formats"></a> + +<p>The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15 +instruction formats where some of the formats have multiple variants. +For the ‘<samp>.insn</samp>’ pseudo directive the assembler recognizes some +of the formats. +Typically, the most general variant of the instruction format is used +by the ‘<samp>.insn</samp>’ directive. +</p> +<p>The following table lists the abbreviations used in the table of +instruction formats: +</p> +<div class="display"> +<table> +<tr><td width="15%"><pre class="display">opcode</pre></td><td width="40%"><pre class="display">Unsigned immediate or opcode name for 7-bits opcode.</pre></td></tr> +<tr><td width="15%"><pre class="display">opcode2</pre></td><td width="40%"><pre class="display">Unsigned immediate or opcode name for 2-bits opcode.</pre></td></tr> +<tr><td width="15%"><pre class="display">func7</pre></td><td width="40%"><pre class="display">Unsigned immediate for 7-bits function code.</pre></td></tr> +<tr><td width="15%"><pre class="display">func6</pre></td><td width="40%"><pre class="display">Unsigned immediate for 6-bits function code.</pre></td></tr> +<tr><td width="15%"><pre class="display">func4</pre></td><td width="40%"><pre class="display">Unsigned immediate for 4-bits function code.</pre></td></tr> +<tr><td width="15%"><pre class="display">func3</pre></td><td width="40%"><pre class="display">Unsigned immediate for 3-bits function code.</pre></td></tr> +<tr><td width="15%"><pre class="display">func2</pre></td><td width="40%"><pre class="display">Unsigned immediate for 2-bits function code.</pre></td></tr> +<tr><td width="15%"><pre class="display">rd</pre></td><td width="40%"><pre class="display">Destination register number for operand x, can be GPR or FPR.</pre></td></tr> +<tr><td width="15%"><pre class="display">rd’</pre></td><td width="40%"><pre class="display">Destination register number for operand x, +only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.</pre></td></tr> +<tr><td width="15%"><pre class="display">rs1</pre></td><td width="40%"><pre class="display">First source register number for operand x, can be GPR or FPR.</pre></td></tr> +<tr><td width="15%"><pre class="display">rs1’</pre></td><td width="40%"><pre class="display">First source register number for operand x, +only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.</pre></td></tr> +<tr><td width="15%"><pre class="display">rs2</pre></td><td width="40%"><pre class="display">Second source register number for operand x, can be GPR or FPR.</pre></td></tr> +<tr><td width="15%"><pre class="display">rs2’</pre></td><td width="40%"><pre class="display">Second source register number for operand x, +only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.</pre></td></tr> +<tr><td width="15%"><pre class="display">simm12</pre></td><td width="40%"><pre class="display">Sign-extended 12-bit immediate for operand x.</pre></td></tr> +<tr><td width="15%"><pre class="display">simm20</pre></td><td width="40%"><pre class="display">Sign-extended 20-bit immediate for operand x.</pre></td></tr> +<tr><td width="15%"><pre class="display">simm6</pre></td><td width="40%"><pre class="display">Sign-extended 6-bit immediate for operand x.</pre></td></tr> +<tr><td width="15%"><pre class="display">uimm5</pre></td><td width="40%"><pre class="display">Unsigned 5-bit immediate for operand x.</pre></td></tr> +<tr><td width="15%"><pre class="display">uimm6</pre></td><td width="40%"><pre class="display">Unsigned 6-bit immediate for operand x.</pre></td></tr> +<tr><td width="15%"><pre class="display">uimm8</pre></td><td width="40%"><pre class="display">Unsigned 8-bit immediate for operand x.</pre></td></tr> +<tr><td width="15%"><pre class="display">symbol</pre></td><td width="40%"><pre class="display">Symbol or lable reference for operand x.</pre></td></tr> +</table> +</div> + +<p>The following table lists all available opcode name: +</p> +<dl compact="compact"> +<dt><code>C0</code></dt> +<dt><code>C1</code></dt> +<dt><code>C2</code></dt> +<dd><p>Opcode space for compressed instructions. +</p> +</dd> +<dt><code>LOAD</code></dt> +<dd><p>Opcode space for load instructions. +</p> +</dd> +<dt><code>LOAD_FP</code></dt> +<dd><p>Opcode space for floating-point load instructions. +</p> +</dd> +<dt><code>STORE</code></dt> +<dd><p>Opcode space for store instructions. +</p> +</dd> +<dt><code>STORE_FP</code></dt> +<dd><p>Opcode space for floating-point store instructions. +</p> +</dd> +<dt><code>AUIPC</code></dt> +<dd><p>Opcode space for auipc instruction. +</p> +</dd> +<dt><code>LUI</code></dt> +<dd><p>Opcode space for lui instruction. +</p> +</dd> +<dt><code>BRANCH</code></dt> +<dd><p>Opcode space for branch instructions. +</p> +</dd> +<dt><code>JAL</code></dt> +<dd><p>Opcode space for jal instruction. +</p> +</dd> +<dt><code>JALR</code></dt> +<dd><p>Opcode space for jalr instruction. +</p> +</dd> +<dt><code>OP</code></dt> +<dd><p>Opcode space for ALU instructions. +</p> +</dd> +<dt><code>OP_32</code></dt> +<dd><p>Opcode space for 32-bits ALU instructions. +</p> +</dd> +<dt><code>OP_IMM</code></dt> +<dd><p>Opcode space for ALU with immediate instructions. +</p> +</dd> +<dt><code>OP_IMM_32</code></dt> +<dd><p>Opcode space for 32-bits ALU with immediate instructions. +</p> +</dd> +<dt><code>OP_FP</code></dt> +<dd><p>Opcode space for floating-point operation instructions. +</p> +</dd> +<dt><code>MADD</code></dt> +<dd><p>Opcode space for madd instruction. +</p> +</dd> +<dt><code>MSUB</code></dt> +<dd><p>Opcode space for msub instruction. +</p> +</dd> +<dt><code>NMADD</code></dt> +<dd><p>Opcode space for nmadd instruction. +</p> +</dd> +<dt><code>NMSUB</code></dt> +<dd><p>Opcode space for msub instruction. +</p> +</dd> +<dt><code>AMO</code></dt> +<dd><p>Opcode space for atomic memory operation instructions. +</p> +</dd> +<dt><code>MISC_MEM</code></dt> +<dd><p>Opcode space for misc instructions. +</p> +</dd> +<dt><code>SYSTEM</code></dt> +<dd><p>Opcode space for system instructions. +</p> +</dd> +<dt><code>CUSTOM_0</code></dt> +<dt><code>CUSTOM_1</code></dt> +<dt><code>CUSTOM_2</code></dt> +<dt><code>CUSTOM_3</code></dt> +<dd><p>Opcode space for customize instructions. +</p> +</dd> +</dl> + +<p>An instruction is two or four bytes in length and must be aligned +on a 2 byte boundary. The first two bits of the instruction specify the +length of the instruction, 00, 01 and 10 indicates a two byte instruction, +11 indicates a four byte instruction. +</p> +<p>The following table lists the RISC-V instruction formats that are available +with the ‘<samp>.insn</samp>’ pseudo directive: +</p> +<dl compact="compact"> +<dt><code>R type: .insn r opcode6, func3, func7, rd, rs1, rs2</code></dt> +<dd><pre class="verbatim">+-------+-----+-----+-------+----+---------+ +| func7 | rs2 | rs1 | func3 | rd | opcode6 | ++-------+-----+-----+-------+----+---------+ +31 25 20 15 12 7 0 +</pre> +</dd> +<dt><code>R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3</code></dt> +<dt><code>R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3</code></dt> +<dd><pre class="verbatim">+-----+-------+-----+-----+-------+----+---------+ +| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 | ++-----+-------+-----+-----+-------+----+---------+ +31 27 25 20 15 12 7 0 +</pre> +</dd> +<dt><code>I type: .insn i opcode6, func3, rd, rs1, simm12</code></dt> +<dt><code>I type: .insn i opcode6, func3, rd, simm12(rs1)</code></dt> +<dd><pre class="verbatim">+--------------+-----+-------+----+---------+ +| simm12[11:0] | rs1 | func3 | rd | opcode6 | ++--------------+-----+-------+----+---------+ +31 20 15 12 7 0 +</pre> +</dd> +<dt><code>S type: .insn s opcode6, func3, rs2, simm12(rs1)</code></dt> +<dd><pre class="verbatim">+--------------+-----+-----+-------+-------------+---------+ +| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 | ++--------------+-----+-----+-------+-------------+---------+ +31 25 20 15 12 7 0 +</pre> +</dd> +<dt><code>B type: .insn s opcode6, func3, rs1, rs2, symbol</code></dt> +<dt><code>SB type: .insn sb opcode6, func3, rs1, rs2, symbol</code></dt> +<dd><pre class="verbatim">+-----------------+-----+-----+-------+----------------+---------+ +| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 | ++-----------------+-----+-----+-------+----------------+---------+ +31 25 20 15 12 7 0 +</pre> +</dd> +<dt><code>U type: .insn u opcode6, rd, simm20</code></dt> +<dd><pre class="verbatim">+--------------------------+----+---------+ +| simm20[20|10:1|11|19:12] | rd | opcode6 | ++--------------------------+----+---------+ +31 12 7 0 +</pre> +</dd> +<dt><code>J type: .insn j opcode6, rd, symbol</code></dt> +<dt><code>UJ type: .insn uj opcode6, rd, symbol</code></dt> +<dd><pre class="verbatim">+------------+--------------+------------+---------------+----+---------+ +| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 | ++------------+--------------+------------+---------------+----+---------+ +31 30 21 20 12 7 0 +</pre> +</dd> +<dt><code>CR type: .insn cr opcode2, func4, rd, rs2</code></dt> +<dd><pre class="verbatim">+-------+--------+-----+---------+ +| func4 | rd/rs1 | rs2 | opcode2 | ++-------+--------+-----+---------+ +15 12 7 2 0 +</pre> +</dd> +<dt><code>CI type: .insn ci opcode2, func3, rd, simm6</code></dt> +<dd><pre class="verbatim">+-------+----------+--------+------------+---------+ +| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 | ++-------+----------+--------+------------+---------+ +15 13 12 7 2 0 +</pre> +</dd> +<dt><code>CIW type: .insn ciw opcode2, func3, rd', uimm8</code></dt> +<dd><pre class="verbatim">+-------+------------+-----+---------+ +| func3 | uimm8[7:0] | rd' | opcode2 | ++-------+-------- ---+-----+---------+ +15 13 5 2 0 +</pre> +</dd> +<dt><code>CSS type: .insn css opcode2, func3, rd, uimm6</code></dt> +<dd><pre class="verbatim">+-------+------------+----+---------+ +| func3 | uimm6[5:0] | rd | opcode2 | ++-------+------------+----+---------+ +15 13 7 2 0 +</pre> +</dd> +<dt><code>CL type: .insn cl opcode2, func3, rd', uimm5(rs1')</code></dt> +<dd><pre class="verbatim">+-------+------------+------+------------+------+---------+ +| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rd' | opcode2 | ++-------+------------+------+------------+------+---------+ +15 13 10 7 5 2 0 +</pre> +</dd> +<dt><code>CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')</code></dt> +<dd><pre class="verbatim">+-------+------------+------+------------+------+---------+ +| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 | ++-------+------------+------+------------+------+---------+ +15 13 10 7 5 2 0 +</pre> +</dd> +<dt><code>CA type: .insn ca opcode2, func6, func2, rd', rs2'</code></dt> +<dd><pre class="verbatim">+-- ----+----------+-------+------+---------+ +| func6 | rd'/rs1' | func2 | rs2' | opcode2 | ++-------+----------+-------+------+---------+ +15 10 7 5 2 0 +</pre> +</dd> +<dt><code>CB type: .insn cb opcode2, func3, rs1', symbol</code></dt> +<dd><pre class="verbatim">+-------+--------------+------+------------------+---------+ +| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 | ++-------+--------------+------+------------------+---------+ +15 13 10 7 2 0 +</pre> +</dd> +<dt><code>CJ type: .insn cj opcode2, symbol</code></dt> +<dd><pre class="verbatim">+-------+-------------------------------+---------+ +| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 | ++-------+-------------------------------+---------+ +15 13 2 0 +</pre> + +</dd> +</dl> + +<p>For the complete list of all instruction format variants see +The RISC-V Instruction Set Manual Volume I: User-Level ISA. +</p> +<hr> +<a name="RISC_002dV_002dATTRIBUTE"></a> +<div class="header"> +<p> +Next: <a href="#RISC_002dV_002dCustomExts" accesskey="n" rel="next">RISC-V-CustomExts</a>, Previous: <a href="#RISC_002dV_002dFormats" accesskey="p" rel="previous">RISC-V-Formats</a>, Up: <a href="#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RISC_002dV-Object-Attribute"></a> +<h4 class="subsection">9.38.6 RISC-V Object Attribute</h4> +<a name="index-Object-Attribute_002c-RISC_002dV"></a> + +<p>RISC-V attributes have a string value if the tag number is odd and an integer +value if the tag number is even. +</p> +<dl compact="compact"> +<dt><span class="roman">Tag_RISCV_stack_align (4)</span></dt> +<dd><p>Tag_RISCV_strict_align records the N-byte stack alignment for this object. The +default value is 16 for RV32I or RV64I, and 4 for RV32E. +</p> +<p>The smallest value will be used if object files with different +Tag_RISCV_stack_align values are merged. +</p> +</dd> +<dt><span class="roman">Tag_RISCV_arch (5)</span></dt> +<dd><p>Tag_RISCV_arch contains a string for the target architecture taken from the +option <samp>-march</samp>. Different architectures will be integrated into a +superset when object files are merged. +</p> +<p>Note that the version information of the target architecture must be presented +explicitly in the attribute and abbreviations must be expanded. The version +information, if not given by <samp>-march</samp>, must be in accordance with the +default specified by the tool. For example, the architecture <code>RV32I</code> has +to be recorded in the attribute as <code>RV32I2P0</code> in which <code>2P0</code> stands +for the default version of its base ISA. On the other hand, the architecture +<code>RV32G</code> has to be presented as <code>RV32I2P0_M2P0_A2P0_F2P0_D2P0</code> in +which the abbreviation <code>G</code> is expanded to the <code>IMAFD</code> combination +with default versions of the standard extensions. +</p> +</dd> +<dt><span class="roman">Tag_RISCV_unaligned_access (6)</span></dt> +<dd><p>Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned +memory accesses, and 1 for files that do allow unaligned memory accesses. +</p> +</dd> +<dt><span class="roman">Tag_RISCV_priv_spec (8)</span></dt> +<dt><span class="roman">Tag_RISCV_priv_spec_minor (10)</span></dt> +<dt><span class="roman">Tag_RISCV_priv_spec_revision (12)</span></dt> +<dd><p>Tag_RISCV_priv_spec contains the major/minor/revision version information of +the privileged specification. It will report errors if object files of +different privileged specification versions are merged. +</p> +</dd> +</dl> + +<hr> +<a name="RISC_002dV_002dCustomExts"></a> +<div class="header"> +<p> +Previous: <a href="#RISC_002dV_002dATTRIBUTE" accesskey="p" rel="previous">RISC-V-ATTRIBUTE</a>, Up: <a href="#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RISC_002dV-Custom-_0028Vendor_002dDefined_0029-Extensions"></a> +<h4 class="subsection">9.38.7 RISC-V Custom (Vendor-Defined) Extensions</h4> +<a name="index-custom-_0028vendor_002ddefined_0029-extensions_002c-RISC_002dV"></a> +<a name="index-RISC_002dV-custom-_0028vendor_002ddefined_0029-extensions"></a> + +<p>The following table lists the custom (vendor-defined) RISC-V +extensions supported and provides the location of their +publicly-released documentation: +</p> +<dl compact="compact"> +<dt><span class="roman">XTheadBa</span></dt> +<dd><p>The XTheadBa extension provides instructions for address calculations. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadBb</span></dt> +<dd><p>The XTheadBb extension provides instructions for basic bit-manipulation +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadBs</span></dt> +<dd><p>The XTheadBs extension provides single-bit instructions. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadCmo</span></dt> +<dd><p>The XTheadCmo extension provides instructions for cache management. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadCondMov</span></dt> +<dd><p>The XTheadCondMov extension provides instructions for conditional moves. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadFMemIdx</span></dt> +<dd><p>The XTheadFMemIdx extension provides floating-point memory operations. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadFmv</span></dt> +<dd><p>The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precision floating point register. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadInt</span></dt> +<dd><p>The XTheadInt extension provides access to ISR stack management instructions. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadMac</span></dt> +<dd><p>The XTheadMac extension provides multiply-accumulate instructions. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadMemIdx</span></dt> +<dd><p>The XTheadMemIdx extension provides GPR memory operations. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadMemPair</span></dt> +<dd><p>The XTheadMemPair extension provides two-GP-register memory operations. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p> +</dd> +<dt><span class="roman">XTheadSync</span></dt> +<dd><p>The XTheadSync extension provides instructions for multi-processor synchronization. +</p> +<p>It is documented in <a href="https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf">https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf</a>. +</p></dd> +<dt><span class="roman">XVentanaCondOps</span></dt> +<dd><p>XVentanaCondOps extension provides instructions for branchless +sequences that perform conditional arithmetic, conditional +bitwise-logic, and conditional select operations. +</p> +<p>It is documented at <a href="https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf">https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf</a>. +</p> +</dd> +</dl> + +<hr> +<a name="RL78_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#RX_002dDependent" accesskey="n" rel="next">RX-Dependent</a>, Previous: <a href="#RISC_002dV_002dDependent" accesskey="p" rel="previous">RISC-V-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RL78-Dependent-Features"></a> +<h3 class="section">9.39 RL78 Dependent Features</h3> + +<a name="index-RL78-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#RL78_002dOpts" accesskey="1">RL78-Opts</a>:</td><td> </td><td align="left" valign="top">RL78 Assembler Command-line Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#RL78_002dModifiers" accesskey="2">RL78-Modifiers</a>:</td><td> </td><td align="left" valign="top">Symbolic Operand Modifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#RL78_002dDirectives" accesskey="3">RL78-Directives</a>:</td><td> </td><td align="left" valign="top">Assembler Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#RL78_002dSyntax" accesskey="4">RL78-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +</table> + +<hr> +<a name="RL78_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#RL78_002dModifiers" accesskey="n" rel="next">RL78-Modifiers</a>, Up: <a href="#RL78_002dDependent" accesskey="u" rel="up">RL78-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RL78-Options"></a> +<h4 class="subsection">9.39.1 RL78 Options</h4> +<a name="index-options_002c-RL78"></a> +<a name="index-RL78-options"></a> + +<dl compact="compact"> +<dt><code>relax</code></dt> +<dd><p>Enable support for link-time relaxation. +</p> +</dd> +<dt><code>norelax</code></dt> +<dd><p>Disable support for link-time relaxation (default). +</p> +</dd> +<dt><code>mg10</code></dt> +<dd><p>Mark the generated binary as targeting the G10 variant of the RL78 +architecture. +</p> +</dd> +<dt><code>mg13</code></dt> +<dd><p>Mark the generated binary as targeting the G13 variant of the RL78 +architecture. +</p> +</dd> +<dt><code>mg14</code></dt> +<dt><code>mrl78</code></dt> +<dd><p>Mark the generated binary as targeting the G14 variant of the RL78 +architecture. This is the default. +</p> +</dd> +<dt><code>m32bit-doubles</code></dt> +<dd><p>Mark the generated binary as one that uses 32-bits to hold the +<code>double</code> floating point type. This is the default. +</p> +</dd> +<dt><code>m64bit-doubles</code></dt> +<dd><p>Mark the generated binary as one that uses 64-bits to hold the +<code>double</code> floating point type. +</p> +</dd> +</dl> + +<hr> +<a name="RL78_002dModifiers"></a> +<div class="header"> +<p> +Next: <a href="#RL78_002dDirectives" accesskey="n" rel="next">RL78-Directives</a>, Previous: <a href="#RL78_002dOpts" accesskey="p" rel="previous">RL78-Opts</a>, Up: <a href="#RL78_002dDependent" accesskey="u" rel="up">RL78-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbolic-Operand-Modifiers-2"></a> +<h4 class="subsection">9.39.2 Symbolic Operand Modifiers</h4> + +<a name="index-RL78-modifiers"></a> +<a name="index-syntax_002c-RL78"></a> + +<p>The RL78 has three modifiers that adjust the relocations used by the +linker: +</p> +<dl compact="compact"> +<dt><code>%lo16()</code></dt> +<dd> +<p>When loading a 20-bit (or wider) address into registers, this modifier +selects the 16 least significant bits. +</p> +<div class="smallexample"> +<pre class="smallexample"> movw ax,#%lo16(_sym) +</pre></div> + +</dd> +<dt><code>%hi16()</code></dt> +<dd> +<p>When loading a 20-bit (or wider) address into registers, this modifier +selects the 16 most significant bits. +</p> +<div class="smallexample"> +<pre class="smallexample"> movw ax,#%hi16(_sym) +</pre></div> + +</dd> +<dt><code>%hi8()</code></dt> +<dd> +<p>When loading a 20-bit (or wider) address into registers, this modifier +selects the 8 bits that would go into CS or ES (i.e. bits 23..16). +</p> +<div class="smallexample"> +<pre class="smallexample"> mov es, #%hi8(_sym) +</pre></div> + +</dd> +</dl> + +<hr> +<a name="RL78_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#RL78_002dSyntax" accesskey="n" rel="next">RL78-Syntax</a>, Previous: <a href="#RL78_002dModifiers" accesskey="p" rel="previous">RL78-Modifiers</a>, Up: <a href="#RL78_002dDependent" accesskey="u" rel="up">RL78-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives-5"></a> +<h4 class="subsection">9.39.3 Assembler Directives</h4> + +<a name="index-assembler-directives_002c-RL78"></a> +<a name="index-RL78-assembler-directives"></a> + +<p>In addition to the common directives, the RL78 adds these: +</p> +<dl compact="compact"> +<dt><code>.double</code></dt> +<dd><p>Output a constant in “double” format, which is either a 32-bit +or a 64-bit floating point value, depending upon the setting of the +<samp>-m32bit-doubles</samp>|<samp>-m64bit-doubles</samp> command-line +option. +</p> +</dd> +<dt><code>.bss</code></dt> +<dd><p>Select the BSS section. +</p> +</dd> +<dt><code>.3byte</code></dt> +<dd><p>Output a constant value in a three byte format. +</p> +</dd> +<dt><code>.int</code></dt> +<dt><code>.word</code></dt> +<dd><p>Output a constant value in a four byte format. +</p> +</dd> +</dl> + +<hr> +<a name="RL78_002dSyntax"></a> +<div class="header"> +<p> +Previous: <a href="#RL78_002dDirectives" accesskey="p" rel="previous">RL78-Directives</a>, Up: <a href="#RL78_002dDependent" accesskey="u" rel="up">RL78-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-for-the-RL78"></a> +<h4 class="subsection">9.39.4 Syntax for the RL78</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#RL78_002dChars" accesskey="1">RL78-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="RL78_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#RL78_002dSyntax" accesskey="u" rel="up">RL78-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-30"></a> +<h4 class="subsubsection">9.39.4.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-RL78"></a> +<a name="index-RL78-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ appearing anywhere on a line indicates the +start of a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-RL78"></a> +<a name="index-statement-separator_002c-RL78"></a> +<a name="index-RL78-line-separator"></a> +<p>The ‘<samp>|</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="RX_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#S_002f390_002dDependent" accesskey="n" rel="next">S/390-Dependent</a>, Previous: <a href="#RL78_002dDependent" accesskey="p" rel="previous">RL78-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RX-Dependent-Features"></a> +<h3 class="section">9.40 RX Dependent Features</h3> + +<a name="index-RX-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#RX_002dOpts" accesskey="1">RX-Opts</a>:</td><td> </td><td align="left" valign="top">RX Assembler Command-line Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#RX_002dModifiers" accesskey="2">RX-Modifiers</a>:</td><td> </td><td align="left" valign="top">Symbolic Operand Modifiers +</td></tr> +<tr><td align="left" valign="top">• <a href="#RX_002dDirectives" accesskey="3">RX-Directives</a>:</td><td> </td><td align="left" valign="top">Assembler Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#RX_002dFloat" accesskey="4">RX-Float</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#RX_002dSyntax" accesskey="5">RX-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +</table> + +<hr> +<a name="RX_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#RX_002dModifiers" accesskey="n" rel="next">RX-Modifiers</a>, Up: <a href="#RX_002dDependent" accesskey="u" rel="up">RX-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="RX-Options"></a> +<h4 class="subsection">9.40.1 RX Options</h4> +<a name="index-options_002c-RX"></a> +<a name="index-RX-options"></a> + +<p>The Renesas RX port of <code>as</code> has a few target specific +command-line options: +</p> +<dl compact="compact"> +<dd> +<a name="index-_002dm32bit_002ddoubles"></a> +</dd> +<dt><code>-m32bit-doubles</code></dt> +<dd><p>This option controls the ABI and indicates to use a 32-bit float ABI. +It has no effect on the assembled instructions, but it does influence +the behaviour of the ‘<samp>.double</samp>’ pseudo-op. +This is the default. +</p> +<a name="index-_002dm64bit_002ddoubles"></a> +</dd> +<dt><code>-m64bit-doubles</code></dt> +<dd><p>This option controls the ABI and indicates to use a 64-bit float ABI. +It has no effect on the assembled instructions, but it does influence +the behaviour of the ‘<samp>.double</samp>’ pseudo-op. +</p> +<a name="index-_002dmbig_002dendian"></a> +</dd> +<dt><code>-mbig-endian</code></dt> +<dd><p>This option controls the ABI and indicates to use a big-endian data +ABI. It has no effect on the assembled instructions, but it does +influence the behaviour of the ‘<samp>.short</samp>’, ‘<samp>.hword</samp>’, ‘<samp>.int</samp>’, +‘<samp>.word</samp>’, ‘<samp>.long</samp>’, ‘<samp>.quad</samp>’ and ‘<samp>.octa</samp>’ pseudo-ops. +</p> +<a name="index-_002dmlittle_002dendian"></a> +</dd> +<dt><code>-mlittle-endian</code></dt> +<dd><p>This option controls the ABI and indicates to use a little-endian data +ABI. It has no effect on the assembled instructions, but it does +influence the behaviour of the ‘<samp>.short</samp>’, ‘<samp>.hword</samp>’, ‘<samp>.int</samp>’, +‘<samp>.word</samp>’, ‘<samp>.long</samp>’, ‘<samp>.quad</samp>’ and ‘<samp>.octa</samp>’ pseudo-ops. +This is the default. +</p> +<a name="index-_002dmuse_002dconventional_002dsection_002dnames"></a> +</dd> +<dt><code>-muse-conventional-section-names</code></dt> +<dd><p>This option controls the default names given to the code (.text), +initialised data (.data) and uninitialised data sections (.bss). +</p> +<a name="index-_002dmuse_002drenesas_002dsection_002dnames"></a> +</dd> +<dt><code>-muse-renesas-section-names</code></dt> +<dd><p>This option controls the default names given to the code (P), +initialised data (D_1) and uninitialised data sections (B_1). +This is the default. +</p> +<a name="index-_002dmsmall_002ddata_002dlimit"></a> +</dd> +<dt><code>-msmall-data-limit</code></dt> +<dd><p>This option tells the assembler that the small data limit feature of +the RX port of GCC is being used. This results in the assembler +generating an undefined reference to a symbol called <code>__gp</code> for +use by the relocations that are needed to support the small data limit +feature. This option is not enabled by default as it would otherwise +pollute the symbol table. +</p> +<a name="index-_002dmpid"></a> +</dd> +<dt><code>-mpid</code></dt> +<dd><p>This option tells the assembler that the position independent data of the +RX port of GCC is being used. This results in the assembler +generating an undefined reference to a symbol called <code>__pid_base</code>, +and also setting the RX_PID flag bit in the e_flags field of the ELF +header of the object file. +</p> +<a name="index-_002dmint_002dregister"></a> +</dd> +<dt><code>-mint-register=<var>num</var></code></dt> +<dd><p>This option tells the assembler how many registers have been reserved +for use by interrupt handlers. This is needed in order to compute the +correct values for the <code>%gpreg</code> and <code>%pidreg</code> meta registers. +</p> +<a name="index-_002dmgcc_002dabi"></a> +</dd> +<dt><code>-mgcc-abi</code></dt> +<dd><p>This option tells the assembler that the old GCC ABI is being used by +the assembled code. With this version of the ABI function arguments +that are passed on the stack are aligned to a 32-bit boundary. +</p> +<a name="index-_002dmrx_002dabi"></a> +</dd> +<dt><code>-mrx-abi</code></dt> +<dd><p>This option tells the assembler that the official RX ABI is being used +by the assembled code. With this version of the ABI function +arguments that are passed on the stack are aligned to their natural +alignments. This option is the default. +</p> +<a name="index-_002dmcpu_003d"></a> +</dd> +<dt><code>-mcpu=<var>name</var></code></dt> +<dd><p>This option tells the assembler the target CPU type. Currently the +<code>rx100</code>, <code>rx200</code>, <code>rx600</code>, <code>rx610</code>, <code>rxv2</code>, +<code>rxv3</code> and <code>rxv3-dfpu</code> are recognised as valid cpu names. +Attempting to assemble an instructionnot supported by the indicated +cpu type will result in an error message being generated. +</p> +<a name="index-_002dmno_002dallow_002dstring_002dinsns"></a> +</dd> +<dt><code>-mno-allow-string-insns</code></dt> +<dd><p>This option tells the assembler to mark the object file that it is +building as one that does not use the string instructions +<code>SMOVF</code>, <code>SCMPU</code>, <code>SMOVB</code>, <code>SMOVU</code>, <code>SUNTIL</code> +<code>SWHILE</code> or the <code>RMPA</code> instruction. In addition the mark +tells the linker to complain if an attempt is made to link the binary +with another one that does use any of these instructions. +</p> +<p>Note - the inverse of this option, <code>-mallow-string-insns</code>, is +not needed. The assembler automatically detects the use of the +the instructions in the source code and labels the resulting +object file appropriately. If no string instructions are detected +then the object file is labelled as being one that can be linked with +either string-using or string-banned object files. +</p></dd> +</dl> + +<hr> +<a name="RX_002dModifiers"></a> +<div class="header"> +<p> +Next: <a href="#RX_002dDirectives" accesskey="n" rel="next">RX-Directives</a>, Previous: <a href="#RX_002dOpts" accesskey="p" rel="previous">RX-Opts</a>, Up: <a href="#RX_002dDependent" accesskey="u" rel="up">RX-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbolic-Operand-Modifiers-3"></a> +<h4 class="subsection">9.40.2 Symbolic Operand Modifiers</h4> + +<a name="index-RX-modifiers"></a> +<a name="index-syntax_002c-RX"></a> +<a name="index-_0025gp"></a> + +<p>The assembler supports one modifier when using symbol addresses +in RX instruction operands. The general syntax is the following: +</p> +<div class="smallexample"> +<pre class="smallexample">%gp(symbol) +</pre></div> + +<p>The modifier returns the offset from the <var>__gp</var> symbol to the +specified symbol as a 16-bit value. The intent is that this offset +should be used in a register+offset move instruction when generating +references to small data. Ie, like this: +</p> +<div class="smallexample"> +<pre class="smallexample"> mov.W %gp(_foo)[%gpreg], r1 +</pre></div> + +<p>The assembler also supports two meta register names which can be used +to refer to registers whose values may not be known to the +programmer. These meta register names are: +</p> +<dl compact="compact"> +<dd> +<a name="index-_0025gpreg"></a> +</dd> +<dt><code>%gpreg</code></dt> +<dd><p>The small data address register. +</p> +<a name="index-_0025pidreg"></a> +</dd> +<dt><code>%pidreg</code></dt> +<dd><p>The PID base address register. +</p> +</dd> +</dl> + +<p>Both registers normally have the value r13, but this can change if +some registers have been reserved for use by interrupt handlers or if +both the small data limit and position independent data features are +being used at the same time. +</p> +<hr> +<a name="RX_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#RX_002dFloat" accesskey="n" rel="next">RX-Float</a>, Previous: <a href="#RX_002dModifiers" accesskey="p" rel="previous">RX-Modifiers</a>, Up: <a href="#RX_002dDependent" accesskey="u" rel="up">RX-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives-6"></a> +<h4 class="subsection">9.40.3 Assembler Directives</h4> + +<a name="index-assembler-directives_002c-RX"></a> +<a name="index-RX-assembler-directives"></a> + +<p>The RX version of <code>as</code> has the following specific +assembler directives: +</p> +<dl compact="compact"> +<dt><code>.3byte</code></dt> +<dd><a name="index-assembler-directive-_002e3byte_002c-RX"></a> +<a name="index-RX-assembler-directive-_002e3byte"></a> +<p>Inserts a 3-byte value into the output file at the current location. +</p> +</dd> +<dt><code>.fetchalign</code></dt> +<dd><a name="index-assembler-directive-_002efetchalign_002c-RX"></a> +<a name="index-RX-assembler-directive-_002efetchalign"></a> +<p>If the next opcode following this directive spans a fetch line +boundary (8 byte boundary), the opcode is aligned to that boundary. +If the next opcode does not span a fetch line, this directive has no +effect. Note that one or more labels may be between this directive +and the opcode; those labels are aligned as well. Any inserted bytes +due to alignment will form a NOP opcode. +</p> +</dd> +</dl> + +<hr> +<a name="RX_002dFloat"></a> +<div class="header"> +<p> +Next: <a href="#RX_002dSyntax" accesskey="n" rel="next">RX-Syntax</a>, Previous: <a href="#RX_002dDirectives" accesskey="p" rel="previous">RX-Directives</a>, Up: <a href="#RX_002dDependent" accesskey="u" rel="up">RX-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-12"></a> +<h4 class="subsection">9.40.4 Floating Point</h4> + +<a name="index-floating-point_002c-RX"></a> +<a name="index-RX-floating-point"></a> + +<p>The floating point formats generated by directives are these. +</p> +<dl compact="compact"> +<dd><a name="index-float-directive_002c-RX"></a> + +</dd> +<dt><code>.float</code></dt> +<dd><p><code>Single</code> precision (32-bit) floating point constants. +</p> +<a name="index-double-directive_002c-RX"></a> +</dd> +<dt><code>.double</code></dt> +<dd><p>If the <samp>-m64bit-doubles</samp> command-line option has been specified +then then <code>double</code> directive generates <code>double</code> precision +(64-bit) floating point constants, otherwise it generates +<code>single</code> precision (32-bit) floating point constants. To force +the generation of 64-bit floating point constants used the <code>dc.d</code> +directive instead. +</p> +</dd> +</dl> + +<hr> +<a name="RX_002dSyntax"></a> +<div class="header"> +<p> +Previous: <a href="#RX_002dFloat" accesskey="p" rel="previous">RX-Float</a>, Up: <a href="#RX_002dDependent" accesskey="u" rel="up">RX-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-for-the-RX"></a> +<h4 class="subsection">9.40.5 Syntax for the RX</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#RX_002dChars" accesskey="1">RX-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="RX_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#RX_002dSyntax" accesskey="u" rel="up">RX-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-31"></a> +<h4 class="subsubsection">9.40.5.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-RX"></a> +<a name="index-RX-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ appearing anywhere on a line indicates the +start of a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-RX"></a> +<a name="index-statement-separator_002c-RX"></a> +<a name="index-RX-line-separator"></a> +<p>The ‘<samp>!</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="S_002f390_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#SCORE_002dDependent" accesskey="n" rel="next">SCORE-Dependent</a>, Previous: <a href="#RX_002dDependent" accesskey="p" rel="previous">RX-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="IBM-S_002f390-Dependent-Features"></a> +<h3 class="section">9.41 IBM S/390 Dependent Features</h3> + +<a name="index-s390-support"></a> + +<p>The s390 version of <code>as</code> supports two architectures modes +and eleven chip levels. The architecture modes are the Enterprise System +Architecture (ESA) and the newer z/Architecture mode. The chip levels +are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec +(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 +(or arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14). +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#s390-Options" accesskey="1">s390 Options</a>:</td><td> </td><td align="left" valign="top">Command-line Options. +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Characters" accesskey="2">s390 Characters</a>:</td><td> </td><td align="left" valign="top">Special Characters. +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Syntax" accesskey="3">s390 Syntax</a>:</td><td> </td><td align="left" valign="top">Assembler Instruction syntax. +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Directives" accesskey="4">s390 Directives</a>:</td><td> </td><td align="left" valign="top">Assembler Directives. +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Floating-Point" accesskey="5">s390 Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point. +</td></tr> +</table> + +<hr> +<a name="s390-Options"></a> +<div class="header"> +<p> +Next: <a href="#s390-Characters" accesskey="n" rel="next">s390 Characters</a>, Up: <a href="#S_002f390_002dDependent" accesskey="u" rel="up">S/390-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-21"></a> +<h4 class="subsection">9.41.1 Options</h4> +<a name="index-options-for-s390"></a> +<a name="index-s390-options"></a> + +<p>The following table lists all available s390 specific options: +</p> +<dl compact="compact"> +<dd><a name="index-_002dm31-option_002c-s390"></a> +<a name="index-_002dm64-option_002c-s390"></a> +</dd> +<dt><code>-m31 | -m64</code></dt> +<dd><p>Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. +</p> +<p>These options are only available with the ELF object file format, and +require that the necessary BFD support has been included (on a 31-bit +platform you must add –enable-64-bit-bfd on the call to the configure +script to enable 64-bit usage and use s390x as target platform). +</p> +<a name="index-_002dmesa-option_002c-s390"></a> +<a name="index-_002dmzarch-option_002c-s390"></a> +</dd> +<dt><code>-mesa | -mzarch</code></dt> +<dd><p>Select the architecture mode, either the Enterprise System Architecture +(esa) mode or the z/Architecture mode (zarch). +</p> +<p>The 64-bit instructions are only available with the z/Architecture mode. +The combination of ‘<samp>-m64</samp>’ and ‘<samp>-mesa</samp>’ results in a warning +message. +</p> +<a name="index-_002dmarch_003d-option_002c-s390"></a> +</dd> +<dt><code>-march=<var>CPU</var></code></dt> +<dd><p>This option specifies the target processor. The following processor names +are recognized: +<code>g5</code> (or <code>arch3</code>), +<code>g6</code>, +<code>z900</code> (or <code>arch5</code>), +<code>z990</code> (or <code>arch6</code>), +<code>z9-109</code>, +<code>z9-ec</code> (or <code>arch7</code>), +<code>z10</code> (or <code>arch8</code>), +<code>z196</code> (or <code>arch9</code>), +<code>zEC12</code> (or <code>arch10</code>), +<code>z13</code> (or <code>arch11</code>), +<code>z14</code> (or <code>arch12</code>), +<code>z15</code> (or <code>arch13</code>), and +<code>z16</code> (or <code>arch14</code>). +</p> +<p>Assembling an instruction that is not supported on the target +processor results in an error message. +</p> +<p>The processor names starting with <code>arch</code> refer to the edition +number in the Principle of Operations manual. They can be used as +alternate processor names and have been added for compatibility with +the IBM XL compiler. +</p> +<p><code>arch3</code>, <code>g5</code> and <code>g6</code> cannot be used with the +‘<samp>-mzarch</samp>’ option since the z/Architecture mode is not supported +on these processor levels. +</p> +<p>There is no <code>arch4</code> option supported. <code>arch4</code> matches +<code>-march=arch5 -mesa</code>. +</p> +<a name="index-_002dmregnames-option_002c-s390"></a> +</dd> +<dt><code>-mregnames</code></dt> +<dd><p>Allow symbolic names for registers. +</p> +<a name="index-_002dmno_002dregnames-option_002c-s390"></a> +</dd> +<dt><code>-mno-regnames</code></dt> +<dd><p>Do not allow symbolic names for registers. +</p> +<a name="index-_002dmwarn_002dareg_002dzero-option_002c-s390"></a> +</dd> +<dt><code>-mwarn-areg-zero</code></dt> +<dd><p>Warn whenever the operand for a base or index register has been specified +but evaluates to zero. This can indicate the misuse of general purpose +register 0 as an address register. +</p> +</dd> +</dl> + +<hr> +<a name="s390-Characters"></a> +<div class="header"> +<p> +Next: <a href="#s390-Syntax" accesskey="n" rel="next">s390 Syntax</a>, Previous: <a href="#s390-Options" accesskey="p" rel="previous">s390 Options</a>, Up: <a href="#S_002f390_002dDependent" accesskey="u" rel="up">S/390-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-32"></a> +<h4 class="subsection">9.41.2 Special Characters</h4> +<a name="index-line-comment-character_002c-s390"></a> +<a name="index-s390-line-comment-character"></a> + +<p>‘<samp>#</samp>’ is the line comment character. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-s390"></a> +<a name="index-statement-separator_002c-s390"></a> +<a name="index-s390-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used instead of a newline to separate +statements. +</p> +<hr> +<a name="s390-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#s390-Directives" accesskey="n" rel="next">s390 Directives</a>, Previous: <a href="#s390-Characters" accesskey="p" rel="previous">s390 Characters</a>, Up: <a href="#S_002f390_002dDependent" accesskey="u" rel="up">S/390-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-syntax"></a> +<h4 class="subsection">9.41.3 Instruction syntax</h4> +<a name="index-instruction-syntax_002c-s390"></a> +<a name="index-s390-instruction-syntax"></a> + +<p>The assembler syntax closely follows the syntax outlined in +Enterprise Systems Architecture/390 Principles of Operation (SA22-7201) +and the z/Architecture Principles of Operation (SA22-7832). +</p> +<p>Each instruction has two major parts, the instruction mnemonic +and the instruction operands. The instruction format varies. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#s390-Register" accesskey="1">s390 Register</a>:</td><td> </td><td align="left" valign="top">Register Naming +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Mnemonics" accesskey="2">s390 Mnemonics</a>:</td><td> </td><td align="left" valign="top">Instruction Mnemonics +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Operands" accesskey="3">s390 Operands</a>:</td><td> </td><td align="left" valign="top">Instruction Operands +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Formats" accesskey="4">s390 Formats</a>:</td><td> </td><td align="left" valign="top">Instruction Formats +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Aliases" accesskey="5">s390 Aliases</a>:</td><td> </td><td align="left" valign="top">Instruction Aliases +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Operand-Modifier" accesskey="6">s390 Operand Modifier</a>:</td><td> </td><td align="left" valign="top">Instruction Operand Modifier +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Instruction-Marker" accesskey="7">s390 Instruction Marker</a>:</td><td> </td><td align="left" valign="top">Instruction Marker +</td></tr> +<tr><td align="left" valign="top">• <a href="#s390-Literal-Pool-Entries" accesskey="8">s390 Literal Pool Entries</a>:</td><td> </td><td align="left" valign="top">Literal Pool Entries +</td></tr> +</table> + +<hr> +<a name="s390-Register"></a> +<div class="header"> +<p> +Next: <a href="#s390-Mnemonics" accesskey="n" rel="next">s390 Mnemonics</a>, Up: <a href="#s390-Syntax" accesskey="u" rel="up">s390 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-naming"></a> +<h4 class="subsubsection">9.41.3.1 Register naming</h4> +<a name="index-register-naming_002c-s390"></a> +<a name="index-s390-register-naming"></a> + +<p>The <code>as</code> recognizes a number of predefined symbols for the +various processor registers. A register specification in one of the +instruction formats is an unsigned integer between 0 and 15. The specific +instruction and the position of the register in the instruction format +denotes the type of the register. The register symbols are prefixed with +‘<samp>%</samp>’: +</p> +<div class="display"> +<table> +<tr><td><pre class="display">%rN</pre></td><td><pre class="display">the 16 general purpose registers, 0 <= N <= 15</pre></td></tr> +<tr><td><pre class="display">%fN</pre></td><td><pre class="display">the 16 floating point registers, 0 <= N <= 15</pre></td></tr> +<tr><td><pre class="display">%aN</pre></td><td><pre class="display">the 16 access registers, 0 <= N <= 15</pre></td></tr> +<tr><td><pre class="display">%cN</pre></td><td><pre class="display">the 16 control registers, 0 <= N <= 15</pre></td></tr> +<tr><td><pre class="display">%lit</pre></td><td><pre class="display">an alias for the general purpose register %r13</pre></td></tr> +<tr><td><pre class="display">%sp</pre></td><td><pre class="display">an alias for the general purpose register %r15</pre></td></tr> +</table> +</div> + +<hr> +<a name="s390-Mnemonics"></a> +<div class="header"> +<p> +Next: <a href="#s390-Operands" accesskey="n" rel="next">s390 Operands</a>, Previous: <a href="#s390-Register" accesskey="p" rel="previous">s390 Register</a>, Up: <a href="#s390-Syntax" accesskey="u" rel="up">s390 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-Mnemonics"></a> +<h4 class="subsubsection">9.41.3.2 Instruction Mnemonics</h4> +<a name="index-instruction-mnemonics_002c-s390"></a> +<a name="index-s390-instruction-mnemonics"></a> + +<p>All instructions documented in the Principles of Operation are supported +with the mnemonic and order of operands as described. +The instruction mnemonic identifies the instruction format +(<a href="#s390-Formats">s390 Formats</a>) and the specific operation code for the instruction. +For example, the ‘<samp>lr</samp>’ mnemonic denotes the instruction format ‘<samp>RR</samp>’ +with the operation code ‘<samp>0x18</samp>’. +</p> +<p>The definition of the various mnemonics follows a scheme, where the first +character usually hint at the type of the instruction: +</p> +<div class="display"> +<table> +<tr><td><pre class="display">a</pre></td><td><pre class="display">add instruction, for example ‘<samp>al</samp>’ for add logical 32-bit</pre></td></tr> +<tr><td><pre class="display">b</pre></td><td><pre class="display">branch instruction, for example ‘<samp>bc</samp>’ for branch on condition</pre></td></tr> +<tr><td><pre class="display">c</pre></td><td><pre class="display">compare or convert instruction, for example ‘<samp>cr</samp>’ for compare +register 32-bit</pre></td></tr> +<tr><td><pre class="display">d</pre></td><td><pre class="display">divide instruction, for example ‘<samp>dlr</samp>’ devide logical register +64-bit to 32-bit</pre></td></tr> +<tr><td><pre class="display">i</pre></td><td><pre class="display">insert instruction, for example ‘<samp>ic</samp>’ insert character</pre></td></tr> +<tr><td><pre class="display">l</pre></td><td><pre class="display">load instruction, for example ‘<samp>ltr</samp>’ load and test register</pre></td></tr> +<tr><td><pre class="display">mv</pre></td><td><pre class="display">move instruction, for example ‘<samp>mvc</samp>’ move character</pre></td></tr> +<tr><td><pre class="display">m</pre></td><td><pre class="display">multiply instruction, for example ‘<samp>mh</samp>’ multiply halfword</pre></td></tr> +<tr><td><pre class="display">n</pre></td><td><pre class="display">and instruction, for example ‘<samp>ni</samp>’ and immediate</pre></td></tr> +<tr><td><pre class="display">o</pre></td><td><pre class="display">or instruction, for example ‘<samp>oc</samp>’ or character</pre></td></tr> +<tr><td><pre class="display">sla, sll</pre></td><td><pre class="display">shift left single instruction</pre></td></tr> +<tr><td><pre class="display">sra, srl</pre></td><td><pre class="display">shift right single instruction</pre></td></tr> +<tr><td><pre class="display">st</pre></td><td><pre class="display">store instruction, for example ‘<samp>stm</samp>’ store multiple</pre></td></tr> +<tr><td><pre class="display">s</pre></td><td><pre class="display">subtract instruction, for example ‘<samp>slr</samp>’ subtract +logical 32-bit</pre></td></tr> +<tr><td><pre class="display">t</pre></td><td><pre class="display">test or translate instruction, of example ‘<samp>tm</samp>’ test under mask</pre></td></tr> +<tr><td><pre class="display">x</pre></td><td><pre class="display">exclusive or instruction, for example ‘<samp>xc</samp>’ exclusive or +character</pre></td></tr> +</table> +</div> + +<p>Certain characters at the end of the mnemonic may describe a property +of the instruction: +</p> +<div class="display"> +<table> +<tr><td><pre class="display">c</pre></td><td><pre class="display">the instruction uses a 8-bit character operand</pre></td></tr> +<tr><td><pre class="display">f</pre></td><td><pre class="display">the instruction extends a 32-bit operand to 64 bit</pre></td></tr> +<tr><td><pre class="display">g</pre></td><td><pre class="display">the operands are treated as 64-bit values</pre></td></tr> +<tr><td><pre class="display">h</pre></td><td><pre class="display">the operand uses a 16-bit halfword operand</pre></td></tr> +<tr><td><pre class="display">i</pre></td><td><pre class="display">the instruction uses an immediate operand</pre></td></tr> +<tr><td><pre class="display">l</pre></td><td><pre class="display">the instruction uses unsigned, logical operands</pre></td></tr> +<tr><td><pre class="display">m</pre></td><td><pre class="display">the instruction uses a mask or operates on multiple values</pre></td></tr> +<tr><td><pre class="display">r</pre></td><td><pre class="display">if r is the last character, the instruction operates on registers</pre></td></tr> +<tr><td><pre class="display">y</pre></td><td><pre class="display">the instruction uses 20-bit displacements</pre></td></tr> +</table> +</div> + +<p>There are many exceptions to the scheme outlined in the above lists, in +particular for the privileged instructions. For non-privileged +instruction it works quite well, for example the instruction ‘<samp>clgfr</samp>’ +c: compare instruction, l: unsigned operands, g: 64-bit operands, +f: 32- to 64-bit extension, r: register operands. The instruction compares +an 64-bit value in a register with the zero extended 32-bit value from +a second register. +For a complete list of all mnemonics see appendix B in the Principles +of Operation. +</p> +<hr> +<a name="s390-Operands"></a> +<div class="header"> +<p> +Next: <a href="#s390-Formats" accesskey="n" rel="next">s390 Formats</a>, Previous: <a href="#s390-Mnemonics" accesskey="p" rel="previous">s390 Mnemonics</a>, Up: <a href="#s390-Syntax" accesskey="u" rel="up">s390 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-Operands"></a> +<h4 class="subsubsection">9.41.3.3 Instruction Operands</h4> +<a name="index-instruction-operands_002c-s390"></a> +<a name="index-s390-instruction-operands"></a> + +<p>Instruction operands can be grouped into three classes, operands located +in registers, immediate operands, and operands in storage. +</p> +<p>A register operand can be located in general, floating-point, access, +or control register. The register is identified by a four-bit field. +The field containing the register operand is called the R field. +</p> +<p>Immediate operands are contained within the instruction and can have +8, 16 or 32 bits. The field containing the immediate operand is called +the I field. Dependent on the instruction the I field is either signed +or unsigned. +</p> +<p>A storage operand consists of an address and a length. The address of a +storage operands can be specified in any of these ways: +</p> +<ul> +<li> The content of a single general R +</li><li> The sum of the content of a general register called the base +register B plus the content of a displacement field D +</li><li> The sum of the contents of two general registers called the +index register X and the base register B plus the content of a +displacement field +</li><li> The sum of the current instruction address and a 32-bit signed +immediate field multiplied by two. +</li></ul> + +<p>The length of a storage operand can be: +</p> +<ul> +<li> Implied by the instruction +</li><li> Specified by a bitmask +</li><li> Specified by a four-bit or eight-bit length field L +</li><li> Specified by the content of a general register +</li></ul> + +<p>The notation for storage operand addresses formed from multiple fields is +as follows: +</p> +<dl compact="compact"> +<dt><code>Dn(Bn)</code></dt> +<dd><p>the address for operand number n is formed from the content of general +register Bn called the base register and the displacement field Dn. +</p></dd> +<dt><code>Dn(Xn,Bn)</code></dt> +<dd><p>the address for operand number n is formed from the content of general +register Xn called the index register, general register Bn called the +base register and the displacement field Dn. +</p></dd> +<dt><code>Dn(Ln,Bn)</code></dt> +<dd><p>the address for operand number n is formed from the content of general +register Bn called the base register and the displacement field Dn. +The length of the operand n is specified by the field Ln. +</p></dd> +</dl> + +<p>The base registers Bn and the index registers Xn of a storage operand can +be skipped. If Bn and Xn are skipped, a zero will be stored to the operand +field. The notation changes as follows: +</p> +<div class="display"> +<table> +<thead><tr><th width="30%"><pre class="display">full notation</pre></th><th width="30%"><pre class="display">short notation</pre></th></tr></thead> +<tr><td width="30%"><pre class="display">Dn(0,Bn)</pre></td><td width="30%"><pre class="display">Dn(Bn)</pre></td></tr> +<tr><td width="30%"><pre class="display">Dn(0,0)</pre></td><td width="30%"><pre class="display">Dn</pre></td></tr> +<tr><td width="30%"><pre class="display">Dn(0)</pre></td><td width="30%"><pre class="display">Dn</pre></td></tr> +<tr><td width="30%"><pre class="display">Dn(Ln,0)</pre></td><td width="30%"><pre class="display">Dn(Ln)</pre></td></tr> +</table> +</div> + + +<hr> +<a name="s390-Formats"></a> +<div class="header"> +<p> +Next: <a href="#s390-Aliases" accesskey="n" rel="next">s390 Aliases</a>, Previous: <a href="#s390-Operands" accesskey="p" rel="previous">s390 Operands</a>, Up: <a href="#s390-Syntax" accesskey="u" rel="up">s390 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-Formats"></a> +<h4 class="subsubsection">9.41.3.4 Instruction Formats</h4> +<a name="index-instruction-formats_002c-s390"></a> +<a name="index-s390-instruction-formats"></a> + +<p>The Principles of Operation manuals lists 35 instruction formats where +some of the formats have multiple variants. For the ‘<samp>.insn</samp>’ +pseudo directive the assembler recognizes some of the formats. +Typically, the most general variant of the instruction format is used +by the ‘<samp>.insn</samp>’ directive. +</p> +<p>The following table lists the abbreviations used in the table of +instruction formats: +</p> +<div class="display"> +<table> +<tr><td><pre class="display">OpCode / OpCd</pre></td><td><pre class="display">Part of the op code.</pre></td></tr> +<tr><td><pre class="display">Bx</pre></td><td><pre class="display">Base register number for operand x.</pre></td></tr> +<tr><td><pre class="display">Dx</pre></td><td><pre class="display">Displacement for operand x.</pre></td></tr> +<tr><td><pre class="display">DLx</pre></td><td><pre class="display">Displacement lower 12 bits for operand x.</pre></td></tr> +<tr><td><pre class="display">DHx</pre></td><td><pre class="display">Displacement higher 8-bits for operand x.</pre></td></tr> +<tr><td><pre class="display">Rx</pre></td><td><pre class="display">Register number for operand x.</pre></td></tr> +<tr><td><pre class="display">Xx</pre></td><td><pre class="display">Index register number for operand x.</pre></td></tr> +<tr><td><pre class="display">Ix</pre></td><td><pre class="display">Signed immediate for operand x.</pre></td></tr> +<tr><td><pre class="display">Ux</pre></td><td><pre class="display">Unsigned immediate for operand x.</pre></td></tr> +</table> +</div> + +<p>An instruction is two, four, or six bytes in length and must be aligned +on a 2 byte boundary. The first two bits of the instruction specify the +length of the instruction, 00 indicates a two byte instruction, 01 and 10 +indicates a four byte instruction, and 11 indicates a six byte instruction. +</p> +<p>The following table lists the s390 instruction formats that are available +with the ‘<samp>.insn</samp>’ pseudo directive: +</p> +<dl compact="compact"> +<dt><code>E format</code></dt> +<dd><pre class="verbatim">+-------------+ +| OpCode | ++-------------+ +0 15 +</pre> +</dd> +<dt><code>RI format: <insn> R1,I2</code></dt> +<dd><pre class="verbatim">+--------+----+----+------------------+ +| OpCode | R1 |OpCd| I2 | ++--------+----+----+------------------+ +0 8 12 16 31 +</pre> +</dd> +<dt><code>RIE format: <insn> R1,R3,I2</code></dt> +<dd><pre class="verbatim">+--------+----+----+------------------+--------+--------+ +| OpCode | R1 | R3 | I2 |////////| OpCode | ++--------+----+----+------------------+--------+--------+ +0 8 12 16 32 40 47 +</pre> +</dd> +<dt><code>RIL format: <insn> R1,I2</code></dt> +<dd><pre class="verbatim">+--------+----+----+------------------------------------+ +| OpCode | R1 |OpCd| I2 | ++--------+----+----+------------------------------------+ +0 8 12 16 47 +</pre> +</dd> +<dt><code>RILU format: <insn> R1,U2</code></dt> +<dd><pre class="verbatim">+--------+----+----+------------------------------------+ +| OpCode | R1 |OpCd| U2 | ++--------+----+----+------------------------------------+ +0 8 12 16 47 +</pre> +</dd> +<dt><code>RIS format: <insn> R1,I2,M3,D4(B4)</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+--------+--------+ +| OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | ++--------+----+----+----+-------------+--------+--------+ +0 8 12 16 20 32 36 47 +</pre> +</dd> +<dt><code>RR format: <insn> R1,R2</code></dt> +<dd><pre class="verbatim">+--------+----+----+ +| OpCode | R1 | R2 | ++--------+----+----+ +0 8 12 15 +</pre> +</dd> +<dt><code>RRE format: <insn> R1,R2</code></dt> +<dd><pre class="verbatim">+------------------+--------+----+----+ +| OpCode |////////| R1 | R2 | ++------------------+--------+----+----+ +0 16 24 28 31 +</pre> +</dd> +<dt><code>RRF format: <insn> R1,R2,R3,M4</code></dt> +<dd><pre class="verbatim">+------------------+----+----+----+----+ +| OpCode | R3 | M4 | R1 | R2 | ++------------------+----+----+----+----+ +0 16 20 24 28 31 +</pre> +</dd> +<dt><code>RRS format: <insn> R1,R2,M3,D4(B4)</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+----+----+--------+ +| OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | ++--------+----+----+----+-------------+----+----+--------+ +0 8 12 16 20 32 36 40 47 +</pre> +</dd> +<dt><code>RS format: <insn> R1,R3,D2(B2)</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+ +| OpCode | R1 | R3 | B2 | D2 | ++--------+----+----+----+-------------+ +0 8 12 16 20 31 +</pre> +</dd> +<dt><code>RSE format: <insn> R1,R3,D2(B2)</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+--------+--------+ +| OpCode | R1 | R3 | B2 | D2 |////////| OpCode | ++--------+----+----+----+-------------+--------+--------+ +0 8 12 16 20 32 40 47 +</pre> +</dd> +<dt><code>RSI format: <insn> R1,R3,I2</code></dt> +<dd><pre class="verbatim">+--------+----+----+------------------------------------+ +| OpCode | R1 | R3 | I2 | ++--------+----+----+------------------------------------+ +0 8 12 16 47 +</pre> +</dd> +<dt><code>RSY format: <insn> R1,R3,D2(B2)</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+--------+--------+ +| OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | ++--------+----+----+----+-------------+--------+--------+ +0 8 12 16 20 32 40 47 +</pre> +</dd> +<dt><code>RX format: <insn> R1,D2(X2,B2)</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+ +| OpCode | R1 | X2 | B2 | D2 | ++--------+----+----+----+-------------+ +0 8 12 16 20 31 +</pre> +</dd> +<dt><code>RXE format: <insn> R1,D2(X2,B2)</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+--------+--------+ +| OpCode | R1 | X2 | B2 | D2 |////////| OpCode | ++--------+----+----+----+-------------+--------+--------+ +0 8 12 16 20 32 40 47 +</pre> +</dd> +<dt><code>RXF format: <insn> R1,R3,D2(X2,B2)</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+----+---+--------+ +| OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | ++--------+----+----+----+-------------+----+---+--------+ +0 8 12 16 20 32 36 40 47 +</pre> +</dd> +<dt><code>RXY format: <insn> R1,D2(X2,B2)</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+--------+--------+ +| OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | ++--------+----+----+----+-------------+--------+--------+ +0 8 12 16 20 32 36 40 47 +</pre> +</dd> +<dt><code>S format: <insn> D2(B2)</code></dt> +<dd><pre class="verbatim">+------------------+----+-------------+ +| OpCode | B2 | D2 | ++------------------+----+-------------+ +0 16 20 31 +</pre> +</dd> +<dt><code>SI format: <insn> D1(B1),I2</code></dt> +<dd><pre class="verbatim">+--------+---------+----+-------------+ +| OpCode | I2 | B1 | D1 | ++--------+---------+----+-------------+ +0 8 16 20 31 +</pre> +</dd> +<dt><code>SIY format: <insn> D1(B1),U2</code></dt> +<dd><pre class="verbatim">+--------+---------+----+-------------+--------+--------+ +| OpCode | I2 | B1 | DL1 | DH1 | OpCode | ++--------+---------+----+-------------+--------+--------+ +0 8 16 20 32 36 40 47 +</pre> +</dd> +<dt><code>SIL format: <insn> D1(B1),I2</code></dt> +<dd><pre class="verbatim">+------------------+----+-------------+-----------------+ +| OpCode | B1 | D1 | I2 | ++------------------+----+-------------+-----------------+ +0 16 20 32 47 +</pre> +</dd> +<dt><code>SS format: <insn> D1(R1,B1),D2(B3),R3</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+----+------------+ +| OpCode | R1 | R3 | B1 | D1 | B2 | D2 | ++--------+----+----+----+-------------+----+------------+ +0 8 12 16 20 32 36 47 +</pre> +</dd> +<dt><code>SSE format: <insn> D1(B1),D2(B2)</code></dt> +<dd><pre class="verbatim">+------------------+----+-------------+----+------------+ +| OpCode | B1 | D1 | B2 | D2 | ++------------------+----+-------------+----+------------+ +0 8 12 16 20 32 36 47 +</pre> +</dd> +<dt><code>SSF format: <insn> D1(B1),D2(B2),R3</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+----+------------+ +| OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | ++--------+----+----+----+-------------+----+------------+ +0 8 12 16 20 32 36 47 +</pre> +</dd> +<dt><code>VRV format: <insn> V1,D2(V2,B2),M3</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+----+------------+ +| OpCode | V1 | V2 | B2 | D2 | M3 | Opcode | ++--------+----+----+----+-------------+----+------------+ +0 8 12 16 20 32 36 47 +</pre> +</dd> +<dt><code>VRI format: <insn> V1,V2,I3,M4,M5</code></dt> +<dd><pre class="verbatim">+--------+----+----+-------------+----+----+------------+ +| OpCode | V1 | V2 | I3 | M5 | M4 | Opcode | ++--------+----+----+-------------+----+----+------------+ +0 8 12 16 28 32 36 47 +</pre> +</dd> +<dt><code>VRX format: <insn> V1,D2(R2,B2),M3</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+----+------------+ +| OpCode | V1 | R2 | B2 | D2 | M3 | Opcode | ++--------+----+----+----+-------------+----+------------+ +0 8 12 16 20 32 36 47 +</pre> +</dd> +<dt><code>VRS format: <insn> R1,V3,D2(B2),M4</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+-------------+----+------------+ +| OpCode | R1 | V3 | B2 | D2 | M4 | Opcode | ++--------+----+----+----+-------------+----+------------+ +0 8 12 16 20 32 36 47 +</pre> +</dd> +<dt><code>VRR format: <insn> V1,V2,V3,M4,M5,M6</code></dt> +<dd><pre class="verbatim">+--------+----+----+----+---+----+----+----+------------+ +| OpCode | V1 | V2 | V3 |///| M6 | M5 | M4 | Opcode | ++--------+----+----+----+---+----+----+----+------------+ +0 8 12 16 24 28 32 36 47 +</pre> +</dd> +<dt><code>VSI format: <insn> V1,D2(B2),I3</code></dt> +<dd><pre class="verbatim">+--------+---------+----+-------------+----+------------+ +| OpCode | I3 | B2 | D2 | V1 | Opcode | ++--------+---------+----+-------------+----+------------+ +0 8 16 20 32 36 47 +</pre> +</dd> +</dl> + +<p>For the complete list of all instruction format variants see the +Principles of Operation manuals. +</p> +<hr> +<a name="s390-Aliases"></a> +<div class="header"> +<p> +Next: <a href="#s390-Operand-Modifier" accesskey="n" rel="next">s390 Operand Modifier</a>, Previous: <a href="#s390-Formats" accesskey="p" rel="previous">s390 Formats</a>, Up: <a href="#s390-Syntax" accesskey="u" rel="up">s390 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-Aliases"></a> +<h4 class="subsubsection">9.41.3.5 Instruction Aliases</h4> +<a name="index-instruction-aliases_002c-s390"></a> +<a name="index-s390-instruction-aliases"></a> + +<p>A specific bit pattern can have multiple mnemonics, for example +the bit pattern ‘<samp>0xa7000000</samp>’ has the mnemonics ‘<samp>tmh</samp>’ and +‘<samp>tmlh</samp>’. In addition, there are a number of mnemonics recognized by +<code>as</code> that are not present in the Principles of Operation. +These are the short forms of the branch instructions, where the condition +code mask operand is encoded in the mnemonic. This is relevant for the +branch instructions, the compare and branch instructions, and the +compare and trap instructions. +</p> +<p>For the branch instructions there are 20 condition code strings that can +be used as part of the mnemonic in place of a mask operand in the instruction +format: +</p> +<div class="display"> +<table> +<thead><tr><th width="30%"><pre class="display">instruction</pre></th><th width="30%"><pre class="display">short form</pre></th></tr></thead> +<tr><td width="30%"><pre class="display">bcr M1,R2</pre></td><td width="30%"><pre class="display">b<m>r R2</pre></td></tr> +<tr><td width="30%"><pre class="display">bc M1,D2(X2,B2)</pre></td><td width="30%"><pre class="display">b<m> D2(X2,B2)</pre></td></tr> +<tr><td width="30%"><pre class="display">brc M1,I2</pre></td><td width="30%"><pre class="display">j<m> I2</pre></td></tr> +<tr><td width="30%"><pre class="display">brcl M1,I2</pre></td><td width="30%"><pre class="display">jg<m> I2</pre></td></tr> +</table> +</div> + +<p>In the mnemonic for a branch instruction the condition code string <m> +can be any of the following: +</p> +<div class="display"> +<table> +<tr><td><pre class="display">o</pre></td><td><pre class="display">jump on overflow / if ones</pre></td></tr> +<tr><td><pre class="display">h</pre></td><td><pre class="display">jump on A high</pre></td></tr> +<tr><td><pre class="display">p</pre></td><td><pre class="display">jump on plus</pre></td></tr> +<tr><td><pre class="display">nle</pre></td><td><pre class="display">jump on not low or equal</pre></td></tr> +<tr><td><pre class="display">l</pre></td><td><pre class="display">jump on A low</pre></td></tr> +<tr><td><pre class="display">m</pre></td><td><pre class="display">jump on minus</pre></td></tr> +<tr><td><pre class="display">nhe</pre></td><td><pre class="display">jump on not high or equal</pre></td></tr> +<tr><td><pre class="display">lh</pre></td><td><pre class="display">jump on low or high</pre></td></tr> +<tr><td><pre class="display">ne</pre></td><td><pre class="display">jump on A not equal B</pre></td></tr> +<tr><td><pre class="display">nz</pre></td><td><pre class="display">jump on not zero / if not zeros</pre></td></tr> +<tr><td><pre class="display">e</pre></td><td><pre class="display">jump on A equal B</pre></td></tr> +<tr><td><pre class="display">z</pre></td><td><pre class="display">jump on zero / if zeroes</pre></td></tr> +<tr><td><pre class="display">nlh</pre></td><td><pre class="display">jump on not low or high</pre></td></tr> +<tr><td><pre class="display">he</pre></td><td><pre class="display">jump on high or equal</pre></td></tr> +<tr><td><pre class="display">nl</pre></td><td><pre class="display">jump on A not low</pre></td></tr> +<tr><td><pre class="display">nm</pre></td><td><pre class="display">jump on not minus / if not mixed</pre></td></tr> +<tr><td><pre class="display">le</pre></td><td><pre class="display">jump on low or equal</pre></td></tr> +<tr><td><pre class="display">nh</pre></td><td><pre class="display">jump on A not high</pre></td></tr> +<tr><td><pre class="display">np</pre></td><td><pre class="display">jump on not plus</pre></td></tr> +<tr><td><pre class="display">no</pre></td><td><pre class="display">jump on not overflow / if not ones</pre></td></tr> +</table> +</div> + +<p>For the compare and branch, and compare and trap instructions there +are 12 condition code strings that can be used as part of the mnemonic in +place of a mask operand in the instruction format: +</p> +<div class="display"> +<table> +<thead><tr><th width="40%"><pre class="display">instruction</pre></th><th width="40%"><pre class="display">short form</pre></th></tr></thead> +<tr><td width="40%"><pre class="display">crb R1,R2,M3,D4(B4)</pre></td><td width="40%"><pre class="display">crb<m> R1,R2,D4(B4)</pre></td></tr> +<tr><td width="40%"><pre class="display">cgrb R1,R2,M3,D4(B4)</pre></td><td width="40%"><pre class="display">cgrb<m> R1,R2,D4(B4)</pre></td></tr> +<tr><td width="40%"><pre class="display">crj R1,R2,M3,I4</pre></td><td width="40%"><pre class="display">crj<m> R1,R2,I4</pre></td></tr> +<tr><td width="40%"><pre class="display">cgrj R1,R2,M3,I4</pre></td><td width="40%"><pre class="display">cgrj<m> R1,R2,I4</pre></td></tr> +<tr><td width="40%"><pre class="display">cib R1,I2,M3,D4(B4)</pre></td><td width="40%"><pre class="display">cib<m> R1,I2,D4(B4)</pre></td></tr> +<tr><td width="40%"><pre class="display">cgib R1,I2,M3,D4(B4)</pre></td><td width="40%"><pre class="display">cgib<m> R1,I2,D4(B4)</pre></td></tr> +<tr><td width="40%"><pre class="display">cij R1,I2,M3,I4</pre></td><td width="40%"><pre class="display">cij<m> R1,I2,I4</pre></td></tr> +<tr><td width="40%"><pre class="display">cgij R1,I2,M3,I4</pre></td><td width="40%"><pre class="display">cgij<m> R1,I2,I4</pre></td></tr> +<tr><td width="40%"><pre class="display">crt R1,R2,M3</pre></td><td width="40%"><pre class="display">crt<m> R1,R2</pre></td></tr> +<tr><td width="40%"><pre class="display">cgrt R1,R2,M3</pre></td><td width="40%"><pre class="display">cgrt<m> R1,R2</pre></td></tr> +<tr><td width="40%"><pre class="display">cit R1,I2,M3</pre></td><td width="40%"><pre class="display">cit<m> R1,I2</pre></td></tr> +<tr><td width="40%"><pre class="display">cgit R1,I2,M3</pre></td><td width="40%"><pre class="display">cgit<m> R1,I2</pre></td></tr> +<tr><td width="40%"><pre class="display">clrb R1,R2,M3,D4(B4)</pre></td><td width="40%"><pre class="display">clrb<m> R1,R2,D4(B4)</pre></td></tr> +<tr><td width="40%"><pre class="display">clgrb R1,R2,M3,D4(B4)</pre></td><td width="40%"><pre class="display">clgrb<m> R1,R2,D4(B4)</pre></td></tr> +<tr><td width="40%"><pre class="display">clrj R1,R2,M3,I4</pre></td><td width="40%"><pre class="display">clrj<m> R1,R2,I4</pre></td></tr> +<tr><td width="40%"><pre class="display">clgrj R1,R2,M3,I4</pre></td><td width="40%"><pre class="display">clgrj<m> R1,R2,I4</pre></td></tr> +<tr><td width="40%"><pre class="display">clib R1,I2,M3,D4(B4)</pre></td><td width="40%"><pre class="display">clib<m> R1,I2,D4(B4)</pre></td></tr> +<tr><td width="40%"><pre class="display">clgib R1,I2,M3,D4(B4)</pre></td><td width="40%"><pre class="display">clgib<m> R1,I2,D4(B4)</pre></td></tr> +<tr><td width="40%"><pre class="display">clij R1,I2,M3,I4</pre></td><td width="40%"><pre class="display">clij<m> R1,I2,I4</pre></td></tr> +<tr><td width="40%"><pre class="display">clgij R1,I2,M3,I4</pre></td><td width="40%"><pre class="display">clgij<m> R1,I2,I4</pre></td></tr> +<tr><td width="40%"><pre class="display">clrt R1,R2,M3</pre></td><td width="40%"><pre class="display">clrt<m> R1,R2</pre></td></tr> +<tr><td width="40%"><pre class="display">clgrt R1,R2,M3</pre></td><td width="40%"><pre class="display">clgrt<m> R1,R2</pre></td></tr> +<tr><td width="40%"><pre class="display">clfit R1,I2,M3</pre></td><td width="40%"><pre class="display">clfit<m> R1,I2</pre></td></tr> +<tr><td width="40%"><pre class="display">clgit R1,I2,M3</pre></td><td width="40%"><pre class="display">clgit<m> R1,I2</pre></td></tr> +</table> +</div> + +<p>In the mnemonic for a compare and branch and compare and trap instruction +the condition code string <m> can be any of the following: +</p> +<div class="display"> +<table> +<tr><td><pre class="display">h</pre></td><td><pre class="display">jump on A high</pre></td></tr> +<tr><td><pre class="display">nle</pre></td><td><pre class="display">jump on not low or equal</pre></td></tr> +<tr><td><pre class="display">l</pre></td><td><pre class="display">jump on A low</pre></td></tr> +<tr><td><pre class="display">nhe</pre></td><td><pre class="display">jump on not high or equal</pre></td></tr> +<tr><td><pre class="display">ne</pre></td><td><pre class="display">jump on A not equal B</pre></td></tr> +<tr><td><pre class="display">lh</pre></td><td><pre class="display">jump on low or high</pre></td></tr> +<tr><td><pre class="display">e</pre></td><td><pre class="display">jump on A equal B</pre></td></tr> +<tr><td><pre class="display">nlh</pre></td><td><pre class="display">jump on not low or high</pre></td></tr> +<tr><td><pre class="display">nl</pre></td><td><pre class="display">jump on A not low</pre></td></tr> +<tr><td><pre class="display">he</pre></td><td><pre class="display">jump on high or equal</pre></td></tr> +<tr><td><pre class="display">nh</pre></td><td><pre class="display">jump on A not high</pre></td></tr> +<tr><td><pre class="display">le</pre></td><td><pre class="display">jump on low or equal</pre></td></tr> +</table> +</div> + +<hr> +<a name="s390-Operand-Modifier"></a> +<div class="header"> +<p> +Next: <a href="#s390-Instruction-Marker" accesskey="n" rel="next">s390 Instruction Marker</a>, Previous: <a href="#s390-Aliases" accesskey="p" rel="previous">s390 Aliases</a>, Up: <a href="#s390-Syntax" accesskey="u" rel="up">s390 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-Operand-Modifier"></a> +<h4 class="subsubsection">9.41.3.6 Instruction Operand Modifier</h4> +<a name="index-instruction-operand-modifier_002c-s390"></a> +<a name="index-s390-instruction-operand-modifier"></a> + +<p>If a symbol modifier is attached to a symbol in an expression for an +instruction operand field, the symbol term is replaced with a reference +to an object in the global offset table (GOT) or the procedure linkage +table (PLT). The following expressions are allowed: +‘<samp>symbol@modifier + constant</samp>’, +‘<samp>symbol@modifier + label + constant</samp>’, and +‘<samp>symbol@modifier - label + constant</samp>’. +The term ‘<samp>symbol</samp>’ is the symbol that will be entered into the GOT or +PLT, ‘<samp>label</samp>’ is a local label, and ‘<samp>constant</samp>’ is an arbitrary +expression that the assembler can evaluate to a constant value. +</p> +<p>The term ‘<samp>(symbol + constant1)@modifier +/- label + constant2</samp>’ +is also accepted but a warning message is printed and the term is +converted to ‘<samp>symbol@modifier +/- label + constant1 + constant2</samp>’. +</p> +<dl compact="compact"> +<dt><code>@got</code></dt> +<dt><code>@got12</code></dt> +<dd><p>The @got modifier can be used for displacement fields, 16-bit immediate +fields and 32-bit pc-relative immediate fields. The @got12 modifier is +synonym to @got. The symbol is added to the GOT. For displacement +fields and 16-bit immediate fields the symbol term is replaced with +the offset from the start of the GOT to the GOT slot for the symbol. +For a 32-bit pc-relative field the pc-relative offset to the GOT +slot from the current instruction address is used. +</p></dd> +<dt><code>@gotent</code></dt> +<dd><p>The @gotent modifier can be used for 32-bit pc-relative immediate fields. +The symbol is added to the GOT and the symbol term is replaced with +the pc-relative offset from the current instruction to the GOT slot for the +symbol. +</p></dd> +<dt><code>@gotoff</code></dt> +<dd><p>The @gotoff modifier can be used for 16-bit immediate fields. The symbol +term is replaced with the offset from the start of the GOT to the +address of the symbol. +</p></dd> +<dt><code>@gotplt</code></dt> +<dd><p>The @gotplt modifier can be used for displacement fields, 16-bit immediate +fields, and 32-bit pc-relative immediate fields. A procedure linkage +table entry is generated for the symbol and a jump slot for the symbol +is added to the GOT. For displacement fields and 16-bit immediate +fields the symbol term is replaced with the offset from the start of the +GOT to the jump slot for the symbol. For a 32-bit pc-relative field +the pc-relative offset to the jump slot from the current instruction +address is used. +</p></dd> +<dt><code>@plt</code></dt> +<dd><p>The @plt modifier can be used for 16-bit and 32-bit pc-relative immediate +fields. A procedure linkage table entry is generated for the symbol. +The symbol term is replaced with the relative offset from the current +instruction to the PLT entry for the symbol. +</p></dd> +<dt><code>@pltoff</code></dt> +<dd><p>The @pltoff modifier can be used for 16-bit immediate fields. The symbol +term is replaced with the offset from the start of the PLT to the address +of the symbol. +</p></dd> +<dt><code>@gotntpoff</code></dt> +<dd><p>The @gotntpoff modifier can be used for displacement fields. The symbol +is added to the static TLS block and the negated offset to the symbol +in the static TLS block is added to the GOT. The symbol term is replaced +with the offset to the GOT slot from the start of the GOT. +</p></dd> +<dt><code>@indntpoff</code></dt> +<dd><p>The @indntpoff modifier can be used for 32-bit pc-relative immediate +fields. The symbol is added to the static TLS block and the negated offset +to the symbol in the static TLS block is added to the GOT. The symbol term +is replaced with the pc-relative offset to the GOT slot from the current +instruction address. +</p></dd> +</dl> + +<p>For more information about the thread local storage modifiers +‘<samp>gotntpoff</samp>’ and ‘<samp>indntpoff</samp>’ see the ELF extension documentation +‘<samp>ELF Handling For Thread-Local Storage</samp>’. +</p> +<hr> +<a name="s390-Instruction-Marker"></a> +<div class="header"> +<p> +Next: <a href="#s390-Literal-Pool-Entries" accesskey="n" rel="next">s390 Literal Pool Entries</a>, Previous: <a href="#s390-Operand-Modifier" accesskey="p" rel="previous">s390 Operand Modifier</a>, Up: <a href="#s390-Syntax" accesskey="u" rel="up">s390 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Instruction-Marker"></a> +<h4 class="subsubsection">9.41.3.7 Instruction Marker</h4> +<a name="index-instruction-marker_002c-s390"></a> +<a name="index-s390-instruction-marker"></a> + +<p>The thread local storage instruction markers are used by the linker to +perform code optimization. +</p> +<dl compact="compact"> +<dt><code>:tls_load</code></dt> +<dd><p>The :tls_load marker is used to flag the load instruction in the initial +exec TLS model that retrieves the offset from the thread pointer to a +thread local storage variable from the GOT. +</p></dd> +<dt><code>:tls_gdcall</code></dt> +<dd><p>The :tls_gdcall marker is used to flag the branch-and-save instruction to +the __tls_get_offset function in the global dynamic TLS model. +</p></dd> +<dt><code>:tls_ldcall</code></dt> +<dd><p>The :tls_ldcall marker is used to flag the branch-and-save instruction to +the __tls_get_offset function in the local dynamic TLS model. +</p></dd> +</dl> + +<p>For more information about the thread local storage instruction marker +and the linker optimizations see the ELF extension documentation +‘<samp>ELF Handling For Thread-Local Storage</samp>’. +</p> +<hr> +<a name="s390-Literal-Pool-Entries"></a> +<div class="header"> +<p> +Previous: <a href="#s390-Instruction-Marker" accesskey="p" rel="previous">s390 Instruction Marker</a>, Up: <a href="#s390-Syntax" accesskey="u" rel="up">s390 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Literal-Pool-Entries"></a> +<h4 class="subsubsection">9.41.3.8 Literal Pool Entries</h4> +<a name="index-literal-pool-entries_002c-s390"></a> +<a name="index-s390-literal-pool-entries"></a> + +<p>A literal pool is a collection of values. To access the values a pointer +to the literal pool is loaded to a register, the literal pool register. +Usually, register %r13 is used as the literal pool register +(<a href="#s390-Register">s390 Register</a>). Literal pool entries are created by adding the +suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an +instruction operand. The expression is added to the literal pool and the +operand is replaced with the offset to the literal in the literal pool. +</p> +<dl compact="compact"> +<dt><code>:lit1</code></dt> +<dd><p>The literal pool entry is created as an 8-bit value. An operand modifier +must not be used for the original expression. +</p></dd> +<dt><code>:lit2</code></dt> +<dd><p>The literal pool entry is created as a 16 bit value. The operand modifier +@got may be used in the original expression. The term ‘<samp>x@got:lit2</samp>’ +will put the got offset for the global symbol x to the literal pool as +16 bit value. +</p></dd> +<dt><code>:lit4</code></dt> +<dd><p>The literal pool entry is created as a 32-bit value. The operand modifier +@got and @plt may be used in the original expression. The term +‘<samp>x@got:lit4</samp>’ will put the got offset for the global symbol x to the +literal pool as a 32-bit value. The term ‘<samp>x@plt:lit4</samp>’ will put the +plt offset for the global symbol x to the literal pool as a 32-bit value. +</p></dd> +<dt><code>:lit8</code></dt> +<dd><p>The literal pool entry is created as a 64-bit value. The operand modifier +@got and @plt may be used in the original expression. The term +‘<samp>x@got:lit8</samp>’ will put the got offset for the global symbol x to the +literal pool as a 64-bit value. The term ‘<samp>x@plt:lit8</samp>’ will put the +plt offset for the global symbol x to the literal pool as a 64-bit value. +</p></dd> +</dl> + +<p>The assembler directive ‘<samp>.ltorg</samp>’ is used to emit all literal pool +entries to the current position. +</p> +<hr> +<a name="s390-Directives"></a> +<div class="header"> +<p> +Next: <a href="#s390-Floating-Point" accesskey="n" rel="next">s390 Floating Point</a>, Previous: <a href="#s390-Syntax" accesskey="p" rel="previous">s390 Syntax</a>, Up: <a href="#S_002f390_002dDependent" accesskey="u" rel="up">S/390-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives-7"></a> +<h4 class="subsection">9.41.4 Assembler Directives</h4> + +<p><code>as</code> for s390 supports all of the standard ELF +assembler directives as outlined in the main part of this document. +Some directives have been extended and there are some additional +directives, which are only available for the s390 <code>as</code>. +</p> +<dl compact="compact"> +<dd><a name="index-_002einsn-directive_002c-s390"></a> +</dd> +<dt><code>.insn</code></dt> +<dd><p>This directive permits the numeric representation of an instructions +and makes the assembler insert the operands according to one of the +instructions formats for ‘<samp>.insn</samp>’ (<a href="#s390-Formats">s390 Formats</a>). +For example, the instruction ‘<samp>l %r1,24(%r15)</samp>’ could be written as +‘<samp>.insn rx,0x58000000,%r1,24(%r15)</samp>’. +<a name="index-_002eshort-directive_002c-s390"></a> +<a name="index-_002elong-directive_002c-s390"></a> +<a name="index-_002equad-directive_002c-s390"></a> +</p></dd> +<dt><code>.short</code></dt> +<dt><code>.long</code></dt> +<dt><code>.quad</code></dt> +<dd><p>This directive places one or more 16-bit (.short), 32-bit (.long), or +64-bit (.quad) values into the current section. If an ELF or TLS modifier +is used only the following expressions are allowed: +‘<samp>symbol@modifier + constant</samp>’, +‘<samp>symbol@modifier + label + constant</samp>’, and +‘<samp>symbol@modifier - label + constant</samp>’. +The following modifiers are available: +</p><dl compact="compact"> +<dt><code>@got</code></dt> +<dt><code>@got12</code></dt> +<dd><p>The @got modifier can be used for .short, .long and .quad. The @got12 +modifier is synonym to @got. The symbol is added to the GOT. The symbol +term is replaced with offset from the start of the GOT to the GOT slot for +the symbol. +</p></dd> +<dt><code>@gotoff</code></dt> +<dd><p>The @gotoff modifier can be used for .short, .long and .quad. The symbol +term is replaced with the offset from the start of the GOT to the address +of the symbol. +</p></dd> +<dt><code>@gotplt</code></dt> +<dd><p>The @gotplt modifier can be used for .long and .quad. A procedure linkage +table entry is generated for the symbol and a jump slot for the symbol +is added to the GOT. The symbol term is replaced with the offset from the +start of the GOT to the jump slot for the symbol. +</p></dd> +<dt><code>@plt</code></dt> +<dd><p>The @plt modifier can be used for .long and .quad. A procedure linkage +table entry us generated for the symbol. The symbol term is replaced with +the address of the PLT entry for the symbol. +</p></dd> +<dt><code>@pltoff</code></dt> +<dd><p>The @pltoff modifier can be used for .short, .long and .quad. The symbol +term is replaced with the offset from the start of the PLT to the address +of the symbol. +</p></dd> +<dt><code>@tlsgd</code></dt> +<dt><code>@tlsldm</code></dt> +<dd><p>The @tlsgd and @tlsldm modifier can be used for .long and .quad. A +tls_index structure for the symbol is added to the GOT. The symbol term is +replaced with the offset from the start of the GOT to the tls_index structure. +</p></dd> +<dt><code>@gotntpoff</code></dt> +<dt><code>@indntpoff</code></dt> +<dd><p>The @gotntpoff and @indntpoff modifier can be used for .long and .quad. +The symbol is added to the static TLS block and the negated offset to the +symbol in the static TLS block is added to the GOT. For @gotntpoff the +symbol term is replaced with the offset from the start of the GOT to the +GOT slot, for @indntpoff the symbol term is replaced with the address +of the GOT slot. +</p></dd> +<dt><code>@dtpoff</code></dt> +<dd><p>The @dtpoff modifier can be used for .long and .quad. The symbol term +is replaced with the offset of the symbol relative to the start of the +TLS block it is contained in. +</p></dd> +<dt><code>@ntpoff</code></dt> +<dd><p>The @ntpoff modifier can be used for .long and .quad. The symbol term +is replaced with the offset of the symbol relative to the TCB pointer. +</p></dd> +</dl> + +<p>For more information about the thread local storage modifiers see the +ELF extension documentation ‘<samp>ELF Handling For Thread-Local Storage</samp>’. +</p> +<a name="index-_002eltorg-directive_002c-s390"></a> +</dd> +<dt><code>.ltorg</code></dt> +<dd><p>This directive causes the current contents of the literal pool to be +dumped to the current location (<a href="#s390-Literal-Pool-Entries">s390 Literal Pool Entries</a>). +</p> +<a name="index-_002emachine-directive_002c-s390"></a> +</dd> +<dt><code>.machine <var>STRING</var>[+<var>EXTENSION</var>]…</code></dt> +<dd> +<p>This directive allows changing the machine for which code is +generated. <code>string</code> may be any of the <code>-march=</code> +selection options, or <code>push</code>, or <code>pop</code>. <code>.machine +push</code> saves the currently selected cpu, which may be restored with +<code>.machine pop</code>. Be aware that the cpu string has to be put +into double quotes in case it contains characters not appropriate +for identifiers. So you have to write <code>"z9-109"</code> instead of +just <code>z9-109</code>. Extensions can be specified after the cpu +name, separated by plus characters. Valid extensions are: +<code>htm</code>, +<code>nohtm</code>, +<code>vx</code>, +<code>novx</code>. +They extend the basic instruction set with features from a higher +cpu level, or remove support for a feature from the given cpu +level. +</p> +<p>Example: <code>z13+nohtm</code> allows all instructions of the z13 cpu +except instructions from the HTM facility. +</p> +<a name="index-_002emachinemode-directive_002c-s390"></a> +</dd> +<dt><code>.machinemode string</code></dt> +<dd><p>This directive allows one to change the architecture mode for which code +is being generated. <code>string</code> may be <code>esa</code>, <code>zarch</code>, +<code>zarch_nohighgprs</code>, <code>push</code>, or <code>pop</code>. +<code>.machinemode zarch_nohighgprs</code> can be used to prevent the +<code>highgprs</code> flag from being set in the ELF header of the output +file. This is useful in situations where the code is gated with a +runtime check which makes sure that the code is only executed on +kernels providing the <code>highgprs</code> feature. +<code>.machinemode push</code> saves the currently selected mode, which may +be restored with <code>.machinemode pop</code>. +</p></dd> +</dl> + +<hr> +<a name="s390-Floating-Point"></a> +<div class="header"> +<p> +Previous: <a href="#s390-Directives" accesskey="p" rel="previous">s390 Directives</a>, Up: <a href="#S_002f390_002dDependent" accesskey="u" rel="up">S/390-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-13"></a> +<h4 class="subsection">9.41.5 Floating Point</h4> +<a name="index-floating-point_002c-s390"></a> +<a name="index-s390-floating-point"></a> + +<p>The assembler recognizes both the <small>IEEE</small> floating-point instruction and +the hexadecimal floating-point instructions. The floating-point constructors +‘<samp>.float</samp>’, ‘<samp>.single</samp>’, and ‘<samp>.double</samp>’ always emit the +<small>IEEE</small> format. To assemble hexadecimal floating-point constants the +‘<samp>.long</samp>’ and ‘<samp>.quad</samp>’ directives must be used. +</p> +<hr> +<a name="SCORE_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#SH_002dDependent" accesskey="n" rel="next">SH-Dependent</a>, Previous: <a href="#S_002f390_002dDependent" accesskey="p" rel="previous">S/390-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="SCORE-Dependent-Features"></a> +<h3 class="section">9.42 SCORE Dependent Features</h3> + +<a name="index-SCORE-processor"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#SCORE_002dOpts" accesskey="1">SCORE-Opts</a>:</td><td> </td><td align="left" valign="top">Assembler options +</td></tr> +<tr><td align="left" valign="top">• <a href="#SCORE_002dPseudo" accesskey="2">SCORE-Pseudo</a>:</td><td> </td><td align="left" valign="top">SCORE Assembler Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#SCORE_002dSyntax" accesskey="3">SCORE-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +</table> + +<hr> +<a name="SCORE_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#SCORE_002dPseudo" accesskey="n" rel="next">SCORE-Pseudo</a>, Up: <a href="#SCORE_002dDependent" accesskey="u" rel="up">SCORE-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-22"></a> +<h4 class="subsection">9.42.1 Options</h4> + +<a name="index-options-for-SCORE"></a> +<a name="index-SCORE-options"></a> +<a name="index-architectures_002c-SCORE"></a> +<a name="index-SCORE-architectures"></a> + +<p>The following table lists all available SCORE options. +</p> +<dl compact="compact"> +<dt><code>-G <var>num</var></code></dt> +<dd><p>This option sets the largest size of an object that can be referenced +implicitly with the <code>gp</code> register. The default value is 8. +</p> +</dd> +<dt><code>-EB</code></dt> +<dd><p>Assemble code for a big-endian cpu +</p> +</dd> +<dt><code>-EL</code></dt> +<dd><p>Assemble code for a little-endian cpu +</p> +</dd> +<dt><code>-FIXDD</code></dt> +<dd><p>Assemble code for fix data dependency +</p> +</dd> +<dt><code>-NWARN</code></dt> +<dd><p>Assemble code for no warning message for fix data dependency +</p> +</dd> +<dt><code>-SCORE5</code></dt> +<dd><p>Assemble code for target is SCORE5 +</p> +</dd> +<dt><code>-SCORE5U</code></dt> +<dd><p>Assemble code for target is SCORE5U +</p> +</dd> +<dt><code>-SCORE7</code></dt> +<dd><p>Assemble code for target is SCORE7, this is default setting +</p> +</dd> +<dt><code>-SCORE3</code></dt> +<dd><p>Assemble code for target is SCORE3 +</p> +</dd> +<dt><code>-march=score7</code></dt> +<dd><p>Assemble code for target is SCORE7, this is default setting +</p> +</dd> +<dt><code>-march=score3</code></dt> +<dd><p>Assemble code for target is SCORE3 +</p> +</dd> +<dt><code>-USE_R1</code></dt> +<dd><p>Assemble code for no warning message when using temp register r1 +</p> +</dd> +<dt><code>-KPIC</code></dt> +<dd><p>Generate code for PIC. This option tells the assembler to generate +score position-independent macro expansions. It also tells the +assembler to mark the output file as PIC. +</p> +</dd> +<dt><code>-O0</code></dt> +<dd><p>Assembler will not perform any optimizations +</p> +</dd> +<dt><code>-V</code></dt> +<dd><p>Sunplus release version +</p> +</dd> +</dl> + +<hr> +<a name="SCORE_002dPseudo"></a> +<div class="header"> +<p> +Next: <a href="#SCORE_002dSyntax" accesskey="n" rel="next">SCORE-Syntax</a>, Previous: <a href="#SCORE_002dOpts" accesskey="p" rel="previous">SCORE-Opts</a>, Up: <a href="#SCORE_002dDependent" accesskey="u" rel="up">SCORE-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="SCORE-Assembler-Directives"></a> +<h4 class="subsection">9.42.2 SCORE Assembler Directives</h4> + +<a name="index-directives-for-SCORE"></a> +<a name="index-SCORE-directives"></a> +<p>A number of assembler directives are available for SCORE. The +following table is far from complete. +</p> +<dl compact="compact"> +<dt><code>.set nwarn</code></dt> +<dd><p>Let the assembler not to generate warnings if the source machine +language instructions happen data dependency. +</p> +</dd> +<dt><code>.set fixdd</code></dt> +<dd><p>Let the assembler to insert bubbles (32 bit nop instruction / +16 bit nop! Instruction) if the source machine language instructions +happen data dependency. +</p> +</dd> +<dt><code>.set nofixdd</code></dt> +<dd><p>Let the assembler to generate warnings if the source machine +language instructions happen data dependency. (Default) +</p> +</dd> +<dt><code>.set r1</code></dt> +<dd><p>Let the assembler not to generate warnings if the source program +uses r1. allow user to use r1 +</p> +</dd> +<dt><code>set nor1</code></dt> +<dd><p>Let the assembler to generate warnings if the source program uses +r1. (Default) +</p> +</dd> +<dt><code>.sdata</code></dt> +<dd><p>Tell the assembler to add subsequent data into the sdata section +</p> +</dd> +<dt><code>.rdata</code></dt> +<dd><p>Tell the assembler to add subsequent data into the rdata section +</p> +</dd> +<dt><code>.frame "frame-register", "offset", "return-pc-register"</code></dt> +<dd><p>Describe a stack frame. "frame-register" is the frame register, +"offset" is the distance from the frame register to the virtual +frame pointer, "return-pc-register" is the return program register. +You must use ".ent" before ".frame" and only one ".frame" can be +used per ".ent". +</p> +</dd> +<dt><code>.mask "bitmask", "frameoffset"</code></dt> +<dd><p>Indicate which of the integer registers are saved in the current +function’s stack frame, this is for the debugger to explain the +frame chain. +</p> +</dd> +<dt><code>.ent "proc-name"</code></dt> +<dd><p>Set the beginning of the procedure "proc_name". Use this directive +when you want to generate information for the debugger. +</p> +</dd> +<dt><code>.end proc-name</code></dt> +<dd><p>Set the end of a procedure. Use this directive to generate information +for the debugger. +</p> +</dd> +<dt><code>.bss</code></dt> +<dd><p>Switch the destination of following statements into the bss section, +which is used for data that is uninitialized anywhere. +</p> +</dd> +</dl> + +<hr> +<a name="SCORE_002dSyntax"></a> +<div class="header"> +<p> +Previous: <a href="#SCORE_002dPseudo" accesskey="p" rel="previous">SCORE-Pseudo</a>, Up: <a href="#SCORE_002dDependent" accesskey="u" rel="up">SCORE-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="SCORE-Syntax"></a> +<h4 class="subsection">9.42.3 SCORE Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#SCORE_002dChars" accesskey="1">SCORE-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="SCORE_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#SCORE_002dSyntax" accesskey="u" rel="up">SCORE-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-33"></a> +<h4 class="subsubsection">9.42.3.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-SCORE"></a> +<a name="index-SCORE-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ appearing anywhere on a line indicates the +start of a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-SCORE"></a> +<a name="index-statement-separator_002c-SCORE"></a> +<a name="index-SCORE-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="SH_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Sparc_002dDependent" accesskey="n" rel="next">Sparc-Dependent</a>, Previous: <a href="#SCORE_002dDependent" accesskey="p" rel="previous">SCORE-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Renesas-_002f-SuperH-SH-Dependent-Features"></a> +<h3 class="section">9.43 Renesas / SuperH SH Dependent Features</h3> + +<a name="index-SH-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#SH-Options" accesskey="1">SH Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#SH-Syntax" accesskey="2">SH Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#SH-Floating-Point" accesskey="3">SH Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#SH-Directives" accesskey="4">SH Directives</a>:</td><td> </td><td align="left" valign="top">SH Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#SH-Opcodes" accesskey="5">SH Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="SH-Options"></a> +<div class="header"> +<p> +Next: <a href="#SH-Syntax" accesskey="n" rel="next">SH Syntax</a>, Up: <a href="#SH_002dDependent" accesskey="u" rel="up">SH-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-23"></a> +<h4 class="subsection">9.43.1 Options</h4> + +<a name="index-SH-options"></a> +<a name="index-options_002c-SH"></a> +<p><code>as</code> has following command-line options for the Renesas +(formerly Hitachi) / SuperH SH family. +</p> +<dl compact="compact"> +<dd><a name="index-_002d_002dlittle"></a> +<a name="index-_002d_002dbig"></a> +<a name="index-_002d_002drelax"></a> +<a name="index-_002d_002dsmall"></a> +<a name="index-_002d_002ddsp"></a> +<a name="index-_002d_002drenesas"></a> +<a name="index-_002d_002dallow_002dreg_002dprefix"></a> + +</dd> +<dt><code>--little</code></dt> +<dd><p>Generate little endian code. +</p> +</dd> +<dt><code>--big</code></dt> +<dd><p>Generate big endian code. +</p> +</dd> +<dt><code>--relax</code></dt> +<dd><p>Alter jump instructions for long displacements. +</p> +</dd> +<dt><code>--small</code></dt> +<dd><p>Align sections to 4 byte boundaries, not 16. +</p> +</dd> +<dt><code>--dsp</code></dt> +<dd><p>Enable sh-dsp insns, and disable sh3e / sh4 insns. +</p> +</dd> +<dt><code>--renesas</code></dt> +<dd><p>Disable optimization with section symbol for compatibility with +Renesas assembler. +</p> +</dd> +<dt><code>--allow-reg-prefix</code></dt> +<dd><p>Allow ’$’ as a register name prefix. +</p> +<a name="index-_002d_002dfdpic"></a> +</dd> +<dt><code>--fdpic</code></dt> +<dd><p>Generate an FDPIC object file. +</p> +</dd> +<dt><code>--isa=sh4 | sh4a</code></dt> +<dd><p>Specify the sh4 or sh4a instruction set. +</p></dd> +<dt><code>--isa=dsp</code></dt> +<dd><p>Enable sh-dsp insns, and disable sh3e / sh4 insns. +</p></dd> +<dt><code>--isa=fp</code></dt> +<dd><p>Enable sh2e, sh3e, sh4, and sh4a insn sets. +</p></dd> +<dt><code>--isa=all</code></dt> +<dd><p>Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. +</p> +</dd> +<dt><code>-h-tick-hex</code></dt> +<dd><p>Support H’00 style hex constants in addition to 0x00 style. +</p> +</dd> +</dl> + +<hr> +<a name="SH-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#SH-Floating-Point" accesskey="n" rel="next">SH Floating Point</a>, Previous: <a href="#SH-Options" accesskey="p" rel="previous">SH Options</a>, Up: <a href="#SH_002dDependent" accesskey="u" rel="up">SH-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-27"></a> +<h4 class="subsection">9.43.2 Syntax</h4> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#SH_002dChars" accesskey="1">SH-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#SH_002dRegs" accesskey="2">SH-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#SH_002dAddressing" accesskey="3">SH-Addressing</a>:</td><td> </td><td align="left" valign="top">Addressing Modes +</td></tr> +</table> + +<hr> +<a name="SH_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#SH_002dRegs" accesskey="n" rel="next">SH-Regs</a>, Up: <a href="#SH-Syntax" accesskey="u" rel="up">SH Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-34"></a> +<h4 class="subsubsection">9.43.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-SH"></a> +<a name="index-SH-line-comment-character"></a> +<p>‘<samp>!</samp>’ is the line comment character. +</p> +<a name="index-line-separator_002c-SH"></a> +<a name="index-statement-separator_002c-SH"></a> +<a name="index-SH-line-separator"></a> +<p>You can use ‘<samp>;</samp>’ instead of a newline to separate statements. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-symbol-names_002c-_0024-in-3"></a> +<a name="index-_0024-in-symbol-names-3"></a> +<p>Since ‘<samp>$</samp>’ has no special meaning, you may use it in symbol names. +</p> +<hr> +<a name="SH_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#SH_002dAddressing" accesskey="n" rel="next">SH-Addressing</a>, Previous: <a href="#SH_002dChars" accesskey="p" rel="previous">SH-Chars</a>, Up: <a href="#SH-Syntax" accesskey="u" rel="up">SH Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-15"></a> +<h4 class="subsubsection">9.43.2.2 Register Names</h4> + +<a name="index-SH-registers"></a> +<a name="index-registers_002c-SH"></a> +<p>You can use the predefined symbols ‘<samp>r0</samp>’, ‘<samp>r1</samp>’, ‘<samp>r2</samp>’, +‘<samp>r3</samp>’, ‘<samp>r4</samp>’, ‘<samp>r5</samp>’, ‘<samp>r6</samp>’, ‘<samp>r7</samp>’, ‘<samp>r8</samp>’, +‘<samp>r9</samp>’, ‘<samp>r10</samp>’, ‘<samp>r11</samp>’, ‘<samp>r12</samp>’, ‘<samp>r13</samp>’, ‘<samp>r14</samp>’, +and ‘<samp>r15</samp>’ to refer to the SH registers. +</p> +<p>The SH also has these control registers: +</p> +<dl compact="compact"> +<dt><code>pr</code></dt> +<dd><p>procedure register (holds return address) +</p> +</dd> +<dt><code>pc</code></dt> +<dd><p>program counter +</p> +</dd> +<dt><code>mach</code></dt> +<dt><code>macl</code></dt> +<dd><p>high and low multiply accumulator registers +</p> +</dd> +<dt><code>sr</code></dt> +<dd><p>status register +</p> +</dd> +<dt><code>gbr</code></dt> +<dd><p>global base register +</p> +</dd> +<dt><code>vbr</code></dt> +<dd><p>vector base register (for interrupt vectors) +</p></dd> +</dl> + +<hr> +<a name="SH_002dAddressing"></a> +<div class="header"> +<p> +Previous: <a href="#SH_002dRegs" accesskey="p" rel="previous">SH-Regs</a>, Up: <a href="#SH-Syntax" accesskey="u" rel="up">SH Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Addressing-Modes-4"></a> +<h4 class="subsubsection">9.43.2.3 Addressing Modes</h4> + +<a name="index-addressing-modes_002c-SH"></a> +<a name="index-SH-addressing-modes"></a> +<p><code>as</code> understands the following addressing modes for the SH. +<code>R<var>n</var></code> in the following refers to any of the numbered +registers, but <em>not</em> the control registers. +</p> +<dl compact="compact"> +<dt><code>R<var>n</var></code></dt> +<dd><p>Register direct +</p> +</dd> +<dt><code>@R<var>n</var></code></dt> +<dd><p>Register indirect +</p> +</dd> +<dt><code>@-R<var>n</var></code></dt> +<dd><p>Register indirect with pre-decrement +</p> +</dd> +<dt><code>@R<var>n</var>+</code></dt> +<dd><p>Register indirect with post-increment +</p> +</dd> +<dt><code>@(<var>disp</var>, R<var>n</var>)</code></dt> +<dd><p>Register indirect with displacement +</p> +</dd> +<dt><code>@(R0, R<var>n</var>)</code></dt> +<dd><p>Register indexed +</p> +</dd> +<dt><code>@(<var>disp</var>, GBR)</code></dt> +<dd><p><code>GBR</code> offset +</p> +</dd> +<dt><code>@(R0, GBR)</code></dt> +<dd><p>GBR indexed +</p> +</dd> +<dt><code><var>addr</var></code></dt> +<dt><code>@(<var>disp</var>, PC)</code></dt> +<dd><p>PC relative address (for branch or for addressing memory). The +<code>as</code> implementation allows you to use the simpler form +<var>addr</var> anywhere a PC relative address is called for; the alternate +form is supported for compatibility with other assemblers. +</p> +</dd> +<dt><code>#<var>imm</var></code></dt> +<dd><p>Immediate data +</p></dd> +</dl> + +<hr> +<a name="SH-Floating-Point"></a> +<div class="header"> +<p> +Next: <a href="#SH-Directives" accesskey="n" rel="next">SH Directives</a>, Previous: <a href="#SH-Syntax" accesskey="p" rel="previous">SH Syntax</a>, Up: <a href="#SH_002dDependent" accesskey="u" rel="up">SH-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-14"></a> +<h4 class="subsection">9.43.3 Floating Point</h4> + +<a name="index-floating-point_002c-SH-_0028IEEE_0029"></a> +<a name="index-SH-floating-point-_0028IEEE_0029"></a> +<p>SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other +SH groups can use <code>.float</code> directive to generate <small>IEEE</small> +floating-point numbers. +</p> +<p>SH2E and SH3E support single-precision floating point calculations as +well as entirely PCAPI compatible emulation of double-precision +floating point calculations. SH2E and SH3E instructions are a subset of +the floating point calculations conforming to the IEEE754 standard. +</p> +<p>In addition to single-precision and double-precision floating-point +operation capability, the on-chip FPU of SH4 has a 128-bit graphic +engine that enables 32-bit floating-point data to be processed 128 +bits at a time. It also supports 4 * 4 array operations and inner +product operations. Also, a superscalar architecture is employed that +enables simultaneous execution of two instructions (including FPU +instructions), providing performance of up to twice that of +conventional architectures at the same frequency. +</p> +<hr> +<a name="SH-Directives"></a> +<div class="header"> +<p> +Next: <a href="#SH-Opcodes" accesskey="n" rel="next">SH Opcodes</a>, Previous: <a href="#SH-Floating-Point" accesskey="p" rel="previous">SH Floating Point</a>, Up: <a href="#SH_002dDependent" accesskey="u" rel="up">SH-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="SH-Machine-Directives"></a> +<h4 class="subsection">9.43.4 SH Machine Directives</h4> + +<a name="index-SH-machine-directives"></a> +<a name="index-machine-directives_002c-SH"></a> +<a name="index-uaword-directive_002c-SH"></a> +<a name="index-ualong-directive_002c-SH"></a> +<a name="index-uaquad-directive_002c-SH"></a> + +<dl compact="compact"> +<dt><code>uaword</code></dt> +<dt><code>ualong</code></dt> +<dt><code>uaquad</code></dt> +<dd><p><code>as</code> will issue a warning when a misaligned <code>.word</code>, +<code>.long</code>, or <code>.quad</code> directive is used. You may use +<code>.uaword</code>, <code>.ualong</code>, or <code>.uaquad</code> to indicate that the +value is intentionally misaligned. +</p></dd> +</dl> + +<hr> +<a name="SH-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#SH-Directives" accesskey="p" rel="previous">SH Directives</a>, Up: <a href="#SH_002dDependent" accesskey="u" rel="up">SH-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-18"></a> +<h4 class="subsection">9.43.5 Opcodes</h4> + +<a name="index-SH-opcode-summary"></a> +<a name="index-opcode-summary_002c-SH"></a> +<a name="index-mnemonics_002c-SH"></a> +<a name="index-instruction-summary_002c-SH"></a> +<p>For detailed information on the SH machine instruction set, see +<cite>SH-Microcomputer User’s Manual</cite> (Renesas) or +<cite>SH-4 32-bit CPU Core Architecture</cite> (SuperH) and +<cite>SuperH (SH) 64-Bit RISC Series</cite> (SuperH). +</p> +<p><code>as</code> implements all the standard SH opcodes. No additional +pseudo-instructions are needed on this family. Note, however, that +because <code>as</code> supports a simpler form of PC-relative +addressing, you may simply write (for example) +</p> +<div class="example"> +<pre class="example">mov.l bar,r0 +</pre></div> + +<p>where other assemblers might require an explicit displacement to +<code>bar</code> from the program counter: +</p> +<div class="example"> +<pre class="example">mov.l @(<var>disp</var>, PC) +</pre></div> + + + + +<hr> +<a name="Sparc_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dDependent" accesskey="n" rel="next">TIC54X-Dependent</a>, Previous: <a href="#SH_002dDependent" accesskey="p" rel="previous">SH-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="SPARC-Dependent-Features"></a> +<h3 class="section">9.44 SPARC Dependent Features</h3> + +<a name="index-SPARC-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Sparc_002dOpts" accesskey="1">Sparc-Opts</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sparc_002dAligned_002dData" accesskey="2">Sparc-Aligned-Data</a>:</td><td> </td><td align="left" valign="top">Option to enforce aligned data +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sparc_002dSyntax" accesskey="3">Sparc-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sparc_002dFloat" accesskey="4">Sparc-Float</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sparc_002dDirectives" accesskey="5">Sparc-Directives</a>:</td><td> </td><td align="left" valign="top">Sparc Machine Directives +</td></tr> +</table> + +<hr> +<a name="Sparc_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#Sparc_002dAligned_002dData" accesskey="n" rel="next">Sparc-Aligned-Data</a>, Up: <a href="#Sparc_002dDependent" accesskey="u" rel="up">Sparc-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-24"></a> +<h4 class="subsection">9.44.1 Options</h4> + +<a name="index-options-for-SPARC"></a> +<a name="index-SPARC-options"></a> +<a name="index-architectures_002c-SPARC"></a> +<a name="index-SPARC-architectures"></a> +<p>The SPARC chip family includes several successive versions, using the same +core instruction set, but including a few additional instructions at +each version. There are exceptions to this however. For details on what +instructions each variant supports, please see the chip’s architecture +reference manual. +</p> +<p>By default, <code>as</code> assumes the core instruction set (SPARC +v6), but “bumps” the architecture level as needed: it switches to +successively higher architectures as it encounters instructions that +only exist in the higher levels. +</p> +<p>If not configured for SPARC v9 (<code>sparc64-*-*</code>) GAS will not bump +past sparclite by default, an option must be passed to enable the +v9 instructions. +</p> +<p>GAS treats sparclite as being compatible with v8, unless an architecture +is explicitly requested. SPARC v9 is always incompatible with sparclite. +</p> + +<dl compact="compact"> +<dd><a name="index-_002dAv6"></a> +<a name="index-_002dAv7"></a> +<a name="index-_002dAv8"></a> +<a name="index-_002dAleon"></a> +<a name="index-_002dAsparclet"></a> +<a name="index-_002dAsparclite"></a> +<a name="index-_002dAv9"></a> +<a name="index-_002dAv9a"></a> +<a name="index-_002dAv9b"></a> +<a name="index-_002dAv9c"></a> +<a name="index-_002dAv9d"></a> +<a name="index-_002dAv9e"></a> +<a name="index-_002dAv9v"></a> +<a name="index-_002dAv9m"></a> +<a name="index-_002dAsparc"></a> +<a name="index-_002dAsparcvis"></a> +<a name="index-_002dAsparcvis2"></a> +<a name="index-_002dAsparcfmaf"></a> +<a name="index-_002dAsparcima"></a> +<a name="index-_002dAsparcvis3"></a> +<a name="index-_002dAsparcvis3r"></a> +</dd> +<dt><code>-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite</code></dt> +<dt><code>-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |</code></dt> +<dt><code>-Av8plusv | -Av8plusm | -Av8plusm8</code></dt> +<dt><code>-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8</code></dt> +<dt><code>-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima</code></dt> +<dt><code>-Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6</code></dt> +<dd><p>Use one of the ‘<samp>-A</samp>’ options to select one of the SPARC +architectures explicitly. If you select an architecture explicitly, +<code>as</code> reports a fatal error if it encounters an instruction +or feature requiring an incompatible or higher level. +</p> +<p>‘<samp>-Av8plus</samp>’, ‘<samp>-Av8plusa</samp>’, ‘<samp>-Av8plusb</samp>’, ‘<samp>-Av8plusc</samp>’, +‘<samp>-Av8plusd</samp>’, and ‘<samp>-Av8plusv</samp>’ select a 32 bit environment. +</p> +<p>‘<samp>-Av9</samp>’, ‘<samp>-Av9a</samp>’, ‘<samp>-Av9b</samp>’, ‘<samp>-Av9c</samp>’, ‘<samp>-Av9d</samp>’, +‘<samp>-Av9e</samp>’, ‘<samp>-Av9v</samp>’ and ‘<samp>-Av9m</samp>’ select a 64 bit +environment and are not available unless GAS is explicitly configured +with 64 bit environment support. +</p> +<p>‘<samp>-Av8plusa</samp>’ and ‘<samp>-Av9a</samp>’ enable the SPARC V9 instruction set with +UltraSPARC VIS 1.0 extensions. +</p> +<p>‘<samp>-Av8plusb</samp>’ and ‘<samp>-Av9b</samp>’ enable the UltraSPARC VIS 2.0 instructions, +as well as the instructions enabled by ‘<samp>-Av8plusa</samp>’ and ‘<samp>-Av9a</samp>’. +</p> +<p>‘<samp>-Av8plusc</samp>’ and ‘<samp>-Av9c</samp>’ enable the UltraSPARC Niagara instructions, +as well as the instructions enabled by ‘<samp>-Av8plusb</samp>’ and ‘<samp>-Av9b</samp>’. +</p> +<p>‘<samp>-Av8plusd</samp>’ and ‘<samp>-Av9d</samp>’ enable the floating point fused +multiply-add, VIS 3.0, and HPC extension instructions, as well as the +instructions enabled by ‘<samp>-Av8plusc</samp>’ and ‘<samp>-Av9c</samp>’. +</p> +<p>‘<samp>-Av8pluse</samp>’ and ‘<samp>-Av9e</samp>’ enable the cryptographic +instructions, as well as the instructions enabled by ‘<samp>-Av8plusd</samp>’ +and ‘<samp>-Av9d</samp>’. +</p> +<p>‘<samp>-Av8plusv</samp>’ and ‘<samp>-Av9v</samp>’ enable floating point unfused +multiply-add, and integer multiply-add, as well as the instructions +enabled by ‘<samp>-Av8pluse</samp>’ and ‘<samp>-Av9e</samp>’. +</p> +<p>‘<samp>-Av8plusm</samp>’ and ‘<samp>-Av9m</samp>’ enable the VIS 4.0, subtract extended, +xmpmul, xmontmul and xmontsqr instructions, as well as the instructions +enabled by ‘<samp>-Av8plusv</samp>’ and ‘<samp>-Av9v</samp>’. +</p> +<p>‘<samp>-Av8plusm8</samp>’ and ‘<samp>-Av9m8</samp>’ enable the instructions introduced +in the Oracle SPARC Architecture 2017 and the M8 processor, as +well as the instructions enabled by ‘<samp>-Av8plusm</samp>’ and ‘<samp>-Av9m</samp>’. +</p> +<p>‘<samp>-Asparc</samp>’ specifies a v9 environment. It is equivalent to +‘<samp>-Av9</samp>’ if the word size is 64-bit, and ‘<samp>-Av8plus</samp>’ otherwise. +</p> +<p>‘<samp>-Asparcvis</samp>’ specifies a v9a environment. It is equivalent to +‘<samp>-Av9a</samp>’ if the word size is 64-bit, and ‘<samp>-Av8plusa</samp>’ otherwise. +</p> +<p>‘<samp>-Asparcvis2</samp>’ specifies a v9b environment. It is equivalent to +‘<samp>-Av9b</samp>’ if the word size is 64-bit, and ‘<samp>-Av8plusb</samp>’ otherwise. +</p> +<p>‘<samp>-Asparcfmaf</samp>’ specifies a v9b environment with the floating point +fused multiply-add instructions enabled. +</p> +<p>‘<samp>-Asparcima</samp>’ specifies a v9b environment with the integer +multiply-add instructions enabled. +</p> +<p>‘<samp>-Asparcvis3</samp>’ specifies a v9b environment with the VIS 3.0, +HPC , and floating point fused multiply-add instructions enabled. +</p> +<p>‘<samp>-Asparcvis3r</samp>’ specifies a v9b environment with the VIS 3.0, HPC, +and floating point unfused multiply-add instructions enabled. +</p> +<p>‘<samp>-Asparc5</samp>’ is equivalent to ‘<samp>-Av9m</samp>’. +</p> +<p>‘<samp>-Asparc6</samp>’ is equivalent to ‘<samp>-Av9m8</samp>’. +</p> +</dd> +<dt><code>-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc</code></dt> +<dt><code>-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |</code></dt> +<dt><code>-xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b</code></dt> +<dt><code>-xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v</code></dt> +<dt><code>-xarch=v9m | -xarch=v9m8</code></dt> +<dt><code>-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2</code></dt> +<dt><code>-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3</code></dt> +<dt><code>-xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6</code></dt> +<dd><p>For compatibility with the SunOS v9 assembler. These options are +equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, +-Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, +-Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2, +-Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and +-Asparc6 respectively. +</p> +</dd> +<dt><code>-bump</code></dt> +<dd><p>Warn whenever it is necessary to switch to another level. +If an architecture level is explicitly requested, GAS will not issue +warnings until that level is reached, and will then bump the level +as required (except between incompatible levels). +</p> +</dd> +<dt><code>-32 | -64</code></dt> +<dd><p>Select the word size, either 32 bits or 64 bits. +These options are only available with the ELF object file format, +and require that the necessary BFD support has been included. +</p> +</dd> +<dt><code>--dcti-couples-detect</code></dt> +<dd><p>Warn if a DCTI (delayed control transfer instruction) couple is found +when generating code for a variant of the SPARC architecture in which +the execution of the couple is unpredictable, or very slow. This is +disabled by default. +</p></dd> +</dl> + +<hr> +<a name="Sparc_002dAligned_002dData"></a> +<div class="header"> +<p> +Next: <a href="#Sparc_002dSyntax" accesskey="n" rel="next">Sparc-Syntax</a>, Previous: <a href="#Sparc_002dOpts" accesskey="p" rel="previous">Sparc-Opts</a>, Up: <a href="#Sparc_002dDependent" accesskey="u" rel="up">Sparc-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Enforcing-aligned-data"></a> +<h4 class="subsection">9.44.2 Enforcing aligned data</h4> + +<a name="index-data-alignment-on-SPARC"></a> +<a name="index-SPARC-data-alignment"></a> +<p>SPARC GAS normally permits data to be misaligned. For example, it +permits the <code>.long</code> pseudo-op to be used on a byte boundary. +However, the native SunOS assemblers issue an error when they see +misaligned data. +</p> +<a name="index-_002d_002denforce_002daligned_002ddata"></a> +<p>You can use the <code>--enforce-aligned-data</code> option to make SPARC GAS +also issue an error about misaligned data, just as the SunOS +assemblers do. +</p> +<p>The <code>--enforce-aligned-data</code> option is not the default because gcc +issues misaligned data pseudo-ops when it initializes certain packed +data structures (structures defined using the <code>packed</code> attribute). +You may have to assemble with GAS in order to initialize packed data +structures in your own code. +</p> +<a name="index-SPARC-syntax"></a> +<a name="index-syntax_002c-SPARC"></a> +<hr> +<a name="Sparc_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#Sparc_002dFloat" accesskey="n" rel="next">Sparc-Float</a>, Previous: <a href="#Sparc_002dAligned_002dData" accesskey="p" rel="previous">Sparc-Aligned-Data</a>, Up: <a href="#Sparc_002dDependent" accesskey="u" rel="up">Sparc-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Sparc-Syntax"></a> +<h4 class="subsection">9.44.3 Sparc Syntax</h4> +<p>The assembler syntax closely follows The Sparc Architecture Manual, +versions 8 and 9, as well as most extensions defined by Sun +for their UltraSPARC and Niagara line of processors. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Sparc_002dChars" accesskey="1">Sparc-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sparc_002dRegs" accesskey="2">Sparc-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sparc_002dConstants" accesskey="3">Sparc-Constants</a>:</td><td> </td><td align="left" valign="top">Constant Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sparc_002dRelocs" accesskey="4">Sparc-Relocs</a>:</td><td> </td><td align="left" valign="top">Relocations +</td></tr> +<tr><td align="left" valign="top">• <a href="#Sparc_002dSize_002dTranslations" accesskey="5">Sparc-Size-Translations</a>:</td><td> </td><td align="left" valign="top">Size Translations +</td></tr> +</table> + +<hr> +<a name="Sparc_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#Sparc_002dRegs" accesskey="n" rel="next">Sparc-Regs</a>, Up: <a href="#Sparc_002dSyntax" accesskey="u" rel="up">Sparc-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-35"></a> +<h4 class="subsubsection">9.44.3.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-Sparc"></a> +<a name="index-Sparc-line-comment-character"></a> +<p>A ‘<samp>!</samp>’ character appearing anywhere on a line indicates the start +of a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-Sparc"></a> +<a name="index-statement-separator_002c-Sparc"></a> +<a name="index-Sparc-line-separator"></a> +<p>‘<samp>;</samp>’ can be used instead of a newline to separate statements. +</p> +<hr> +<a name="Sparc_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#Sparc_002dConstants" accesskey="n" rel="next">Sparc-Constants</a>, Previous: <a href="#Sparc_002dChars" accesskey="p" rel="previous">Sparc-Chars</a>, Up: <a href="#Sparc_002dSyntax" accesskey="u" rel="up">Sparc-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-16"></a> +<h4 class="subsubsection">9.44.3.2 Register Names</h4> +<a name="index-Sparc-registers"></a> +<a name="index-register-names_002c-Sparc"></a> + +<p>The Sparc integer register file is broken down into global, +outgoing, local, and incoming. +</p> +<ul> +<li> The 8 global registers are referred to as ‘<samp>%g<var>n</var></samp>’. + +</li><li> The 8 outgoing registers are referred to as ‘<samp>%o<var>n</var></samp>’. + +</li><li> The 8 local registers are referred to as ‘<samp>%l<var>n</var></samp>’. + +</li><li> The 8 incoming registers are referred to as ‘<samp>%i<var>n</var></samp>’. + +</li><li> The frame pointer register ‘<samp>%i6</samp>’ can be referenced using +the alias ‘<samp>%fp</samp>’. + +</li><li> The stack pointer register ‘<samp>%o6</samp>’ can be referenced using +the alias ‘<samp>%sp</samp>’. +</li></ul> + +<p>Floating point registers are simply referred to as ‘<samp>%f<var>n</var></samp>’. +When assembling for pre-V9, only 32 floating point registers +are available. For V9 and later there are 64, but there are +restrictions when referencing the upper 32 registers. They +can only be accessed as double or quad, and thus only even +or quad numbered accesses are allowed. For example, ‘<samp>%f34</samp>’ +is a legal floating point register, but ‘<samp>%f35</samp>’ is not. +</p> +<p>Floating point registers accessed as double can also be referred using +the ‘<samp>%d<var>n</var></samp>’ notation, where <var>n</var> is even. Similarly, +floating point registers accessed as quad can be referred using the +‘<samp>%q<var>n</var></samp>’ notation, where <var>n</var> is a multiple of 4. For +example, ‘<samp>%f4</samp>’ can be denoted as both ‘<samp>%d4</samp>’ and ‘<samp>%q4</samp>’. +On the other hand, ‘<samp>%f2</samp>’ can be denoted as ‘<samp>%d2</samp>’ but not as +‘<samp>%q2</samp>’. +</p> +<p>Certain V9 instructions allow access to ancillary state registers. +Most simply they can be referred to as ‘<samp>%asr<var>n</var></samp>’ where +<var>n</var> can be from 16 to 31. However, there are some aliases +defined to reference ASR registers defined for various UltraSPARC +processors: +</p> +<ul> +<li> The tick compare register is referred to as ‘<samp>%tick_cmpr</samp>’. + +</li><li> The system tick register is referred to as ‘<samp>%stick</samp>’. An alias, +‘<samp>%sys_tick</samp>’, exists but is deprecated and should not be used +by new software. + +</li><li> The system tick compare register is referred to as ‘<samp>%stick_cmpr</samp>’. +An alias, ‘<samp>%sys_tick_cmpr</samp>’, exists but is deprecated and should +not be used by new software. + +</li><li> The software interrupt register is referred to as ‘<samp>%softint</samp>’. + +</li><li> The set software interrupt register is referred to as ‘<samp>%set_softint</samp>’. +The mnemonic ‘<samp>%softint_set</samp>’ is provided as an alias. + +</li><li> The clear software interrupt register is referred to as +‘<samp>%clear_softint</samp>’. The mnemonic ‘<samp>%softint_clear</samp>’ is provided +as an alias. + +</li><li> The performance instrumentation counters register is referred to as +‘<samp>%pic</samp>’. + +</li><li> The performance control register is referred to as ‘<samp>%pcr</samp>’. + +</li><li> The graphics status register is referred to as ‘<samp>%gsr</samp>’. + +</li><li> The V9 dispatch control register is referred to as ‘<samp>%dcr</samp>’. +</li></ul> + +<p>Various V9 branch and conditional move instructions allow +specification of which set of integer condition codes to +test. These are referred to as ‘<samp>%xcc</samp>’ and ‘<samp>%icc</samp>’. +</p> +<p>Additionally, GAS supports the so-called “natural” condition codes; +these are referred to as ‘<samp>%ncc</samp>’ and reference to ‘<samp>%icc</samp>’ if +the word size is 32, ‘<samp>%xcc</samp>’ if the word size is 64. +</p> +<p>In V9, there are 4 sets of floating point condition codes +which are referred to as ‘<samp>%fcc<var>n</var></samp>’. +</p> +<p>Several special privileged and non-privileged registers +exist: +</p> +<ul> +<li> The V9 address space identifier register is referred to as ‘<samp>%asi</samp>’. + +</li><li> The V9 restorable windows register is referred to as ‘<samp>%canrestore</samp>’. + +</li><li> The V9 savable windows register is referred to as ‘<samp>%cansave</samp>’. + +</li><li> The V9 clean windows register is referred to as ‘<samp>%cleanwin</samp>’. + +</li><li> The V9 current window pointer register is referred to as ‘<samp>%cwp</samp>’. + +</li><li> The floating-point queue register is referred to as ‘<samp>%fq</samp>’. + +</li><li> The V8 co-processor queue register is referred to as ‘<samp>%cq</samp>’. + +</li><li> The floating point status register is referred to as ‘<samp>%fsr</samp>’. + +</li><li> The other windows register is referred to as ‘<samp>%otherwin</samp>’. + +</li><li> The V9 program counter register is referred to as ‘<samp>%pc</samp>’. + +</li><li> The V9 next program counter register is referred to as ‘<samp>%npc</samp>’. + +</li><li> The V9 processor interrupt level register is referred to as ‘<samp>%pil</samp>’. + +</li><li> The V9 processor state register is referred to as ‘<samp>%pstate</samp>’. + +</li><li> The trap base address register is referred to as ‘<samp>%tba</samp>’. + +</li><li> The V9 tick register is referred to as ‘<samp>%tick</samp>’. + +</li><li> The V9 trap level is referred to as ‘<samp>%tl</samp>’. + +</li><li> The V9 trap program counter is referred to as ‘<samp>%tpc</samp>’. + +</li><li> The V9 trap next program counter is referred to as ‘<samp>%tnpc</samp>’. + +</li><li> The V9 trap state is referred to as ‘<samp>%tstate</samp>’. + +</li><li> The V9 trap type is referred to as ‘<samp>%tt</samp>’. + +</li><li> The V9 condition codes is referred to as ‘<samp>%ccr</samp>’. + +</li><li> The V9 floating-point registers state is referred to as ‘<samp>%fprs</samp>’. + +</li><li> The V9 version register is referred to as ‘<samp>%ver</samp>’. + +</li><li> The V9 window state register is referred to as ‘<samp>%wstate</samp>’. + +</li><li> The Y register is referred to as ‘<samp>%y</samp>’. + +</li><li> The V8 window invalid mask register is referred to as ‘<samp>%wim</samp>’. + +</li><li> The V8 processor state register is referred to as ‘<samp>%psr</samp>’. + +</li><li> The V9 global register level register is referred to as ‘<samp>%gl</samp>’. +</li></ul> + +<p>Several special register names exist for hypervisor mode code: +</p> +<ul> +<li> The hyperprivileged processor state register is referred to as +‘<samp>%hpstate</samp>’. + +</li><li> The hyperprivileged trap state register is referred to as ‘<samp>%htstate</samp>’. + +</li><li> The hyperprivileged interrupt pending register is referred to as +‘<samp>%hintp</samp>’. + +</li><li> The hyperprivileged trap base address register is referred to as +‘<samp>%htba</samp>’. + +</li><li> The hyperprivileged implementation version register is referred +to as ‘<samp>%hver</samp>’. + +</li><li> The hyperprivileged system tick offset register is referred to as +‘<samp>%hstick_offset</samp>’. Note that there is no ‘<samp>%hstick</samp>’ register, +the normal ‘<samp>%stick</samp>’ is used. + +</li><li> The hyperprivileged system tick enable register is referred to as +‘<samp>%hstick_enable</samp>’. + +</li><li> The hyperprivileged system tick compare register is referred +to as ‘<samp>%hstick_cmpr</samp>’. +</li></ul> + +<hr> +<a name="Sparc_002dConstants"></a> +<div class="header"> +<p> +Next: <a href="#Sparc_002dRelocs" accesskey="n" rel="next">Sparc-Relocs</a>, Previous: <a href="#Sparc_002dRegs" accesskey="p" rel="previous">Sparc-Regs</a>, Up: <a href="#Sparc_002dSyntax" accesskey="u" rel="up">Sparc-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Constants-2"></a> +<h4 class="subsubsection">9.44.3.3 Constants</h4> +<a name="index-Sparc-constants"></a> +<a name="index-constants_002c-Sparc"></a> + +<p>Several Sparc instructions take an immediate operand field for +which mnemonic names exist. Two such examples are ‘<samp>membar</samp>’ +and ‘<samp>prefetch</samp>’. Another example are the set of V9 +memory access instruction that allow specification of an +address space identifier. +</p> +<p>The ‘<samp>membar</samp>’ instruction specifies a memory barrier that is +the defined by the operand which is a bitmask. The supported +mask mnemonics are: +</p> +<ul> +<li> ‘<samp>#Sync</samp>’ requests that all operations (including nonmemory +reference operations) appearing prior to the <code>membar</code> must have +been performed and the effects of any exceptions become visible before +any instructions after the <code>membar</code> may be initiated. This +corresponds to <code>membar</code> cmask field bit 2. + +</li><li> ‘<samp>#MemIssue</samp>’ requests that all memory reference operations +appearing prior to the <code>membar</code> must have been performed before +any memory operation after the <code>membar</code> may be initiated. This +corresponds to <code>membar</code> cmask field bit 1. + +</li><li> ‘<samp>#Lookaside</samp>’ requests that a store appearing prior to the +<code>membar</code> must complete before any load following the +<code>membar</code> referencing the same address can be initiated. This +corresponds to <code>membar</code> cmask field bit 0. + +</li><li> ‘<samp>#StoreStore</samp>’ defines that the effects of all stores appearing +prior to the <code>membar</code> instruction must be visible to all +processors before the effect of any stores following the +<code>membar</code>. Equivalent to the deprecated <code>stbar</code> instruction. +This corresponds to <code>membar</code> mmask field bit 3. + +</li><li> ‘<samp>#LoadStore</samp>’ defines all loads appearing prior to the +<code>membar</code> instruction must have been performed before the effect +of any stores following the <code>membar</code> is visible to any other +processor. This corresponds to <code>membar</code> mmask field bit 2. + +</li><li> ‘<samp>#StoreLoad</samp>’ defines that the effects of all stores appearing +prior to the <code>membar</code> instruction must be visible to all +processors before loads following the <code>membar</code> may be performed. +This corresponds to <code>membar</code> mmask field bit 1. + +</li><li> ‘<samp>#LoadLoad</samp>’ defines that all loads appearing prior to the +<code>membar</code> instruction must have been performed before any loads +following the <code>membar</code> may be performed. This corresponds to +<code>membar</code> mmask field bit 0. + +</li></ul> + +<p>These values can be ored together, for example: +</p> +<div class="example"> +<pre class="example">membar #Sync +membar #StoreLoad | #LoadLoad +membar #StoreLoad | #StoreStore +</pre></div> + +<p>The <code>prefetch</code> and <code>prefetcha</code> instructions take a prefetch +function code. The following prefetch function code constant +mnemonics are available: +</p> +<ul> +<li> ‘<samp>#n_reads</samp>’ requests a prefetch for several reads, and corresponds +to a prefetch function code of 0. + +<p>‘<samp>#one_read</samp>’ requests a prefetch for one read, and corresponds +to a prefetch function code of 1. +</p> +<p>‘<samp>#n_writes</samp>’ requests a prefetch for several writes (and possibly +reads), and corresponds to a prefetch function code of 2. +</p> +<p>‘<samp>#one_write</samp>’ requests a prefetch for one write, and corresponds +to a prefetch function code of 3. +</p> +<p>‘<samp>#page</samp>’ requests a prefetch page, and corresponds to a prefetch +function code of 4. +</p> +<p>‘<samp>#invalidate</samp>’ requests a prefetch invalidate, and corresponds to +a prefetch function code of 16. +</p> +<p>‘<samp>#unified</samp>’ requests a prefetch to the nearest unified cache, and +corresponds to a prefetch function code of 17. +</p> +<p>‘<samp>#n_reads_strong</samp>’ requests a strong prefetch for several reads, +and corresponds to a prefetch function code of 20. +</p> +<p>‘<samp>#one_read_strong</samp>’ requests a strong prefetch for one read, +and corresponds to a prefetch function code of 21. +</p> +<p>‘<samp>#n_writes_strong</samp>’ requests a strong prefetch for several writes, +and corresponds to a prefetch function code of 22. +</p> +<p>‘<samp>#one_write_strong</samp>’ requests a strong prefetch for one write, +and corresponds to a prefetch function code of 23. +</p> +<p>Onle one prefetch code may be specified. Here are some examples: +</p> +<div class="example"> +<pre class="example">prefetch [%l0 + %l2], #one_read +prefetch [%g2 + 8], #n_writes +prefetcha [%g1] 0x8, #unified +prefetcha [%o0 + 0x10] %asi, #n_reads +</pre></div> + +<p>The actual behavior of a given prefetch function code is processor +specific. If a processor does not implement a given prefetch +function code, it will treat the prefetch instruction as a nop. +</p> +<p>For instructions that accept an immediate address space identifier, +<code>as</code> provides many mnemonics corresponding to +V9 defined as well as UltraSPARC and Niagara extended values. +For example, ‘<samp>#ASI_P</samp>’ and ‘<samp>#ASI_BLK_INIT_QUAD_LDD_AIUS</samp>’. +See the V9 and processor specific manuals for details. +</p> +</li></ul> + +<hr> +<a name="Sparc_002dRelocs"></a> +<div class="header"> +<p> +Next: <a href="#Sparc_002dSize_002dTranslations" accesskey="n" rel="next">Sparc-Size-Translations</a>, Previous: <a href="#Sparc_002dConstants" accesskey="p" rel="previous">Sparc-Constants</a>, Up: <a href="#Sparc_002dSyntax" accesskey="u" rel="up">Sparc-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Relocations-4"></a> +<h4 class="subsubsection">9.44.3.4 Relocations</h4> +<a name="index-Sparc-relocations"></a> +<a name="index-relocations_002c-Sparc"></a> + +<p>ELF relocations are available as defined in the 32-bit and 64-bit +Sparc ELF specifications. +</p> +<p><code>R_SPARC_HI22</code> is obtained using ‘<samp>%hi</samp>’ and <code>R_SPARC_LO10</code> +is obtained using ‘<samp>%lo</samp>’. Likewise <code>R_SPARC_HIX22</code> is +obtained from ‘<samp>%hix</samp>’ and <code>R_SPARC_LOX10</code> is obtained +using ‘<samp>%lox</samp>’. For example: +</p> +<div class="example"> +<pre class="example">sethi %hi(symbol), %g1 +or %g1, %lo(symbol), %g1 + +sethi %hix(symbol), %g1 +xor %g1, %lox(symbol), %g1 +</pre></div> + +<p>These “high” mnemonics extract bits 31:10 of their operand, +and the “low” mnemonics extract bits 9:0 of their operand. +</p> +<p>V9 code model relocations can be requested as follows: +</p> +<ul> +<li> <code>R_SPARC_HH22</code> is requested using ‘<samp>%hh</samp>’. It can +also be generated using ‘<samp>%uhi</samp>’. +</li><li> <code>R_SPARC_HM10</code> is requested using ‘<samp>%hm</samp>’. It can +also be generated using ‘<samp>%ulo</samp>’. +</li><li> <code>R_SPARC_LM22</code> is requested using ‘<samp>%lm</samp>’. + +</li><li> <code>R_SPARC_H44</code> is requested using ‘<samp>%h44</samp>’. +</li><li> <code>R_SPARC_M44</code> is requested using ‘<samp>%m44</samp>’. +</li><li> <code>R_SPARC_L44</code> is requested using ‘<samp>%l44</samp>’ or ‘<samp>%l34</samp>’. +</li><li> <code>R_SPARC_H34</code> is requested using ‘<samp>%h34</samp>’. +</li></ul> + +<p>The ‘<samp>%l34</samp>’ generates a <code>R_SPARC_L44</code> relocation because it +calculates the necessary value, and therefore no explicit +<code>R_SPARC_L34</code> relocation needed to be created for this purpose. +</p> +<p>The ‘<samp>%h34</samp>’ and ‘<samp>%l34</samp>’ relocations are used for the abs34 code +model. Here is an example abs34 address generation sequence: +</p> +<div class="example"> +<pre class="example">sethi %h34(symbol), %g1 +sllx %g1, 2, %g1 +or %g1, %l34(symbol), %g1 +</pre></div> + +<p>The PC relative relocation <code>R_SPARC_PC22</code> can be obtained by +enclosing an operand inside of ‘<samp>%pc22</samp>’. Likewise, the +<code>R_SPARC_PC10</code> relocation can be obtained using ‘<samp>%pc10</samp>’. +These are mostly used when assembling PIC code. For example, the +standard PIC sequence on Sparc to get the base of the global offset +table, PC relative, into a register, can be performed as: +</p> +<div class="example"> +<pre class="example">sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 +add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 +</pre></div> + +<p>Several relocations exist to allow the link editor to potentially +optimize GOT data references. The <code>R_SPARC_GOTDATA_OP_HIX22</code> +relocation can obtained by enclosing an operand inside of +‘<samp>%gdop_hix22</samp>’. The <code>R_SPARC_GOTDATA_OP_LOX10</code> +relocation can obtained by enclosing an operand inside of +‘<samp>%gdop_lox10</samp>’. Likewise, <code>R_SPARC_GOTDATA_OP</code> can be +obtained by enclosing an operand inside of ‘<samp>%gdop</samp>’. +For example, assuming the GOT base is in register <code>%l7</code>: +</p> +<div class="example"> +<pre class="example">sethi %gdop_hix22(symbol), %l1 +xor %l1, %gdop_lox10(symbol), %l1 +ld [%l7 + %l1], %l2, %gdop(symbol) +</pre></div> + +<p>There are many relocations that can be requested for access to +thread local storage variables. All of the Sparc TLS mnemonics +are supported: +</p> +<ul> +<li> <code>R_SPARC_TLS_GD_HI22</code> is requested using ‘<samp>%tgd_hi22</samp>’. +</li><li> <code>R_SPARC_TLS_GD_LO10</code> is requested using ‘<samp>%tgd_lo10</samp>’. +</li><li> <code>R_SPARC_TLS_GD_ADD</code> is requested using ‘<samp>%tgd_add</samp>’. +</li><li> <code>R_SPARC_TLS_GD_CALL</code> is requested using ‘<samp>%tgd_call</samp>’. + +</li><li> <code>R_SPARC_TLS_LDM_HI22</code> is requested using ‘<samp>%tldm_hi22</samp>’. +</li><li> <code>R_SPARC_TLS_LDM_LO10</code> is requested using ‘<samp>%tldm_lo10</samp>’. +</li><li> <code>R_SPARC_TLS_LDM_ADD</code> is requested using ‘<samp>%tldm_add</samp>’. +</li><li> <code>R_SPARC_TLS_LDM_CALL</code> is requested using ‘<samp>%tldm_call</samp>’. + +</li><li> <code>R_SPARC_TLS_LDO_HIX22</code> is requested using ‘<samp>%tldo_hix22</samp>’. +</li><li> <code>R_SPARC_TLS_LDO_LOX10</code> is requested using ‘<samp>%tldo_lox10</samp>’. +</li><li> <code>R_SPARC_TLS_LDO_ADD</code> is requested using ‘<samp>%tldo_add</samp>’. + +</li><li> <code>R_SPARC_TLS_IE_HI22</code> is requested using ‘<samp>%tie_hi22</samp>’. +</li><li> <code>R_SPARC_TLS_IE_LO10</code> is requested using ‘<samp>%tie_lo10</samp>’. +</li><li> <code>R_SPARC_TLS_IE_LD</code> is requested using ‘<samp>%tie_ld</samp>’. +</li><li> <code>R_SPARC_TLS_IE_LDX</code> is requested using ‘<samp>%tie_ldx</samp>’. +</li><li> <code>R_SPARC_TLS_IE_ADD</code> is requested using ‘<samp>%tie_add</samp>’. + +</li><li> <code>R_SPARC_TLS_LE_HIX22</code> is requested using ‘<samp>%tle_hix22</samp>’. +</li><li> <code>R_SPARC_TLS_LE_LOX10</code> is requested using ‘<samp>%tle_lox10</samp>’. +</li></ul> + +<p>Here are some example TLS model sequences. +</p> +<p>First, General Dynamic: +</p> +<div class="example"> +<pre class="example">sethi %tgd_hi22(symbol), %l1 +add %l1, %tgd_lo10(symbol), %l1 +add %l7, %l1, %o0, %tgd_add(symbol) +call __tls_get_addr, %tgd_call(symbol) +nop +</pre></div> + +<p>Local Dynamic: +</p> +<div class="example"> +<pre class="example">sethi %tldm_hi22(symbol), %l1 +add %l1, %tldm_lo10(symbol), %l1 +add %l7, %l1, %o0, %tldm_add(symbol) +call __tls_get_addr, %tldm_call(symbol) +nop + +sethi %tldo_hix22(symbol), %l1 +xor %l1, %tldo_lox10(symbol), %l1 +add %o0, %l1, %l1, %tldo_add(symbol) +</pre></div> + +<p>Initial Exec: +</p> +<div class="example"> +<pre class="example">sethi %tie_hi22(symbol), %l1 +add %l1, %tie_lo10(symbol), %l1 +ld [%l7 + %l1], %o0, %tie_ld(symbol) +add %g7, %o0, %o0, %tie_add(symbol) + +sethi %tie_hi22(symbol), %l1 +add %l1, %tie_lo10(symbol), %l1 +ldx [%l7 + %l1], %o0, %tie_ldx(symbol) +add %g7, %o0, %o0, %tie_add(symbol) +</pre></div> + +<p>And finally, Local Exec: +</p> +<div class="example"> +<pre class="example">sethi %tle_hix22(symbol), %l1 +add %l1, %tle_lox10(symbol), %l1 +add %g7, %l1, %l1 +</pre></div> + +<p>When assembling for 64-bit, and a secondary constant addend is +specified in an address expression that would normally generate +an <code>R_SPARC_LO10</code> relocation, the assembler will emit an +<code>R_SPARC_OLO10</code> instead. +</p> +<hr> +<a name="Sparc_002dSize_002dTranslations"></a> +<div class="header"> +<p> +Previous: <a href="#Sparc_002dRelocs" accesskey="p" rel="previous">Sparc-Relocs</a>, Up: <a href="#Sparc_002dSyntax" accesskey="u" rel="up">Sparc-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Size-Translations"></a> +<h4 class="subsubsection">9.44.3.5 Size Translations</h4> +<a name="index-Sparc-size-translations"></a> +<a name="index-size_002c-translations_002c-Sparc"></a> + +<p>Often it is desirable to write code in an operand size agnostic +manner. <code>as</code> provides support for this via +operand size opcode translations. Translations are supported +for loads, stores, shifts, compare-and-swap atomics, and the +‘<samp>clr</samp>’ synthetic instruction. +</p> +<p>If generating 32-bit code, <code>as</code> will generate the +32-bit opcode. Whereas if 64-bit code is being generated, +the 64-bit opcode will be emitted. For example <code>ldn</code> +will be transformed into <code>ld</code> for 32-bit code and +<code>ldx</code> for 64-bit code. +</p> +<p>Here is an example meant to demonstrate all the supported +opcode translations: +</p> +<div class="example"> +<pre class="example">ldn [%o0], %o1 +ldna [%o0] %asi, %o2 +stn %o1, [%o0] +stna %o2, [%o0] %asi +slln %o3, 3, %o3 +srln %o4, 8, %o4 +sran %o5, 12, %o5 +casn [%o0], %o1, %o2 +casna [%o0] %asi, %o1, %o2 +clrn %g1 +</pre></div> + +<p>In 32-bit mode <code>as</code> will emit: +</p> +<div class="example"> +<pre class="example">ld [%o0], %o1 +lda [%o0] %asi, %o2 +st %o1, [%o0] +sta %o2, [%o0] %asi +sll %o3, 3, %o3 +srl %o4, 8, %o4 +sra %o5, 12, %o5 +cas [%o0], %o1, %o2 +casa [%o0] %asi, %o1, %o2 +clr %g1 +</pre></div> + +<p>And in 64-bit mode <code>as</code> will emit: +</p> +<div class="example"> +<pre class="example">ldx [%o0], %o1 +ldxa [%o0] %asi, %o2 +stx %o1, [%o0] +stxa %o2, [%o0] %asi +sllx %o3, 3, %o3 +srlx %o4, 8, %o4 +srax %o5, 12, %o5 +casx [%o0], %o1, %o2 +casxa [%o0] %asi, %o1, %o2 +clrx %g1 +</pre></div> + +<p>Finally, the ‘<samp>.nword</samp>’ translating directive is supported +as well. It is documented in the section on Sparc machine +directives. +</p> +<hr> +<a name="Sparc_002dFloat"></a> +<div class="header"> +<p> +Next: <a href="#Sparc_002dDirectives" accesskey="n" rel="next">Sparc-Directives</a>, Previous: <a href="#Sparc_002dSyntax" accesskey="p" rel="previous">Sparc-Syntax</a>, Up: <a href="#Sparc_002dDependent" accesskey="u" rel="up">Sparc-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-15"></a> +<h4 class="subsection">9.44.4 Floating Point</h4> + +<a name="index-floating-point_002c-SPARC-_0028IEEE_0029"></a> +<a name="index-SPARC-floating-point-_0028IEEE_0029"></a> +<p>The Sparc uses <small>IEEE</small> floating-point numbers. +</p> +<hr> +<a name="Sparc_002dDirectives"></a> +<div class="header"> +<p> +Previous: <a href="#Sparc_002dFloat" accesskey="p" rel="previous">Sparc-Float</a>, Up: <a href="#Sparc_002dDependent" accesskey="u" rel="up">Sparc-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Sparc-Machine-Directives"></a> +<h4 class="subsection">9.44.5 Sparc Machine Directives</h4> + +<a name="index-SPARC-machine-directives"></a> +<a name="index-machine-directives_002c-SPARC"></a> +<p>The Sparc version of <code>as</code> supports the following additional +machine directives: +</p> +<dl compact="compact"> +<dd><a name="index-align-directive_002c-SPARC"></a> +</dd> +<dt><code>.align</code></dt> +<dd><p>This must be followed by the desired alignment in bytes. +</p> +<a name="index-common-directive_002c-SPARC"></a> +</dd> +<dt><code>.common</code></dt> +<dd><p>This must be followed by a symbol name, a positive number, and +<code>"bss"</code>. This behaves somewhat like <code>.comm</code>, but the +syntax is different. +</p> +<a name="index-half-directive_002c-SPARC"></a> +</dd> +<dt><code>.half</code></dt> +<dd><p>This is functionally identical to <code>.short</code>. +</p> +<a name="index-nword-directive_002c-SPARC"></a> +</dd> +<dt><code>.nword</code></dt> +<dd><p>On the Sparc, the <code>.nword</code> directive produces native word sized value, +ie. if assembling with -32 it is equivalent to <code>.word</code>, if assembling +with -64 it is equivalent to <code>.xword</code>. +</p> +<a name="index-proc-directive_002c-SPARC"></a> +</dd> +<dt><code>.proc</code></dt> +<dd><p>This directive is ignored. Any text following it on the same +line is also ignored. +</p> +<a name="index-register-directive_002c-SPARC"></a> +</dd> +<dt><code>.register</code></dt> +<dd><p>This directive declares use of a global application or system register. +It must be followed by a register name %g2, %g3, %g6 or %g7, comma and +the symbol name for that register. If symbol name is <code>#scratch</code>, +it is a scratch register, if it is <code>#ignore</code>, it just suppresses any +errors about using undeclared global register, but does not emit any +information about it into the object file. This can be useful e.g. if you +save the register before use and restore it after. +</p> +<a name="index-reserve-directive_002c-SPARC"></a> +</dd> +<dt><code>.reserve</code></dt> +<dd><p>This must be followed by a symbol name, a positive number, and +<code>"bss"</code>. This behaves somewhat like <code>.lcomm</code>, but the +syntax is different. +</p> +<a name="index-seg-directive_002c-SPARC"></a> +</dd> +<dt><code>.seg</code></dt> +<dd><p>This must be followed by <code>"text"</code>, <code>"data"</code>, or +<code>"data1"</code>. It behaves like <code>.text</code>, <code>.data</code>, or +<code>.data 1</code>. +</p> +<a name="index-skip-directive_002c-SPARC"></a> +</dd> +<dt><code>.skip</code></dt> +<dd><p>This is functionally identical to the <code>.space</code> directive. +</p> +<a name="index-word-directive_002c-SPARC"></a> +</dd> +<dt><code>.word</code></dt> +<dd><p>On the Sparc, the <code>.word</code> directive produces 32 bit values, +instead of the 16 bit values it produces on many other machines. +</p> +<a name="index-xword-directive_002c-SPARC"></a> +</dd> +<dt><code>.xword</code></dt> +<dd><p>On the Sparc V9 processor, the <code>.xword</code> directive produces +64 bit values. +</p></dd> +</dl> + +<hr> +<a name="TIC54X_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#TIC6X_002dDependent" accesskey="n" rel="next">TIC6X-Dependent</a>, Previous: <a href="#Sparc_002dDependent" accesskey="p" rel="previous">Sparc-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TIC54X-Dependent-Features"></a> +<h3 class="section">9.45 TIC54X Dependent Features</h3> + +<a name="index-TIC54X-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dOpts" accesskey="1">TIC54X-Opts</a>:</td><td> </td><td align="left" valign="top">Command-line Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dBlock" accesskey="2">TIC54X-Block</a>:</td><td> </td><td align="left" valign="top">Blocking +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dEnv" accesskey="3">TIC54X-Env</a>:</td><td> </td><td align="left" valign="top">Environment Settings +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dConstants" accesskey="4">TIC54X-Constants</a>:</td><td> </td><td align="left" valign="top">Constants Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dSubsyms" accesskey="5">TIC54X-Subsyms</a>:</td><td> </td><td align="left" valign="top">String Substitution +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dLocals" accesskey="6">TIC54X-Locals</a>:</td><td> </td><td align="left" valign="top">Local Label Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dBuiltins" accesskey="7">TIC54X-Builtins</a>:</td><td> </td><td align="left" valign="top">Builtin Assembler Math Functions +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dExt" accesskey="8">TIC54X-Ext</a>:</td><td> </td><td align="left" valign="top">Extended Addressing Support +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dDirectives" accesskey="9">TIC54X-Directives</a>:</td><td> </td><td align="left" valign="top">Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dMacros">TIC54X-Macros</a>:</td><td> </td><td align="left" valign="top">Macro Features +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dMMRegs">TIC54X-MMRegs</a>:</td><td> </td><td align="left" valign="top">Memory-mapped Registers +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dSyntax">TIC54X-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +</table> + +<hr> +<a name="TIC54X_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dBlock" accesskey="n" rel="next">TIC54X-Block</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-25"></a> +<h4 class="subsection">9.45.1 Options</h4> + +<a name="index-options_002c-TIC54X"></a> +<a name="index-TIC54X-options"></a> +<p>The TMS320C54X version of <code>as</code> has a few machine-dependent options. +</p> +<a name="index-_002dmfar_002dmode-option_002c-far_002dmode"></a> +<a name="index-_002dmf-option_002c-far_002dmode"></a> +<p>You can use the ‘<samp>-mfar-mode</samp>’ option to enable extended addressing mode. +All addresses will be assumed to be > 16 bits, and the appropriate +relocation types will be used. This option is equivalent to using the +‘<samp>.far_mode</samp>’ directive in the assembly code. If you do not use the +‘<samp>-mfar-mode</samp>’ option, all references will be assumed to be 16 bits. +This option may be abbreviated to ‘<samp>-mf</samp>’. +</p> +<a name="index-_002dmcpu-option_002c-cpu"></a> +<p>You can use the ‘<samp>-mcpu</samp>’ option to specify a particular CPU. +This option is equivalent to using the ‘<samp>.version</samp>’ directive in the +assembly code. For recognized CPU codes, see +See <a href="#TIC54X_002dDirectives"><code>.version</code></a>. The default CPU version is +‘<samp>542</samp>’. +</p> +<a name="index-_002dmerrors_002dto_002dfile-option_002c-stderr-redirect"></a> +<a name="index-_002dme-option_002c-stderr-redirect"></a> +<p>You can use the ‘<samp>-merrors-to-file</samp>’ option to redirect error output +to a file (this provided for those deficient environments which don’t +provide adequate output redirection). This option may be abbreviated to +‘<samp>-me</samp>’. +</p> +<hr> +<a name="TIC54X_002dBlock"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dEnv" accesskey="n" rel="next">TIC54X-Env</a>, Previous: <a href="#TIC54X_002dOpts" accesskey="p" rel="previous">TIC54X-Opts</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Blocking"></a> +<h4 class="subsection">9.45.2 Blocking</h4> +<p>A blocked section or memory block is guaranteed not to cross the blocking +boundary (usually a page, or 128 words) if it is smaller than the +blocking size, or to start on a page boundary if it is larger than the +blocking size. +</p> +<hr> +<a name="TIC54X_002dEnv"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dConstants" accesskey="n" rel="next">TIC54X-Constants</a>, Previous: <a href="#TIC54X_002dBlock" accesskey="p" rel="previous">TIC54X-Block</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Environment-Settings"></a> +<h4 class="subsection">9.45.3 Environment Settings</h4> + +<a name="index-environment-settings_002c-TIC54X"></a> +<a name="index-A_005fDIR-environment-variable_002c-TIC54X"></a> +<a name="index-C54XDSP_005fDIR-environment-variable_002c-TIC54X"></a> +<p>‘<samp>C54XDSP_DIR</samp>’ and ‘<samp>A_DIR</samp>’ are semicolon-separated +paths which are added to the list of directories normally searched for +source and include files. ‘<samp>C54XDSP_DIR</samp>’ will override ‘<samp>A_DIR</samp>’. +</p> +<hr> +<a name="TIC54X_002dConstants"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dSubsyms" accesskey="n" rel="next">TIC54X-Subsyms</a>, Previous: <a href="#TIC54X_002dEnv" accesskey="p" rel="previous">TIC54X-Env</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Constants-Syntax"></a> +<h4 class="subsection">9.45.4 Constants Syntax</h4> + +<a name="index-constants_002c-TIC54X"></a> +<p>The TIC54X version of <code>as</code> allows the following additional +constant formats, using a suffix to indicate the radix: +</p><div class="smallexample"> +<pre class="smallexample"><a name="index-binary-constants_002c-TIC54X"></a> +Binary <code>000000B, 011000b</code> +Octal <code>10Q, 224q</code> +Hexadecimal <code>45h, 0FH</code> + +</pre></div> + +<hr> +<a name="TIC54X_002dSubsyms"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dLocals" accesskey="n" rel="next">TIC54X-Locals</a>, Previous: <a href="#TIC54X_002dConstants" accesskey="p" rel="previous">TIC54X-Constants</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="String-Substitution"></a> +<h4 class="subsection">9.45.5 String Substitution</h4> +<p>A subset of allowable symbols (which we’ll call subsyms) may be assigned +arbitrary string values. This is roughly equivalent to C preprocessor +#define macros. When <code>as</code> encounters one of these +symbols, the symbol is replaced in the input stream by its string value. +Subsym names <strong>must</strong> begin with a letter. +</p> +<p>Subsyms may be defined using the <code>.asg</code> and <code>.eval</code> directives +(See <a href="#TIC54X_002dDirectives"><code>.asg</code></a>, +See <a href="#TIC54X_002dDirectives"><code>.eval</code></a>. +</p> +<p>Expansion is recursive until a previously encountered symbol is seen, at +which point substitution stops. +</p> +<p>In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, and SYM1 +is replaced with x. At this point, x has already been encountered +and the substitution stops. +</p> +<div class="smallexample"> +<pre class="smallexample"> .asg "x",SYM1 + .asg "SYM1",SYM2 + .asg "SYM2",x + add x,a ; final code assembled is "add x, a" +</pre></div> + +<p>Macro parameters are converted to subsyms; a side effect of this is the normal +<code>as</code> ’\ARG’ dereferencing syntax is unnecessary. Subsyms +defined within a macro will have global scope, unless the <code>.var</code> +directive is used to identify the subsym as a local macro variable +see <a href="#TIC54X_002dDirectives"><code>.var</code></a>. +</p> +<p>Substitution may be forced in situations where replacement might be +ambiguous by placing colons on either side of the subsym. The following +code: +</p> +<div class="smallexample"> +<pre class="smallexample"> .eval "10",x +LAB:X: add #x, a +</pre></div> + +<p>When assembled becomes: +</p> +<div class="smallexample"> +<pre class="smallexample">LAB10 add #10, a +</pre></div> + +<p>Smaller parts of the string assigned to a subsym may be accessed with +the following syntax: +</p> +<dl compact="compact"> +<dt><code><code>:<var>symbol</var>(<var>char_index</var>):</code></code></dt> +<dd><p>Evaluates to a single-character string, the character at <var>char_index</var>. +</p></dd> +<dt><code><code>:<var>symbol</var>(<var>start</var>,<var>length</var>):</code></code></dt> +<dd><p>Evaluates to a substring of <var>symbol</var> beginning at <var>start</var> with +length <var>length</var>. +</p></dd> +</dl> + +<hr> +<a name="TIC54X_002dLocals"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dBuiltins" accesskey="n" rel="next">TIC54X-Builtins</a>, Previous: <a href="#TIC54X_002dSubsyms" accesskey="p" rel="previous">TIC54X-Subsyms</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Local-Labels"></a> +<h4 class="subsection">9.45.6 Local Labels</h4> +<p>Local labels may be defined in two ways: +</p> +<ul> +<li> $N, where N is a decimal number between 0 and 9 +</li><li> LABEL?, where LABEL is any legal symbol name. +</li></ul> + +<p>Local labels thus defined may be redefined or automatically generated. +The scope of a local label is based on when it may be undefined or reset. +This happens when one of the following situations is encountered: +</p> +<ul> +<li> .newblock directive see <a href="#TIC54X_002dDirectives"><code>.newblock</code></a> +</li><li> The current section is changed (.sect, .text, or .data) +</li><li> Entering or leaving an included file +</li><li> The macro scope where the label was defined is exited +</li></ul> + +<hr> +<a name="TIC54X_002dBuiltins"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dExt" accesskey="n" rel="next">TIC54X-Ext</a>, Previous: <a href="#TIC54X_002dLocals" accesskey="p" rel="previous">TIC54X-Locals</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Math-Builtins"></a> +<h4 class="subsection">9.45.7 Math Builtins</h4> + +<a name="index-math-builtins_002c-TIC54X"></a> +<a name="index-TIC54X-builtin-math-functions"></a> +<a name="index-builtin-math-functions_002c-TIC54X"></a> + +<p>The following built-in functions may be used to generate a +floating-point value. All return a floating-point value except +‘<samp>$cvi</samp>’, ‘<samp>$int</samp>’, and ‘<samp>$sgn</samp>’, which return an integer +value. +</p> +<dl compact="compact"> +<dd><a name="index-_0024acos-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$acos(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point arccosine of <var>expr</var>. +</p> +<a name="index-_0024asin-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$asin(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point arcsine of <var>expr</var>. +</p> +<a name="index-_0024atan-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$atan(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point arctangent of <var>expr</var>. +</p> +<a name="index-_0024atan2-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$atan2(<var>expr1</var>,<var>expr2</var>)</code></code></dt> +<dd><p>Returns the floating point arctangent of <var>expr1</var> / <var>expr2</var>. +</p> +<a name="index-_0024ceil-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$ceil(<var>expr</var>)</code></code></dt> +<dd><p>Returns the smallest integer not less than <var>expr</var> as floating point. +</p> +<a name="index-_0024cosh-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$cosh(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point hyperbolic cosine of <var>expr</var>. +</p> +<a name="index-_0024cos-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$cos(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point cosine of <var>expr</var>. +</p> +<a name="index-_0024cvf-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$cvf(<var>expr</var>)</code></code></dt> +<dd><p>Returns the integer value <var>expr</var> converted to floating-point. +</p> +<a name="index-_0024cvi-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$cvi(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point value <var>expr</var> converted to integer. +</p> +<a name="index-_0024exp-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$exp(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point value e ^ <var>expr</var>. +</p> +<a name="index-_0024fabs-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$fabs(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point absolute value of <var>expr</var>. +</p> +<a name="index-_0024floor-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$floor(<var>expr</var>)</code></code></dt> +<dd><p>Returns the largest integer that is not greater than <var>expr</var> as +floating point. +</p> +<a name="index-_0024fmod-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$fmod(<var>expr1</var>,<var>expr2</var>)</code></code></dt> +<dd><p>Returns the floating point remainder of <var>expr1</var> / <var>expr2</var>. +</p> +<a name="index-_0024int-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$int(<var>expr</var>)</code></code></dt> +<dd><p>Returns 1 if <var>expr</var> evaluates to an integer, zero otherwise. +</p> +<a name="index-_0024ldexp-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$ldexp(<var>expr1</var>,<var>expr2</var>)</code></code></dt> +<dd><p>Returns the floating point value <var>expr1</var> * 2 ^ <var>expr2</var>. +</p> +<a name="index-_0024log10-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$log10(<var>expr</var>)</code></code></dt> +<dd><p>Returns the base 10 logarithm of <var>expr</var>. +</p> +<a name="index-_0024log-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$log(<var>expr</var>)</code></code></dt> +<dd><p>Returns the natural logarithm of <var>expr</var>. +</p> +<a name="index-_0024max-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$max(<var>expr1</var>,<var>expr2</var>)</code></code></dt> +<dd><p>Returns the floating point maximum of <var>expr1</var> and <var>expr2</var>. +</p> +<a name="index-_0024min-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$min(<var>expr1</var>,<var>expr2</var>)</code></code></dt> +<dd><p>Returns the floating point minimum of <var>expr1</var> and <var>expr2</var>. +</p> +<a name="index-_0024pow-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$pow(<var>expr1</var>,<var>expr2</var>)</code></code></dt> +<dd><p>Returns the floating point value <var>expr1</var> ^ <var>expr2</var>. +</p> +<a name="index-_0024round-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$round(<var>expr</var>)</code></code></dt> +<dd><p>Returns the nearest integer to <var>expr</var> as a floating point number. +</p> +<a name="index-_0024sgn-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$sgn(<var>expr</var>)</code></code></dt> +<dd><p>Returns -1, 0, or 1 based on the sign of <var>expr</var>. +</p> +<a name="index-_0024sin-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$sin(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point sine of <var>expr</var>. +</p> +<a name="index-_0024sinh-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$sinh(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point hyperbolic sine of <var>expr</var>. +</p> +<a name="index-_0024sqrt-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$sqrt(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point square root of <var>expr</var>. +</p> +<a name="index-_0024tan-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$tan(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point tangent of <var>expr</var>. +</p> +<a name="index-_0024tanh-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$tanh(<var>expr</var>)</code></code></dt> +<dd><p>Returns the floating point hyperbolic tangent of <var>expr</var>. +</p> +<a name="index-_0024trunc-math-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$trunc(<var>expr</var>)</code></code></dt> +<dd><p>Returns the integer value of <var>expr</var> truncated towards zero as +floating point. +</p> +</dd> +</dl> + +<hr> +<a name="TIC54X_002dExt"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dDirectives" accesskey="n" rel="next">TIC54X-Directives</a>, Previous: <a href="#TIC54X_002dBuiltins" accesskey="p" rel="previous">TIC54X-Builtins</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Extended-Addressing"></a> +<h4 class="subsection">9.45.8 Extended Addressing</h4> +<p>The <code>LDX</code> pseudo-op is provided for loading the extended addressing bits +of a label or address. For example, if an address <code>_label</code> resides +in extended program memory, the value of <code>_label</code> may be loaded as +follows: +</p><div class="smallexample"> +<pre class="smallexample"> ldx #_label,16,a ; loads extended bits of _label + or #_label,a ; loads lower 16 bits of _label + bacc a ; full address is in accumulator A +</pre></div> + +<hr> +<a name="TIC54X_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dMacros" accesskey="n" rel="next">TIC54X-Macros</a>, Previous: <a href="#TIC54X_002dExt" accesskey="p" rel="previous">TIC54X-Ext</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-2"></a> +<h4 class="subsection">9.45.9 Directives</h4> + +<a name="index-machine-directives_002c-TIC54X"></a> +<a name="index-TIC54X-machine-directives"></a> + +<dl compact="compact"> +<dd> +<a name="index-align-directive_002c-TIC54X"></a> +<a name="index-even-directive_002c-TIC54X"></a> +</dd> +<dt><code>.align [<var>size</var>]</code></dt> +<dt><code>.even</code></dt> +<dd><p>Align the section program counter on the next boundary, based on +<var>size</var>. <var>size</var> may be any power of 2. <code>.even</code> is +equivalent to <code>.align</code> with a <var>size</var> of 2. +</p><dl compact="compact"> +<dt><code>1</code></dt> +<dd><p>Align SPC to word boundary +</p></dd> +<dt><code>2</code></dt> +<dd><p>Align SPC to longword boundary (same as .even) +</p></dd> +<dt><code>128</code></dt> +<dd><p>Align SPC to page boundary +</p></dd> +</dl> + +<a name="index-asg-directive_002c-TIC54X"></a> +</dd> +<dt><code>.asg <var>string</var>, <var>name</var></code></dt> +<dd><p>Assign <var>name</var> the string <var>string</var>. String replacement is +performed on <var>string</var> before assignment. +</p> +<a name="index-eval-directive_002c-TIC54X"></a> +</dd> +<dt><code>.eval <var>string</var>, <var>name</var></code></dt> +<dd><p>Evaluate the contents of string <var>string</var> and assign the result as a +string to the subsym <var>name</var>. String replacement is performed on +<var>string</var> before assignment. +</p> +<a name="index-bss-directive_002c-TIC54X"></a> +</dd> +<dt><code>.bss <var>symbol</var>, <var>size</var> [, [<var>blocking_flag</var>] [,<var>alignment_flag</var>]]</code></dt> +<dd><p>Reserve space for <var>symbol</var> in the .bss section. <var>size</var> is in +words. If present, <var>blocking_flag</var> indicates the allocated space +should be aligned on a page boundary if it would otherwise cross a page +boundary. If present, <var>alignment_flag</var> causes the assembler to +allocate <var>size</var> on a long word boundary. +</p> +<a name="index-byte-directive_002c-TIC54X"></a> +<a name="index-ubyte-directive_002c-TIC54X"></a> +<a name="index-char-directive_002c-TIC54X"></a> +<a name="index-uchar-directive_002c-TIC54X"></a> +</dd> +<dt><code>.byte <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.ubyte <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.char <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.uchar <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dd><p>Place one or more bytes into consecutive words of the current section. +The upper 8 bits of each word is zero-filled. If a label is used, it +points to the word allocated for the first byte encountered. +</p> +<a name="index-clink-directive_002c-TIC54X"></a> +</dd> +<dt><code>.clink ["<var>section_name</var>"]</code></dt> +<dd><p>Set STYP_CLINK flag for this section, which indicates to the linker that +if no symbols from this section are referenced, the section should not +be included in the link. If <var>section_name</var> is omitted, the current +section is used. +</p> +<a name="index-c_005fmode-directive_002c-TIC54X"></a> +</dd> +<dt><code>.c_mode</code></dt> +<dd><p>TBD. +</p> +<a name="index-copy-directive_002c-TIC54X"></a> +</dd> +<dt><code>.copy "<var>filename</var>" | <var>filename</var></code></dt> +<dt><code>.include "<var>filename</var>" | <var>filename</var></code></dt> +<dd><p>Read source statements from <var>filename</var>. The normal include search +path is used. Normally .copy will cause statements from the included +file to be printed in the assembly listing and .include will not, but +this distinction is not currently implemented. +</p> +<a name="index-data-directive_002c-TIC54X"></a> +</dd> +<dt><code>.data</code></dt> +<dd><p>Begin assembling code into the .data section. +</p> +<a name="index-double-directive_002c-TIC54X"></a> +<a name="index-ldouble-directive_002c-TIC54X"></a> +<a name="index-float-directive_002c-TIC54X"></a> +<a name="index-xfloat-directive_002c-TIC54X"></a> +</dd> +<dt><code>.double <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.ldouble <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.float <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.xfloat <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dd><p>Place an IEEE single-precision floating-point representation of one or +more floating-point values into the current section. All but +<code>.xfloat</code> align the result on a longword boundary. Values are +stored most-significant word first. +</p> +<a name="index-drlist-directive_002c-TIC54X"></a> +<a name="index-drnolist-directive_002c-TIC54X"></a> +</dd> +<dt><code>.drlist</code></dt> +<dt><code>.drnolist</code></dt> +<dd><p>Control printing of directives to the listing file. Ignored. +</p> +<a name="index-emsg-directive_002c-TIC54X"></a> +<a name="index-mmsg-directive_002c-TIC54X"></a> +<a name="index-wmsg-directive_002c-TIC54X"></a> +</dd> +<dt><code>.emsg <var>string</var></code></dt> +<dt><code>.mmsg <var>string</var></code></dt> +<dt><code>.wmsg <var>string</var></code></dt> +<dd><p>Emit a user-defined error, message, or warning, respectively. +</p> +<a name="index-far_005fmode-directive_002c-TIC54X"></a> +</dd> +<dt><code>.far_mode</code></dt> +<dd><p>Use extended addressing when assembling statements. This should appear +only once per file, and is equivalent to the -mfar-mode option see <a href="#TIC54X_002dOpts"><code>-mfar-mode</code></a>. +</p> +<a name="index-fclist-directive_002c-TIC54X"></a> +<a name="index-fcnolist-directive_002c-TIC54X"></a> +</dd> +<dt><code>.fclist</code></dt> +<dt><code>.fcnolist</code></dt> +<dd><p>Control printing of false conditional blocks to the listing file. +</p> +<a name="index-field-directive_002c-TIC54X"></a> +</dd> +<dt><code>.field <var>value</var> [,<var>size</var>]</code></dt> +<dd><p>Initialize a bitfield of <var>size</var> bits in the current section. If +<var>value</var> is relocatable, then <var>size</var> must be 16. <var>size</var> +defaults to 16 bits. If <var>value</var> does not fit into <var>size</var> bits, +the value will be truncated. Successive <code>.field</code> directives will +pack starting at the current word, filling the most significant bits +first, and aligning to the start of the next word if the field size does +not fit into the space remaining in the current word. A <code>.align</code> +directive with an operand of 1 will force the next <code>.field</code> +directive to begin packing into a new word. If a label is used, it +points to the word that contains the specified field. +</p> +<a name="index-global-directive_002c-TIC54X"></a> +<a name="index-def-directive_002c-TIC54X"></a> +<a name="index-ref-directive_002c-TIC54X"></a> +</dd> +<dt><code>.global <var>symbol</var> [,...,<var>symbol_n</var>]</code></dt> +<dt><code>.def <var>symbol</var> [,...,<var>symbol_n</var>]</code></dt> +<dt><code>.ref <var>symbol</var> [,...,<var>symbol_n</var>]</code></dt> +<dd><p><code>.def</code> nominally identifies a symbol defined in the current file +and available to other files. <code>.ref</code> identifies a symbol used in +the current file but defined elsewhere. Both map to the standard +<code>.global</code> directive. +</p> +<a name="index-half-directive_002c-TIC54X"></a> +<a name="index-uhalf-directive_002c-TIC54X"></a> +<a name="index-short-directive_002c-TIC54X"></a> +<a name="index-ushort-directive_002c-TIC54X"></a> +<a name="index-int-directive_002c-TIC54X"></a> +<a name="index-uint-directive_002c-TIC54X"></a> +<a name="index-word-directive_002c-TIC54X"></a> +<a name="index-uword-directive_002c-TIC54X"></a> +</dd> +<dt><code>.half <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.uhalf <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.short <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.ushort <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.int <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.uint <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.word <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.uword <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dd><p>Place one or more values into consecutive words of the current section. +If a label is used, it points to the word allocated for the first value +encountered. +</p> +<a name="index-label-directive_002c-TIC54X"></a> +</dd> +<dt><code>.label <var>symbol</var></code></dt> +<dd><p>Define a special <var>symbol</var> to refer to the load time address of the +current section program counter. +</p> +<a name="index-length-directive_002c-TIC54X"></a> +<a name="index-width-directive_002c-TIC54X"></a> +</dd> +<dt><code>.length</code></dt> +<dt><code>.width</code></dt> +<dd><p>Set the page length and width of the output listing file. Ignored. +</p> +<a name="index-list-directive_002c-TIC54X"></a> +<a name="index-nolist-directive_002c-TIC54X"></a> +</dd> +<dt><code>.list</code></dt> +<dt><code>.nolist</code></dt> +<dd><p>Control whether the source listing is printed. Ignored. +</p> +<a name="index-long-directive_002c-TIC54X"></a> +<a name="index-ulong-directive_002c-TIC54X"></a> +<a name="index-xlong-directive_002c-TIC54X"></a> +</dd> +<dt><code>.long <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.ulong <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dt><code>.xlong <var>value</var> [,...,<var>value_n</var>]</code></dt> +<dd><p>Place one or more 32-bit values into consecutive words in the current +section. The most significant word is stored first. <code>.long</code> and +<code>.ulong</code> align the result on a longword boundary; <code>xlong</code> does +not. +</p> +<a name="index-loop-directive_002c-TIC54X"></a> +<a name="index-break-directive_002c-TIC54X"></a> +<a name="index-endloop-directive_002c-TIC54X"></a> +</dd> +<dt><code>.loop [<var>count</var>]</code></dt> +<dt><code>.break [<var>condition</var>]</code></dt> +<dt><code>.endloop</code></dt> +<dd><p>Repeatedly assemble a block of code. <code>.loop</code> begins the block, and +<code>.endloop</code> marks its termination. <var>count</var> defaults to 1024, +and indicates the number of times the block should be repeated. +<code>.break</code> terminates the loop so that assembly begins after the +<code>.endloop</code> directive. The optional <var>condition</var> will cause the +loop to terminate only if it evaluates to zero. +</p> +<a name="index-macro-directive_002c-TIC54X"></a> +<a name="index-endm-directive_002c-TIC54X"></a> +</dd> +<dt><code><var>macro_name</var> .macro [<var>param1</var>][,...<var>param_n</var>]</code></dt> +<dt><code>[.mexit]</code></dt> +<dt><code>.endm</code></dt> +<dd><p>See the section on macros for more explanation (See <a href="#TIC54X_002dMacros">TIC54X-Macros</a>. +</p> +<a name="index-mlib-directive_002c-TIC54X"></a> +</dd> +<dt><code>.mlib "<var>filename</var>" | <var>filename</var></code></dt> +<dd><p>Load the macro library <var>filename</var>. <var>filename</var> must be an +archived library (BFD ar-compatible) of text files, expected to contain +only macro definitions. The standard include search path is used. +</p> +<a name="index-mlist-directive_002c-TIC54X"></a> +<a name="index-mnolist-directive_002c-TIC54X"></a> +</dd> +<dt><code>.mlist</code></dt> +<dt><code>.mnolist</code></dt> +<dd><p>Control whether to include macro and loop block expansions in the +listing output. Ignored. +</p> +<a name="index-mmregs-directive_002c-TIC54X"></a> +</dd> +<dt><code>.mmregs</code></dt> +<dd><p>Define global symbolic names for the ’c54x registers. Supposedly +equivalent to executing <code>.set</code> directives for each register with +its memory-mapped value, but in reality is provided only for +compatibility and does nothing. +</p> +<a name="index-newblock-directive_002c-TIC54X"></a> +</dd> +<dt><code>.newblock</code></dt> +<dd><p>This directive resets any TIC54X local labels currently defined. Normal +<code>as</code> local labels are unaffected. +</p> +<a name="index-option-directive_002c-TIC54X"></a> +</dd> +<dt><code>.option <var>option_list</var></code></dt> +<dd><p>Set listing options. Ignored. +</p> +<a name="index-sblock-directive_002c-TIC54X"></a> +</dd> +<dt><code>.sblock "<var>section_name</var>" | <var>section_name</var> [,"<var>name_n</var>" | <var>name_n</var>]</code></dt> +<dd><p>Designate <var>section_name</var> for blocking. Blocking guarantees that a +section will start on a page boundary (128 words) if it would otherwise +cross a page boundary. Only initialized sections may be designated with +this directive. See also See <a href="#TIC54X_002dBlock">TIC54X-Block</a>. +</p> +<a name="index-sect-directive_002c-TIC54X"></a> +</dd> +<dt><code>.sect "<var>section_name</var>"</code></dt> +<dd><p>Define a named initialized section and make it the current section. +</p> +<a name="index-set-directive_002c-TIC54X"></a> +<a name="index-equ-directive_002c-TIC54X"></a> +</dd> +<dt><code><var>symbol</var> .set "<var>value</var>"</code></dt> +<dt><code><var>symbol</var> .equ "<var>value</var>"</code></dt> +<dd><p>Equate a constant <var>value</var> to a <var>symbol</var>, which is placed in the +symbol table. <var>symbol</var> may not be previously defined. +</p> +<a name="index-space-directive_002c-TIC54X"></a> +<a name="index-bes-directive_002c-TIC54X"></a> +</dd> +<dt><code>.space <var>size_in_bits</var></code></dt> +<dt><code>.bes <var>size_in_bits</var></code></dt> +<dd><p>Reserve the given number of bits in the current section and zero-fill +them. If a label is used with <code>.space</code>, it points to the +<strong>first</strong> word reserved. With <code>.bes</code>, the label points to the +<strong>last</strong> word reserved. +</p> +<a name="index-sslist-directive_002c-TIC54X"></a> +<a name="index-ssnolist-directive_002c-TIC54X"></a> +</dd> +<dt><code>.sslist</code></dt> +<dt><code>.ssnolist</code></dt> +<dd><p>Controls the inclusion of subsym replacement in the listing output. Ignored. +</p> +<a name="index-string-directive_002c-TIC54X"></a> +<a name="index-pstring-directive_002c-TIC54X"></a> +</dd> +<dt><code>.string "<var>string</var>" [,...,"<var>string_n</var>"]</code></dt> +<dt><code>.pstring "<var>string</var>" [,...,"<var>string_n</var>"]</code></dt> +<dd><p>Place 8-bit characters from <var>string</var> into the current section. +<code>.string</code> zero-fills the upper 8 bits of each word, while +<code>.pstring</code> puts two characters into each word, filling the +most-significant bits first. Unused space is zero-filled. If a label +is used, it points to the first word initialized. +</p> +<a name="index-struct-directive_002c-TIC54X"></a> +<a name="index-tag-directive_002c-TIC54X"></a> +<a name="index-endstruct-directive_002c-TIC54X"></a> +</dd> +<dt><code>[<var>stag</var>] .struct [<var>offset</var>]</code></dt> +<dt><code>[<var>name_1</var>] element [<var>count_1</var>]</code></dt> +<dt><code>[<var>name_2</var>] element [<var>count_2</var>]</code></dt> +<dt><code>[<var>tname</var>] .tag <var>stagx</var> [<var>tcount</var>]</code></dt> +<dt><code>...</code></dt> +<dt><code>[<var>name_n</var>] element [<var>count_n</var>]</code></dt> +<dt><code>[<var>ssize</var>] .endstruct</code></dt> +<dt><code><var>label</var> .tag [<var>stag</var>]</code></dt> +<dd><p>Assign symbolic offsets to the elements of a structure. <var>stag</var> +defines a symbol to use to reference the structure. <var>offset</var> +indicates a starting value to use for the first element encountered; +otherwise it defaults to zero. Each element can have a named offset, +<var>name</var>, which is a symbol assigned the value of the element’s offset +into the structure. If <var>stag</var> is missing, these become global +symbols. <var>count</var> adjusts the offset that many times, as if +<code>element</code> were an array. <code>element</code> may be one of +<code>.byte</code>, <code>.word</code>, <code>.long</code>, <code>.float</code>, or any +equivalent of those, and the structure offset is adjusted accordingly. +<code>.field</code> and <code>.string</code> are also allowed; the size of +<code>.field</code> is one bit, and <code>.string</code> is considered to be one +word in size. Only element descriptors, structure/union tags, +<code>.align</code> and conditional assembly directives are allowed within +<code>.struct</code>/<code>.endstruct</code>. <code>.align</code> aligns member offsets +to word boundaries only. <var>ssize</var>, if provided, will always be +assigned the size of the structure. +</p> +<p>The <code>.tag</code> directive, in addition to being used to define a +structure/union element within a structure, may be used to apply a +structure to a symbol. Once applied to <var>label</var>, the individual +structure elements may be applied to <var>label</var> to produce the desired +offsets using <var>label</var> as the structure base. +</p> +<a name="index-tab-directive_002c-TIC54X"></a> +</dd> +<dt><code>.tab</code></dt> +<dd><p>Set the tab size in the output listing. Ignored. +</p> +<a name="index-union-directive_002c-TIC54X"></a> +<a name="index-tag-directive_002c-TIC54X-1"></a> +<a name="index-endunion-directive_002c-TIC54X"></a> +</dd> +<dt><code>[<var>utag</var>] .union</code></dt> +<dt><code>[<var>name_1</var>] element [<var>count_1</var>]</code></dt> +<dt><code>[<var>name_2</var>] element [<var>count_2</var>]</code></dt> +<dt><code>[<var>tname</var>] .tag <var>utagx</var>[,<var>tcount</var>]</code></dt> +<dt><code>...</code></dt> +<dt><code>[<var>name_n</var>] element [<var>count_n</var>]</code></dt> +<dt><code>[<var>usize</var>] .endstruct</code></dt> +<dt><code><var>label</var> .tag [<var>utag</var>]</code></dt> +<dd><p>Similar to <code>.struct</code>, but the offset after each element is reset to +zero, and the <var>usize</var> is set to the maximum of all defined elements. +Starting offset for the union is always zero. +</p> +<a name="index-usect-directive_002c-TIC54X"></a> +</dd> +<dt><code>[<var>symbol</var>] .usect "<var>section_name</var>", <var>size</var>, [,[<var>blocking_flag</var>] [,<var>alignment_flag</var>]]</code></dt> +<dd><p>Reserve space for variables in a named, uninitialized section (similar to +.bss). <code>.usect</code> allows definitions sections independent of .bss. +<var>symbol</var> points to the first location reserved by this allocation. +The symbol may be used as a variable name. <var>size</var> is the allocated +size in words. <var>blocking_flag</var> indicates whether to block this +section on a page boundary (128 words) (see <a href="#TIC54X_002dBlock">TIC54X-Block</a>). +<var>alignment flag</var> indicates whether the section should be +longword-aligned. +</p> +<a name="index-var-directive_002c-TIC54X"></a> +</dd> +<dt><code>.var <var>sym</var>[,..., <var>sym_n</var>]</code></dt> +<dd><p>Define a subsym to be a local variable within a macro. See +See <a href="#TIC54X_002dMacros">TIC54X-Macros</a>. +</p> +<a name="index-version-directive_002c-TIC54X"></a> +</dd> +<dt><code>.version <var>version</var></code></dt> +<dd><p>Set which processor to build instructions for. Though the following +values are accepted, the op is ignored. +</p><dl compact="compact"> +<dt><code>541</code></dt> +<dt><code>542</code></dt> +<dt><code>543</code></dt> +<dt><code>545</code></dt> +<dt><code>545LP</code></dt> +<dt><code>546LP</code></dt> +<dt><code>548</code></dt> +<dt><code>549</code></dt> +</dl> +</dd> +</dl> + +<hr> +<a name="TIC54X_002dMacros"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dMMRegs" accesskey="n" rel="next">TIC54X-MMRegs</a>, Previous: <a href="#TIC54X_002dDirectives" accesskey="p" rel="previous">TIC54X-Directives</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Macros-1"></a> +<h4 class="subsection">9.45.10 Macros</h4> + +<a name="index-TIC54X_002dspecific-macros"></a> +<a name="index-macros_002c-TIC54X"></a> +<p>Macros do not require explicit dereferencing of arguments (i.e., \ARG). +</p> +<p>During macro expansion, the macro parameters are converted to subsyms. +If the number of arguments passed the macro invocation exceeds the +number of parameters defined, the last parameter is assigned the string +equivalent of all remaining arguments. If fewer arguments are given +than parameters, the missing parameters are assigned empty strings. To +include a comma in an argument, you must enclose the argument in quotes. +</p> +<a name="index-subsym-builtins_002c-TIC54X"></a> +<a name="index-TIC54X-subsym-builtins"></a> +<a name="index-builtin-subsym-functions_002c-TIC54X"></a> +<p>The following built-in subsym functions allow examination of the string +value of subsyms (or ordinary strings). The arguments are strings +unless otherwise indicated (subsyms passed as args will be replaced by +the strings they represent). +</p><dl compact="compact"> +<dd><a name="index-_0024symlen-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$symlen(<var>str</var>)</code></code></dt> +<dd><p>Returns the length of <var>str</var>. +</p> +<a name="index-_0024symcmp-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$symcmp(<var>str1</var>,<var>str2</var>)</code></code></dt> +<dd><p>Returns 0 if <var>str1</var> == <var>str2</var>, non-zero otherwise. +</p> +<a name="index-_0024firstch-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$firstch(<var>str</var>,<var>ch</var>)</code></code></dt> +<dd><p>Returns index of the first occurrence of character constant <var>ch</var> in +<var>str</var>. +</p> +<a name="index-_0024lastch-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$lastch(<var>str</var>,<var>ch</var>)</code></code></dt> +<dd><p>Returns index of the last occurrence of character constant <var>ch</var> in +<var>str</var>. +</p> +<a name="index-_0024isdefed-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$isdefed(<var>symbol</var>)</code></code></dt> +<dd><p>Returns zero if the symbol <var>symbol</var> is not in the symbol table, +non-zero otherwise. +</p> +<a name="index-_0024ismember-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$ismember(<var>symbol</var>,<var>list</var>)</code></code></dt> +<dd><p>Assign the first member of comma-separated string <var>list</var> to +<var>symbol</var>; <var>list</var> is reassigned the remainder of the list. Returns +zero if <var>list</var> is a null string. Both arguments must be subsyms. +</p> +<a name="index-_0024iscons-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$iscons(<var>expr</var>)</code></code></dt> +<dd><p>Returns 1 if string <var>expr</var> is binary, 2 if octal, 3 if hexadecimal, +4 if a character, 5 if decimal, and zero if not an integer. +</p> +<a name="index-_0024isname-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$isname(<var>name</var>)</code></code></dt> +<dd><p>Returns 1 if <var>name</var> is a valid symbol name, zero otherwise. +</p> +<a name="index-_0024isreg-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$isreg(<var>reg</var>)</code></code></dt> +<dd><p>Returns 1 if <var>reg</var> is a valid predefined register name (AR0-AR7 only). +</p> +<a name="index-_0024structsz-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$structsz(<var>stag</var>)</code></code></dt> +<dd><p>Returns the size of the structure or union represented by <var>stag</var>. +</p> +<a name="index-_0024structacc-subsym-builtin_002c-TIC54X"></a> +</dd> +<dt><code><code>$structacc(<var>stag</var>)</code></code></dt> +<dd><p>Returns the reference point of the structure or union represented by +<var>stag</var>. Always returns zero. +</p> +</dd> +</dl> + +<hr> +<a name="TIC54X_002dMMRegs"></a> +<div class="header"> +<p> +Next: <a href="#TIC54X_002dSyntax" accesskey="n" rel="next">TIC54X-Syntax</a>, Previous: <a href="#TIC54X_002dMacros" accesskey="p" rel="previous">TIC54X-Macros</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Memory_002dmapped-Registers"></a> +<h4 class="subsection">9.45.11 Memory-mapped Registers</h4> + +<a name="index-TIC54X-memory_002dmapped-registers"></a> +<a name="index-registers_002c-TIC54X-memory_002dmapped"></a> +<a name="index-memory_002dmapped-registers_002c-TIC54X"></a> +<p>The following symbols are recognized as memory-mapped registers: +</p> + +<hr> +<a name="TIC54X_002dSyntax"></a> +<div class="header"> +<p> +Previous: <a href="#TIC54X_002dMMRegs" accesskey="p" rel="previous">TIC54X-MMRegs</a>, Up: <a href="#TIC54X_002dDependent" accesskey="u" rel="up">TIC54X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TIC54X-Syntax"></a> +<h4 class="subsection">9.45.12 TIC54X Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#TIC54X_002dChars" accesskey="1">TIC54X-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="TIC54X_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#TIC54X_002dSyntax" accesskey="u" rel="up">TIC54X-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-36"></a> +<h4 class="subsubsection">9.45.12.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-TIC54X"></a> +<a name="index-TIC54X-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ appearing anywhere on a line indicates the +start of a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<p>The presence of an asterisk (‘<samp>*</samp>’) at the start of a line also +indicates a comment that extends to the end of that line. +</p> +<a name="index-line-separator_002c-TIC54X"></a> +<a name="index-statement-separator_002c-TIC54X"></a> +<a name="index-TIC54X-line-separator"></a> +<p>The TIC54X assembler does not currently support a line separator +character. +</p> + +<hr> +<a name="TIC6X_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#TILE_002dGx_002dDependent" accesskey="n" rel="next">TILE-Gx-Dependent</a>, Previous: <a href="#TIC54X_002dDependent" accesskey="p" rel="previous">TIC54X-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TIC6X-Dependent-Features"></a> +<h3 class="section">9.46 TIC6X Dependent Features</h3> + +<a name="index-TIC6X-support"></a> +<a name="index-TMS320C6X-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#TIC6X-Options" accesskey="1">TIC6X Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC6X-Syntax" accesskey="2">TIC6X Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#TIC6X-Directives" accesskey="3">TIC6X Directives</a>:</td><td> </td><td align="left" valign="top">Directives +</td></tr> +</table> + +<hr> +<a name="TIC6X-Options"></a> +<div class="header"> +<p> +Next: <a href="#TIC6X-Syntax" accesskey="n" rel="next">TIC6X Syntax</a>, Up: <a href="#TIC6X_002dDependent" accesskey="u" rel="up">TIC6X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TIC6X-Options-1"></a> +<h4 class="subsection">9.46.1 TIC6X Options</h4> +<a name="index-TIC6X-options"></a> +<a name="index-options-for-TIC6X"></a> + +<dl compact="compact"> +<dd> +<a name="index-_002dmarch_003d-command_002dline-option_002c-TIC6X"></a> +</dd> +<dt><code>-march=<var>arch</var></code></dt> +<dd><p>Enable (only) instructions from architecture <var>arch</var>. By default, +all instructions are permitted. +</p> +<p>The following values of <var>arch</var> are accepted: <code>c62x</code>, +<code>c64x</code>, <code>c64x+</code>, <code>c67x</code>, <code>c67x+</code>, <code>c674x</code>. +</p> +<a name="index-_002dmdsbt-command_002dline-option_002c-TIC6X"></a> +<a name="index-_002dmno_002ddsbt-command_002dline-option_002c-TIC6X"></a> +</dd> +<dt><code>-mdsbt</code></dt> +<dt><code>-mno-dsbt</code></dt> +<dd><p>The <samp>-mdsbt</samp> option causes the assembler to generate the +<code>Tag_ABI_DSBT</code> attribute with a value of 1, indicating that the +code is using DSBT addressing. The <samp>-mno-dsbt</samp> option, the +default, causes the tag to have a value of 0, indicating that the code +does not use DSBT addressing. The linker will emit a warning if +objects of different type (DSBT and non-DSBT) are linked together. +</p> +<a name="index-_002dmpid_003d-command_002dline-option_002c-TIC6X"></a> +</dd> +<dt><code>-mpid=no</code></dt> +<dt><code>-mpid=near</code></dt> +<dt><code>-mpid=far</code></dt> +<dd><p>The <samp>-mpid=</samp> option causes the assembler to generate the +<code>Tag_ABI_PID</code> attribute with a value indicating the form of data +addressing used by the code. <samp>-mpid=no</samp>, the default, +indicates position-dependent data addressing, <samp>-mpid=near</samp> +indicates position-independent addressing with GOT accesses using near +DP addressing, and <samp>-mpid=far</samp> indicates position-independent +addressing with GOT accesses using far DP addressing. The linker will +emit a warning if objects built with different settings of this option +are linked together. +</p> +<a name="index-_002dmpic-command_002dline-option_002c-TIC6X"></a> +<a name="index-_002dmno_002dpic-command_002dline-option_002c-TIC6X"></a> +</dd> +<dt><code>-mpic</code></dt> +<dt><code>-mno-pic</code></dt> +<dd><p>The <samp>-mpic</samp> option causes the assembler to generate the +<code>Tag_ABI_PIC</code> attribute with a value of 1, indicating that the +code is using position-independent code addressing, The +<code>-mno-pic</code> option, the default, causes the tag to have a value of +0, indicating position-dependent code addressing. The linker will +emit a warning if objects of different type (position-dependent and +position-independent) are linked together. +</p> +<a name="index-TIC6X-big_002dendian-output"></a> +<a name="index-TIC6X-little_002dendian-output"></a> +<a name="index-big_002dendian-output_002c-TIC6X"></a> +<a name="index-little_002dendian-output_002c-TIC6X"></a> +</dd> +<dt><code>-mbig-endian</code></dt> +<dt><code>-mlittle-endian</code></dt> +<dd><p>Generate code for the specified endianness. The default is +little-endian. +</p> +</dd> +</dl> + +<hr> +<a name="TIC6X-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#TIC6X-Directives" accesskey="n" rel="next">TIC6X Directives</a>, Previous: <a href="#TIC6X-Options" accesskey="p" rel="previous">TIC6X Options</a>, Up: <a href="#TIC6X_002dDependent" accesskey="u" rel="up">TIC6X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TIC6X-Syntax-1"></a> +<h4 class="subsection">9.46.2 TIC6X Syntax</h4> + +<a name="index-line-comment-character_002c-TIC6X"></a> +<a name="index-TIC6X-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ on a line indicates the start of a comment +that extends to the end of the current line. If a ‘<samp>#</samp>’ or +‘<samp>*</samp>’ appears as the first character of a line, the whole line is +treated as a comment. Note that if a line starts with a ‘<samp>#</samp>’ +character then it can also be a logical line number directive +(see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-TIC6X"></a> +<a name="index-statement-separator_002c-TIC6X"></a> +<a name="index-TIC6X-line-separator"></a> +<p>The ‘<samp>@</samp>’ character can be used instead of a newline to separate +statements. +</p> +<p>Instruction, register and functional unit names are case-insensitive. +<code>as</code> requires fully-specified functional unit names, +such as ‘<samp>.S1</samp>’, ‘<samp>.L1X</samp>’ or ‘<samp>.D1T2</samp>’, on all instructions +using a functional unit. +</p> +<p>For some instructions, there may be syntactic ambiguity between +register or functional unit names and the names of labels or other +symbols. To avoid this, enclose the ambiguous symbol name in +parentheses; register and functional unit names may not be enclosed in +parentheses. +</p> +<hr> +<a name="TIC6X-Directives"></a> +<div class="header"> +<p> +Previous: <a href="#TIC6X-Syntax" accesskey="p" rel="previous">TIC6X Syntax</a>, Up: <a href="#TIC6X_002dDependent" accesskey="u" rel="up">TIC6X-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TIC6X-Directives-1"></a> +<h4 class="subsection">9.46.3 TIC6X Directives</h4> + +<a name="index-machine-directives_002c-TIC6X"></a> +<a name="index-TIC6X-machine-directives"></a> + +<p>Directives controlling the set of instructions accepted by the +assembler have effect for instructions between the directive and any +subsequent directive overriding it. +</p> +<dl compact="compact"> +<dd> +<a name="index-_002earch-directive_002c-TIC6X"></a> +</dd> +<dt><code>.arch <var>arch</var></code></dt> +<dd><p>This has the same effect as <samp>-march=<var>arch</var></samp>. +</p> +<a name="index-_002ecantunwind-directive_002c-TIC6X"></a> +</dd> +<dt><code>.cantunwind</code></dt> +<dd><p>Prevents unwinding through the current function. No personality routine +or exception table data is required or permitted. +</p> +<p>If this is not specified then frame unwinding information will be +constructed from CFI directives. see <a href="#CFI-directives">CFI directives</a>. +</p> +<a name="index-_002ec6xabi_005fattribute-directive_002c-TIC6X"></a> +</dd> +<dt><code>.c6xabi_attribute <var>tag</var>, <var>value</var></code></dt> +<dd><p>Set the C6000 EABI build attribute <var>tag</var> to <var>value</var>. +</p> +<p>The <var>tag</var> is either an attribute number or one of +<code>Tag_ISA</code>, <code>Tag_ABI_wchar_t</code>, +<code>Tag_ABI_stack_align_needed</code>, +<code>Tag_ABI_stack_align_preserved</code>, <code>Tag_ABI_DSBT</code>, +<code>Tag_ABI_PID</code>, <code>Tag_ABI_PIC</code>, +<code>TAG_ABI_array_object_alignment</code>, +<code>TAG_ABI_array_object_align_expected</code>, +<code>Tag_ABI_compatibility</code> and <code>Tag_ABI_conformance</code>. The +<var>value</var> is either a <code>number</code>, <code>"string"</code>, or +<code>number, "string"</code> depending on the tag. +</p> +<a name="index-_002eehtype-directive_002c-TIC6X"></a> +</dd> +<dt><code>.ehtype <var>symbol</var></code></dt> +<dd><p>Output an exception type table reference to <var>symbol</var>. +</p> +<a name="index-_002eendp-directive_002c-TIC6X"></a> +</dd> +<dt><code>.endp</code></dt> +<dd><p>Marks the end of and exception table or function. If preceded by a +<code>.handlerdata</code> directive then this also switched back to the previous +text section. +</p> +<a name="index-_002ehandlerdata-directive_002c-TIC6X"></a> +</dd> +<dt><code>.handlerdata</code></dt> +<dd><p>Marks the end of the current function, and the start of the exception table +entry for that function. Anything between this directive and the +<code>.endp</code> directive will be added to the exception table entry. +</p> +<p>Must be preceded by a CFI block containing a <code>.cfi_lsda</code> directive. +</p> +<a name="index-_002enocmp-directive_002c-TIC6X"></a> +</dd> +<dt><code>.nocmp</code></dt> +<dd><p>Disallow use of C64x+ compact instructions in the current text +section. +</p> +<a name="index-_002epersonalityindex-directive_002c-TIC6X"></a> +</dd> +<dt><code>.personalityindex <var>index</var></code></dt> +<dd><p>Sets the personality routine for the current function to the ABI specified +compact routine number <var>index</var> +</p> +<a name="index-_002epersonality-directive_002c-TIC6X"></a> +</dd> +<dt><code>.personality <var>name</var></code></dt> +<dd><p>Sets the personality routine for the current function to <var>name</var>. +</p> +<a name="index-_002escomm-directive_002c-TIC6X"></a> +</dd> +<dt><code>.scomm <var>symbol</var>, <var>size</var>, <var>align</var></code></dt> +<dd><p>Like <code>.comm</code>, creating a common symbol <var>symbol</var> with size <var>size</var> +and alignment <var>align</var>, but unlike when using <code>.comm</code>, this symbol +will be placed into the small BSS section by the linker. +</p> +</dd> +</dl> + + +<hr> +<a name="TILE_002dGx_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#TILEPro_002dDependent" accesskey="n" rel="next">TILEPro-Dependent</a>, Previous: <a href="#TIC6X_002dDependent" accesskey="p" rel="previous">TIC6X-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TILE_002dGx-Dependent-Features"></a> +<h3 class="section">9.47 TILE-Gx Dependent Features</h3> + +<a name="index-TILE_002dGx-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#TILE_002dGx-Options" accesskey="1">TILE-Gx Options</a>:</td><td> </td><td align="left" valign="top">TILE-Gx Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILE_002dGx-Syntax" accesskey="2">TILE-Gx Syntax</a>:</td><td> </td><td align="left" valign="top">TILE-Gx Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILE_002dGx-Directives" accesskey="3">TILE-Gx Directives</a>:</td><td> </td><td align="left" valign="top">TILE-Gx Directives +</td></tr> +</table> + +<hr> +<a name="TILE_002dGx-Options"></a> +<div class="header"> +<p> +Next: <a href="#TILE_002dGx-Syntax" accesskey="n" rel="next">TILE-Gx Syntax</a>, Up: <a href="#TILE_002dGx_002dDependent" accesskey="u" rel="up">TILE-Gx-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-26"></a> +<h4 class="subsection">9.47.1 Options</h4> + +<p>The following table lists all available TILE-Gx specific options: +</p> +<dl compact="compact"> +<dd><a name="index-_002dm32-option_002c-TILE_002dGx"></a> +<a name="index-_002dm64-option_002c-TILE_002dGx"></a> +</dd> +<dt><code>-m32 | -m64</code></dt> +<dd><p>Select the word size, either 32 bits or 64 bits. +</p> +<a name="index-_002dEB-option_002c-TILE_002dGx"></a> +<a name="index-_002dEL-option_002c-TILE_002dGx"></a> +</dd> +<dt><code>-EB | -EL</code></dt> +<dd><p>Select the endianness, either big-endian (-EB) or little-endian (-EL). +</p> +</dd> +</dl> + +<hr> +<a name="TILE_002dGx-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#TILE_002dGx-Directives" accesskey="n" rel="next">TILE-Gx Directives</a>, Previous: <a href="#TILE_002dGx-Options" accesskey="p" rel="previous">TILE-Gx Options</a>, Up: <a href="#TILE_002dGx_002dDependent" accesskey="u" rel="up">TILE-Gx-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-28"></a> +<h4 class="subsection">9.47.2 Syntax</h4> +<a name="index-TILE_002dGx-syntax"></a> +<a name="index-syntax_002c-TILE_002dGx"></a> + +<p>Block comments are delimited by ‘<samp>/*</samp>’ and ‘<samp>*/</samp>’. End of line +comments may be introduced by ‘<samp>#</samp>’. +</p> +<p>Instructions consist of a leading opcode or macro name followed by +whitespace and an optional comma-separated list of operands: +</p> +<div class="smallexample"> +<pre class="smallexample"><var>opcode</var> [<var>operand</var>, …] +</pre></div> + +<p>Instructions must be separated by a newline or semicolon. +</p> +<p>There are two ways to write code: either write naked instructions, +which the assembler is free to combine into VLIW bundles, or specify +the VLIW bundles explicitly. +</p> +<p>Bundles are specified using curly braces: +</p> +<div class="smallexample"> +<pre class="smallexample">{ <var>add</var> r3,r4,r5 ; <var>add</var> r7,r8,r9 ; <var>lw</var> r10,r11 } +</pre></div> + +<p>A bundle can span multiple lines. If you want to put multiple +instructions on a line, whether in a bundle or not, you need to +separate them with semicolons as in this example. +</p> +<p>A bundle may contain one or more instructions, up to the limit +specified by the ISA (currently three). If fewer instructions are +specified than the hardware supports in a bundle, the assembler +inserts <code>fnop</code> instructions automatically. +</p> +<p>The assembler will prefer to preserve the ordering of instructions +within the bundle, putting the first instruction in a lower-numbered +pipeline than the next one, etc. This fact, combined with the +optional use of explicit <code>fnop</code> or <code>nop</code> instructions, +allows precise control over which pipeline executes each instruction. +</p> +<p>If the instructions cannot be bundled in the listed order, the +assembler will automatically try to find a valid pipeline +assignment. If there is no way to bundle the instructions together, +the assembler reports an error. +</p> +<p>The assembler does not yet auto-bundle (automatically combine multiple +instructions into one bundle), but it reserves the right to do so in +the future. If you want to force an instruction to run by itself, put +it in a bundle explicitly with curly braces and use <code>nop</code> +instructions (not <code>fnop</code>) to fill the remaining pipeline slots in +that bundle. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#TILE_002dGx-Opcodes" accesskey="1">TILE-Gx Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcode Naming Conventions. +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILE_002dGx-Registers" accesskey="2">TILE-Gx Registers</a>:</td><td> </td><td align="left" valign="top">Register Naming. +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILE_002dGx-Modifiers" accesskey="3">TILE-Gx Modifiers</a>:</td><td> </td><td align="left" valign="top">Symbolic Operand Modifiers. +</td></tr> +</table> + +<hr> +<a name="TILE_002dGx-Opcodes"></a> +<div class="header"> +<p> +Next: <a href="#TILE_002dGx-Registers" accesskey="n" rel="next">TILE-Gx Registers</a>, Up: <a href="#TILE_002dGx-Syntax" accesskey="u" rel="up">TILE-Gx Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcode-Names"></a> +<h4 class="subsubsection">9.47.2.1 Opcode Names</h4> +<a name="index-TILE_002dGx-opcode-names"></a> +<a name="index-opcode-names_002c-TILE_002dGx"></a> + +<p>For a complete list of opcodes and descriptions of their semantics, +see <cite>TILE-Gx Instruction Set Architecture</cite>, available upon +request at www.tilera.com. +</p> +<hr> +<a name="TILE_002dGx-Registers"></a> +<div class="header"> +<p> +Next: <a href="#TILE_002dGx-Modifiers" accesskey="n" rel="next">TILE-Gx Modifiers</a>, Previous: <a href="#TILE_002dGx-Opcodes" accesskey="p" rel="previous">TILE-Gx Opcodes</a>, Up: <a href="#TILE_002dGx-Syntax" accesskey="u" rel="up">TILE-Gx Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-17"></a> +<h4 class="subsubsection">9.47.2.2 Register Names</h4> +<a name="index-TILE_002dGx-register-names"></a> +<a name="index-register-names_002c-TILE_002dGx"></a> + +<p>General-purpose registers are represented by predefined symbols of the +form ‘<samp>r<var>N</var></samp>’, where <var>N</var> represents a number between +<code>0</code> and <code>63</code>. However, the following registers have +canonical names that must be used instead: +</p> +<dl compact="compact"> +<dt><code>r54</code></dt> +<dd><p>sp +</p> +</dd> +<dt><code>r55</code></dt> +<dd><p>lr +</p> +</dd> +<dt><code>r56</code></dt> +<dd><p>sn +</p> +</dd> +<dt><code>r57</code></dt> +<dd><p>idn0 +</p> +</dd> +<dt><code>r58</code></dt> +<dd><p>idn1 +</p> +</dd> +<dt><code>r59</code></dt> +<dd><p>udn0 +</p> +</dd> +<dt><code>r60</code></dt> +<dd><p>udn1 +</p> +</dd> +<dt><code>r61</code></dt> +<dd><p>udn2 +</p> +</dd> +<dt><code>r62</code></dt> +<dd><p>udn3 +</p> +</dd> +<dt><code>r63</code></dt> +<dd><p>zero +</p> +</dd> +</dl> + +<p>The assembler will emit a warning if a numeric name is used instead of +the non-numeric name. The <code>.no_require_canonical_reg_names</code> +assembler pseudo-op turns off this +warning. <code>.require_canonical_reg_names</code> turns it back on. +</p> +<hr> +<a name="TILE_002dGx-Modifiers"></a> +<div class="header"> +<p> +Previous: <a href="#TILE_002dGx-Registers" accesskey="p" rel="previous">TILE-Gx Registers</a>, Up: <a href="#TILE_002dGx-Syntax" accesskey="u" rel="up">TILE-Gx Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbolic-Operand-Modifiers-4"></a> +<h4 class="subsubsection">9.47.2.3 Symbolic Operand Modifiers</h4> +<a name="index-TILE_002dGx-modifiers"></a> +<a name="index-symbol-modifiers_002c-TILE_002dGx"></a> + +<p>The assembler supports several modifiers when using symbol addresses +in TILE-Gx instruction operands. The general syntax is the following: +</p> +<div class="smallexample"> +<pre class="smallexample">modifier(symbol) +</pre></div> + +<p>The following modifiers are supported: +</p> +<dl compact="compact"> +<dt><code>hw0</code></dt> +<dd> +<p>This modifier is used to load bits 0-15 of the symbol’s address. +</p> +</dd> +<dt><code>hw1</code></dt> +<dd> +<p>This modifier is used to load bits 16-31 of the symbol’s address. +</p> +</dd> +<dt><code>hw2</code></dt> +<dd> +<p>This modifier is used to load bits 32-47 of the symbol’s address. +</p> +</dd> +<dt><code>hw3</code></dt> +<dd> +<p>This modifier is used to load bits 48-63 of the symbol’s address. +</p> +</dd> +<dt><code>hw0_last</code></dt> +<dd> +<p>This modifier yields the same value as <code>hw0</code>, but it also checks +that the value does not overflow. +</p> +</dd> +<dt><code>hw1_last</code></dt> +<dd> +<p>This modifier yields the same value as <code>hw1</code>, but it also checks +that the value does not overflow. +</p> +</dd> +<dt><code>hw2_last</code></dt> +<dd> +<p>This modifier yields the same value as <code>hw2</code>, but it also checks +that the value does not overflow. +</p> +<p>A 48-bit symbolic value is constructed by using the following idiom: +</p> +<div class="smallexample"> +<pre class="smallexample">moveli r0, hw2_last(sym) +shl16insli r0, r0, hw1(sym) +shl16insli r0, r0, hw0(sym) +</pre></div> + +</dd> +<dt><code>hw0_got</code></dt> +<dd> +<p>This modifier is used to load bits 0-15 of the symbol’s offset in the +GOT entry corresponding to the symbol. +</p> +</dd> +<dt><code>hw0_last_got</code></dt> +<dd> +<p>This modifier yields the same value as <code>hw0_got</code>, but it also +checks that the value does not overflow. +</p> +</dd> +<dt><code>hw1_last_got</code></dt> +<dd> +<p>This modifier is used to load bits 16-31 of the symbol’s offset in the +GOT entry corresponding to the symbol, and it also checks that the +value does not overflow. +</p> +</dd> +<dt><code>plt</code></dt> +<dd> +<p>This modifier is used for function symbols. It causes a +<em>procedure linkage table</em>, an array of code stubs, to be created +at the time the shared object is created or linked against, together +with a global offset table entry. The value is a pc-relative offset +to the corresponding stub code in the procedure linkage table. This +arrangement causes the run-time symbol resolver to be called to look +up and set the value of the symbol the first time the function is +called (at latest; depending environment variables). It is only safe +to leave the symbol unresolved this way if all references are function +calls. +</p> +</dd> +<dt><code>hw0_plt</code></dt> +<dd> +<p>This modifier is used to load bits 0-15 of the pc-relative address of +a plt entry. +</p> +</dd> +<dt><code>hw1_plt</code></dt> +<dd> +<p>This modifier is used to load bits 16-31 of the pc-relative address of +a plt entry. +</p> +</dd> +<dt><code>hw1_last_plt</code></dt> +<dd> +<p>This modifier yields the same value as <code>hw1_plt</code>, but it also +checks that the value does not overflow. +</p> +</dd> +<dt><code>hw2_last_plt</code></dt> +<dd> +<p>This modifier is used to load bits 32-47 of the pc-relative address of +a plt entry, and it also checks that the value does not overflow. +</p> +</dd> +<dt><code>hw0_tls_gd</code></dt> +<dd> +<p>This modifier is used to load bits 0-15 of the offset of the GOT entry +of the symbol’s TLS descriptor, to be used for general-dynamic TLS +accesses. +</p> +</dd> +<dt><code>hw0_last_tls_gd</code></dt> +<dd> +<p>This modifier yields the same value as <code>hw0_tls_gd</code>, but it also +checks that the value does not overflow. +</p> +</dd> +<dt><code>hw1_last_tls_gd</code></dt> +<dd> +<p>This modifier is used to load bits 16-31 of the offset of the GOT +entry of the symbol’s TLS descriptor, to be used for general-dynamic +TLS accesses. It also checks that the value does not overflow. +</p> +</dd> +<dt><code>hw0_tls_ie</code></dt> +<dd> +<p>This modifier is used to load bits 0-15 of the offset of the GOT entry +containing the offset of the symbol’s address from the TCB, to be used +for initial-exec TLS accesses. +</p> +</dd> +<dt><code>hw0_last_tls_ie</code></dt> +<dd> +<p>This modifier yields the same value as <code>hw0_tls_ie</code>, but it also +checks that the value does not overflow. +</p> +</dd> +<dt><code>hw1_last_tls_ie</code></dt> +<dd> +<p>This modifier is used to load bits 16-31 of the offset of the GOT +entry containing the offset of the symbol’s address from the TCB, to +be used for initial-exec TLS accesses. It also checks that the value +does not overflow. +</p> +</dd> +<dt><code>hw0_tls_le</code></dt> +<dd> +<p>This modifier is used to load bits 0-15 of the offset of the symbol’s +address from the TCB, to be used for local-exec TLS accesses. +</p> +</dd> +<dt><code>hw0_last_tls_le</code></dt> +<dd> +<p>This modifier yields the same value as <code>hw0_tls_le</code>, but it also +checks that the value does not overflow. +</p> +</dd> +<dt><code>hw1_last_tls_le</code></dt> +<dd> +<p>This modifier is used to load bits 16-31 of the offset of the symbol’s +address from the TCB, to be used for local-exec TLS accesses. It +also checks that the value does not overflow. +</p> +</dd> +<dt><code>tls_gd_call</code></dt> +<dd> +<p>This modifier is used to tag an instruction as the “call” part of a +calling sequence for a TLS GD reference of its operand. +</p> +</dd> +<dt><code>tls_gd_add</code></dt> +<dd> +<p>This modifier is used to tag an instruction as the “add” part of a +calling sequence for a TLS GD reference of its operand. +</p> +</dd> +<dt><code>tls_ie_load</code></dt> +<dd> +<p>This modifier is used to tag an instruction as the “load” part of a +calling sequence for a TLS IE reference of its operand. +</p> +</dd> +</dl> + +<hr> +<a name="TILE_002dGx-Directives"></a> +<div class="header"> +<p> +Previous: <a href="#TILE_002dGx-Syntax" accesskey="p" rel="previous">TILE-Gx Syntax</a>, Up: <a href="#TILE_002dGx_002dDependent" accesskey="u" rel="up">TILE-Gx-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TILE_002dGx-Directives-1"></a> +<h4 class="subsection">9.47.3 TILE-Gx Directives</h4> +<a name="index-machine-directives_002c-TILE_002dGx"></a> +<a name="index-TILE_002dGx-machine-directives"></a> + +<dl compact="compact"> +<dd> +<a name="index-_002ealign-directive_002c-TILE_002dGx"></a> +</dd> +<dt><code>.align <var>expression</var> [, <var>expression</var>]</code></dt> +<dd><p>This is the generic <var>.align</var> directive. The first argument is the +requested alignment in bytes. +</p> +<a name="index-_002eallow_005fsuspicious_005fbundles-directive_002c-TILE_002dGx"></a> +</dd> +<dt><code>.allow_suspicious_bundles</code></dt> +<dd><p>Turns on error checking for combinations of instructions in a bundle +that probably indicate a programming error. This is on by default. +</p> +</dd> +<dt><code>.no_allow_suspicious_bundles</code></dt> +<dd><p>Turns off error checking for combinations of instructions in a bundle +that probably indicate a programming error. +</p> +<a name="index-_002erequire_005fcanonical_005freg_005fnames-directive_002c-TILE_002dGx"></a> +</dd> +<dt><code>.require_canonical_reg_names</code></dt> +<dd><p>Require that canonical register names be used, and emit a warning if +the numeric names are used. This is on by default. +</p> +</dd> +<dt><code>.no_require_canonical_reg_names</code></dt> +<dd><p>Permit the use of numeric names for registers that have canonical +names. +</p> +</dd> +</dl> + +<hr> +<a name="TILEPro_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#V850_002dDependent" accesskey="n" rel="next">V850-Dependent</a>, Previous: <a href="#TILE_002dGx_002dDependent" accesskey="p" rel="previous">TILE-Gx-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TILEPro-Dependent-Features"></a> +<h3 class="section">9.48 TILEPro Dependent Features</h3> + +<a name="index-TILEPro-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#TILEPro-Options" accesskey="1">TILEPro Options</a>:</td><td> </td><td align="left" valign="top">TILEPro Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILEPro-Syntax" accesskey="2">TILEPro Syntax</a>:</td><td> </td><td align="left" valign="top">TILEPro Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILEPro-Directives" accesskey="3">TILEPro Directives</a>:</td><td> </td><td align="left" valign="top">TILEPro Directives +</td></tr> +</table> + +<hr> +<a name="TILEPro-Options"></a> +<div class="header"> +<p> +Next: <a href="#TILEPro-Syntax" accesskey="n" rel="next">TILEPro Syntax</a>, Up: <a href="#TILEPro_002dDependent" accesskey="u" rel="up">TILEPro-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-27"></a> +<h4 class="subsection">9.48.1 Options</h4> + +<p><code>as</code> has no machine-dependent command-line options for +TILEPro. +</p> +<hr> +<a name="TILEPro-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#TILEPro-Directives" accesskey="n" rel="next">TILEPro Directives</a>, Previous: <a href="#TILEPro-Options" accesskey="p" rel="previous">TILEPro Options</a>, Up: <a href="#TILEPro_002dDependent" accesskey="u" rel="up">TILEPro-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-29"></a> +<h4 class="subsection">9.48.2 Syntax</h4> +<a name="index-TILEPro-syntax"></a> +<a name="index-syntax_002c-TILEPro"></a> + +<p>Block comments are delimited by ‘<samp>/*</samp>’ and ‘<samp>*/</samp>’. End of line +comments may be introduced by ‘<samp>#</samp>’. +</p> +<p>Instructions consist of a leading opcode or macro name followed by +whitespace and an optional comma-separated list of operands: +</p> +<div class="smallexample"> +<pre class="smallexample"><var>opcode</var> [<var>operand</var>, …] +</pre></div> + +<p>Instructions must be separated by a newline or semicolon. +</p> +<p>There are two ways to write code: either write naked instructions, +which the assembler is free to combine into VLIW bundles, or specify +the VLIW bundles explicitly. +</p> +<p>Bundles are specified using curly braces: +</p> +<div class="smallexample"> +<pre class="smallexample">{ <var>add</var> r3,r4,r5 ; <var>add</var> r7,r8,r9 ; <var>lw</var> r10,r11 } +</pre></div> + +<p>A bundle can span multiple lines. If you want to put multiple +instructions on a line, whether in a bundle or not, you need to +separate them with semicolons as in this example. +</p> +<p>A bundle may contain one or more instructions, up to the limit +specified by the ISA (currently three). If fewer instructions are +specified than the hardware supports in a bundle, the assembler +inserts <code>fnop</code> instructions automatically. +</p> +<p>The assembler will prefer to preserve the ordering of instructions +within the bundle, putting the first instruction in a lower-numbered +pipeline than the next one, etc. This fact, combined with the +optional use of explicit <code>fnop</code> or <code>nop</code> instructions, +allows precise control over which pipeline executes each instruction. +</p> +<p>If the instructions cannot be bundled in the listed order, the +assembler will automatically try to find a valid pipeline +assignment. If there is no way to bundle the instructions together, +the assembler reports an error. +</p> +<p>The assembler does not yet auto-bundle (automatically combine multiple +instructions into one bundle), but it reserves the right to do so in +the future. If you want to force an instruction to run by itself, put +it in a bundle explicitly with curly braces and use <code>nop</code> +instructions (not <code>fnop</code>) to fill the remaining pipeline slots in +that bundle. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#TILEPro-Opcodes" accesskey="1">TILEPro Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcode Naming Conventions. +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILEPro-Registers" accesskey="2">TILEPro Registers</a>:</td><td> </td><td align="left" valign="top">Register Naming. +</td></tr> +<tr><td align="left" valign="top">• <a href="#TILEPro-Modifiers" accesskey="3">TILEPro Modifiers</a>:</td><td> </td><td align="left" valign="top">Symbolic Operand Modifiers. +</td></tr> +</table> + +<hr> +<a name="TILEPro-Opcodes"></a> +<div class="header"> +<p> +Next: <a href="#TILEPro-Registers" accesskey="n" rel="next">TILEPro Registers</a>, Up: <a href="#TILEPro-Syntax" accesskey="u" rel="up">TILEPro Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcode-Names-1"></a> +<h4 class="subsubsection">9.48.2.1 Opcode Names</h4> +<a name="index-TILEPro-opcode-names"></a> +<a name="index-opcode-names_002c-TILEPro"></a> + +<p>For a complete list of opcodes and descriptions of their semantics, +see <cite>TILE Processor User Architecture Manual</cite>, available upon +request at www.tilera.com. +</p> +<hr> +<a name="TILEPro-Registers"></a> +<div class="header"> +<p> +Next: <a href="#TILEPro-Modifiers" accesskey="n" rel="next">TILEPro Modifiers</a>, Previous: <a href="#TILEPro-Opcodes" accesskey="p" rel="previous">TILEPro Opcodes</a>, Up: <a href="#TILEPro-Syntax" accesskey="u" rel="up">TILEPro Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-18"></a> +<h4 class="subsubsection">9.48.2.2 Register Names</h4> +<a name="index-TILEPro-register-names"></a> +<a name="index-register-names_002c-TILEPro"></a> + +<p>General-purpose registers are represented by predefined symbols of the +form ‘<samp>r<var>N</var></samp>’, where <var>N</var> represents a number between +<code>0</code> and <code>63</code>. However, the following registers have +canonical names that must be used instead: +</p> +<dl compact="compact"> +<dt><code>r54</code></dt> +<dd><p>sp +</p> +</dd> +<dt><code>r55</code></dt> +<dd><p>lr +</p> +</dd> +<dt><code>r56</code></dt> +<dd><p>sn +</p> +</dd> +<dt><code>r57</code></dt> +<dd><p>idn0 +</p> +</dd> +<dt><code>r58</code></dt> +<dd><p>idn1 +</p> +</dd> +<dt><code>r59</code></dt> +<dd><p>udn0 +</p> +</dd> +<dt><code>r60</code></dt> +<dd><p>udn1 +</p> +</dd> +<dt><code>r61</code></dt> +<dd><p>udn2 +</p> +</dd> +<dt><code>r62</code></dt> +<dd><p>udn3 +</p> +</dd> +<dt><code>r63</code></dt> +<dd><p>zero +</p> +</dd> +</dl> + +<p>The assembler will emit a warning if a numeric name is used instead of +the canonical name. The <code>.no_require_canonical_reg_names</code> +assembler pseudo-op turns off this +warning. <code>.require_canonical_reg_names</code> turns it back on. +</p> +<hr> +<a name="TILEPro-Modifiers"></a> +<div class="header"> +<p> +Previous: <a href="#TILEPro-Registers" accesskey="p" rel="previous">TILEPro Registers</a>, Up: <a href="#TILEPro-Syntax" accesskey="u" rel="up">TILEPro Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Symbolic-Operand-Modifiers-5"></a> +<h4 class="subsubsection">9.48.2.3 Symbolic Operand Modifiers</h4> +<a name="index-TILEPro-modifiers"></a> +<a name="index-symbol-modifiers_002c-TILEPro"></a> + +<p>The assembler supports several modifiers when using symbol addresses +in TILEPro instruction operands. The general syntax is the following: +</p> +<div class="smallexample"> +<pre class="smallexample">modifier(symbol) +</pre></div> + +<p>The following modifiers are supported: +</p> +<dl compact="compact"> +<dt><code>lo16</code></dt> +<dd> +<p>This modifier is used to load the low 16 bits of the symbol’s address, +sign-extended to a 32-bit value (sign-extension allows it to be +range-checked against signed 16 bit immediate operands without +complaint). +</p> +</dd> +<dt><code>hi16</code></dt> +<dd> +<p>This modifier is used to load the high 16 bits of the symbol’s +address, also sign-extended to a 32-bit value. +</p> +</dd> +<dt><code>ha16</code></dt> +<dd> +<p><code>ha16(N)</code> is identical to <code>hi16(N)</code>, except if +<code>lo16(N)</code> is negative it adds one to the <code>hi16(N)</code> +value. This way <code>lo16</code> and <code>ha16</code> can be added to create any +32-bit value using <code>auli</code>. For example, here is how you move an +arbitrary 32-bit address into r3: +</p> +<div class="smallexample"> +<pre class="smallexample">moveli r3, lo16(sym) +auli r3, r3, ha16(sym) +</pre></div> + +</dd> +<dt><code>got</code></dt> +<dd> +<p>This modifier is used to load the offset of the GOT entry +corresponding to the symbol. +</p> +</dd> +<dt><code>got_lo16</code></dt> +<dd> +<p>This modifier is used to load the sign-extended low 16 bits of the +offset of the GOT entry corresponding to the symbol. +</p> +</dd> +<dt><code>got_hi16</code></dt> +<dd> +<p>This modifier is used to load the sign-extended high 16 bits of the +offset of the GOT entry corresponding to the symbol. +</p> +</dd> +<dt><code>got_ha16</code></dt> +<dd> +<p>This modifier is like <code>got_hi16</code>, but it adds one if +<code>got_lo16</code> of the input value is negative. +</p> +</dd> +<dt><code>plt</code></dt> +<dd> +<p>This modifier is used for function symbols. It causes a +<em>procedure linkage table</em>, an array of code stubs, to be created +at the time the shared object is created or linked against, together +with a global offset table entry. The value is a pc-relative offset +to the corresponding stub code in the procedure linkage table. This +arrangement causes the run-time symbol resolver to be called to look +up and set the value of the symbol the first time the function is +called (at latest; depending environment variables). It is only safe +to leave the symbol unresolved this way if all references are function +calls. +</p> +</dd> +<dt><code>tls_gd</code></dt> +<dd> +<p>This modifier is used to load the offset of the GOT entry of the +symbol’s TLS descriptor, to be used for general-dynamic TLS accesses. +</p> +</dd> +<dt><code>tls_gd_lo16</code></dt> +<dd> +<p>This modifier is used to load the sign-extended low 16 bits of the +offset of the GOT entry of the symbol’s TLS descriptor, to be used for +general dynamic TLS accesses. +</p> +</dd> +<dt><code>tls_gd_hi16</code></dt> +<dd> +<p>This modifier is used to load the sign-extended high 16 bits of the +offset of the GOT entry of the symbol’s TLS descriptor, to be used for +general dynamic TLS accesses. +</p> +</dd> +<dt><code>tls_gd_ha16</code></dt> +<dd> +<p>This modifier is like <code>tls_gd_hi16</code>, but it adds one to the value +if <code>tls_gd_lo16</code> of the input value is negative. +</p> +</dd> +<dt><code>tls_ie</code></dt> +<dd> +<p>This modifier is used to load the offset of the GOT entry containing +the offset of the symbol’s address from the TCB, to be used for +initial-exec TLS accesses. +</p> +</dd> +<dt><code>tls_ie_lo16</code></dt> +<dd> +<p>This modifier is used to load the low 16 bits of the offset of the GOT +entry containing the offset of the symbol’s address from the TCB, to +be used for initial-exec TLS accesses. +</p> +</dd> +<dt><code>tls_ie_hi16</code></dt> +<dd> +<p>This modifier is used to load the high 16 bits of the offset of the +GOT entry containing the offset of the symbol’s address from the TCB, +to be used for initial-exec TLS accesses. +</p> +</dd> +<dt><code>tls_ie_ha16</code></dt> +<dd> +<p>This modifier is like <code>tls_ie_hi16</code>, but it adds one to the value +if <code>tls_ie_lo16</code> of the input value is negative. +</p> +</dd> +<dt><code>tls_le</code></dt> +<dd> +<p>This modifier is used to load the offset of the symbol’s address from +the TCB, to be used for local-exec TLS accesses. +</p> +</dd> +<dt><code>tls_le_lo16</code></dt> +<dd> +<p>This modifier is used to load the low 16 bits of the offset of the +symbol’s address from the TCB, to be used for local-exec TLS accesses. +</p> +</dd> +<dt><code>tls_le_hi16</code></dt> +<dd> +<p>This modifier is used to load the high 16 bits of the offset of the +symbol’s address from the TCB, to be used for local-exec TLS accesses. +</p> +</dd> +<dt><code>tls_le_ha16</code></dt> +<dd> +<p>This modifier is like <code>tls_le_hi16</code>, but it adds one to the value +if <code>tls_le_lo16</code> of the input value is negative. +</p> +</dd> +<dt><code>tls_gd_call</code></dt> +<dd> +<p>This modifier is used to tag an instruction as the “call” part of a +calling sequence for a TLS GD reference of its operand. +</p> +</dd> +<dt><code>tls_gd_add</code></dt> +<dd> +<p>This modifier is used to tag an instruction as the “add” part of a +calling sequence for a TLS GD reference of its operand. +</p> +</dd> +<dt><code>tls_ie_load</code></dt> +<dd> +<p>This modifier is used to tag an instruction as the “load” part of a +calling sequence for a TLS IE reference of its operand. +</p> +</dd> +</dl> + +<hr> +<a name="TILEPro-Directives"></a> +<div class="header"> +<p> +Previous: <a href="#TILEPro-Syntax" accesskey="p" rel="previous">TILEPro Syntax</a>, Up: <a href="#TILEPro_002dDependent" accesskey="u" rel="up">TILEPro-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="TILEPro-Directives-1"></a> +<h4 class="subsection">9.48.3 TILEPro Directives</h4> +<a name="index-machine-directives_002c-TILEPro"></a> +<a name="index-TILEPro-machine-directives"></a> + +<dl compact="compact"> +<dd> +<a name="index-_002ealign-directive_002c-TILEPro"></a> +</dd> +<dt><code>.align <var>expression</var> [, <var>expression</var>]</code></dt> +<dd><p>This is the generic <var>.align</var> directive. The first argument is the +requested alignment in bytes. +</p> +<a name="index-_002eallow_005fsuspicious_005fbundles-directive_002c-TILEPro"></a> +</dd> +<dt><code>.allow_suspicious_bundles</code></dt> +<dd><p>Turns on error checking for combinations of instructions in a bundle +that probably indicate a programming error. This is on by default. +</p> +</dd> +<dt><code>.no_allow_suspicious_bundles</code></dt> +<dd><p>Turns off error checking for combinations of instructions in a bundle +that probably indicate a programming error. +</p> +<a name="index-_002erequire_005fcanonical_005freg_005fnames-directive_002c-TILEPro"></a> +</dd> +<dt><code>.require_canonical_reg_names</code></dt> +<dd><p>Require that canonical register names be used, and emit a warning if +the numeric names are used. This is on by default. +</p> +</dd> +<dt><code>.no_require_canonical_reg_names</code></dt> +<dd><p>Permit the use of numeric names for registers that have canonical +names. +</p> +</dd> +</dl> + + + +<hr> +<a name="V850_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Vax_002dDependent" accesskey="n" rel="next">Vax-Dependent</a>, Previous: <a href="#TILEPro_002dDependent" accesskey="p" rel="previous">TILEPro-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="v850-Dependent-Features"></a> +<h3 class="section">9.49 v850 Dependent Features</h3> + +<a name="index-V850-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#V850-Options" accesskey="1">V850 Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#V850-Syntax" accesskey="2">V850 Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#V850-Floating-Point" accesskey="3">V850 Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#V850-Directives" accesskey="4">V850 Directives</a>:</td><td> </td><td align="left" valign="top">V850 Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#V850-Opcodes" accesskey="5">V850 Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="V850-Options"></a> +<div class="header"> +<p> +Next: <a href="#V850-Syntax" accesskey="n" rel="next">V850 Syntax</a>, Up: <a href="#V850_002dDependent" accesskey="u" rel="up">V850-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-28"></a> +<h4 class="subsection">9.49.1 Options</h4> +<a name="index-V850-options-_0028none_0029"></a> +<a name="index-options-for-V850-_0028none_0029"></a> +<p><code>as</code> supports the following additional command-line options +for the V850 processor family: +</p> +<a name="index-command_002dline-options_002c-V850"></a> +<a name="index-V850-command_002dline-options"></a> +<dl compact="compact"> +<dd> +<a name="index-_002dwsigned_005foverflow-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-wsigned_overflow</code></dt> +<dd><p>Causes warnings to be produced when signed immediate values overflow the +space available for then within their opcodes. By default this option +is disabled as it is possible to receive spurious warnings due to using +exact bit patterns as immediate constants. +</p> +<a name="index-_002dwunsigned_005foverflow-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-wunsigned_overflow</code></dt> +<dd><p>Causes warnings to be produced when unsigned immediate values overflow +the space available for then within their opcodes. By default this +option is disabled as it is possible to receive spurious warnings due to +using exact bit patterns as immediate constants. +</p> +<a name="index-_002dmv850-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mv850</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002dmv850e-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mv850e</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002dmv850e1-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mv850e1</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E1 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002dmv850any-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mv850any</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850 processor but support instructions that are specific to the +extended variants of the process. This allows the production of +binaries that contain target specific code, but which are also intended +to be used in a generic fashion. For example libgcc.a contains generic +routines used by the code produced by GCC for all versions of the v850 +architecture, together with support routines only used by the V850E +architecture. +</p> +<a name="index-_002dmv850e2-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mv850e2</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E2 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002dmv850e2v3-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mv850e2v3</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E2V3 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002dmv850e2v4-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mv850e2v4</code></dt> +<dd><p>This is an alias for <samp>-mv850e3v5</samp>. +</p> +<a name="index-_002dmv850e3v5-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mv850e3v5</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E3V5 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002dmrelax-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mrelax</code></dt> +<dd><p>Enables relaxation. This allows the .longcall and .longjump pseudo +ops to be used in the assembler source code. These ops label sections +of code which are either a long function call or a long branch. The +assembler will then flag these sections of code and the linker will +attempt to relax them. +</p> +<a name="index-_002dmgcc_002dabi-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mgcc-abi</code></dt> +<dd><p>Marks the generated object file as supporting the old GCC ABI. +</p> +<a name="index-_002dmrh850_002dabi-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mrh850-abi</code></dt> +<dd><p>Marks the generated object file as supporting the RH850 ABI. This is +the default. +</p> +<a name="index-_002dm8byte_002dalign-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-m8byte-align</code></dt> +<dd><p>Marks the generated object file as supporting a maximum 64-bits of +alignment for variables defined in the source code. +</p> +<a name="index-_002dm4byte_002dalign-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-m4byte-align</code></dt> +<dd><p>Marks the generated object file as supporting a maximum 32-bits of +alignment for variables defined in the source code. This is the +default. +</p> +<a name="index-_002dmsoft_002dfloat-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-msoft-float</code></dt> +<dd><p>Marks the generated object file as not using any floating point +instructions - and hence can be linked with other V850 binaries +that do or do not use floating point. This is the default for +binaries for architectures earlier than the <code>e2v3</code>. +</p> +<a name="index-_002dmhard_002dfloat-command_002dline-option_002c-V850"></a> +</dd> +<dt><code>-mhard-float</code></dt> +<dd><p>Marks the generated object file as one that uses floating point +instructions - and hence can only be linked with other V850 binaries +that use the same kind of floating point instructions, or with +binaries that do not use floating point at all. This is the default +for binaries the <code>e2v3</code> and later architectures. +</p> +</dd> +</dl> + +<hr> +<a name="V850-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#V850-Floating-Point" accesskey="n" rel="next">V850 Floating Point</a>, Previous: <a href="#V850-Options" accesskey="p" rel="previous">V850 Options</a>, Up: <a href="#V850_002dDependent" accesskey="u" rel="up">V850-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-30"></a> +<h4 class="subsection">9.49.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#V850_002dChars" accesskey="1">V850-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#V850_002dRegs" accesskey="2">V850-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +</table> + +<hr> +<a name="V850_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#V850_002dRegs" accesskey="n" rel="next">V850-Regs</a>, Up: <a href="#V850-Syntax" accesskey="u" rel="up">V850 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-37"></a> +<h4 class="subsubsection">9.49.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-V850"></a> +<a name="index-V850-line-comment-character"></a> +<p>‘<samp>#</samp>’ is the line comment character. If a ‘<samp>#</samp>’ appears as the +first character of a line, the whole line is treated as a comment, but +in this case the line can also be a logical line number directive +(see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +<p>Two dashes (‘<samp>--</samp>’) can also be used to start a line comment. +</p> +<a name="index-line-separator_002c-V850"></a> +<a name="index-statement-separator_002c-V850"></a> +<a name="index-V850-line-separator"></a> + +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> +<hr> +<a name="V850_002dRegs"></a> +<div class="header"> +<p> +Previous: <a href="#V850_002dChars" accesskey="p" rel="previous">V850-Chars</a>, Up: <a href="#V850-Syntax" accesskey="u" rel="up">V850 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-19"></a> +<h4 class="subsubsection">9.49.2.2 Register Names</h4> + +<a name="index-V850-register-names"></a> +<a name="index-register-names_002c-V850"></a> +<p><code>as</code> supports the following names for registers: +</p><dl compact="compact"> +<dd><a name="index-zero-register_002c-V850"></a> +</dd> +<dt><code>general register 0</code></dt> +<dd><p>r0, zero +</p></dd> +<dt><code>general register 1</code></dt> +<dd><p>r1 +</p></dd> +<dt><code>general register 2</code></dt> +<dd><p>r2, hp +<a name="index-sp-register_002c-V850"></a> +</p></dd> +<dt><code>general register 3</code></dt> +<dd><p>r3, sp +<a name="index-gp-register_002c-V850"></a> +</p></dd> +<dt><code>general register 4</code></dt> +<dd><p>r4, gp +<a name="index-tp-register_002c-V850"></a> +</p></dd> +<dt><code>general register 5</code></dt> +<dd><p>r5, tp +</p></dd> +<dt><code>general register 6</code></dt> +<dd><p>r6 +</p></dd> +<dt><code>general register 7</code></dt> +<dd><p>r7 +</p></dd> +<dt><code>general register 8</code></dt> +<dd><p>r8 +</p></dd> +<dt><code>general register 9</code></dt> +<dd><p>r9 +</p></dd> +<dt><code>general register 10</code></dt> +<dd><p>r10 +</p></dd> +<dt><code>general register 11</code></dt> +<dd><p>r11 +</p></dd> +<dt><code>general register 12</code></dt> +<dd><p>r12 +</p></dd> +<dt><code>general register 13</code></dt> +<dd><p>r13 +</p></dd> +<dt><code>general register 14</code></dt> +<dd><p>r14 +</p></dd> +<dt><code>general register 15</code></dt> +<dd><p>r15 +</p></dd> +<dt><code>general register 16</code></dt> +<dd><p>r16 +</p></dd> +<dt><code>general register 17</code></dt> +<dd><p>r17 +</p></dd> +<dt><code>general register 18</code></dt> +<dd><p>r18 +</p></dd> +<dt><code>general register 19</code></dt> +<dd><p>r19 +</p></dd> +<dt><code>general register 20</code></dt> +<dd><p>r20 +</p></dd> +<dt><code>general register 21</code></dt> +<dd><p>r21 +</p></dd> +<dt><code>general register 22</code></dt> +<dd><p>r22 +</p></dd> +<dt><code>general register 23</code></dt> +<dd><p>r23 +</p></dd> +<dt><code>general register 24</code></dt> +<dd><p>r24 +</p></dd> +<dt><code>general register 25</code></dt> +<dd><p>r25 +</p></dd> +<dt><code>general register 26</code></dt> +<dd><p>r26 +</p></dd> +<dt><code>general register 27</code></dt> +<dd><p>r27 +</p></dd> +<dt><code>general register 28</code></dt> +<dd><p>r28 +</p></dd> +<dt><code>general register 29</code></dt> +<dd><p>r29 +<a name="index-ep-register_002c-V850"></a> +</p></dd> +<dt><code>general register 30</code></dt> +<dd><p>r30, ep +<a name="index-lp-register_002c-V850"></a> +</p></dd> +<dt><code>general register 31</code></dt> +<dd><p>r31, lp +<a name="index-eipc-register_002c-V850"></a> +</p></dd> +<dt><code>system register 0</code></dt> +<dd><p>eipc +<a name="index-eipsw-register_002c-V850"></a> +</p></dd> +<dt><code>system register 1</code></dt> +<dd><p>eipsw +<a name="index-fepc-register_002c-V850"></a> +</p></dd> +<dt><code>system register 2</code></dt> +<dd><p>fepc +<a name="index-fepsw-register_002c-V850"></a> +</p></dd> +<dt><code>system register 3</code></dt> +<dd><p>fepsw +<a name="index-ecr-register_002c-V850"></a> +</p></dd> +<dt><code>system register 4</code></dt> +<dd><p>ecr +<a name="index-psw-register_002c-V850"></a> +</p></dd> +<dt><code>system register 5</code></dt> +<dd><p>psw +<a name="index-ctpc-register_002c-V850"></a> +</p></dd> +<dt><code>system register 16</code></dt> +<dd><p>ctpc +<a name="index-ctpsw-register_002c-V850"></a> +</p></dd> +<dt><code>system register 17</code></dt> +<dd><p>ctpsw +<a name="index-dbpc-register_002c-V850"></a> +</p></dd> +<dt><code>system register 18</code></dt> +<dd><p>dbpc +<a name="index-dbpsw-register_002c-V850"></a> +</p></dd> +<dt><code>system register 19</code></dt> +<dd><p>dbpsw +<a name="index-ctbp-register_002c-V850"></a> +</p></dd> +<dt><code>system register 20</code></dt> +<dd><p>ctbp +</p></dd> +</dl> + +<hr> +<a name="V850-Floating-Point"></a> +<div class="header"> +<p> +Next: <a href="#V850-Directives" accesskey="n" rel="next">V850 Directives</a>, Previous: <a href="#V850-Syntax" accesskey="p" rel="previous">V850 Syntax</a>, Up: <a href="#V850_002dDependent" accesskey="u" rel="up">V850-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-16"></a> +<h4 class="subsection">9.49.3 Floating Point</h4> + +<a name="index-floating-point_002c-V850-_0028IEEE_0029"></a> +<a name="index-V850-floating-point-_0028IEEE_0029"></a> +<p>The V850 family uses <small>IEEE</small> floating-point numbers. +</p> +<hr> +<a name="V850-Directives"></a> +<div class="header"> +<p> +Next: <a href="#V850-Opcodes" accesskey="n" rel="next">V850 Opcodes</a>, Previous: <a href="#V850-Floating-Point" accesskey="p" rel="previous">V850 Floating Point</a>, Up: <a href="#V850_002dDependent" accesskey="u" rel="up">V850-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="V850-Machine-Directives"></a> +<h4 class="subsection">9.49.4 V850 Machine Directives</h4> + +<a name="index-machine-directives_002c-V850"></a> +<a name="index-V850-machine-directives"></a> +<dl compact="compact"> +<dd><a name="index-offset-directive_002c-V850"></a> +</dd> +<dt><code>.offset <var><expression></var></code></dt> +<dd><p>Moves the offset into the current section to the specified amount. +</p> +<a name="index-section-directive_002c-V850"></a> +</dd> +<dt><code>.section "name", <type></code></dt> +<dd><p>This is an extension to the standard .section directive. It sets the +current section to be <type> and creates an alias for this section +called "name". +</p> +<a name="index-_002ev850-directive_002c-V850"></a> +</dd> +<dt><code>.v850</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002ev850e-directive_002c-V850"></a> +</dd> +<dt><code>.v850e</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002ev850e1-directive_002c-V850"></a> +</dd> +<dt><code>.v850e1</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E1 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002ev850e2-directive_002c-V850"></a> +</dd> +<dt><code>.v850e2</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E2 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002ev850e2v3-directive_002c-V850"></a> +</dd> +<dt><code>.v850e2v3</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E2V3 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002ev850e2v4-directive_002c-V850"></a> +</dd> +<dt><code>.v850e2v4</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E3V5 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +<a name="index-_002ev850e3v5-directive_002c-V850"></a> +</dd> +<dt><code>.v850e3v5</code></dt> +<dd><p>Specifies that the assembled code should be marked as being targeted at +the V850E3V5 processor. This allows the linker to detect attempts to link +such code with code assembled for other processors. +</p> +</dd> +</dl> + +<hr> +<a name="V850-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#V850-Directives" accesskey="p" rel="previous">V850 Directives</a>, Up: <a href="#V850_002dDependent" accesskey="u" rel="up">V850-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-19"></a> +<h4 class="subsection">9.49.5 Opcodes</h4> + +<a name="index-V850-opcodes"></a> +<a name="index-opcodes-for-V850"></a> +<p><code>as</code> implements all the standard V850 opcodes. +</p> +<p><code>as</code> also implements the following pseudo ops: +</p> +<dl compact="compact"> +<dd> +<a name="index-hi0-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>hi0()</code></dt> +<dd><p>Computes the higher 16 bits of the given expression and stores it into +the immediate operand field of the given instruction. For example: +</p> +<p>‘<samp>mulhi hi0(here - there), r5, r6</samp>’ +</p> +<p>computes the difference between the address of labels ’here’ and +’there’, takes the upper 16 bits of this difference, shifts it down 16 +bits and then multiplies it by the lower 16 bits in register 5, putting +the result into register 6. +</p> +<a name="index-lo-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>lo()</code></dt> +<dd><p>Computes the lower 16 bits of the given expression and stores it into +the immediate operand field of the given instruction. For example: +</p> +<p>‘<samp>addi lo(here - there), r5, r6</samp>’ +</p> +<p>computes the difference between the address of labels ’here’ and +’there’, takes the lower 16 bits of this difference and adds it to +register 5, putting the result into register 6. +</p> +<a name="index-hi-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>hi()</code></dt> +<dd><p>Computes the higher 16 bits of the given expression and then adds the +value of the most significant bit of the lower 16 bits of the expression +and stores the result into the immediate operand field of the given +instruction. For example the following code can be used to compute the +address of the label ’here’ and store it into register 6: +</p> +<p>‘<samp>movhi hi(here), r0, r6</samp>’ + ‘<samp>movea lo(here), r6, r6</samp>’ +</p> +<p>The reason for this special behaviour is that movea performs a sign +extension on its immediate operand. So for example if the address of +’here’ was 0xFFFFFFFF then without the special behaviour of the hi() +pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the +movea instruction would takes its immediate operand, 0xFFFF, sign extend +it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF +which is wrong (the fifth nibble is E). With the hi() pseudo op adding +in the top bit of the lo() pseudo op, the movhi instruction actually +stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction +stores 0xFFFFFFFF into r6 - the right value. +</p> +<a name="index-hilo-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>hilo()</code></dt> +<dd><p>Computes the 32 bit value of the given expression and stores it into +the immediate operand field of the given instruction (which must be a +mov instruction). For example: +</p> +<p>‘<samp>mov hilo(here), r6</samp>’ +</p> +<p>computes the absolute address of label ’here’ and puts the result into +register 6. +</p> +<a name="index-sdaoff-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>sdaoff()</code></dt> +<dd><p>Computes the offset of the named variable from the start of the Small +Data Area (whose address is held in register 4, the GP register) and +stores the result as a 16 bit signed value in the immediate operand +field of the given instruction. For example: +</p> +<p>‘<samp>ld.w sdaoff(_a_variable)[gp],r6</samp>’ +</p> +<p>loads the contents of the location pointed to by the label ’_a_variable’ +into register 6, provided that the label is located somewhere within +/- +32K of the address held in the GP register. [Note the linker assumes +that the GP register contains a fixed address set to the address of the +label called ’__gp’. This can either be set up automatically by the +linker, or specifically set by using the ‘<samp>--defsym __gp=<value></samp>’ +command-line option]. +</p> +<a name="index-tdaoff-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>tdaoff()</code></dt> +<dd><p>Computes the offset of the named variable from the start of the Tiny +Data Area (whose address is held in register 30, the EP register) and +stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate +operand field of the given instruction. For example: +</p> +<p>‘<samp>sld.w tdaoff(_a_variable)[ep],r6</samp>’ +</p> +<p>loads the contents of the location pointed to by the label ’_a_variable’ +into register 6, provided that the label is located somewhere within +256 +bytes of the address held in the EP register. [Note the linker assumes +that the EP register contains a fixed address set to the address of the +label called ’__ep’. This can either be set up automatically by the +linker, or specifically set by using the ‘<samp>--defsym __ep=<value></samp>’ +command-line option]. +</p> +<a name="index-zdaoff-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>zdaoff()</code></dt> +<dd><p>Computes the offset of the named variable from address 0 and stores the +result as a 16 bit signed value in the immediate operand field of the +given instruction. For example: +</p> +<p>‘<samp>movea zdaoff(_a_variable),zero,r6</samp>’ +</p> +<p>puts the address of the label ’_a_variable’ into register 6, assuming +that the label is somewhere within the first 32K of memory. (Strictly +speaking it also possible to access the last 32K of memory as well, as +the offsets are signed). +</p> +<a name="index-ctoff-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>ctoff()</code></dt> +<dd><p>Computes the offset of the named variable from the start of the Call +Table Area (whose address is held in system register 20, the CTBP +register) and stores the result a 6 or 16 bit unsigned value in the +immediate field of then given instruction or piece of data. For +example: +</p> +<p>‘<samp>callt ctoff(table_func1)</samp>’ +</p> +<p>will put the call the function whose address is held in the call table +at the location labeled ’table_func1’. +</p> +<a name="index-longcall-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>.longcall <code>name</code></code></dt> +<dd><p>Indicates that the following sequence of instructions is a long call +to function <code>name</code>. The linker will attempt to shorten this call +sequence if <code>name</code> is within a 22bit offset of the call. Only +valid if the <code>-mrelax</code> command-line switch has been enabled. +</p> +<a name="index-longjump-pseudo_002dop_002c-V850"></a> +</dd> +<dt><code>.longjump <code>name</code></code></dt> +<dd><p>Indicates that the following sequence of instructions is a long jump +to label <code>name</code>. The linker will attempt to shorten this code +sequence if <code>name</code> is within a 22bit offset of the jump. Only +valid if the <code>-mrelax</code> command-line switch has been enabled. +</p> +</dd> +</dl> + + +<p>For information on the V850 instruction set, see <cite>V850 +Family 32-/16-Bit single-Chip Microcontroller Architecture Manual</cite> from NEC. +Ltd. +</p> +<hr> +<a name="Vax_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Visium_002dDependent" accesskey="n" rel="next">Visium-Dependent</a>, Previous: <a href="#V850_002dDependent" accesskey="p" rel="previous">V850-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="VAX-Dependent-Features"></a> +<h3 class="section">9.50 VAX Dependent Features</h3> +<a name="index-VAX-support"></a> + + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#VAX_002dOpts" accesskey="1">VAX-Opts</a>:</td><td> </td><td align="left" valign="top">VAX Command-Line Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#VAX_002dfloat" accesskey="2">VAX-float</a>:</td><td> </td><td align="left" valign="top">VAX Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#VAX_002ddirectives" accesskey="3">VAX-directives</a>:</td><td> </td><td align="left" valign="top">Vax Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#VAX_002dopcodes" accesskey="4">VAX-opcodes</a>:</td><td> </td><td align="left" valign="top">VAX Opcodes +</td></tr> +<tr><td align="left" valign="top">• <a href="#VAX_002dbranch" accesskey="5">VAX-branch</a>:</td><td> </td><td align="left" valign="top">VAX Branch Improvement +</td></tr> +<tr><td align="left" valign="top">• <a href="#VAX_002doperands" accesskey="6">VAX-operands</a>:</td><td> </td><td align="left" valign="top">VAX Operands +</td></tr> +<tr><td align="left" valign="top">• <a href="#VAX_002dno" accesskey="7">VAX-no</a>:</td><td> </td><td align="left" valign="top">Not Supported on VAX +</td></tr> +<tr><td align="left" valign="top">• <a href="#VAX_002dSyntax" accesskey="8">VAX-Syntax</a>:</td><td> </td><td align="left" valign="top">VAX Syntax +</td></tr> +</table> + + +<hr> +<a name="VAX_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#VAX_002dfloat" accesskey="n" rel="next">VAX-float</a>, Up: <a href="#Vax_002dDependent" accesskey="u" rel="up">Vax-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="VAX-Command_002dLine-Options"></a> +<h4 class="subsection">9.50.1 VAX Command-Line Options</h4> + +<a name="index-command_002dline-options-ignored_002c-VAX"></a> +<a name="index-VAX-command_002dline-options-ignored"></a> +<p>The Vax version of <code>as</code> accepts any of the following options, +gives a warning message that the option was ignored and proceeds. +These options are for compatibility with scripts designed for other +people’s assemblers. +</p> +<dl compact="compact"> +<dd><a name="index-_002dD_002c-ignored-on-VAX"></a> +<a name="index-_002dS_002c-ignored-on-VAX"></a> +<a name="index-_002dT_002c-ignored-on-VAX"></a> +</dd> +<dt><code><code>-D</code> (Debug)</code></dt> +<dt><code><code>-S</code> (Symbol Table)</code></dt> +<dt><code><code>-T</code> (Token Trace)</code></dt> +<dd><p>These are obsolete options used to debug old assemblers. +</p> +<a name="index-_002dd_002c-VAX-option"></a> +</dd> +<dt><code><code>-d</code> (Displacement size for JUMPs)</code></dt> +<dd><p>This option expects a number following the ‘<samp>-d</samp>’. Like options +that expect filenames, the number may immediately follow the +‘<samp>-d</samp>’ (old standard) or constitute the whole of the command-line +argument that follows ‘<samp>-d</samp>’ (<small>GNU</small> standard). +</p> +<a name="index-_002dV_002c-redundant-on-VAX"></a> +</dd> +<dt><code><code>-V</code> (Virtualize Interpass Temporary File)</code></dt> +<dd><p>Some other assemblers use a temporary file. This option +commanded them to keep the information in active memory rather +than in a disk file. <code>as</code> always does this, so this +option is redundant. +</p> +<a name="index-_002dJ_002c-ignored-on-VAX"></a> +</dd> +<dt><code><code>-J</code> (JUMPify Longer Branches)</code></dt> +<dd><p>Many 32-bit computers permit a variety of branch instructions +to do the same job. Some of these instructions are short (and +fast) but have a limited range; others are long (and slow) but +can branch anywhere in virtual memory. Often there are 3 +flavors of branch: short, medium and long. Some other +assemblers would emit short and medium branches, unless told by +this option to emit short and long branches. +</p> +<a name="index-_002dt_002c-ignored-on-VAX"></a> +</dd> +<dt><code><code>-t</code> (Temporary File Directory)</code></dt> +<dd><p>Some other assemblers may use a temporary file, and this option +takes a filename being the directory to site the temporary +file. Since <code>as</code> does not use a temporary disk file, this +option makes no difference. ‘<samp>-t</samp>’ needs exactly one +filename. +</p></dd> +</dl> + +<a name="index-VMS-_0028VAX_0029-options"></a> +<a name="index-options-for-VAX_002fVMS"></a> +<a name="index-VAX_002fVMS-options"></a> +<a name="index-Vax_002d11-C-compatibility"></a> +<a name="index-symbols-with-uppercase_002c-VAX_002fVMS"></a> +<p>The Vax version of the assembler accepts additional options when +compiled for VMS: +</p> +<dl compact="compact"> +<dd><a name="index-_002dh-option_002c-VAX_002fVMS"></a> +</dd> +<dt>‘<samp>-h <var>n</var></samp>’</dt> +<dd><p>External symbol or section (used for global variables) names are not +case sensitive on VAX/VMS and always mapped to upper case. This is +contrary to the C language definition which explicitly distinguishes +upper and lower case. To implement a standard conforming C compiler, +names must be changed (mapped) to preserve the case information. The +default mapping is to convert all lower case characters to uppercase and +adding an underscore followed by a 6 digit hex value, representing a 24 +digit binary value. The one digits in the binary value represent which +characters are uppercase in the original symbol name. +</p> +<p>The ‘<samp>-h <var>n</var></samp>’ option determines how we map names. This takes +several values. No ‘<samp>-h</samp>’ switch at all allows case hacking as +described above. A value of zero (‘<samp>-h0</samp>’) implies names should be +upper case, and inhibits the case hack. A value of 2 (‘<samp>-h2</samp>’) +implies names should be all lower case, with no case hack. A value of 3 +(‘<samp>-h3</samp>’) implies that case should be preserved. The value 1 is +unused. The <code>-H</code> option directs <code>as</code> to display +every mapped symbol during assembly. +</p> +<p>Symbols whose names include a dollar sign ‘<samp>$</samp>’ are exceptions to the +general name mapping. These symbols are normally only used to reference +VMS library names. Such symbols are always mapped to upper case. +</p> +<a name="index-_002d_002b-option_002c-VAX_002fVMS"></a> +</dd> +<dt>‘<samp>-+</samp>’</dt> +<dd><p>The ‘<samp>-+</samp>’ option causes <code>as</code> to truncate any symbol +name larger than 31 characters. The ‘<samp>-+</samp>’ option also prevents some +code following the ‘<samp>_main</samp>’ symbol normally added to make the object +file compatible with Vax-11 "C". +</p> +<a name="index-_002d1-option_002c-VAX_002fVMS"></a> +</dd> +<dt>‘<samp>-1</samp>’</dt> +<dd><p>This option is ignored for backward compatibility with <code>as</code> +version 1.x. +</p> +<a name="index-_002dH-option_002c-VAX_002fVMS"></a> +</dd> +<dt>‘<samp>-H</samp>’</dt> +<dd><p>The ‘<samp>-H</samp>’ option causes <code>as</code> to print every symbol +which was changed by case mapping. +</p></dd> +</dl> + +<hr> +<a name="VAX_002dfloat"></a> +<div class="header"> +<p> +Next: <a href="#VAX_002ddirectives" accesskey="n" rel="next">VAX-directives</a>, Previous: <a href="#VAX_002dOpts" accesskey="p" rel="previous">VAX-Opts</a>, Up: <a href="#Vax_002dDependent" accesskey="u" rel="up">Vax-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="VAX-Floating-Point"></a> +<h4 class="subsection">9.50.2 VAX Floating Point</h4> + +<a name="index-VAX-floating-point"></a> +<a name="index-floating-point_002c-VAX"></a> +<p>Conversion of flonums to floating point is correct, and +compatible with previous assemblers. Rounding is +towards zero if the remainder is exactly half the least significant bit. +</p> +<p><code>D</code>, <code>F</code>, <code>G</code> and <code>H</code> floating point formats +are understood. +</p> +<p>Immediate floating literals (<em>e.g.</em> ‘<samp>S`$6.9</samp>’) +are rendered correctly. Again, rounding is towards zero in the +boundary case. +</p> +<a name="index-float-directive_002c-VAX"></a> +<a name="index-double-directive_002c-VAX"></a> +<p>The <code>.float</code> directive produces <code>f</code> format numbers. +The <code>.double</code> directive produces <code>d</code> format numbers. +</p> +<hr> +<a name="VAX_002ddirectives"></a> +<div class="header"> +<p> +Next: <a href="#VAX_002dopcodes" accesskey="n" rel="next">VAX-opcodes</a>, Previous: <a href="#VAX_002dfloat" accesskey="p" rel="previous">VAX-float</a>, Up: <a href="#Vax_002dDependent" accesskey="u" rel="up">Vax-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Vax-Machine-Directives"></a> +<h4 class="subsection">9.50.3 Vax Machine Directives</h4> + +<a name="index-machine-directives_002c-VAX"></a> +<a name="index-VAX-machine-directives"></a> +<p>The Vax version of the assembler supports four directives for +generating Vax floating point constants. They are described in the +table below. +</p> +<a name="index-wide-floating-point-directives_002c-VAX"></a> +<dl compact="compact"> +<dd><a name="index-dfloat-directive_002c-VAX"></a> +</dd> +<dt><code>.dfloat</code></dt> +<dd><p>This expects zero or more flonums, separated by commas, and +assembles Vax <code>d</code> format 64-bit floating point constants. +</p> +<a name="index-ffloat-directive_002c-VAX"></a> +</dd> +<dt><code>.ffloat</code></dt> +<dd><p>This expects zero or more flonums, separated by commas, and +assembles Vax <code>f</code> format 32-bit floating point constants. +</p> +<a name="index-gfloat-directive_002c-VAX"></a> +</dd> +<dt><code>.gfloat</code></dt> +<dd><p>This expects zero or more flonums, separated by commas, and +assembles Vax <code>g</code> format 64-bit floating point constants. +</p> +<a name="index-hfloat-directive_002c-VAX"></a> +</dd> +<dt><code>.hfloat</code></dt> +<dd><p>This expects zero or more flonums, separated by commas, and +assembles Vax <code>h</code> format 128-bit floating point constants. +</p> +</dd> +</dl> + +<hr> +<a name="VAX_002dopcodes"></a> +<div class="header"> +<p> +Next: <a href="#VAX_002dbranch" accesskey="n" rel="next">VAX-branch</a>, Previous: <a href="#VAX_002ddirectives" accesskey="p" rel="previous">VAX-directives</a>, Up: <a href="#Vax_002dDependent" accesskey="u" rel="up">Vax-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="VAX-Opcodes"></a> +<h4 class="subsection">9.50.4 VAX Opcodes</h4> + +<a name="index-VAX-opcode-mnemonics"></a> +<a name="index-opcode-mnemonics_002c-VAX"></a> +<a name="index-mnemonics-for-opcodes_002c-VAX"></a> +<p>All DEC mnemonics are supported. Beware that <code>case…</code> +instructions have exactly 3 operands. The dispatch table that +follows the <code>case…</code> instruction should be made with +<code>.word</code> statements. This is compatible with all unix +assemblers we know of. +</p> +<hr> +<a name="VAX_002dbranch"></a> +<div class="header"> +<p> +Next: <a href="#VAX_002doperands" accesskey="n" rel="next">VAX-operands</a>, Previous: <a href="#VAX_002dopcodes" accesskey="p" rel="previous">VAX-opcodes</a>, Up: <a href="#Vax_002dDependent" accesskey="u" rel="up">Vax-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="VAX-Branch-Improvement"></a> +<h4 class="subsection">9.50.5 VAX Branch Improvement</h4> + +<a name="index-VAX-branch-improvement"></a> +<a name="index-branch-improvement_002c-VAX"></a> +<a name="index-pseudo_002dops-for-branch_002c-VAX"></a> +<p>Certain pseudo opcodes are permitted. They are for branch +instructions. They expand to the shortest branch instruction that +reaches the target. Generally these mnemonics are made by +substituting ‘<samp>j</samp>’ for ‘<samp>b</samp>’ at the start of a DEC mnemonic. +This feature is included both for compatibility and to help +compilers. If you do not need this feature, avoid these +opcodes. Here are the mnemonics, and the code they can expand into. +</p> +<dl compact="compact"> +<dt><code>jbsb</code></dt> +<dd><p>‘<samp>Jsb</samp>’ is already an instruction mnemonic, so we chose ‘<samp>jbsb</samp>’. +</p><dl compact="compact"> +<dt>(byte displacement)</dt> +<dd><p><kbd>bsbb …</kbd> +</p></dd> +<dt>(word displacement)</dt> +<dd><p><kbd>bsbw …</kbd> +</p></dd> +<dt>(long displacement)</dt> +<dd><p><kbd>jsb …</kbd> +</p></dd> +</dl> +</dd> +<dt><code>jbr</code></dt> +<dt><code>jr</code></dt> +<dd><p>Unconditional branch. +</p><dl compact="compact"> +<dt>(byte displacement)</dt> +<dd><p><kbd>brb …</kbd> +</p></dd> +<dt>(word displacement)</dt> +<dd><p><kbd>brw …</kbd> +</p></dd> +<dt>(long displacement)</dt> +<dd><p><kbd>jmp …</kbd> +</p></dd> +</dl> +</dd> +<dt><code>j<var>COND</var></code></dt> +<dd><p><var>COND</var> may be any one of the conditional branches +<code>neq</code>, <code>nequ</code>, <code>eql</code>, <code>eqlu</code>, <code>gtr</code>, +<code>geq</code>, <code>lss</code>, <code>gtru</code>, <code>lequ</code>, <code>vc</code>, <code>vs</code>, +<code>gequ</code>, <code>cc</code>, <code>lssu</code>, <code>cs</code>. +<var>COND</var> may also be one of the bit tests +<code>bs</code>, <code>bc</code>, <code>bss</code>, <code>bcs</code>, <code>bsc</code>, <code>bcc</code>, +<code>bssi</code>, <code>bcci</code>, <code>lbs</code>, <code>lbc</code>. +<var>NOTCOND</var> is the opposite condition to <var>COND</var>. +</p><dl compact="compact"> +<dt>(byte displacement)</dt> +<dd><p><kbd>b<var>COND</var> …</kbd> +</p></dd> +<dt>(word displacement)</dt> +<dd><p><kbd>b<var>NOTCOND</var> foo ; brw … ; foo:</kbd> +</p></dd> +<dt>(long displacement)</dt> +<dd><p><kbd>b<var>NOTCOND</var> foo ; jmp … ; foo:</kbd> +</p></dd> +</dl> +</dd> +<dt><code>jacb<var>X</var></code></dt> +<dd><p><var>X</var> may be one of <code>b d f g h l w</code>. +</p><dl compact="compact"> +<dt>(word displacement)</dt> +<dd><p><kbd><var>OPCODE</var> …</kbd> +</p></dd> +<dt>(long displacement)</dt> +<dd><div class="example"> +<pre class="example"><var>OPCODE</var> …, foo ; +brb bar ; +foo: jmp … ; +bar: +</pre></div> +</dd> +</dl> +</dd> +<dt><code>jaob<var>YYY</var></code></dt> +<dd><p><var>YYY</var> may be one of <code>lss leq</code>. +</p></dd> +<dt><code>jsob<var>ZZZ</var></code></dt> +<dd><p><var>ZZZ</var> may be one of <code>geq gtr</code>. +</p><dl compact="compact"> +<dt>(byte displacement)</dt> +<dd><p><kbd><var>OPCODE</var> …</kbd> +</p></dd> +<dt>(word displacement)</dt> +<dd><div class="example"> +<pre class="example"><var>OPCODE</var> …, foo ; +brb bar ; +foo: brw <var>destination</var> ; +bar: +</pre></div> +</dd> +<dt>(long displacement)</dt> +<dd><div class="example"> +<pre class="example"><var>OPCODE</var> …, foo ; +brb bar ; +foo: jmp <var>destination</var> ; +bar: +</pre></div> +</dd> +</dl> +</dd> +<dt><code>aobleq</code></dt> +<dt><code>aoblss</code></dt> +<dt><code>sobgeq</code></dt> +<dt><code>sobgtr</code></dt> +<dd><dl compact="compact"> +<dt>(byte displacement)</dt> +<dd><p><kbd><var>OPCODE</var> …</kbd> +</p></dd> +<dt>(word displacement)</dt> +<dd><div class="example"> +<pre class="example"><var>OPCODE</var> …, foo ; +brb bar ; +foo: brw <var>destination</var> ; +bar: +</pre></div> +</dd> +<dt>(long displacement)</dt> +<dd><div class="example"> +<pre class="example"><var>OPCODE</var> …, foo ; +brb bar ; +foo: jmp <var>destination</var> ; +bar: +</pre></div> +</dd> +</dl> +</dd> +</dl> + +<hr> +<a name="VAX_002doperands"></a> +<div class="header"> +<p> +Next: <a href="#VAX_002dno" accesskey="n" rel="next">VAX-no</a>, Previous: <a href="#VAX_002dbranch" accesskey="p" rel="previous">VAX-branch</a>, Up: <a href="#Vax_002dDependent" accesskey="u" rel="up">Vax-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="VAX-Operands"></a> +<h4 class="subsection">9.50.6 VAX Operands</h4> + +<a name="index-VAX-operand-notation"></a> +<a name="index-operand-notation_002c-VAX"></a> +<a name="index-immediate-character_002c-VAX"></a> +<a name="index-VAX-immediate-character"></a> +<p>The immediate character is ‘<samp>$</samp>’ for Unix compatibility, not +‘<samp>#</samp>’ as DEC writes it. +</p> +<a name="index-indirect-character_002c-VAX"></a> +<a name="index-VAX-indirect-character"></a> +<p>The indirect character is ‘<samp>*</samp>’ for Unix compatibility, not +‘<samp>@</samp>’ as DEC writes it. +</p> +<a name="index-displacement-sizing-character_002c-VAX"></a> +<a name="index-VAX-displacement-sizing-character"></a> +<p>The displacement sizing character is ‘<samp>`</samp>’ (an accent grave) for +Unix compatibility, not ‘<samp>^</samp>’ as DEC writes it. The letter +preceding ‘<samp>`</samp>’ may have either case. ‘<samp>G</samp>’ is not +understood, but all other letters (<code>b i l s w</code>) are understood. +</p> +<a name="index-register-names_002c-VAX"></a> +<a name="index-VAX-register-names"></a> +<p>Register names understood are <code>r0 r1 r2 … r15 ap fp sp +pc</code>. Upper and lower case letters are equivalent. +</p> +<p>For instance +</p><div class="smallexample"> +<pre class="smallexample">tstb *w`$4(r5) +</pre></div> + +<p>Any expression is permitted in an operand. Operands are comma +separated. +</p> + +<hr> +<a name="VAX_002dno"></a> +<div class="header"> +<p> +Next: <a href="#VAX_002dSyntax" accesskey="n" rel="next">VAX-Syntax</a>, Previous: <a href="#VAX_002doperands" accesskey="p" rel="previous">VAX-operands</a>, Up: <a href="#Vax_002dDependent" accesskey="u" rel="up">Vax-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Not-Supported-on-VAX"></a> +<h4 class="subsection">9.50.7 Not Supported on VAX</h4> + +<a name="index-VAX-bitfields-not-supported"></a> +<a name="index-bitfields_002c-not-supported-on-VAX"></a> +<p>Vax bit fields can not be assembled with <code>as</code>. Someone +can add the required code if they really need it. +</p> +<hr> +<a name="VAX_002dSyntax"></a> +<div class="header"> +<p> +Previous: <a href="#VAX_002dno" accesskey="p" rel="previous">VAX-no</a>, Up: <a href="#Vax_002dDependent" accesskey="u" rel="up">Vax-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="VAX-Syntax"></a> +<h4 class="subsection">9.50.8 VAX Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#VAX_002dChars" accesskey="1">VAX-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="VAX_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#VAX_002dSyntax" accesskey="u" rel="up">VAX-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-38"></a> +<h4 class="subsubsection">9.50.8.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-VAX"></a> +<a name="index-VAX-line-comment-character"></a> +<p>The presence of a ‘<samp>#</samp>’ appearing anywhere on a line indicates the +start of a comment that extends to the end of that line. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-VAX"></a> +<a name="index-statement-separator_002c-VAX"></a> +<a name="index-VAX-line-separator"></a> +<p>The ‘<samp>;</samp>’ character can be used to separate statements on the same +line. +</p> + +<hr> +<a name="Visium_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#WebAssembly_002dDependent" accesskey="n" rel="next">WebAssembly-Dependent</a>, Previous: <a href="#Vax_002dDependent" accesskey="p" rel="previous">Vax-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Visium-Dependent-Features"></a> +<h3 class="section">9.51 Visium Dependent Features</h3> + + +<a name="index-Visium-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Visium-Options" accesskey="1">Visium Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#Visium-Syntax" accesskey="2">Visium Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#Visium-Opcodes" accesskey="3">Visium Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="Visium-Options"></a> +<div class="header"> +<p> +Next: <a href="#Visium-Syntax" accesskey="n" rel="next">Visium Syntax</a>, Up: <a href="#Visium_002dDependent" accesskey="u" rel="up">Visium-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-29"></a> +<h4 class="subsection">9.51.1 Options</h4> +<a name="index-Visium-options"></a> +<a name="index-options-for-Visium"></a> + +<p>The Visium assembler implements one machine-specific option: +</p> +<dl compact="compact"> +<dd><a name="index-_002dmtune_003darch-command_002dline-option_002c-Visium"></a> +</dd> +<dt><code>-mtune=<var>arch</var></code></dt> +<dd><p>This option specifies the target architecture. If an attempt is made to +assemble an instruction that will not execute on the target architecture, +the assembler will issue an error message. +</p> +<p>The following names are recognized: +<code>mcm24</code> +<code>mcm</code> +<code>gr5</code> +<code>gr6</code> +</p></dd> +</dl> + +<hr> +<a name="Visium-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#Visium-Opcodes" accesskey="n" rel="next">Visium Opcodes</a>, Previous: <a href="#Visium-Options" accesskey="p" rel="previous">Visium Options</a>, Up: <a href="#Visium_002dDependent" accesskey="u" rel="up">Visium-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-31"></a> +<h4 class="subsection">9.51.2 Syntax</h4> + +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Visium-Characters" accesskey="1">Visium Characters</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#Visium-Registers" accesskey="2">Visium Registers</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +</table> + +<hr> +<a name="Visium-Characters"></a> +<div class="header"> +<p> +Next: <a href="#Visium-Registers" accesskey="n" rel="next">Visium Registers</a>, Up: <a href="#Visium-Syntax" accesskey="u" rel="up">Visium Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-39"></a> +<h4 class="subsubsection">9.51.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-Visium"></a> +<a name="index-Visium-line-comment-character"></a> +<p>Line comments are introduced either by the ‘<samp>!</samp>’ character or by the +‘<samp>;</samp>’ character appearing anywhere on a line. +</p> +<p>A hash character (‘<samp>#</samp>’) as the first character on a line also +marks the start of a line comment, but in this case it could also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-Visium"></a> +<a name="index-statement-separator_002c-Visium"></a> +<a name="index-Visium-line-separator"></a> +<p>The Visium assembler does not currently support a line separator character. +</p> +<hr> +<a name="Visium-Registers"></a> +<div class="header"> +<p> +Previous: <a href="#Visium-Characters" accesskey="p" rel="previous">Visium Characters</a>, Up: <a href="#Visium-Syntax" accesskey="u" rel="up">Visium Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-20"></a> +<h4 class="subsubsection">9.51.2.2 Register Names</h4> +<a name="index-Visium-registers"></a> +<a name="index-register-names_002c-Visium"></a> +<p>Registers can be specified either by using their canonical mnemonic names +or by using their alias if they have one, for example ‘<samp>sp</samp>’. +</p> +<hr> +<a name="Visium-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#Visium-Syntax" accesskey="p" rel="previous">Visium Syntax</a>, Up: <a href="#Visium_002dDependent" accesskey="u" rel="up">Visium-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-20"></a> +<h4 class="subsection">9.51.3 Opcodes</h4> +<p>All the standard opcodes of the architecture are implemented, along with the +following three pseudo-instructions: <code>cmp</code>, <code>cmpc</code>, <code>move</code>. +</p> +<p>In addition, the following two illegal opcodes are implemented and used by the simulation: +</p> +<div class="example"> +<pre class="example">stop 5-bit immediate, SourceA +trace 5-bit immediate, SourceA +</pre></div> + + +<hr> +<a name="WebAssembly_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#XGATE_002dDependent" accesskey="n" rel="next">XGATE-Dependent</a>, Previous: <a href="#Visium_002dDependent" accesskey="p" rel="previous">Visium-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="WebAssembly-Dependent-Features"></a> +<h3 class="section">9.52 WebAssembly Dependent Features</h3> + + +<a name="index-WebAssembly-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#WebAssembly_002dNotes" accesskey="1">WebAssembly-Notes</a>:</td><td> </td><td align="left" valign="top">Notes +</td></tr> +<tr><td align="left" valign="top">• <a href="#WebAssembly_002dSyntax" accesskey="2">WebAssembly-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#WebAssembly_002dFloating_002dPoint" accesskey="3">WebAssembly-Floating-Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#WebAssembly_002dOpcodes" accesskey="4">WebAssembly-Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +<tr><td align="left" valign="top">• <a href="#WebAssembly_002dmodule_002dlayout" accesskey="5">WebAssembly-module-layout</a>:</td><td> </td><td align="left" valign="top">Module Layout +</td></tr> +</table> + +<hr> +<a name="WebAssembly_002dNotes"></a> +<div class="header"> +<p> +Next: <a href="#WebAssembly_002dSyntax" accesskey="n" rel="next">WebAssembly-Syntax</a>, Up: <a href="#WebAssembly_002dDependent" accesskey="u" rel="up">WebAssembly-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Notes-3"></a> +<h4 class="subsection">9.52.1 Notes</h4> +<a name="index-WebAssembly-notes"></a> +<a name="index-notes-for-WebAssembly"></a> + +<p>While WebAssembly provides its own module format for executables, this +documentation describes how to use <code>as</code> to produce +intermediate ELF object format files. +</p> +<hr> +<a name="WebAssembly_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#WebAssembly_002dFloating_002dPoint" accesskey="n" rel="next">WebAssembly-Floating-Point</a>, Previous: <a href="#WebAssembly_002dNotes" accesskey="p" rel="previous">WebAssembly-Notes</a>, Up: <a href="#WebAssembly_002dDependent" accesskey="u" rel="up">WebAssembly-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-32"></a> +<h4 class="subsection">9.52.2 Syntax</h4> +<a name="index-WebAssembly-Syntax"></a> +<p>The assembler syntax directly encodes sequences of opcodes as defined +in the WebAssembly binary encoding specification at +https://github.com/webassembly/spec/BinaryEncoding.md. Structured +sexp-style expressions are not supported as input. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#WebAssembly_002dChars" accesskey="1">WebAssembly-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#WebAssembly_002dRelocs" accesskey="2">WebAssembly-Relocs</a>:</td><td> </td><td align="left" valign="top">Relocations +</td></tr> +<tr><td align="left" valign="top">• <a href="#WebAssembly_002dSignatures" accesskey="3">WebAssembly-Signatures</a>:</td><td> </td><td align="left" valign="top">Signatures +</td></tr> +</table> + +<hr> +<a name="WebAssembly_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#WebAssembly_002dRelocs" accesskey="n" rel="next">WebAssembly-Relocs</a>, Up: <a href="#WebAssembly_002dSyntax" accesskey="u" rel="up">WebAssembly-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-40"></a> +<h4 class="subsubsection">9.52.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-WebAssembly"></a> +<a name="index-WebAssembly-line-comment-character"></a> +<p>‘<samp>#</samp>’ and ‘<samp>;</samp>’ are the line comment characters. Note that if +‘<samp>#</samp>’ is the first character on a line then it can also be a +logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<hr> +<a name="WebAssembly_002dRelocs"></a> +<div class="header"> +<p> +Next: <a href="#WebAssembly_002dSignatures" accesskey="n" rel="next">WebAssembly-Signatures</a>, Previous: <a href="#WebAssembly_002dChars" accesskey="p" rel="previous">WebAssembly-Chars</a>, Up: <a href="#WebAssembly_002dSyntax" accesskey="u" rel="up">WebAssembly-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Relocations-5"></a> +<h4 class="subsubsection">9.52.2.2 Relocations</h4> +<a name="index-WebAssembly-relocations"></a> +<a name="index-relocations_002c-WebAssembly"></a> + +<p>Special relocations are available by using the ‘<samp>@<var>plt</var></samp>’, +‘<samp>@<var>got</var></samp>’, or ‘<samp>@<var>got</var></samp>’ suffixes after a constant +expression, which correspond to the R_ASMJS_LEB128_PLT, +R_ASMJS_LEB128_GOT, and R_ASMJS_LEB128_GOT_CODE relocations, +respectively. +</p> +<p>The ‘<samp>@<var>plt</var></samp>’ suffix is followed by a symbol name in braces; +the symbol value is used to determine the function signature for which +a PLT stub is generated. Currently, the symbol <em>name</em> is parsed +from its last ‘<samp>F</samp>’ character to determine the argument count of +the function, which is also necessary for generating a PLT stub. +</p> +<hr> +<a name="WebAssembly_002dSignatures"></a> +<div class="header"> +<p> +Previous: <a href="#WebAssembly_002dRelocs" accesskey="p" rel="previous">WebAssembly-Relocs</a>, Up: <a href="#WebAssembly_002dSyntax" accesskey="u" rel="up">WebAssembly-Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Signatures"></a> +<h4 class="subsubsection">9.52.2.3 Signatures</h4> +<a name="index-WebAssembly-signatures"></a> +<a name="index-signatures_002c-WebAssembly"></a> + +<p>Function signatures are specified with the <code>signature</code> +pseudo-opcode, followed by a simple function signature imitating a +C++-mangled function type: <code>F</code> followed by an optional <code>v</code>, +then a sequence of <code>i</code>, <code>l</code>, <code>f</code>, and <code>d</code> +characters to mark i32, i64, f32, and f64 parameters, respectively; +followed by a final <code>E</code> to mark the end of the function +signature. +</p> +<hr> +<a name="WebAssembly_002dFloating_002dPoint"></a> +<div class="header"> +<p> +Next: <a href="#WebAssembly_002dOpcodes" accesskey="n" rel="next">WebAssembly-Opcodes</a>, Previous: <a href="#WebAssembly_002dSyntax" accesskey="p" rel="previous">WebAssembly-Syntax</a>, Up: <a href="#WebAssembly_002dDependent" accesskey="u" rel="up">WebAssembly-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-17"></a> +<h4 class="subsection">9.52.3 Floating Point</h4> +<a name="index-floating-point_002c-WebAssembly-_0028IEEE_0029"></a> +<a name="index-WebAssembly-floating-point-_0028IEEE_0029"></a> +<p>WebAssembly uses little-endian <small>IEEE</small> floating-point numbers. +</p> +<hr> +<a name="WebAssembly_002dOpcodes"></a> +<div class="header"> +<p> +Next: <a href="#WebAssembly_002dmodule_002dlayout" accesskey="n" rel="next">WebAssembly-module-layout</a>, Previous: <a href="#WebAssembly_002dFloating_002dPoint" accesskey="p" rel="previous">WebAssembly-Floating-Point</a>, Up: <a href="#WebAssembly_002dDependent" accesskey="u" rel="up">WebAssembly-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Regular-Opcodes"></a> +<h4 class="subsection">9.52.4 Regular Opcodes</h4> +<a name="index-opcodes_002c-WebAssembly"></a> +<a name="index-WebAssembly-opcodes"></a> +<p>Ordinary instructions are encoded with the WebAssembly mnemonics as +listed at: +<a href="https://github.com/WebAssembly/design/blob/master/BinaryEncoding.md">https://github.com/WebAssembly/design/blob/master/BinaryEncoding.md</a>. +</p> +<p>Opcodes are written directly in the order in which they are encoded, +without going through an intermediate sexp-style expression as in the +<code>was</code> format. +</p> +<p>For “typed” opcodes (block, if, etc.), the type of the block is +specified in square brackets following the opcode: <code>if[i]</code>, +<code>if[]</code>. +</p> +<hr> +<a name="WebAssembly_002dmodule_002dlayout"></a> +<div class="header"> +<p> +Previous: <a href="#WebAssembly_002dOpcodes" accesskey="p" rel="previous">WebAssembly-Opcodes</a>, Up: <a href="#WebAssembly_002dDependent" accesskey="u" rel="up">WebAssembly-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="WebAssembly-Module-Layout"></a> +<h4 class="subsection">9.52.5 WebAssembly Module Layout</h4> +<a name="index-module-layout_002c-WebAssembly"></a> +<a name="index-WebAssembly-module-layout"></a> +<p><code>as</code> will only produce ELF output, not a valid +WebAssembly module. It is possible to make <code>as</code> produce +output in a single ELF section which becomes a valid WebAssembly +module, but a linker script to do so may be preferable, as it doesn’t +require running the entire module through the assembler at once. +</p> +<hr> +<a name="XGATE_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#XSTORMY16_002dDependent" accesskey="n" rel="next">XSTORMY16-Dependent</a>, Previous: <a href="#WebAssembly_002dDependent" accesskey="p" rel="previous">WebAssembly-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="XGATE-Dependent-Features"></a> +<h3 class="section">9.53 XGATE Dependent Features</h3> + +<a name="index-XGATE-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#XGATE_002dOpts" accesskey="1">XGATE-Opts</a>:</td><td> </td><td align="left" valign="top">XGATE Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#XGATE_002dSyntax" accesskey="2">XGATE-Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#XGATE_002dDirectives" accesskey="3">XGATE-Directives</a>:</td><td> </td><td align="left" valign="top">Assembler Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#XGATE_002dFloat" accesskey="4">XGATE-Float</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#XGATE_002dopcodes" accesskey="5">XGATE-opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="XGATE_002dOpts"></a> +<div class="header"> +<p> +Next: <a href="#XGATE_002dSyntax" accesskey="n" rel="next">XGATE-Syntax</a>, Up: <a href="#XGATE_002dDependent" accesskey="u" rel="up">XGATE-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="XGATE-Options"></a> +<h4 class="subsection">9.53.1 XGATE Options</h4> + +<a name="index-options_002c-XGATE"></a> +<a name="index-XGATE-options"></a> +<p>The Freescale XGATE version of <code>as</code> has a few machine +dependent options. +</p> +<dl compact="compact"> +<dd> +<a name="index-_002dmshort-1"></a> +</dd> +<dt><code>-mshort</code></dt> +<dd><p>This option controls the ABI and indicates to use a 16-bit integer ABI. +It has no effect on the assembled instructions. +This is the default. +</p> +<a name="index-_002dmlong-1"></a> +</dd> +<dt><code>-mlong</code></dt> +<dd><p>This option controls the ABI and indicates to use a 32-bit integer ABI. +</p> +<a name="index-_002dmshort_002ddouble-1"></a> +</dd> +<dt><code>-mshort-double</code></dt> +<dd><p>This option controls the ABI and indicates to use a 32-bit float ABI. +This is the default. +</p> +<a name="index-_002dmlong_002ddouble-1"></a> +</dd> +<dt><code>-mlong-double</code></dt> +<dd><p>This option controls the ABI and indicates to use a 64-bit float ABI. +</p> +<a name="index-_002d_002dprint_002dinsn_002dsyntax-1"></a> +</dd> +<dt><code>--print-insn-syntax</code></dt> +<dd><p>You can use the ‘<samp>--print-insn-syntax</samp>’ option to obtain the +syntax description of the instruction when an error is detected. +</p> +<a name="index-_002d_002dprint_002dopcodes-1"></a> +</dd> +<dt><code>--print-opcodes</code></dt> +<dd><p>The ‘<samp>--print-opcodes</samp>’ option prints the list of all the +instructions with their syntax. Once the list is printed +<code>as</code> exits. +</p> +</dd> +</dl> + +<hr> +<a name="XGATE_002dSyntax"></a> +<div class="header"> +<p> +Next: <a href="#XGATE_002dDirectives" accesskey="n" rel="next">XGATE-Directives</a>, Previous: <a href="#XGATE_002dOpts" accesskey="p" rel="previous">XGATE-Opts</a>, Up: <a href="#XGATE_002dDependent" accesskey="u" rel="up">XGATE-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-33"></a> +<h4 class="subsection">9.53.2 Syntax</h4> + +<a name="index-XGATE-syntax"></a> +<a name="index-syntax_002c-XGATE"></a> + +<p>In XGATE RISC syntax, the instruction name comes first and it may +be followed by up to three operands. Operands are separated by commas +(‘<samp>,</samp>’). <code>as</code> will complain if too many operands are specified +for a given instruction. The same will happen if you specified too few + operands. +</p> +<div class="smallexample"> +<pre class="smallexample">nop +ldl #23 +CMP R1, R2 +</pre></div> + +<a name="index-line-comment-character_002c-XGATE"></a> +<a name="index-XGATE-line-comment-character"></a> +<p>The presence of a ‘<samp>;</samp>’ character or a ‘<samp>!</samp>’ character anywhere +on a line indicates the start of a comment that extends to the end of +that line. +</p> +<p>A ‘<samp>*</samp>’ or a ‘<samp>#</samp>’ character at the start of a line also +introduces a line comment, but these characters do not work elsewhere +on the line. If the first character of the line is a ‘<samp>#</samp>’ then as +well as starting a comment, the line could also be logical line number +directive (see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-XGATE"></a> +<a name="index-statement-separator_002c-XGATE"></a> +<a name="index-XGATE-line-separator"></a> +<p>The XGATE assembler does not currently support a line separator +character. +</p> +<a name="index-XGATE-addressing-modes"></a> +<a name="index-addressing-modes_002c-XGATE"></a> +<p>The following addressing modes are understood for XGATE: +</p><dl compact="compact"> +<dt><em>Inherent</em></dt> +<dd><p>‘<samp></samp>’ +</p> +</dd> +<dt><em>Immediate 3 Bit Wide</em></dt> +<dd><p>‘<samp>#<var>number</var></samp>’ +</p> +</dd> +<dt><em>Immediate 4 Bit Wide</em></dt> +<dd><p>‘<samp>#<var>number</var></samp>’ +</p> +</dd> +<dt><em>Immediate 8 Bit Wide</em></dt> +<dd><p>‘<samp>#<var>number</var></samp>’ +</p> +</dd> +<dt><em>Monadic Addressing</em></dt> +<dd><p>‘<samp><var>reg</var></samp>’ +</p> +</dd> +<dt><em>Dyadic Addressing</em></dt> +<dd><p>‘<samp><var>reg</var>, <var>reg</var></samp>’ +</p> +</dd> +<dt><em>Triadic Addressing</em></dt> +<dd><p>‘<samp><var>reg</var>, <var>reg</var>, <var>reg</var></samp>’ +</p> +</dd> +<dt><em>Relative Addressing 9 Bit Wide</em></dt> +<dd><p>‘<samp>*<var>symbol</var></samp>’ +</p> +</dd> +<dt><em>Relative Addressing 10 Bit Wide</em></dt> +<dd><p>‘<samp>*<var>symbol</var></samp>’ +</p> +</dd> +<dt><em>Index Register plus Immediate Offset</em></dt> +<dd><p>‘<samp><var>reg</var>, (<var>reg</var>, #<var>number</var>)</samp>’ +</p> +</dd> +<dt><em>Index Register plus Register Offset</em></dt> +<dd><p>‘<samp><var>reg</var>, <var>reg</var>, <var>reg</var></samp>’ +</p> +</dd> +<dt><em>Index Register plus Register Offset with Post-increment</em></dt> +<dd><p>‘<samp><var>reg</var>, <var>reg</var>, <var>reg</var>+</samp>’ +</p> +</dd> +<dt><em>Index Register plus Register Offset with Pre-decrement</em></dt> +<dd><p>‘<samp><var>reg</var>, <var>reg</var>, -<var>reg</var></samp>’ +</p> +<p>The register can be either ‘<samp>R0</samp>’, ‘<samp>R1</samp>’, ‘<samp>R2</samp>’, ‘<samp>R3</samp>’, +‘<samp>R4</samp>’, ‘<samp>R5</samp>’, ‘<samp>R6</samp>’ or ‘<samp>R7</samp>’. +</p> +</dd> +</dl> + +<p>Convene macro opcodes to deal with 16-bit values have been added. +</p> +<dl compact="compact"> +<dt><em>Immediate 16 Bit Wide</em></dt> +<dd><p>‘<samp>#<var>number</var></samp>’, or ‘<samp>*<var>symbol</var></samp>’ +</p> +<p>For example: +</p> +<div class="smallexample"> +<pre class="smallexample">ldw R1, #1024 +ldw R3, timer +ldw R1, (R1, #0) +COM R1 +stw R2, (R1, #0) +</pre></div> +</dd> +</dl> + +<hr> +<a name="XGATE_002dDirectives"></a> +<div class="header"> +<p> +Next: <a href="#XGATE_002dFloat" accesskey="n" rel="next">XGATE-Float</a>, Previous: <a href="#XGATE_002dSyntax" accesskey="p" rel="previous">XGATE-Syntax</a>, Up: <a href="#XGATE_002dDependent" accesskey="u" rel="up">XGATE-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives-8"></a> +<h4 class="subsection">9.53.3 Assembler Directives</h4> + +<a name="index-assembler-directives_002c-XGATE"></a> +<a name="index-XGATE-assembler-directives"></a> + +<p>The XGATE version of <code>as</code> have the following +specific assembler directives: +</p> +<hr> +<a name="XGATE_002dFloat"></a> +<div class="header"> +<p> +Next: <a href="#XGATE_002dopcodes" accesskey="n" rel="next">XGATE-opcodes</a>, Previous: <a href="#XGATE_002dDirectives" accesskey="p" rel="previous">XGATE-Directives</a>, Up: <a href="#XGATE_002dDependent" accesskey="u" rel="up">XGATE-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-18"></a> +<h4 class="subsection">9.53.4 Floating Point</h4> + +<a name="index-floating-point_002c-XGATE"></a> +<a name="index-XGATE-floating-point"></a> +<p>Packed decimal (P) format floating literals are not supported(yet). +</p> +<p>The floating point formats generated by directives are these. +</p> +<dl compact="compact"> +<dd><a name="index-float-directive_002c-XGATE"></a> +</dd> +<dt><code>.float</code></dt> +<dd><p><code>Single</code> precision floating point constants. +</p> +<a name="index-double-directive_002c-XGATE"></a> +</dd> +<dt><code>.double</code></dt> +<dd><p><code>Double</code> precision floating point constants. +</p> +<a name="index-extend-directive-XGATE"></a> +<a name="index-ldouble-directive-XGATE"></a> +</dd> +<dt><code>.extend</code></dt> +<dt><code>.ldouble</code></dt> +<dd><p><code>Extended</code> precision (<code>long double</code>) floating point constants. +</p></dd> +</dl> + +<hr> +<a name="XGATE_002dopcodes"></a> +<div class="header"> +<p> +Previous: <a href="#XGATE_002dFloat" accesskey="p" rel="previous">XGATE-Float</a>, Up: <a href="#XGATE_002dDependent" accesskey="u" rel="up">XGATE-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-21"></a> +<h4 class="subsection">9.53.5 Opcodes</h4> + +<a name="index-XGATE-opcodes"></a> +<a name="index-instruction-set_002c-XGATE"></a> + + + +<hr> +<a name="XSTORMY16_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa_002dDependent" accesskey="n" rel="next">Xtensa-Dependent</a>, Previous: <a href="#XGATE_002dDependent" accesskey="p" rel="previous">XGATE-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="XStormy16-Dependent-Features"></a> +<h3 class="section">9.54 XStormy16 Dependent Features</h3> + +<a name="index-XStormy16-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#XStormy16-Syntax" accesskey="1">XStormy16 Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#XStormy16-Directives" accesskey="2">XStormy16 Directives</a>:</td><td> </td><td align="left" valign="top">Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#XStormy16-Opcodes" accesskey="3">XStormy16 Opcodes</a>:</td><td> </td><td align="left" valign="top">Pseudo-Opcodes +</td></tr> +</table> + +<hr> +<a name="XStormy16-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#XStormy16-Directives" accesskey="n" rel="next">XStormy16 Directives</a>, Up: <a href="#XSTORMY16_002dDependent" accesskey="u" rel="up">XSTORMY16-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-34"></a> +<h4 class="subsection">9.54.1 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#XStormy16_002dChars" accesskey="1">XStormy16-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +</table> + +<hr> +<a name="XStormy16_002dChars"></a> +<div class="header"> +<p> +Up: <a href="#XStormy16-Syntax" accesskey="u" rel="up">XStormy16 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-41"></a> +<h4 class="subsubsection">9.54.1.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-XStormy16"></a> +<a name="index-XStormy16-line-comment-character"></a> +<p>‘<samp>#</samp>’ is the line comment character. If a ‘<samp>#</samp>’ appears as the +first character of a line, the whole line is treated as a comment, but +in this case the line can also be a logical line number directive +(see <a href="#Comments">Comments</a>) or a preprocessor control command +(see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-comment-character_002c-XStormy16"></a> +<a name="index-XStormy16-comment-character"></a> +<p>A semicolon (‘<samp>;</samp>’) can be used to start a comment that extends +from wherever the character appears on the line up to the end of the +line. +</p> +<a name="index-line-separator_002c-XStormy16"></a> +<a name="index-statement-separator_002c-XStormy16"></a> +<a name="index-XStormy16-line-separator"></a> + +<p>The ‘<samp>|</samp>’ character can be used to separate statements on the same +line. +</p> + +<hr> +<a name="XStormy16-Directives"></a> +<div class="header"> +<p> +Next: <a href="#XStormy16-Opcodes" accesskey="n" rel="next">XStormy16 Opcodes</a>, Previous: <a href="#XStormy16-Syntax" accesskey="p" rel="previous">XStormy16 Syntax</a>, Up: <a href="#XSTORMY16_002dDependent" accesskey="u" rel="up">XSTORMY16-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="XStormy16-Machine-Directives"></a> +<h4 class="subsection">9.54.2 XStormy16 Machine Directives</h4> + +<a name="index-machine-directives_002c-XStormy16"></a> +<a name="index-XStormy16-machine-directives"></a> +<dl compact="compact"> +<dd> +<a name="index-16bit_005fpointers-directive_002c-XStormy16"></a> +</dd> +<dt><code>.16bit_pointers</code></dt> +<dd><p>Like the <samp>--16bit-pointers</samp> command-line option this directive +indicates that the assembly code makes use of 16-bit pointers. +</p> +<a name="index-32bit_005fpointers-directive_002c-XStormy16"></a> +</dd> +<dt><code>.32bit_pointers</code></dt> +<dd><p>Like the <samp>--32bit-pointers</samp> command-line option this directive +indicates that the assembly code makes use of 32-bit pointers. +</p> +<a name="index-_002eno_005fpointers-directive_002c-XStormy16"></a> +</dd> +<dt><code>.no_pointers</code></dt> +<dd><p>Like the <samp>--no-pointers</samp> command-line option this directive +indicates that the assembly code does not makes use pointers. +</p> +</dd> +</dl> + +<hr> +<a name="XStormy16-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#XStormy16-Directives" accesskey="p" rel="previous">XStormy16 Directives</a>, Up: <a href="#XSTORMY16_002dDependent" accesskey="u" rel="up">XSTORMY16-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="XStormy16-Pseudo_002dOpcodes"></a> +<h4 class="subsection">9.54.3 XStormy16 Pseudo-Opcodes</h4> + +<a name="index-XStormy16-pseudo_002dopcodes"></a> +<a name="index-pseudo_002dopcodes-for-XStormy16"></a> +<p><code>as</code> implements all the standard XStormy16 opcodes. +</p> +<p><code>as</code> also implements the following pseudo ops: +</p> +<dl compact="compact"> +<dd> +<a name="index-_0040lo-pseudo_002dop_002c-XStormy16"></a> +</dd> +<dt><code>@lo()</code></dt> +<dd><p>Computes the lower 16 bits of the given expression and stores it into +the immediate operand field of the given instruction. For example: +</p> +<p>‘<samp>add r6, @lo(here - there)</samp>’ +</p> +<p>computes the difference between the address of labels ’here’ and +’there’, takes the lower 16 bits of this difference and adds it to +register 6. +</p> +<a name="index-_0040hi-pseudo_002dop_002c-XStormy16"></a> +</dd> +<dt><code>@hi()</code></dt> +<dd><p>Computes the higher 16 bits of the given expression and stores it into +the immediate operand field of the given instruction. For example: +</p> +<p>‘<samp>addc r7, @hi(here - there)</samp>’ +</p> +<p>computes the difference between the address of labels ’here’ and +’there’, takes the upper 16 bits of this difference, shifts it down 16 +bits and then adds it, along with the carry bit, to the value in +register 7. +</p> +</dd> +</dl> + +<hr> +<a name="Xtensa_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Z80_002dDependent" accesskey="n" rel="next">Z80-Dependent</a>, Previous: <a href="#XSTORMY16_002dDependent" accesskey="p" rel="previous">XSTORMY16-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Xtensa-Dependent-Features"></a> +<h3 class="section">9.55 Xtensa Dependent Features</h3> + +<a name="index-Xtensa-architecture"></a> +<p>This chapter covers features of the <small>GNU</small> assembler that are specific +to the Xtensa architecture. For details about the Xtensa instruction +set, please consult the <cite>Xtensa Instruction Set Architecture (ISA) +Reference Manual</cite>. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Xtensa-Options" accesskey="1">Xtensa Options</a>:</td><td> </td><td align="left" valign="top">Command-line Options. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa-Syntax" accesskey="2">Xtensa Syntax</a>:</td><td> </td><td align="left" valign="top">Assembler Syntax for Xtensa Processors. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa-Optimizations" accesskey="3">Xtensa Optimizations</a>:</td><td> </td><td align="left" valign="top">Assembler Optimizations. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa-Relaxation" accesskey="4">Xtensa Relaxation</a>:</td><td> </td><td align="left" valign="top">Other Automatic Transformations. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa-Directives" accesskey="5">Xtensa Directives</a>:</td><td> </td><td align="left" valign="top">Directives for Xtensa Processors. +</td></tr> +</table> + +<hr> +<a name="Xtensa-Options"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa-Syntax" accesskey="n" rel="next">Xtensa Syntax</a>, Up: <a href="#Xtensa_002dDependent" accesskey="u" rel="up">Xtensa-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Command_002dline-Options-2"></a> +<h4 class="subsection">9.55.1 Command-line Options</h4> + +<dl compact="compact"> +<dt><code>--text-section-literals | --no-text-section-literals</code></dt> +<dd><a name="index-_002d_002dtext_002dsection_002dliterals"></a> +<a name="index-_002d_002dno_002dtext_002dsection_002dliterals"></a> +<p>Control the treatment of literal pools. The default is +‘<samp>--no-text-section-literals</samp>’, which places literals in +separate sections in the output file. This allows the literal pool to be +placed in a data RAM/ROM. With ‘<samp>--text-section-literals</samp>’, the +literals are interspersed in the text section in order to keep them as +close as possible to their references. This may be necessary for large +assembly files, where the literals would otherwise be out of range of the +<code>L32R</code> instructions in the text section. Literals are grouped into +pools following <code>.literal_position</code> directives or preceding +<code>ENTRY</code> instructions. These options only affect literals referenced +via PC-relative <code>L32R</code> instructions; literals for absolute mode +<code>L32R</code> instructions are handled separately. +See <a href="#Literal-Directive">literal</a>. +</p> +</dd> +<dt><code>--auto-litpools | --no-auto-litpools</code></dt> +<dd><a name="index-_002d_002dauto_002dlitpools"></a> +<a name="index-_002d_002dno_002dauto_002dlitpools"></a> +<p>Control the treatment of literal pools. The default is +‘<samp>--no-auto-litpools</samp>’, which in the absence of +‘<samp>--text-section-literals</samp>’ places literals in separate sections +in the output file. This allows the literal pool to be placed in a data +RAM/ROM. With ‘<samp>--auto-litpools</samp>’, the literals are interspersed +in the text section in order to keep them as close as possible to their +references, explicit <code>.literal_position</code> directives are not +required. This may be necessary for very large functions, where single +literal pool at the beginning of the function may not be reachable by +<code>L32R</code> instructions at the end. These options only affect +literals referenced via PC-relative <code>L32R</code> instructions; literals +for absolute mode <code>L32R</code> instructions are handled separately. +When used together with ‘<samp>--text-section-literals</samp>’, +‘<samp>--auto-litpools</samp>’ takes precedence. +See <a href="#Literal-Directive">literal</a>. +</p> +</dd> +<dt><code>--absolute-literals | --no-absolute-literals</code></dt> +<dd><a name="index-_002d_002dabsolute_002dliterals"></a> +<a name="index-_002d_002dno_002dabsolute_002dliterals"></a> +<p>Indicate to the assembler whether <code>L32R</code> instructions use absolute +or PC-relative addressing. If the processor includes the absolute +addressing option, the default is to use absolute <code>L32R</code> +relocations. Otherwise, only the PC-relative <code>L32R</code> relocations +can be used. +</p> +</dd> +<dt><code>--target-align | --no-target-align</code></dt> +<dd><a name="index-_002d_002dtarget_002dalign"></a> +<a name="index-_002d_002dno_002dtarget_002dalign"></a> +<p>Enable or disable automatic alignment to reduce branch penalties at some +expense in code size. See <a href="#Xtensa-Automatic-Alignment">Automatic +Instruction Alignment</a>. This optimization is enabled by default. Note +that the assembler will always align instructions like <code>LOOP</code> that +have fixed alignment requirements. +</p> +</dd> +<dt><code>--longcalls | --no-longcalls</code></dt> +<dd><a name="index-_002d_002dlongcalls"></a> +<a name="index-_002d_002dno_002dlongcalls"></a> +<p>Enable or disable transformation of call instructions to allow calls +across a greater range of addresses. See <a href="#Xtensa-Call-Relaxation">Function Call Relaxation</a>. This option should be used when call +targets can potentially be out of range. It may degrade both code size +and performance, but the linker can generally optimize away the +unnecessary overhead when a call ends up within range. The default is +‘<samp>--no-longcalls</samp>’. +</p> +</dd> +<dt><code>--transform | --no-transform</code></dt> +<dd><a name="index-_002d_002dtransform"></a> +<a name="index-_002d_002dno_002dtransform"></a> +<p>Enable or disable all assembler transformations of Xtensa instructions, +including both relaxation and optimization. The default is +‘<samp>--transform</samp>’; ‘<samp>--no-transform</samp>’ should only be used in the +rare cases when the instructions must be exactly as specified in the +assembly source. Using ‘<samp>--no-transform</samp>’ causes out of range +instruction operands to be errors. +</p> +</dd> +<dt><code>--rename-section <var>oldname</var>=<var>newname</var></code></dt> +<dd><a name="index-_002d_002drename_002dsection"></a> +<p>Rename the <var>oldname</var> section to <var>newname</var>. This option can be used +multiple times to rename multiple sections. +</p> +</dd> +<dt><code>--trampolines | --no-trampolines</code></dt> +<dd><a name="index-_002d_002dtrampolines"></a> +<a name="index-_002d_002dno_002dtrampolines"></a> +<p>Enable or disable transformation of jump instructions to allow jumps +across a greater range of addresses. See <a href="#Xtensa-Jump-Relaxation">Jump Trampolines</a>. This option should be used when jump targets can +potentially be out of range. In the absence of such jumps this option +does not affect code size or performance. The default is +‘<samp>--trampolines</samp>’. +</p> +</dd> +<dt><code>--abi-windowed | --abi-call0</code></dt> +<dd><a name="index-_002d_002dabi_002dwindowed"></a> +<a name="index-_002d_002dabi_002dcall0"></a> +<p>Choose ABI tag written to the <code>.xtensa.info</code> section. ABI tag +indicates ABI of the assembly code. A warning is issued by the linker +on an attempt to link object files with inconsistent ABI tags. +Default ABI is chosen by the Xtensa core configuration. +</p></dd> +</dl> + + +<hr> +<a name="Xtensa-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa-Optimizations" accesskey="n" rel="next">Xtensa Optimizations</a>, Previous: <a href="#Xtensa-Options" accesskey="p" rel="previous">Xtensa Options</a>, Up: <a href="#Xtensa_002dDependent" accesskey="u" rel="up">Xtensa-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Syntax"></a> +<h4 class="subsection">9.55.2 Assembler Syntax</h4> +<a name="index-syntax_002c-Xtensa-assembler"></a> +<a name="index-Xtensa-assembler-syntax"></a> +<a name="index-FLIX-syntax"></a> + +<p>Block comments are delimited by ‘<samp>/*</samp>’ and ‘<samp>*/</samp>’. End of line +comments may be introduced with either ‘<samp>#</samp>’ or ‘<samp>//</samp>’. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<p>Instructions consist of a leading opcode or macro name followed by +whitespace and an optional comma-separated list of operands: +</p> +<div class="smallexample"> +<pre class="smallexample"><var>opcode</var> [<var>operand</var>, …] +</pre></div> + +<p>Instructions must be separated by a newline or semicolon (‘<samp>;</samp>’). +</p> +<p>FLIX instructions, which bundle multiple opcodes together in a single +instruction, are specified by enclosing the bundled opcodes inside +braces: +</p> +<div class="smallexample"> +<pre class="smallexample">{ +[<var>format</var>] +<var>opcode0</var> [<var>operands</var>] +</pre><pre class="smallexample"><var>opcode1</var> [<var>operands</var>] +</pre><pre class="smallexample"><var>opcode2</var> [<var>operands</var>] +… +} +</pre></div> + +<p>The opcodes in a FLIX instruction are listed in the same order as the +corresponding instruction slots in the TIE format declaration. +Directives and labels are not allowed inside the braces of a FLIX +instruction. A particular TIE format name can optionally be specified +immediately after the opening brace, but this is usually unnecessary. +The assembler will automatically search for a format that can encode the +specified opcodes, so the format name need only be specified in rare +cases where there is more than one applicable format and where it +matters which of those formats is used. A FLIX instruction can also be +specified on a single line by separating the opcodes with semicolons: +</p> +<div class="smallexample"> +<pre class="smallexample">{ [<var>format</var>;] <var>opcode0</var> [<var>operands</var>]; <var>opcode1</var> [<var>operands</var>]; <var>opcode2</var> [<var>operands</var>]; … } +</pre></div> + +<p>If an opcode can only be encoded in a FLIX instruction but is not +specified as part of a FLIX bundle, the assembler will choose the +smallest format where the opcode can be encoded and +will fill unused instruction slots with no-ops. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Xtensa-Opcodes" accesskey="1">Xtensa Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcode Naming Conventions. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa-Registers" accesskey="2">Xtensa Registers</a>:</td><td> </td><td align="left" valign="top">Register Naming. +</td></tr> +</table> + +<hr> +<a name="Xtensa-Opcodes"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa-Registers" accesskey="n" rel="next">Xtensa Registers</a>, Up: <a href="#Xtensa-Syntax" accesskey="u" rel="up">Xtensa Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcode-Names-2"></a> +<h4 class="subsubsection">9.55.2.1 Opcode Names</h4> +<a name="index-Xtensa-opcode-names"></a> +<a name="index-opcode-names_002c-Xtensa"></a> + +<p>See the <cite>Xtensa Instruction Set Architecture (ISA) Reference +Manual</cite> for a complete list of opcodes and descriptions of their +semantics. +</p> +<a name="index-_005f-opcode-prefix"></a> +<p>If an opcode name is prefixed with an underscore character (‘<samp>_</samp>’), +<code>as</code> will not transform that instruction in any way. The +underscore prefix disables both optimization (see <a href="#Xtensa-Optimizations">Xtensa Optimizations</a>) and relaxation (see <a href="#Xtensa-Relaxation">Xtensa Relaxation</a>) for that particular instruction. Only +use the underscore prefix when it is essential to select the exact +opcode produced by the assembler. Using this feature unnecessarily +makes the code less efficient by disabling assembler optimization and +less flexible by disabling relaxation. +</p> +<p>Note that this special handling of underscore prefixes only applies to +Xtensa opcodes, not to either built-in macros or user-defined macros. +When an underscore prefix is used with a macro (e.g., <code>_MOV</code>), it +refers to a different macro. The assembler generally provides built-in +macros both with and without the underscore prefix, where the underscore +versions behave as if the underscore carries through to the instructions +in the macros. For example, <code>_MOV</code> may expand to <code>_MOV.N</code>. +</p> +<p>The underscore prefix only applies to individual instructions, not to +series of instructions. For example, if a series of instructions have +underscore prefixes, the assembler will not transform the individual +instructions, but it may insert other instructions between them (e.g., +to align a <code>LOOP</code> instruction). To prevent the assembler from +modifying a series of instructions as a whole, use the +<code>no-transform</code> directive. See <a href="#Transform-Directive">transform</a>. +</p> +<hr> +<a name="Xtensa-Registers"></a> +<div class="header"> +<p> +Previous: <a href="#Xtensa-Opcodes" accesskey="p" rel="previous">Xtensa Opcodes</a>, Up: <a href="#Xtensa-Syntax" accesskey="u" rel="up">Xtensa Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-21"></a> +<h4 class="subsubsection">9.55.2.2 Register Names</h4> +<a name="index-Xtensa-register-names"></a> +<a name="index-register-names_002c-Xtensa"></a> +<a name="index-sp-register"></a> + +<p>The assembly syntax for a register file entry is the “short” name for +a TIE register file followed by the index into that register file. For +example, the general-purpose <code>AR</code> register file has a short name of +<code>a</code>, so these registers are named <code>a0</code>…<code>a15</code>. +As a special feature, <code>sp</code> is also supported as a synonym for +<code>a1</code>. Additional registers may be added by processor configuration +options and by designer-defined TIE extensions. An initial ‘<samp>$</samp>’ +character is optional in all register names. +</p> +<hr> +<a name="Xtensa-Optimizations"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa-Relaxation" accesskey="n" rel="next">Xtensa Relaxation</a>, Previous: <a href="#Xtensa-Syntax" accesskey="p" rel="previous">Xtensa Syntax</a>, Up: <a href="#Xtensa_002dDependent" accesskey="u" rel="up">Xtensa-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Xtensa-Optimizations-1"></a> +<h4 class="subsection">9.55.3 Xtensa Optimizations</h4> +<a name="index-optimizations"></a> + +<p>The optimizations currently supported by <code>as</code> are +generation of density instructions where appropriate and automatic +branch target alignment. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Density-Instructions" accesskey="1">Density Instructions</a>:</td><td> </td><td align="left" valign="top">Using Density Instructions. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa-Automatic-Alignment" accesskey="2">Xtensa Automatic Alignment</a>:</td><td> </td><td align="left" valign="top">Automatic Instruction Alignment. +</td></tr> +</table> + +<hr> +<a name="Density-Instructions"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa-Automatic-Alignment" accesskey="n" rel="next">Xtensa Automatic Alignment</a>, Up: <a href="#Xtensa-Optimizations" accesskey="u" rel="up">Xtensa Optimizations</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Using-Density-Instructions"></a> +<h4 class="subsubsection">9.55.3.1 Using Density Instructions</h4> +<a name="index-density-instructions"></a> + +<p>The Xtensa instruction set has a code density option that provides +16-bit versions of some of the most commonly used opcodes. Use of these +opcodes can significantly reduce code size. When possible, the +assembler automatically translates instructions from the core +Xtensa instruction set into equivalent instructions from the Xtensa code +density option. This translation can be disabled by using underscore +prefixes (see <a href="#Xtensa-Opcodes">Opcode Names</a>), by using the +‘<samp>--no-transform</samp>’ command-line option (see <a href="#Xtensa-Options">Command +Line Options</a>), or by using the <code>no-transform</code> directive +(see <a href="#Transform-Directive">transform</a>). +</p> +<p>It is a good idea <em>not</em> to use the density instructions directly. +The assembler will automatically select dense instructions where +possible. If you later need to use an Xtensa processor without the code +density option, the same assembly code will then work without modification. +</p> +<hr> +<a name="Xtensa-Automatic-Alignment"></a> +<div class="header"> +<p> +Previous: <a href="#Density-Instructions" accesskey="p" rel="previous">Density Instructions</a>, Up: <a href="#Xtensa-Optimizations" accesskey="u" rel="up">Xtensa Optimizations</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Automatic-Instruction-Alignment"></a> +<h4 class="subsubsection">9.55.3.2 Automatic Instruction Alignment</h4> +<a name="index-alignment-of-LOOP-instructions"></a> +<a name="index-alignment-of-branch-targets"></a> +<a name="index-LOOP-instructions_002c-alignment"></a> +<a name="index-branch-target-alignment"></a> + +<p>The Xtensa assembler will automatically align certain instructions, both +to optimize performance and to satisfy architectural requirements. +</p> +<p>As an optimization to improve performance, the assembler attempts to +align branch targets so they do not cross instruction fetch boundaries. +(Xtensa processors can be configured with either 32-bit or 64-bit +instruction fetch widths.) An +instruction immediately following a call is treated as a branch target +in this context, because it will be the target of a return from the +call. This alignment has the potential to reduce branch penalties at +some expense in code size. +This optimization is enabled by default. You can disable it with the +‘<samp>--no-target-align</samp>’ command-line option (see <a href="#Xtensa-Options">Command-line Options</a>). +</p> +<p>The target alignment optimization is done without adding instructions +that could increase the execution time of the program. If there are +density instructions in the code preceding a target, the assembler can +change the target alignment by widening some of those instructions to +the equivalent 24-bit instructions. Extra bytes of padding can be +inserted immediately following unconditional jump and return +instructions. +This approach is usually successful in aligning many, but not all, +branch targets. +</p> +<p>The <code>LOOP</code> family of instructions must be aligned such that the +first instruction in the loop body does not cross an instruction fetch +boundary (e.g., with a 32-bit fetch width, a <code>LOOP</code> instruction +must be on either a 1 or 2 mod 4 byte boundary). The assembler knows +about this restriction and inserts the minimal number of 2 or 3 byte +no-op instructions to satisfy it. When no-op instructions are added, +any label immediately preceding the original loop will be moved in order +to refer to the loop instruction, not the newly generated no-op +instruction. To preserve binary compatibility across processors with +different fetch widths, the assembler conservatively assumes a 32-bit +fetch width when aligning <code>LOOP</code> instructions (except if the first +instruction in the loop is a 64-bit instruction). +</p> +<p>Previous versions of the assembler automatically aligned <code>ENTRY</code> +instructions to 4-byte boundaries, but that alignment is now the +programmer’s responsibility. +</p> +<hr> +<a name="Xtensa-Relaxation"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa-Directives" accesskey="n" rel="next">Xtensa Directives</a>, Previous: <a href="#Xtensa-Optimizations" accesskey="p" rel="previous">Xtensa Optimizations</a>, Up: <a href="#Xtensa_002dDependent" accesskey="u" rel="up">Xtensa-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Xtensa-Relaxation-1"></a> +<h4 class="subsection">9.55.4 Xtensa Relaxation</h4> +<a name="index-relaxation"></a> + +<p>When an instruction operand is outside the range allowed for that +particular instruction field, <code>as</code> can transform the code +to use a functionally-equivalent instruction or sequence of +instructions. This process is known as <em>relaxation</em>. This is +typically done for branch instructions because the distance of the +branch targets is not known until assembly-time. The Xtensa assembler +offers branch relaxation and also extends this concept to function +calls, <code>MOVI</code> instructions and other instructions with immediate +fields. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Xtensa-Branch-Relaxation" accesskey="1">Xtensa Branch Relaxation</a>:</td><td> </td><td align="left" valign="top">Relaxation of Branches. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa-Call-Relaxation" accesskey="2">Xtensa Call Relaxation</a>:</td><td> </td><td align="left" valign="top">Relaxation of Function Calls. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa-Jump-Relaxation" accesskey="3">Xtensa Jump Relaxation</a>:</td><td> </td><td align="left" valign="top">Relaxation of Jumps. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Xtensa-Immediate-Relaxation" accesskey="4">Xtensa Immediate Relaxation</a>:</td><td> </td><td align="left" valign="top">Relaxation of other Immediate Fields. +</td></tr> +</table> + +<hr> +<a name="Xtensa-Branch-Relaxation"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa-Call-Relaxation" accesskey="n" rel="next">Xtensa Call Relaxation</a>, Up: <a href="#Xtensa-Relaxation" accesskey="u" rel="up">Xtensa Relaxation</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Conditional-Branch-Relaxation"></a> +<h4 class="subsubsection">9.55.4.1 Conditional Branch Relaxation</h4> +<a name="index-relaxation-of-branch-instructions"></a> +<a name="index-branch-instructions_002c-relaxation"></a> + +<p>When the target of a branch is too far away from the branch itself, +i.e., when the offset from the branch to the target is too large to fit +in the immediate field of the branch instruction, it may be necessary to +replace the branch with a branch around a jump. For example, +</p> +<div class="smallexample"> +<pre class="smallexample"> beqz a2, L +</pre></div> + +<p>may result in: +</p> +<div class="smallexample"> +<pre class="smallexample"> bnez.n a2, M + j L +M: +</pre></div> + +<p>(The <code>BNEZ.N</code> instruction would be used in this example only if the +density option is available. Otherwise, <code>BNEZ</code> would be used.) +</p> +<p>This relaxation works well because the unconditional jump instruction +has a much larger offset range than the various conditional branches. +However, an error will occur if a branch target is beyond the range of a +jump instruction. <code>as</code> cannot relax unconditional jumps. +Similarly, an error will occur if the original input contains an +unconditional jump to a target that is out of range. +</p> +<p>Branch relaxation is enabled by default. It can be disabled by using +underscore prefixes (see <a href="#Xtensa-Opcodes">Opcode Names</a>), the +‘<samp>--no-transform</samp>’ command-line option (see <a href="#Xtensa-Options">Command-line Options</a>), or the <code>no-transform</code> directive +(see <a href="#Transform-Directive">transform</a>). +</p> +<hr> +<a name="Xtensa-Call-Relaxation"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa-Jump-Relaxation" accesskey="n" rel="next">Xtensa Jump Relaxation</a>, Previous: <a href="#Xtensa-Branch-Relaxation" accesskey="p" rel="previous">Xtensa Branch Relaxation</a>, Up: <a href="#Xtensa-Relaxation" accesskey="u" rel="up">Xtensa Relaxation</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Function-Call-Relaxation"></a> +<h4 class="subsubsection">9.55.4.2 Function Call Relaxation</h4> +<a name="index-relaxation-of-call-instructions"></a> +<a name="index-call-instructions_002c-relaxation"></a> + +<p>Function calls may require relaxation because the Xtensa immediate call +instructions (<code>CALL0</code>, <code>CALL4</code>, <code>CALL8</code> and +<code>CALL12</code>) provide a PC-relative offset of only 512 Kbytes in either +direction. For larger programs, it may be necessary to use indirect +calls (<code>CALLX0</code>, <code>CALLX4</code>, <code>CALLX8</code> and <code>CALLX12</code>) +where the target address is specified in a register. The Xtensa +assembler can automatically relax immediate call instructions into +indirect call instructions. This relaxation is done by loading the +address of the called function into the callee’s return address register +and then using a <code>CALLX</code> instruction. So, for example: +</p> +<div class="smallexample"> +<pre class="smallexample"> call8 func +</pre></div> + +<p>might be relaxed to: +</p> +<div class="smallexample"> +<pre class="smallexample"> .literal .L1, func + l32r a8, .L1 + callx8 a8 +</pre></div> + +<p>Because the addresses of targets of function calls are not generally +known until link-time, the assembler must assume the worst and relax all +the calls to functions in other source files, not just those that really +will be out of range. The linker can recognize calls that were +unnecessarily relaxed, and it will remove the overhead introduced by the +assembler for those cases where direct calls are sufficient. +</p> +<p>Call relaxation is disabled by default because it can have a negative +effect on both code size and performance, although the linker can +usually eliminate the unnecessary overhead. If a program is too large +and some of the calls are out of range, function call relaxation can be +enabled using the ‘<samp>--longcalls</samp>’ command-line option or the +<code>longcalls</code> directive (see <a href="#Longcalls-Directive">longcalls</a>). +</p> +<hr> +<a name="Xtensa-Jump-Relaxation"></a> +<div class="header"> +<p> +Next: <a href="#Xtensa-Immediate-Relaxation" accesskey="n" rel="next">Xtensa Immediate Relaxation</a>, Previous: <a href="#Xtensa-Call-Relaxation" accesskey="p" rel="previous">Xtensa Call Relaxation</a>, Up: <a href="#Xtensa-Relaxation" accesskey="u" rel="up">Xtensa Relaxation</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Jump-Relaxation"></a> +<h4 class="subsubsection">9.55.4.3 Jump Relaxation</h4> +<a name="index-relaxation-of-jump-instructions"></a> +<a name="index-jump-instructions_002c-relaxation"></a> + +<p>Jump instruction may require relaxation because the Xtensa jump instruction +(<code>J</code>) provide a PC-relative offset of only 128 Kbytes in either +direction. One option is to use jump long (<code>J.L</code>) instruction, which +depending on jump distance may be assembled as jump (<code>J</code>) or indirect +jump (<code>JX</code>). However it needs a free register. When there’s no spare +register it is possible to plant intermediate jump sites (trampolines) +between the jump instruction and its target. These sites may be located in +areas unreachable by normal code execution flow, in that case they only +contain intermediate jumps, or they may be inserted in the middle of code +block, in which case there’s an additional jump from the beginning of the +trampoline to the instruction past its end. So, for example: +</p> +<div class="smallexample"> +<pre class="smallexample"> j 1f + ... + retw + ... + mov a10, a2 + call8 func + ... +1: + ... +</pre></div> + +<p>might be relaxed to: +</p> +<div class="smallexample"> +<pre class="smallexample"> j .L0_TR_1 + ... + retw +.L0_TR_1: + j 1f + ... + mov a10, a2 + call8 func + ... +1: + ... +</pre></div> + +<p>or to: +</p> +<div class="smallexample"> +<pre class="smallexample"> j .L0_TR_1 + ... + retw + ... + mov a10, a2 + j .L0_TR_0 +.L0_TR_1: + j 1f +.L0_TR_0: + call8 func + ... +1: + ... +</pre></div> + +<p>The Xtensa assembler uses trampolines with jump around only when it cannot +find suitable unreachable trampoline. There may be multiple trampolines +between the jump instruction and its target. +</p> +<p>This relaxation does not apply to jumps to undefined symbols, assuming they +will reach their targets once resolved. +</p> +<p>Jump relaxation is enabled by default because it does not affect code size +or performance while the code itself is small. This relaxation may be +disabled completely with ‘<samp>--no-trampolines</samp>’ or ‘<samp>--no-transform</samp>’ +command-line options (see <a href="#Xtensa-Options">Command-line Options</a>). +</p> +<hr> +<a name="Xtensa-Immediate-Relaxation"></a> +<div class="header"> +<p> +Previous: <a href="#Xtensa-Jump-Relaxation" accesskey="p" rel="previous">Xtensa Jump Relaxation</a>, Up: <a href="#Xtensa-Relaxation" accesskey="u" rel="up">Xtensa Relaxation</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Other-Immediate-Field-Relaxation"></a> +<h4 class="subsubsection">9.55.4.4 Other Immediate Field Relaxation</h4> +<a name="index-immediate-fields_002c-relaxation"></a> +<a name="index-relaxation-of-immediate-fields"></a> + +<p>The assembler normally performs the following other relaxations. They +can be disabled by using underscore prefixes (see <a href="#Xtensa-Opcodes">Opcode Names</a>), the ‘<samp>--no-transform</samp>’ command-line option +(see <a href="#Xtensa-Options">Command-line Options</a>), or the +<code>no-transform</code> directive (see <a href="#Transform-Directive">transform</a>). +</p> +<a name="index-MOVI-instructions_002c-relaxation"></a> +<a name="index-relaxation-of-MOVI-instructions"></a> +<p>The <code>MOVI</code> machine instruction can only materialize values in the +range from -2048 to 2047. Values outside this range are best +materialized with <code>L32R</code> instructions. Thus: +</p> +<div class="smallexample"> +<pre class="smallexample"> movi a0, 100000 +</pre></div> + +<p>is assembled into the following machine code: +</p> +<div class="smallexample"> +<pre class="smallexample"> .literal .L1, 100000 + l32r a0, .L1 +</pre></div> + +<a name="index-L8UI-instructions_002c-relaxation"></a> +<a name="index-L16SI-instructions_002c-relaxation"></a> +<a name="index-L16UI-instructions_002c-relaxation"></a> +<a name="index-L32I-instructions_002c-relaxation"></a> +<a name="index-relaxation-of-L8UI-instructions"></a> +<a name="index-relaxation-of-L16SI-instructions"></a> +<a name="index-relaxation-of-L16UI-instructions"></a> +<a name="index-relaxation-of-L32I-instructions"></a> +<p>The <code>L8UI</code> machine instruction can only be used with immediate +offsets in the range from 0 to 255. The <code>L16SI</code> and <code>L16UI</code> +machine instructions can only be used with offsets from 0 to 510. The +<code>L32I</code> machine instruction can only be used with offsets from 0 to +1020. A load offset outside these ranges can be materialized with +an <code>L32R</code> instruction if the destination register of the load +is different than the source address register. For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> l32i a1, a0, 2040 +</pre></div> + +<p>is translated to: +</p> +<div class="smallexample"> +<pre class="smallexample"> .literal .L1, 2040 + l32r a1, .L1 +</pre><pre class="smallexample"> add a1, a0, a1 + l32i a1, a1, 0 +</pre></div> + +<p>If the load destination and source address register are the same, an +out-of-range offset causes an error. +</p> +<a name="index-ADDI-instructions_002c-relaxation"></a> +<a name="index-relaxation-of-ADDI-instructions"></a> +<p>The Xtensa <code>ADDI</code> instruction only allows immediate operands in the +range from -128 to 127. There are a number of alternate instruction +sequences for the <code>ADDI</code> operation. First, if the +immediate is 0, the <code>ADDI</code> will be turned into a <code>MOV.N</code> +instruction (or the equivalent <code>OR</code> instruction if the code density +option is not available). If the <code>ADDI</code> immediate is outside of +the range -128 to 127, but inside the range -32896 to 32639, an +<code>ADDMI</code> instruction or <code>ADDMI</code>/<code>ADDI</code> sequence will be +used. Finally, if the immediate is outside of this range and a free +register is available, an <code>L32R</code>/<code>ADD</code> sequence will be used +with a literal allocated from the literal pool. +</p> +<p>For example: +</p> +<div class="smallexample"> +<pre class="smallexample"> addi a5, a6, 0 + addi a5, a6, 512 +</pre><pre class="smallexample"> addi a5, a6, 513 + addi a5, a6, 50000 +</pre></div> + +<p>is assembled into the following: +</p> +<div class="smallexample"> +<pre class="smallexample"> .literal .L1, 50000 + mov.n a5, a6 +</pre><pre class="smallexample"> addmi a5, a6, 0x200 + addmi a5, a6, 0x200 + addi a5, a5, 1 +</pre><pre class="smallexample"> l32r a5, .L1 + add a5, a6, a5 +</pre></div> + +<hr> +<a name="Xtensa-Directives"></a> +<div class="header"> +<p> +Previous: <a href="#Xtensa-Relaxation" accesskey="p" rel="previous">Xtensa Relaxation</a>, Up: <a href="#Xtensa_002dDependent" accesskey="u" rel="up">Xtensa-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Directives-3"></a> +<h4 class="subsection">9.55.5 Directives</h4> +<a name="index-Xtensa-directives"></a> +<a name="index-directives_002c-Xtensa"></a> + +<p>The Xtensa assembler supports a region-based directive syntax: +</p> +<div class="smallexample"> +<pre class="smallexample"> .begin <var>directive</var> [<var>options</var>] + … + .end <var>directive</var> +</pre></div> + +<p>All the Xtensa-specific directives that apply to a region of code use +this syntax. +</p> +<p>The directive applies to code between the <code>.begin</code> and the +<code>.end</code>. The state of the option after the <code>.end</code> reverts to +what it was before the <code>.begin</code>. +A nested <code>.begin</code>/<code>.end</code> region can further +change the state of the directive without having to be aware of its +outer state. For example, consider: +</p> +<div class="smallexample"> +<pre class="smallexample"> .begin no-transform +L: add a0, a1, a2 +</pre><pre class="smallexample"> .begin transform +M: add a0, a1, a2 + .end transform +</pre><pre class="smallexample">N: add a0, a1, a2 + .end no-transform +</pre></div> + +<p>The <code>ADD</code> opcodes at <code>L</code> and <code>N</code> in the outer +<code>no-transform</code> region both result in <code>ADD</code> machine instructions, +but the assembler selects an <code>ADD.N</code> instruction for the +<code>ADD</code> at <code>M</code> in the inner <code>transform</code> region. +</p> +<p>The advantage of this style is that it works well inside macros which can +preserve the context of their callers. +</p> +<p>The following directives are available: +</p><table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Schedule-Directive" accesskey="1">Schedule Directive</a>:</td><td> </td><td align="left" valign="top">Enable instruction scheduling. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Longcalls-Directive" accesskey="2">Longcalls Directive</a>:</td><td> </td><td align="left" valign="top">Use Indirect Calls for Greater Range. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Transform-Directive" accesskey="3">Transform Directive</a>:</td><td> </td><td align="left" valign="top">Disable All Assembler Transformations. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Literal-Directive" accesskey="4">Literal Directive</a>:</td><td> </td><td align="left" valign="top">Intermix Literals with Instructions. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Literal-Position-Directive" accesskey="5">Literal Position Directive</a>:</td><td> </td><td align="left" valign="top">Specify Inline Literal Pool Locations. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Literal-Prefix-Directive" accesskey="6">Literal Prefix Directive</a>:</td><td> </td><td align="left" valign="top">Specify Literal Section Name Prefix. +</td></tr> +<tr><td align="left" valign="top">• <a href="#Absolute-Literals-Directive" accesskey="7">Absolute Literals Directive</a>:</td><td> </td><td align="left" valign="top">Control PC-Relative vs. Absolute Literals. +</td></tr> +</table> + +<hr> +<a name="Schedule-Directive"></a> +<div class="header"> +<p> +Next: <a href="#Longcalls-Directive" accesskey="n" rel="next">Longcalls Directive</a>, Up: <a href="#Xtensa-Directives" accesskey="u" rel="up">Xtensa Directives</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="schedule"></a> +<h4 class="subsubsection">9.55.5.1 schedule</h4> +<a name="index-schedule-directive"></a> +<a name="index-no_002dschedule-directive"></a> + +<p>The <code>schedule</code> directive is recognized only for compatibility with +Tensilica’s assembler. +</p> +<div class="smallexample"> +<pre class="smallexample"> .begin [no-]schedule + .end [no-]schedule +</pre></div> + +<p>This directive is ignored and has no effect on <code>as</code>. +</p> +<hr> +<a name="Longcalls-Directive"></a> +<div class="header"> +<p> +Next: <a href="#Transform-Directive" accesskey="n" rel="next">Transform Directive</a>, Previous: <a href="#Schedule-Directive" accesskey="p" rel="previous">Schedule Directive</a>, Up: <a href="#Xtensa-Directives" accesskey="u" rel="up">Xtensa Directives</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="longcalls"></a> +<h4 class="subsubsection">9.55.5.2 longcalls</h4> +<a name="index-longcalls-directive"></a> +<a name="index-no_002dlongcalls-directive"></a> + +<p>The <code>longcalls</code> directive enables or disables function call +relaxation. See <a href="#Xtensa-Call-Relaxation">Function Call Relaxation</a>. +</p> +<div class="smallexample"> +<pre class="smallexample"> .begin [no-]longcalls + .end [no-]longcalls +</pre></div> + +<p>Call relaxation is disabled by default unless the ‘<samp>--longcalls</samp>’ +command-line option is specified. The <code>longcalls</code> directive +overrides the default determined by the command-line options. +</p> +<hr> +<a name="Transform-Directive"></a> +<div class="header"> +<p> +Next: <a href="#Literal-Directive" accesskey="n" rel="next">Literal Directive</a>, Previous: <a href="#Longcalls-Directive" accesskey="p" rel="previous">Longcalls Directive</a>, Up: <a href="#Xtensa-Directives" accesskey="u" rel="up">Xtensa Directives</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="transform"></a> +<h4 class="subsubsection">9.55.5.3 transform</h4> +<a name="index-transform-directive"></a> +<a name="index-no_002dtransform-directive"></a> + +<p>This directive enables or disables all assembler transformation, +including relaxation (see <a href="#Xtensa-Relaxation">Xtensa Relaxation</a>) and +optimization (see <a href="#Xtensa-Optimizations">Xtensa Optimizations</a>). +</p> +<div class="smallexample"> +<pre class="smallexample"> .begin [no-]transform + .end [no-]transform +</pre></div> + +<p>Transformations are enabled by default unless the ‘<samp>--no-transform</samp>’ +option is used. The <code>transform</code> directive overrides the default +determined by the command-line options. An underscore opcode prefix, +disabling transformation of that opcode, always takes precedence over +both directives and command-line flags. +</p> +<hr> +<a name="Literal-Directive"></a> +<div class="header"> +<p> +Next: <a href="#Literal-Position-Directive" accesskey="n" rel="next">Literal Position Directive</a>, Previous: <a href="#Transform-Directive" accesskey="p" rel="previous">Transform Directive</a>, Up: <a href="#Xtensa-Directives" accesskey="u" rel="up">Xtensa Directives</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="literal"></a> +<h4 class="subsubsection">9.55.5.4 literal</h4> +<a name="index-literal-directive"></a> + +<p>The <code>.literal</code> directive is used to define literal pool data, i.e., +read-only 32-bit data accessed via <code>L32R</code> instructions. +</p> +<div class="smallexample"> +<pre class="smallexample"> .literal <var>label</var>, <var>value</var>[, <var>value</var>…] +</pre></div> + +<p>This directive is similar to the standard <code>.word</code> directive, except +that the actual location of the literal data is determined by the +assembler and linker, not by the position of the <code>.literal</code> +directive. Using this directive gives the assembler freedom to locate +the literal data in the most appropriate place and possibly to combine +identical literals. For example, the code: +</p> +<div class="smallexample"> +<pre class="smallexample"> entry sp, 40 + .literal .L1, sym + l32r a4, .L1 +</pre></div> + +<p>can be used to load a pointer to the symbol <code>sym</code> into register +<code>a4</code>. The value of <code>sym</code> will not be placed between the +<code>ENTRY</code> and <code>L32R</code> instructions; instead, the assembler puts +the data in a literal pool. +</p> +<p>Literal pools are placed by default in separate literal sections; +however, when using the ‘<samp>--text-section-literals</samp>’ +option (see <a href="#Xtensa-Options">Command-line Options</a>), the literal +pools for PC-relative mode <code>L32R</code> instructions +are placed in the current section.<a name="DOCF3" href="#FOOT3"><sup>3</sup></a> +These text section literal +pools are created automatically before <code>ENTRY</code> instructions and +manually after ‘<samp>.literal_position</samp>’ directives (see <a href="#Literal-Position-Directive">literal_position</a>). If there are no preceding +<code>ENTRY</code> instructions, explicit <code>.literal_position</code> directives +must be used to place the text section literal pools; otherwise, +<code>as</code> will report an error. +</p> +<p>When literals are placed in separate sections, the literal section names +are derived from the names of the sections where the literals are +defined. The base literal section names are <code>.literal</code> for +PC-relative mode <code>L32R</code> instructions and <code>.lit4</code> for absolute +mode <code>L32R</code> instructions (see <a href="#Absolute-Literals-Directive">absolute-literals</a>). These base names are used for literals defined in +the default <code>.text</code> section. For literals defined in other +sections or within the scope of a <code>literal_prefix</code> directive +(see <a href="#Literal-Prefix-Directive">literal_prefix</a>), the following rules +determine the literal section name: +</p> +<ol> +<li> If the current section is a member of a section group, the literal +section name includes the group name as a suffix to the base +<code>.literal</code> or <code>.lit4</code> name, with a period to separate the base +name and group name. The literal section is also made a member of the +group. + +</li><li> If the current section name (or <code>literal_prefix</code> value) begins with +“<code>.gnu.linkonce.<var>kind</var>.</code>”, the literal section name is formed +by replacing “<code>.<var>kind</var></code>” with the base <code>.literal</code> or +<code>.lit4</code> name. For example, for literals defined in a section named +<code>.gnu.linkonce.t.func</code>, the literal section will be +<code>.gnu.linkonce.literal.func</code> or <code>.gnu.linkonce.lit4.func</code>. + +</li><li> If the current section name (or <code>literal_prefix</code> value) ends with +<code>.text</code>, the literal section name is formed by replacing that +suffix with the base <code>.literal</code> or <code>.lit4</code> name. For example, +for literals defined in a section named <code>.iram0.text</code>, the literal +section will be <code>.iram0.literal</code> or <code>.iram0.lit4</code>. + +</li><li> If none of the preceding conditions apply, the literal section name is +formed by adding the base <code>.literal</code> or <code>.lit4</code> name as a +suffix to the current section name (or <code>literal_prefix</code> value). +</li></ol> + +<hr> +<a name="Literal-Position-Directive"></a> +<div class="header"> +<p> +Next: <a href="#Literal-Prefix-Directive" accesskey="n" rel="next">Literal Prefix Directive</a>, Previous: <a href="#Literal-Directive" accesskey="p" rel="previous">Literal Directive</a>, Up: <a href="#Xtensa-Directives" accesskey="u" rel="up">Xtensa Directives</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="literal_005fposition"></a> +<h4 class="subsubsection">9.55.5.5 literal_position</h4> +<a name="index-literal_005fposition-directive"></a> + +<p>When using ‘<samp>--text-section-literals</samp>’ to place literals inline +in the section being assembled, the <code>.literal_position</code> directive +can be used to mark a potential location for a literal pool. +</p> +<div class="smallexample"> +<pre class="smallexample"> .literal_position +</pre></div> + +<p>The <code>.literal_position</code> directive is ignored when the +‘<samp>--text-section-literals</samp>’ option is not used or when +<code>L32R</code> instructions use the absolute addressing mode. +</p> +<p>The assembler will automatically place text section literal pools +before <code>ENTRY</code> instructions, so the <code>.literal_position</code> +directive is only needed to specify some other location for a literal +pool. You may need to add an explicit jump instruction to skip over an +inline literal pool. +</p> +<p>For example, an interrupt vector does not begin with an <code>ENTRY</code> +instruction so the assembler will be unable to automatically find a good +place to put a literal pool. Moreover, the code for the interrupt +vector must be at a specific starting address, so the literal pool +cannot come before the start of the code. The literal pool for the +vector must be explicitly positioned in the middle of the vector (before +any uses of the literals, due to the negative offsets used by +PC-relative <code>L32R</code> instructions). The <code>.literal_position</code> +directive can be used to do this. In the following code, the literal +for ‘<samp>M</samp>’ will automatically be aligned correctly and is placed after +the unconditional jump. +</p> +<div class="smallexample"> +<pre class="smallexample"> .global M +code_start: +</pre><pre class="smallexample"> j continue + .literal_position + .align 4 +</pre><pre class="smallexample">continue: + movi a4, M +</pre></div> + +<hr> +<a name="Literal-Prefix-Directive"></a> +<div class="header"> +<p> +Next: <a href="#Absolute-Literals-Directive" accesskey="n" rel="next">Absolute Literals Directive</a>, Previous: <a href="#Literal-Position-Directive" accesskey="p" rel="previous">Literal Position Directive</a>, Up: <a href="#Xtensa-Directives" accesskey="u" rel="up">Xtensa Directives</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="literal_005fprefix"></a> +<h4 class="subsubsection">9.55.5.6 literal_prefix</h4> +<a name="index-literal_005fprefix-directive"></a> + +<p>The <code>literal_prefix</code> directive allows you to override the default +literal section names, which are derived from the names of the sections +where the literals are defined. +</p> +<div class="smallexample"> +<pre class="smallexample"> .begin literal_prefix [<var>name</var>] + .end literal_prefix +</pre></div> + +<p>For literals defined within the delimited region, the literal section +names are derived from the <var>name</var> argument instead of the name of +the current section. The rules used to derive the literal section names +do not change. See <a href="#Literal-Directive">literal</a>. If the <var>name</var> +argument is omitted, the literal sections revert to the defaults. This +directive has no effect when using the +‘<samp>--text-section-literals</samp>’ option (see <a href="#Xtensa-Options">Command-line Options</a>). +</p> +<hr> +<a name="Absolute-Literals-Directive"></a> +<div class="header"> +<p> +Previous: <a href="#Literal-Prefix-Directive" accesskey="p" rel="previous">Literal Prefix Directive</a>, Up: <a href="#Xtensa-Directives" accesskey="u" rel="up">Xtensa Directives</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="absolute_002dliterals"></a> +<h4 class="subsubsection">9.55.5.7 absolute-literals</h4> +<a name="index-absolute_002dliterals-directive"></a> +<a name="index-no_002dabsolute_002dliterals-directive"></a> + +<p>The <code>absolute-literals</code> and <code>no-absolute-literals</code> +directives control the absolute vs. PC-relative mode for <code>L32R</code> +instructions. These are relevant only for Xtensa configurations that +include the absolute addressing option for <code>L32R</code> instructions. +</p> +<div class="smallexample"> +<pre class="smallexample"> .begin [no-]absolute-literals + .end [no-]absolute-literals +</pre></div> + +<p>These directives do not change the <code>L32R</code> mode—they only cause +the assembler to emit the appropriate kind of relocation for <code>L32R</code> +instructions and to place the literal values in the appropriate section. +To change the <code>L32R</code> mode, the program must write the +<code>LITBASE</code> special register. It is the programmer’s responsibility +to keep track of the mode and indicate to the assembler which mode is +used in each region of code. +</p> +<p>If the Xtensa configuration includes the absolute <code>L32R</code> addressing +option, the default is to assume absolute <code>L32R</code> addressing unless +the ‘<samp>--no-absolute-literals</samp>’ command-line option is specified. +Otherwise, the default is to assume PC-relative <code>L32R</code> addressing. +The <code>absolute-literals</code> directive can then be used to override +the default determined by the command-line options. +</p> + + +<hr> +<a name="Z80_002dDependent"></a> +<div class="header"> +<p> +Next: <a href="#Z8000_002dDependent" accesskey="n" rel="next">Z8000-Dependent</a>, Previous: <a href="#Xtensa_002dDependent" accesskey="p" rel="previous">Xtensa-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Z80-Dependent-Features"></a> +<h3 class="section">9.56 Z80 Dependent Features</h3> + + + +<a name="index-Z80-support"></a> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Z80-Options" accesskey="1">Z80 Options</a>:</td><td> </td><td align="left" valign="top">Options +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z80-Syntax" accesskey="2">Z80 Syntax</a>:</td><td> </td><td align="left" valign="top">Syntax +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z80-Floating-Point" accesskey="3">Z80 Floating Point</a>:</td><td> </td><td align="left" valign="top">Floating Point +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z80-Directives" accesskey="4">Z80 Directives</a>:</td><td> </td><td align="left" valign="top">Z80 Machine Directives +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z80-Opcodes" accesskey="5">Z80 Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="Z80-Options"></a> +<div class="header"> +<p> +Next: <a href="#Z80-Syntax" accesskey="n" rel="next">Z80 Syntax</a>, Up: <a href="#Z80_002dDependent" accesskey="u" rel="up">Z80-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Command_002dline-Options-3"></a> +<h4 class="subsection">9.56.1 Command-line Options</h4> +<a name="index-Z80-options"></a> +<a name="index-options-for-Z80"></a> +<dl compact="compact"> +<dd> +<a name="index-_002dmarch_003d-command_002dline-option_002c-Z80"></a> +</dd> +<dt><code>-march=<var>CPU</var>[-<var>EXT</var>…][+<var>EXT</var>…]</code></dt> +<dd><p>This option specifies the target processor. The assembler will issue +an error message if an attempt is made to assemble an instruction which +will not execute on the target processor. The following processor names +are recognized: +<code>z80</code>, +<code>z180</code>, +<code>ez80</code>, +<code>gbz80</code>, +<code>z80n</code>, +<code>r800</code>. +In addition to the basic instruction set, the assembler can be told to +accept some extention mnemonics. For example, +<code>-march=z180+sli+infc</code> extends <var>z180</var> with <var>SLI</var> instructions and +<var>IN F,(C)</var>. The following extentions are currently supported: +<code>full</code> (all known instructions), +<code>adl</code> (ADL CPU mode by default, eZ80 only), +<code>sli</code> (instruction known as <var>SLI</var>, <var>SLL</var> or <var>SL1</var>), +<code>xyhl</code> (instructions with halves of index registers: <var>IXL</var>, <var>IXH</var>, +<var>IYL</var>, <var>IYH</var>), +<code>xdcb</code> (instructions like <var>RotOp (II+d),R</var> and <var>BitOp n,(II+d),R</var>), +<code>infc</code> (instruction <var>IN F,(C)</var> or <var>IN (C)</var>), +<code>outc0</code> (instruction <var>OUT (C),0</var>). +Note that rather than extending a basic instruction set, the extention +mnemonics starting with <code>-</code> revoke the respective functionality: +<code>-march=z80-full+xyhl</code> first removes all default extentions and adds +support for index registers halves only. +</p> +<p>If this option is not specified then <code>-march=z80+xyhl+infc</code> is assumed. +</p> +<a name="index-_002dlocal_002dprefix-command_002dline-option_002c-Z80"></a> +</dd> +<dt><code>-local-prefix=<var>prefix</var></code></dt> +<dd><p>Mark all labels with specified prefix as local. But such label can be +marked global explicitly in the code. This option do not change default +local label prefix <code>.L</code>, it is just adds new one. +</p> +<a name="index-_002dcolonless-command_002dline-option_002c-Z80"></a> +</dd> +<dt><code>-colonless</code></dt> +<dd><p>Accept colonless labels. All symbols at line begin are treated as labels. +</p> +<a name="index-_002dsdcc-command_002dline-option_002c-Z80"></a> +</dd> +<dt><code>-sdcc</code></dt> +<dd><p>Accept assembler code produced by SDCC. +</p> +<a name="index-_002dfp_002ds-command_002dline-option_002c-Z80"></a> +</dd> +<dt><code>-fp-s=<var>FORMAT</var></code></dt> +<dd><p>Single precision floating point numbers format. Default: ieee754 (32 bit). +</p> +<a name="index-_002dfp_002dd-command_002dline-option_002c-Z80"></a> +</dd> +<dt><code>-fp-d=<var>FORMAT</var></code></dt> +<dd><p>Double precision floating point numbers format. Default: ieee754 (64 bit). +</p></dd> +</dl> + +<p>Floating point numbers formats. +</p><dl compact="compact"> +<dt><samp><code>ieee754</code></samp></dt> +<dd><p>Single or double precision IEEE754 compatible format. +</p> +</dd> +<dt><samp><code>half</code></samp></dt> +<dd><p>Half precision IEEE754 compatible format (16 bits). +</p> +</dd> +<dt><samp><code>single</code></samp></dt> +<dd><p>Single precision IEEE754 compatible format (32 bits). +</p> +</dd> +<dt><samp><code>double</code></samp></dt> +<dd><p>Double precision IEEE754 compatible format (64 bits). +</p> +</dd> +<dt><samp><code>zeda32</code></samp></dt> +<dd><p>32 bit floating point format from z80float library by Zeda. +</p> +</dd> +<dt><samp><code>math48</code></samp></dt> +<dd><p>48 bit floating point format from Math48 package by Anders Hejlsberg. +</p></dd> +</dl> + +<a name="index-Z80-Syntax"></a> +<hr> +<a name="Z80-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#Z80-Floating-Point" accesskey="n" rel="next">Z80 Floating Point</a>, Previous: <a href="#Z80-Options" accesskey="p" rel="previous">Z80 Options</a>, Up: <a href="#Z80_002dDependent" accesskey="u" rel="up">Z80-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-35"></a> +<h4 class="subsection">9.56.2 Syntax</h4> +<p>The assembler syntax closely follows the ’Z80 family CPU User Manual’ by +Zilog. +In expressions a single ‘<samp>=</samp>’ may be used as “is equal to” +comparison operator. +</p> +<p>Suffices can be used to indicate the radix of integer constants; +‘<samp>H</samp>’ or ‘<samp>h</samp>’ for hexadecimal, ‘<samp>D</samp>’ or ‘<samp>d</samp>’ for decimal, +‘<samp>Q</samp>’, ‘<samp>O</samp>’, ‘<samp>q</samp>’ or ‘<samp>o</samp>’ for octal, and ‘<samp>B</samp>’ for +binary. +</p> +<p>The suffix ‘<samp>b</samp>’ denotes a backreference to local label. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Z80_002dChars" accesskey="1">Z80-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z80_002dRegs" accesskey="2">Z80-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z80_002dCase" accesskey="3">Z80-Case</a>:</td><td> </td><td align="left" valign="top">Case Sensitivity +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z80_002dLabels" accesskey="4">Z80-Labels</a>:</td><td> </td><td align="left" valign="top">Labels +</td></tr> +</table> + +<hr> +<a name="Z80_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#Z80_002dRegs" accesskey="n" rel="next">Z80-Regs</a>, Up: <a href="#Z80-Syntax" accesskey="u" rel="up">Z80 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-42"></a> +<h4 class="subsubsection">9.56.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-Z80"></a> +<a name="index-Z80-line-comment-character"></a> +<p>The semicolon ‘<samp>;</samp>’ is the line comment character; +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-Z80"></a> +<a name="index-statement-separator_002c-Z80"></a> +<a name="index-Z80-line-separator"></a> +<p>The Z80 assembler does not support a line separator character. +</p> +<a name="index-location-counter_002c-Z80"></a> +<a name="index-hexadecimal-prefix_002c-Z80"></a> +<a name="index-Z80-_0024"></a> +<p>The dollar sign ‘<samp>$</samp>’ can be used as a prefix for hexadecimal numbers +and as a symbol denoting the current location counter. +</p> +<a name="index-character-escapes_002c-Z80"></a> +<a name="index-Z80_002c-_005c"></a> +<p>A backslash ‘<samp>\</samp>’ is an ordinary character for the Z80 assembler. +</p> +<a name="index-character-constant_002c-Z80"></a> +<a name="index-single-quote_002c-Z80"></a> +<a name="index-Z80-_0027"></a> +<p>The single quote ‘<samp>'</samp>’ must be followed by a closing quote. If there +is one character in between, it is a character constant, otherwise it is +a string constant. +</p> +<hr> +<a name="Z80_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#Z80_002dCase" accesskey="n" rel="next">Z80-Case</a>, Previous: <a href="#Z80_002dChars" accesskey="p" rel="previous">Z80-Chars</a>, Up: <a href="#Z80-Syntax" accesskey="u" rel="up">Z80 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-22"></a> +<h4 class="subsubsection">9.56.2.2 Register Names</h4> +<a name="index-Z80-registers"></a> +<a name="index-register-names_002c-Z80"></a> + +<p>The registers are referred to with the letters assigned to them by +Zilog. In addition <code>as</code> recognizes ‘<samp>ixl</samp>’ and +‘<samp>ixh</samp>’ as the least and most significant octet in ‘<samp>ix</samp>’, and +similarly ‘<samp>iyl</samp>’ and ‘<samp>iyh</samp>’ as parts of ‘<samp>iy</samp>’. +</p> + +<hr> +<a name="Z80_002dCase"></a> +<div class="header"> +<p> +Next: <a href="#Z80_002dLabels" accesskey="n" rel="next">Z80-Labels</a>, Previous: <a href="#Z80_002dRegs" accesskey="p" rel="previous">Z80-Regs</a>, Up: <a href="#Z80-Syntax" accesskey="u" rel="up">Z80 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Case-Sensitivity"></a> +<h4 class="subsubsection">9.56.2.3 Case Sensitivity</h4> +<a name="index-Z80_002c-case-sensitivity"></a> +<a name="index-case-sensitivity_002c-Z80"></a> + +<p>Upper and lower case are equivalent in register names, opcodes, +condition codes and assembler directives. +The case of letters is significant in labels and symbol names. The case +is also important to distinguish the suffix ‘<samp>b</samp>’ for a backward reference +to a local label from the suffix ‘<samp>B</samp>’ for a number in binary notation. +</p> +<hr> +<a name="Z80_002dLabels"></a> +<div class="header"> +<p> +Previous: <a href="#Z80_002dCase" accesskey="p" rel="previous">Z80-Case</a>, Up: <a href="#Z80-Syntax" accesskey="u" rel="up">Z80 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Labels-2"></a> +<h4 class="subsubsection">9.56.2.4 Labels</h4> + +<a name="index-labels_002c-Z80"></a> +<a name="index-Z80-labels"></a> +<p>Labels started by <code>.L</code> acts as local labels. You may specify custom local +label prefix by <code>-local-prefix</code> command-line option. +Dollar, forward and backward local labels are supported. By default, all labels +are followed by colon. +Legacy code with colonless labels can be built with <code>-colonless</code> +command-line option specified. In this case all tokens at line begin are treated +as labels. +</p> +<hr> +<a name="Z80-Floating-Point"></a> +<div class="header"> +<p> +Next: <a href="#Z80-Directives" accesskey="n" rel="next">Z80 Directives</a>, Previous: <a href="#Z80-Syntax" accesskey="p" rel="previous">Z80 Syntax</a>, Up: <a href="#Z80_002dDependent" accesskey="u" rel="up">Z80-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Floating-Point-19"></a> +<h4 class="subsection">9.56.3 Floating Point</h4> +<a name="index-floating-point_002c-Z80"></a> +<a name="index-Z80-floating-point"></a> +<p>Floating-point numbers of following types are supported: +</p> +<dl compact="compact"> +<dt><samp><code>ieee754</code></samp></dt> +<dd><p>Supported half, single and double precision IEEE754 compatible numbers. +</p> +</dd> +<dt><samp><code>zeda32</code></samp></dt> +<dd><p>32 bit floating point numbers from z80float library by Zeda. +</p> +</dd> +<dt><samp><code>math48</code></samp></dt> +<dd><p>48 bit floating point numbers from Math48 package by Anders Hejlsberg. +</p></dd> +</dl> + +<hr> +<a name="Z80-Directives"></a> +<div class="header"> +<p> +Next: <a href="#Z80-Opcodes" accesskey="n" rel="next">Z80 Opcodes</a>, Previous: <a href="#Z80-Floating-Point" accesskey="p" rel="previous">Z80 Floating Point</a>, Up: <a href="#Z80_002dDependent" accesskey="u" rel="up">Z80-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Z80-Assembler-Directives"></a> +<h4 class="subsection">9.56.4 Z80 Assembler Directives</h4> +<a name="index-Z80_002donly-directives"></a> + +<p><code>as</code> for the Z80 supports some additional directives for +compatibility with other assemblers. +</p> +<p>These are the additional directives in <code>as</code> for the Z80: +</p> +<dl compact="compact"> +<dt><code><code>.assume ADL = <var>expression</var></code></code></dt> +<dd><a name="index-_002eassume-directive_002c-Z80"></a> +<p>Set ADL status for eZ80. Non-zero value enable compilation in ADL mode else +used Z80 mode. ADL and Z80 mode produces incompatible object code. Mixing +both of them within one binary may lead problems with disassembler. +</p> +</dd> +<dt><code><code>db <var>expression</var>|<var>string</var>[,<var>expression</var>|<var>string</var>...]</code></code></dt> +<dd><a name="index-db-directive_002c-Z80"></a> +</dd> +<dt><code><code>defb <var>expression</var>|<var>string</var>[,<var>expression</var>|<var>string</var>...]</code></code></dt> +<dd><a name="index-defb-directive_002c-Z80"></a> +</dd> +<dt><code><code>defm <var>string</var>[,<var>string</var>...]</code></code></dt> +<dd><a name="index-defm-directive_002c-Z80"></a> +<p>For each <var>string</var> the characters are copied to the object file, for +each other <var>expression</var> the value is stored in one byte. +A warning is issued in case of an overflow. +Backslash symbol in the strings is generic symbol, it cannot be used as +escape character. See <a href="#Ascii"><code>.ascii</code></a>. +</p> +</dd> +<dt><code><code>dw <var>expression</var>[,<var>expression</var>...]</code></code></dt> +<dd><a name="index-dw-directive_002c-Z80"></a> +</dd> +<dt><code><code>defw <var>expression</var>[,<var>expression</var>...]</code></code></dt> +<dd><a name="index-defw-directive_002c-Z80"></a> +<p>For each <var>expression</var> the value is stored in two bytes, ignoring +overflow. +</p> +</dd> +<dt><code><code>d24 <var>expression</var>[,<var>expression</var>...]</code></code></dt> +<dd><a name="index-d24-directive_002c-Z80"></a> +</dd> +<dt><code><code>def24 <var>expression</var>[,<var>expression</var>...]</code></code></dt> +<dd><a name="index-def24-directive_002c-Z80"></a> +<p>For each <var>expression</var> the value is stored in three bytes, ignoring +overflow. +</p> +</dd> +<dt><code><code>d32 <var>expression</var>[,<var>expression</var>...]</code></code></dt> +<dd><a name="index-d32-directive_002c-Z80"></a> +</dd> +<dt><code><code>def32 <var>expression</var>[,<var>expression</var>...]</code></code></dt> +<dd><a name="index-def32-directive_002c-Z80"></a> +<p>For each <var>expression</var> the value is stored in four bytes, ignoring +overflow. +</p> +</dd> +<dt><code><code>ds <var>count</var>[, <var>value</var>]</code></code></dt> +<dd><a name="index-ds-directive_002c-Z80"></a> +</dd> +<dt><code><code>defs <var>count</var>[, <var>value</var>]</code></code></dt> +<dd><a name="index-defs-directive_002c-Z80"></a> +<p>Fill <var>count</var> bytes in the object file with <var>value</var>, if +<var>value</var> is omitted it defaults to zero. +</p> +</dd> +<dt><code><code><var>symbol</var> defl <var>expression</var></code></code></dt> +<dd><a name="index-defl-directive_002c-Z80"></a> +<p>The <code>defl</code> directive is like <code>.set</code> but with different +syntax. See <a href="#Set"><code>.set</code></a>. +It set the value of <var>symbol</var> to <var>expression</var>. Symbols defined +with <code>defl</code> are not protected from redefinition. +</p> +</dd> +<dt><code><code><var>symbol</var> equ <var>expression</var></code></code></dt> +<dd><a name="index-equ-directive_002c-Z80"></a> +<p>The <code>equ</code> directive is like <code>.equiv</code> but with different +syntax. See <a href="#Equiv"><code>.equiv</code></a>. +It set the value of <var>symbol</var> to <var>expression</var>. It is an error +if <var>symbol</var> is already defined. Symbols defined with <code>equ</code> +are not protected from redefinition. +</p> +</dd> +<dt><code><code>psect <var>name</var></code></code></dt> +<dd><a name="index-psect-directive_002c-Z80"></a> +<p>A synonym for <code>.section</code>, no second argument should be given. +See <a href="#Section"><code>.section</code></a>. +</p> +</dd> +<dt><code><code>xdef <var>symbol</var></code></code></dt> +<dd><a name="index-xdef-directive_002c-Z80"></a> +<p>A synonym for <code>.global</code>, make <var>symbol</var> is visible to linker. +See <a href="#Global"><code>.global</code></a>. +</p> +</dd> +<dt><code><code>xref <var>name</var></code></code></dt> +<dd><a name="index-xref-directive_002c-Z80"></a> +<p>A synonym for <code>.extern</code> (<a href="#Extern"><code>.extern</code></a>). +</p> +</dd> +</dl> + +<hr> +<a name="Z80-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#Z80-Directives" accesskey="p" rel="previous">Z80 Directives</a>, Up: <a href="#Z80_002dDependent" accesskey="u" rel="up">Z80-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-22"></a> +<h4 class="subsection">9.56.5 Opcodes</h4> +<p>In line with common practice, Z80 mnemonics are used for the Z80, +Z80N, Z180, eZ80, Ascii R800 and the GameBoy Z80. +</p> +<p>In many instructions it is possible to use one of the half index +registers (‘<samp>ixl</samp>’,‘<samp>ixh</samp>’,‘<samp>iyl</samp>’,‘<samp>iyh</samp>’) in stead of an +8-bit general purpose register. This yields instructions that are +documented on the eZ80 and the R800, undocumented on the Z80 and +unsupported on the Z180. +Similarly <code>in f,(c)</code> is documented on the R800, undocumented on +the Z80 and unsupported on the Z180 and the eZ80. +</p> +<p>The assembler also supports the following undocumented Z80-instructions, +that have not been adopted in any other instruction set: +</p><dl compact="compact"> +<dt><code>out (c),0</code></dt> +<dd><p>Sends zero to the port pointed to by register <code>C</code>. +</p> +</dd> +<dt><code>sli <var>m</var></code></dt> +<dd><p>Equivalent to <code><var>m</var> = (<var>m</var><<1)+1</code>, the operand <var>m</var> can +be any operand that is valid for ‘<samp>sla</samp>’. One can use ‘<samp>sll</samp>’ as a +synonym for ‘<samp>sli</samp>’. +</p> +</dd> +<dt><code><var>op</var> (ix+<var>d</var>), <var>r</var></code></dt> +<dd><p>This is equivalent to +</p> +<div class="example"> +<pre class="example">ld <var>r</var>, (ix+<var>d</var>) +<var>op</var> <var>r</var> +ld (ix+<var>d</var>), <var>r</var> +</pre></div> + +<p>The operation ‘<samp><var>op</var></samp>’ may be any of ‘<samp>res <var>b</var>,</samp>’, +‘<samp>set <var>b</var>,</samp>’, ‘<samp>rl</samp>’, ‘<samp>rlc</samp>’, ‘<samp>rr</samp>’, ‘<samp>rrc</samp>’, +‘<samp>sla</samp>’, ‘<samp>sli</samp>’, ‘<samp>sra</samp>’ and ‘<samp>srl</samp>’, and the register +‘<samp><var>r</var></samp>’ may be any of ‘<samp>a</samp>’, ‘<samp>b</samp>’, ‘<samp>c</samp>’, ‘<samp>d</samp>’, +‘<samp>e</samp>’, ‘<samp>h</samp>’ and ‘<samp>l</samp>’. +</p> +</dd> +<dt><code><var>op</var> (iy+<var>d</var>), <var>r</var></code></dt> +<dd><p>As above, but with ‘<samp>iy</samp>’ instead of ‘<samp>ix</samp>’. +</p></dd> +</dl> + +<p>The web site at <a href="http://www.z80.info">http://www.z80.info</a> is a good starting place to +find more information on programming the Z80. +</p> +<p>You may enable or disable any of these instructions for any target CPU +even this instruction is not supported by any real CPU of this type. +Useful for custom CPU cores. +</p> +<hr> +<a name="Z8000_002dDependent"></a> +<div class="header"> +<p> +Previous: <a href="#Z80_002dDependent" accesskey="p" rel="previous">Z80-Dependent</a>, Up: <a href="#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Z8000-Dependent-Features"></a> +<h3 class="section">9.57 Z8000 Dependent Features</h3> + +<a name="index-Z8000-support"></a> +<p>The Z8000 as supports both members of the Z8000 family: the +unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with +24 bit addresses. +</p> +<p>When the assembler is in unsegmented mode (specified with the +<code>unsegm</code> directive), an address takes up one word (16 bit) +sized register. When the assembler is in segmented mode (specified with +the <code>segm</code> directive), a 24-bit address takes up a long (32 bit) +register. See <a href="#Z8000-Directives">Assembler Directives for the Z8000</a>, +for a list of other Z8000 specific assembler directives. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Z8000-Options" accesskey="1">Z8000 Options</a>:</td><td> </td><td align="left" valign="top">Command-line options for the Z8000 +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z8000-Syntax" accesskey="2">Z8000 Syntax</a>:</td><td> </td><td align="left" valign="top">Assembler syntax for the Z8000 +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z8000-Directives" accesskey="3">Z8000 Directives</a>:</td><td> </td><td align="left" valign="top">Special directives for the Z8000 +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z8000-Opcodes" accesskey="4">Z8000 Opcodes</a>:</td><td> </td><td align="left" valign="top">Opcodes +</td></tr> +</table> + +<hr> +<a name="Z8000-Options"></a> +<div class="header"> +<p> +Next: <a href="#Z8000-Syntax" accesskey="n" rel="next">Z8000 Syntax</a>, Up: <a href="#Z8000_002dDependent" accesskey="u" rel="up">Z8000-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Options-30"></a> +<h4 class="subsection">9.57.1 Options</h4> + +<a name="index-Z8000-options"></a> +<a name="index-options_002c-Z8000"></a> +<dl compact="compact"> +<dd><a name="index-_002dz8001-command_002dline-option_002c-Z8000"></a> +</dd> +<dt><samp>-z8001</samp></dt> +<dd><p>Generate segmented code by default. +</p> +<a name="index-_002dz8002-command_002dline-option_002c-Z8000"></a> +</dd> +<dt><samp>-z8002</samp></dt> +<dd><p>Generate unsegmented code by default. +</p></dd> +</dl> + +<hr> +<a name="Z8000-Syntax"></a> +<div class="header"> +<p> +Next: <a href="#Z8000-Directives" accesskey="n" rel="next">Z8000 Directives</a>, Previous: <a href="#Z8000-Options" accesskey="p" rel="previous">Z8000 Options</a>, Up: <a href="#Z8000_002dDependent" accesskey="u" rel="up">Z8000-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Syntax-36"></a> +<h4 class="subsection">9.57.2 Syntax</h4> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Z8000_002dChars" accesskey="1">Z8000-Chars</a>:</td><td> </td><td align="left" valign="top">Special Characters +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z8000_002dRegs" accesskey="2">Z8000-Regs</a>:</td><td> </td><td align="left" valign="top">Register Names +</td></tr> +<tr><td align="left" valign="top">• <a href="#Z8000_002dAddressing" accesskey="3">Z8000-Addressing</a>:</td><td> </td><td align="left" valign="top">Addressing Modes +</td></tr> +</table> + +<hr> +<a name="Z8000_002dChars"></a> +<div class="header"> +<p> +Next: <a href="#Z8000_002dRegs" accesskey="n" rel="next">Z8000-Regs</a>, Up: <a href="#Z8000-Syntax" accesskey="u" rel="up">Z8000 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Special-Characters-43"></a> +<h4 class="subsubsection">9.57.2.1 Special Characters</h4> + +<a name="index-line-comment-character_002c-Z8000"></a> +<a name="index-Z8000-line-comment-character"></a> +<p>‘<samp>!</samp>’ is the line comment character. +</p> +<p>If a ‘<samp>#</samp>’ appears as the first character of a line then the whole +line is treated as a comment, but in this case the line could also be +a logical line number directive (see <a href="#Comments">Comments</a>) or a preprocessor +control command (see <a href="#Preprocessing">Preprocessing</a>). +</p> +<a name="index-line-separator_002c-Z8000"></a> +<a name="index-statement-separator_002c-Z8000"></a> +<a name="index-Z8000-line-separator"></a> +<p>You can use ‘<samp>;</samp>’ instead of a newline to separate statements. +</p> +<hr> +<a name="Z8000_002dRegs"></a> +<div class="header"> +<p> +Next: <a href="#Z8000_002dAddressing" accesskey="n" rel="next">Z8000-Addressing</a>, Previous: <a href="#Z8000_002dChars" accesskey="p" rel="previous">Z8000-Chars</a>, Up: <a href="#Z8000-Syntax" accesskey="u" rel="up">Z8000 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Register-Names-23"></a> +<h4 class="subsubsection">9.57.2.2 Register Names</h4> + +<a name="index-Z8000-registers"></a> +<a name="index-registers_002c-Z8000"></a> +<p>The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer +to different sized groups of registers by register number, with the +prefix ‘<samp>r</samp>’ for 16 bit registers, ‘<samp>rr</samp>’ for 32 bit registers and +‘<samp>rq</samp>’ for 64 bit registers. You can also refer to the contents of +the first eight (of the sixteen 16 bit registers) by bytes. They are +named ‘<samp>rl<var>n</var></samp>’ and ‘<samp>rh<var>n</var></samp>’. +</p> +<div class="smallexample"> +<pre class="smallexample"><em>byte registers</em> +</pre><pre class="smallexample">rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 +rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 + +</pre><pre class="smallexample"><em>word registers</em> +</pre><pre class="smallexample">r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 + +</pre><pre class="smallexample"><em>long word registers</em> +</pre><pre class="smallexample">rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 + +</pre><pre class="smallexample"><em>quad word registers</em> +</pre><pre class="smallexample">rq0 rq4 rq8 rq12 +</pre></div> + +<hr> +<a name="Z8000_002dAddressing"></a> +<div class="header"> +<p> +Previous: <a href="#Z8000_002dRegs" accesskey="p" rel="previous">Z8000-Regs</a>, Up: <a href="#Z8000-Syntax" accesskey="u" rel="up">Z8000 Syntax</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Addressing-Modes-5"></a> +<h4 class="subsubsection">9.57.2.3 Addressing Modes</h4> + +<a name="index-addressing-modes_002c-Z8000"></a> +<a name="index-Z800-addressing-modes"></a> +<p>as understands the following addressing modes for the Z8000: +</p> +<dl compact="compact"> +<dt><code>rl<var>n</var></code></dt> +<dt><code>rh<var>n</var></code></dt> +<dt><code>r<var>n</var></code></dt> +<dt><code>rr<var>n</var></code></dt> +<dt><code>rq<var>n</var></code></dt> +<dd><p>Register direct: 8bit, 16bit, 32bit, and 64bit registers. +</p> +</dd> +<dt><code>@r<var>n</var></code></dt> +<dt><code>@rr<var>n</var></code></dt> +<dd><p>Indirect register: @rr<var>n</var> in segmented mode, @r<var>n</var> in unsegmented +mode. +</p> +</dd> +<dt><code><var>addr</var></code></dt> +<dd><p>Direct: the 16 bit or 24 bit address (depending on whether the assembler +is in segmented or unsegmented mode) of the operand is in the instruction. +</p> +</dd> +<dt><code>address(r<var>n</var>)</code></dt> +<dd><p>Indexed: the 16 or 24 bit address is added to the 16 bit register to produce +the final address in memory of the operand. +</p> +</dd> +<dt><code>r<var>n</var>(#<var>imm</var>)</code></dt> +<dt><code>rr<var>n</var>(#<var>imm</var>)</code></dt> +<dd><p>Base Address: the 16 or 24 bit register is added to the 16 bit sign +extended immediate displacement to produce the final address in memory +of the operand. +</p> +</dd> +<dt><code>r<var>n</var>(r<var>m</var>)</code></dt> +<dt><code>rr<var>n</var>(r<var>m</var>)</code></dt> +<dd><p>Base Index: the 16 or 24 bit register r<var>n</var> or rr<var>n</var> is added to +the sign extended 16 bit index register r<var>m</var> to produce the final +address in memory of the operand. +</p> +</dd> +<dt><code>#<var>xx</var></code></dt> +<dd><p>Immediate data <var>xx</var>. +</p></dd> +</dl> + +<hr> +<a name="Z8000-Directives"></a> +<div class="header"> +<p> +Next: <a href="#Z8000-Opcodes" accesskey="n" rel="next">Z8000 Opcodes</a>, Previous: <a href="#Z8000-Syntax" accesskey="p" rel="previous">Z8000 Syntax</a>, Up: <a href="#Z8000_002dDependent" accesskey="u" rel="up">Z8000-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Assembler-Directives-for-the-Z8000"></a> +<h4 class="subsection">9.57.3 Assembler Directives for the Z8000</h4> + +<a name="index-Z8000-directives"></a> +<a name="index-directives_002c-Z8000"></a> +<p>The Z8000 port of as includes additional assembler directives, +for compatibility with other Z8000 assemblers. These do not begin with +‘<samp>.</samp>’ (unlike the ordinary as directives). +</p> +<dl compact="compact"> +<dd><a name="index-segm"></a> +</dd> +<dt><code>segm</code></dt> +<dd><a name="index-_002ez8001"></a> +</dd> +<dt><code>.z8001</code></dt> +<dd><p>Generate code for the segmented Z8001. +</p> +<a name="index-unsegm"></a> +</dd> +<dt><code>unsegm</code></dt> +<dd><a name="index-_002ez8002"></a> +</dd> +<dt><code>.z8002</code></dt> +<dd><p>Generate code for the unsegmented Z8002. +</p> +<a name="index-name"></a> +</dd> +<dt><code>name</code></dt> +<dd><p>Synonym for <code>.file</code> +</p> +<a name="index-global"></a> +</dd> +<dt><code>global</code></dt> +<dd><p>Synonym for <code>.global</code> +</p> +<a name="index-wval"></a> +</dd> +<dt><code>wval</code></dt> +<dd><p>Synonym for <code>.word</code> +</p> +<a name="index-lval"></a> +</dd> +<dt><code>lval</code></dt> +<dd><p>Synonym for <code>.long</code> +</p> +<a name="index-bval"></a> +</dd> +<dt><code>bval</code></dt> +<dd><p>Synonym for <code>.byte</code> +</p> +<a name="index-sval"></a> +</dd> +<dt><code>sval</code></dt> +<dd><p>Assemble a string. <code>sval</code> expects one string literal, delimited by +single quotes. It assembles each byte of the string into consecutive +addresses. You can use the escape sequence ‘<samp>%<var>xx</var></samp>’ (where +<var>xx</var> represents a two-digit hexadecimal number) to represent the +character whose <small>ASCII</small> value is <var>xx</var>. Use this feature to +describe single quote and other characters that may not appear in string +literals as themselves. For example, the C statement ‘<samp>char *a = "he said \"it's 50% off\"";</samp>’<!-- /@w --> is represented in Z8000 assembly language +(shown with the assembler output in hex at the left) as +</p> +<div class="smallexample"> +<pre class="smallexample">68652073 sval 'he said %22it%27s 50%25 off%22%00' +61696420 +22697427 +73203530 +25206F66 +662200 +</pre></div> + +<a name="index-rsect"></a> +</dd> +<dt><code>rsect</code></dt> +<dd><p>synonym for <code>.section</code> +</p> +<a name="index-block"></a> +</dd> +<dt><code>block</code></dt> +<dd><p>synonym for <code>.space</code> +</p> +<a name="index-even"></a> +</dd> +<dt><code>even</code></dt> +<dd><p>special case of <code>.align</code>; aligns output to even byte boundary. +</p></dd> +</dl> + +<hr> +<a name="Z8000-Opcodes"></a> +<div class="header"> +<p> +Previous: <a href="#Z8000-Directives" accesskey="p" rel="previous">Z8000 Directives</a>, Up: <a href="#Z8000_002dDependent" accesskey="u" rel="up">Z8000-Dependent</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Opcodes-23"></a> +<h4 class="subsection">9.57.4 Opcodes</h4> + +<a name="index-Z8000-opcode-summary"></a> +<a name="index-opcode-summary_002c-Z8000"></a> +<a name="index-mnemonics_002c-Z8000"></a> +<a name="index-instruction-summary_002c-Z8000"></a> +<p>For detailed information on the Z8000 machine instruction set, see +<cite>Z8000 Technical Manual</cite>. +</p> + + + +<hr> +<a name="Reporting-Bugs"></a> +<div class="header"> +<p> +Next: <a href="#Acknowledgements" accesskey="n" rel="next">Acknowledgements</a>, Previous: <a href="#Machine-Dependencies" accesskey="p" rel="previous">Machine Dependencies</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Reporting-Bugs-1"></a> +<h2 class="chapter">10 Reporting Bugs</h2> +<a name="index-bugs-in-assembler"></a> +<a name="index-reporting-bugs-in-assembler"></a> + +<p>Your bug reports play an essential role in making <code>as</code> reliable. +</p> +<p>Reporting a bug may help you by bringing a solution to your problem, or it may +not. But in any case the principal function of a bug report is to help the +entire community by making the next version of <code>as</code> work better. +Bug reports are your contribution to the maintenance of <code>as</code>. +</p> +<p>In order for a bug report to serve its purpose, you must include the +information that enables us to fix the bug. +</p> +<table class="menu" border="0" cellspacing="0"> +<tr><td align="left" valign="top">• <a href="#Bug-Criteria" accesskey="1">Bug Criteria</a>:</td><td> </td><td align="left" valign="top">Have you found a bug? +</td></tr> +<tr><td align="left" valign="top">• <a href="#Bug-Reporting" accesskey="2">Bug Reporting</a>:</td><td> </td><td align="left" valign="top">How to report bugs +</td></tr> +</table> + +<hr> +<a name="Bug-Criteria"></a> +<div class="header"> +<p> +Next: <a href="#Bug-Reporting" accesskey="n" rel="next">Bug Reporting</a>, Up: <a href="#Reporting-Bugs" accesskey="u" rel="up">Reporting Bugs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Have-You-Found-a-Bug_003f"></a> +<h3 class="section">10.1 Have You Found a Bug?</h3> +<a name="index-bug-criteria"></a> + +<p>If you are not sure whether you have found a bug, here are some guidelines: +</p> +<ul> +<li> <a name="index-fatal-signal"></a> +<a name="index-assembler-crash"></a> +<a name="index-crash-of-assembler"></a> +If the assembler gets a fatal signal, for any input whatever, that is a +<code>as</code> bug. Reliable assemblers never crash. + +</li><li> <a name="index-error-on-valid-input"></a> +If <code>as</code> produces an error message for valid input, that is a bug. + +</li><li> <a name="index-invalid-input"></a> +If <code>as</code> does not produce an error message for invalid input, that +is a bug. However, you should note that your idea of “invalid input” might +be our idea of “an extension” or “support for traditional practice”. + +</li><li> If you are an experienced user of assemblers, your suggestions for improvement +of <code>as</code> are welcome in any case. +</li></ul> + +<hr> +<a name="Bug-Reporting"></a> +<div class="header"> +<p> +Previous: <a href="#Bug-Criteria" accesskey="p" rel="previous">Bug Criteria</a>, Up: <a href="#Reporting-Bugs" accesskey="u" rel="up">Reporting Bugs</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="How-to-Report-Bugs"></a> +<h3 class="section">10.2 How to Report Bugs</h3> +<a name="index-bug-reports"></a> +<a name="index-assembler-bugs_002c-reporting"></a> + +<p>A number of companies and individuals offer support for <small>GNU</small> products. If +you obtained <code>as</code> from a support organization, we recommend you +contact that organization first. +</p> +<p>You can find contact information for many support companies and +individuals in the file <samp>etc/SERVICE</samp> in the <small>GNU</small> Emacs +distribution. +</p> +<p>In any event, we also recommend that you send bug reports for <code>as</code> +to <a href="https://bugs.linaro.org/">https://bugs.linaro.org/</a>. +</p> +<p>The fundamental principle of reporting bugs usefully is this: +<strong>report all the facts</strong>. If you are not sure whether to state a +fact or leave it out, state it! +</p> +<p>Often people omit facts because they think they know what causes the problem +and assume that some details do not matter. Thus, you might assume that the +name of a symbol you use in an example does not matter. Well, probably it does +not, but one cannot be sure. Perhaps the bug is a stray memory reference which +happens to fetch from the location where that name is stored in memory; +perhaps, if the name were different, the contents of that location would fool +the assembler into doing the right thing despite the bug. Play it safe and +give a specific, complete example. That is the easiest thing for you to do, +and the most helpful. +</p> +<p>Keep in mind that the purpose of a bug report is to enable us to fix the bug if +it is new to us. Therefore, always write your bug reports on the assumption +that the bug has not been reported previously. +</p> +<p>Sometimes people give a few sketchy facts and ask, “Does this ring a +bell?” This cannot help us fix a bug, so it is basically useless. We +respond by asking for enough details to enable us to investigate. +You might as well expedite matters by sending them to begin with. +</p> +<p>To enable us to fix the bug, you should include all these things: +</p> +<ul> +<li> The version of <code>as</code>. <code>as</code> announces it if you start +it with the ‘<samp>--version</samp>’ argument. + +<p>Without this, we will not know whether there is any point in looking for +the bug in the current version of <code>as</code>. +</p> +</li><li> Any patches you may have applied to the <code>as</code> source. + +</li><li> The type of machine you are using, and the operating system name and +version number. + +</li><li> What compiler (and its version) was used to compile <code>as</code>—e.g. +“<code>gcc-2.7</code>”. + +</li><li> The command arguments you gave the assembler to assemble your example and +observe the bug. To guarantee you will not omit something important, list them +all. A copy of the Makefile (or the output from make) is sufficient. + +<p>If we were to try to guess the arguments, we would probably guess wrong +and then we might not encounter the bug. +</p> +</li><li> A complete input file that will reproduce the bug. If the bug is observed when +the assembler is invoked via a compiler, send the assembler source, not the +high level language source. Most compilers will produce the assembler source +when run with the ‘<samp>-S</samp>’ option. If you are using <code>gcc</code>, use +the options ‘<samp>-v --save-temps</samp>’; this will save the assembler source in a +file with an extension of <samp>.s</samp>, and also show you exactly how +<code>as</code> is being run. + +</li><li> A description of what behavior you observe that you believe is +incorrect. For example, “It gets a fatal signal.” + +<p>Of course, if the bug is that <code>as</code> gets a fatal signal, then we +will certainly notice it. But if the bug is incorrect output, we might not +notice unless it is glaringly wrong. You might as well not give us a chance to +make a mistake. +</p> +<p>Even if the problem you experience is a fatal signal, you should still say so +explicitly. Suppose something strange is going on, such as, your copy of +<code>as</code> is out of sync, or you have encountered a bug in the C +library on your system. (This has happened!) Your copy might crash and ours +would not. If you told us to expect a crash, then when ours fails to crash, we +would know that the bug was not happening for us. If you had not told us to +expect a crash, then we would not be able to draw any conclusion from our +observations. +</p> +</li><li> If you wish to suggest changes to the <code>as</code> source, send us context +diffs, as generated by <code>diff</code> with the ‘<samp>-u</samp>’, ‘<samp>-c</samp>’, or ‘<samp>-p</samp>’ +option. Always send diffs from the old file to the new file. If you even +discuss something in the <code>as</code> source, refer to it by context, not +by line number. + +<p>The line numbers in our development sources will not match those in your +sources. Your line numbers would convey no useful information to us. +</p></li></ul> + +<p>Here are some things that are not necessary: +</p> +<ul> +<li> A description of the envelope of the bug. + +<p>Often people who encounter a bug spend a lot of time investigating +which changes to the input file will make the bug go away and which +changes will not affect it. +</p> +<p>This is often time consuming and not very useful, because the way we +will find the bug is by running a single example under the debugger +with breakpoints, not by pure deduction from a series of examples. +We recommend that you save your time for something else. +</p> +<p>Of course, if you can find a simpler example to report <em>instead</em> +of the original one, that is a convenience for us. Errors in the +output will be easier to spot, running under the debugger will take +less time, and so on. +</p> +<p>However, simplification is not vital; if you do not want to do this, +report the bug anyway and send us the entire test case you used. +</p> +</li><li> A patch for the bug. + +<p>A patch for the bug does help us if it is a good one. But do not omit +the necessary information, such as the test case, on the assumption that +a patch is all we need. We might see problems with your patch and decide +to fix the problem another way, or we might not understand it at all. +</p> +<p>Sometimes with a program as complicated as <code>as</code> it is very hard to +construct an example that will make the program follow a certain path through +the code. If you do not send us the example, we will not be able to construct +one, so we will not be able to verify that the bug is fixed. +</p> +<p>And if we cannot understand what bug you are trying to fix, or why your +patch should be an improvement, we will not install it. A test case will +help us to understand. +</p> +</li><li> A guess about what the bug is or what it depends on. + +<p>Such guesses are usually wrong. Even we cannot guess right about such +things without first using the debugger to find the facts. +</p></li></ul> + +<hr> +<a name="Acknowledgements"></a> +<div class="header"> +<p> +Next: <a href="#GNU-Free-Documentation-License" accesskey="n" rel="next">GNU Free Documentation License</a>, Previous: <a href="#Reporting-Bugs" accesskey="p" rel="previous">Reporting Bugs</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="Acknowledgements-1"></a> +<h2 class="chapter">11 Acknowledgements</h2> + +<p>If you have contributed to GAS and your name isn’t listed here, +it is not meant as a slight. We just don’t know about it. Send mail to the +maintainer, and we’ll correct the situation. Currently +the maintainer is Nick Clifton (email address <code>nickc@redhat.com</code>). +</p> +<p>Dean Elsner wrote the original <small>GNU</small> assembler for the VAX.<a name="DOCF4" href="#FOOT4"><sup>4</sup></a> +</p> +<p>Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug +information and the 68k series machines, most of the preprocessing pass, and +extensive changes in <samp>messages.c</samp>, <samp>input-file.c</samp>, <samp>write.c</samp>. +</p> +<p>K. Richard Pixley maintained GAS for a while, adding various enhancements and +many bug fixes, including merging support for several processors, breaking GAS +up to handle multiple object file format back ends (including heavy rewrite, +testing, an integration of the coff and b.out back ends), adding configuration +including heavy testing and verification of cross assemblers and file splits +and renaming, converted GAS to strictly ANSI C including full prototypes, added +support for m680[34]0 and cpu32, did considerable work on i960 including a COFF +port (including considerable amounts of reverse engineering), a SPARC opcode +file rewrite, DECstation, rs6000, and hp300hpux host ports, updated “know” +assertions and made them work, much other reorganization, cleanup, and lint. +</p> +<p>Ken Raeburn wrote the high-level BFD interface code to replace most of the code +in format-specific I/O modules. +</p> +<p>The original VMS support was contributed by David L. Kashtan. Eric Youngdale +has done much work with it since. +</p> +<p>The Intel 80386 machine description was written by Eliot Dresselhaus. +</p> +<p>Minh Tran-Le at IntelliCorp contributed some AIX 386 support. +</p> +<p>The Motorola 88k machine description was contributed by Devon Bowen of Buffalo +University and Torbjorn Granlund of the Swedish Institute of Computer Science. +</p> +<p>Keith Knowles at the Open Software Foundation wrote the original MIPS back end +(<samp>tc-mips.c</samp>, <samp>tc-mips.h</samp>), and contributed Rose format support +(which hasn’t been merged in yet). Ralph Campbell worked with the MIPS code to +support a.out format. +</p> +<p>Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, +tc-h8300), and IEEE 695 object file format (obj-ieee), was written by +Steve Chamberlain of Cygnus Support. Steve also modified the COFF back end to +use BFD for some low-level operations, for use with the H8/300 and AMD 29k +targets. +</p> +<p>John Gilmore built the AMD 29000 support, added <code>.include</code> support, and +simplified the configuration of which versions accept which directives. He +updated the 68k machine description so that Motorola’s opcodes always produced +fixed-size instructions (e.g., <code>jsr</code>), while synthetic instructions +remained shrinkable (<code>jbsr</code>). John fixed many bugs, including true tested +cross-compilation support, and one bug in relaxation that took a week and +required the proverbial one-bit fix. +</p> +<p>Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the +68k, completed support for some COFF targets (68k, i386 SVR3, and SCO Unix), +added support for MIPS ECOFF and ELF targets, wrote the initial RS/6000 and +PowerPC assembler, and made a few other minor patches. +</p> +<p>Steve Chamberlain made GAS able to generate listings. +</p> +<p>Hewlett-Packard contributed support for the HP9000/300. +</p> +<p>Jeff Law wrote GAS and BFD support for the native HPPA object format (SOM) +along with a fairly extensive HPPA testsuite (for both SOM and ELF object +formats). This work was supported by both the Center for Software Science at +the University of Utah and Cygnus Support. +</p> +<p>Support for ELF format files has been worked on by Mark Eichin of Cygnus +Support (original, incomplete implementation for SPARC), Pete Hoogenboom and +Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open +Software Foundation (i386 mainly), and Ken Raeburn of Cygnus Support (sparc, +and some initial 64-bit support). +</p> +<p>Linas Vepstas added GAS support for the ESA/390 “IBM 370” architecture. +</p> +<p>Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD +support for openVMS/Alpha. +</p> +<p>Timothy Wall, Michael Hayes, and Greg Smart contributed to the various tic* +flavors. +</p> +<p>David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from Tensilica, +Inc. added support for Xtensa processors. +</p> +<p>Several engineers at Cygnus Support have also provided many small bug fixes and +configuration enhancements. +</p> +<p>Jon Beniston added support for the Lattice Mico32 architecture. +</p> +<p>Many others have contributed large or small bugfixes and enhancements. If +you have contributed significant work and are not mentioned on this list, and +want to be, let us know. Some of the history has been lost; we are not +intentionally leaving anyone out. +</p> +<hr> +<a name="GNU-Free-Documentation-License"></a> +<div class="header"> +<p> +Next: <a href="#AS-Index" accesskey="n" rel="next">AS Index</a>, Previous: <a href="#Acknowledgements" accesskey="p" rel="previous">Acknowledgements</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="GNU-Free-Documentation-License-1"></a> +<h2 class="appendix">Appendix A GNU Free Documentation License</h2> +<div align="center">Version 1.3, 3 November 2008 +</div> + +<div class="display"> +<pre class="display">Copyright © 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. +<a href="http://fsf.org/">http://fsf.org/</a> + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. +</pre></div> + +<ol> +<li> PREAMBLE + +<p>The purpose of this License is to make a manual, textbook, or other +functional and useful document <em>free</em> in the sense of freedom: to +assure everyone the effective freedom to copy and redistribute it, +with or without modifying it, either commercially or noncommercially. +Secondarily, this License preserves for the author and publisher a way +to get credit for their work, while not being considered responsible +for modifications made by others. +</p> +<p>This License is a kind of “copyleft”, which means that derivative +works of the document must themselves be free in the same sense. It +complements the GNU General Public License, which is a copyleft +license designed for free software. +</p> +<p>We have designed this License in order to use it for manuals for free +software, because free software needs free documentation: a free +program should come with manuals providing the same freedoms that the +software does. But this License is not limited to software manuals; +it can be used for any textual work, regardless of subject matter or +whether it is published as a printed book. We recommend this License +principally for works whose purpose is instruction or reference. +</p> +</li><li> APPLICABILITY AND DEFINITIONS + +<p>This License applies to any manual or other work, in any medium, that +contains a notice placed by the copyright holder saying it can be +distributed under the terms of this License. Such a notice grants a +world-wide, royalty-free license, unlimited in duration, to use that +work under the conditions stated herein. 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These Warranty +Disclaimers are considered to be included by reference in this +License, but only as regards disclaiming warranties: any other +implication that these Warranty Disclaimers may have is void and has +no effect on the meaning of this License. +</p> +</li><li> VERBATIM COPYING + +<p>You may copy and distribute the Document in any medium, either +commercially or noncommercially, provided that this License, the +copyright notices, and the license notice saying this License applies +to the Document are reproduced in all copies, and that you add no other +conditions whatsoever to those of this License. You may not use +technical measures to obstruct or control the reading or further +copying of the copies you make or distribute. However, you may accept +compensation in exchange for copies. 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In addition, you must do these things in the Modified Version: +</p> +<ol> +<li> Use in the Title Page (and on the covers, if any) a title distinct +from that of the Document, and from those of previous versions +(which should, if there were any, be listed in the History section +of the Document). You may use the same title as a previous version +if the original publisher of that version gives permission. + +</li><li> List on the Title Page, as authors, one or more persons or entities +responsible for authorship of the modifications in the Modified +Version, together with at least five of the principal authors of the +Document (all of its principal authors, if it has fewer than five), +unless they release you from this requirement. + +</li><li> State on the Title page the name of the publisher of the +Modified Version, as the publisher. + +</li><li> Preserve all the copyright notices of the Document. + +</li><li> Add an appropriate copyright notice for your modifications +adjacent to the other copyright notices. + +</li><li> Include, immediately after the copyright notices, a license notice +giving the public permission to use the Modified Version under the +terms of this License, in the form shown in the Addendum below. + +</li><li> Preserve in that license notice the full lists of Invariant Sections +and required Cover Texts given in the Document’s license notice. + +</li><li> Include an unaltered copy of this License. + +</li><li> Preserve the section Entitled “History”, Preserve its Title, and add +to it an item stating at least the title, year, new authors, and +publisher of the Modified Version as given on the Title Page. If +there is no section Entitled “History” in the Document, create one +stating the title, year, authors, and publisher of the Document as +given on its Title Page, then add an item describing the Modified +Version as stated in the previous sentence. + +</li><li> Preserve the network location, if any, given in the Document for +public access to a Transparent copy of the Document, and likewise +the network locations given in the Document for previous versions +it was based on. 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To do this, add their titles to the +list of Invariant Sections in the Modified Version’s license notice. +These titles must be distinct from any other section titles. +</p> +<p>You may add a section Entitled “Endorsements”, provided it contains +nothing but endorsements of your Modified Version by various +parties—for example, statements of peer review or that the text has +been approved by an organization as the authoritative definition of a +standard. +</p> +<p>You may add a passage of up to five words as a Front-Cover Text, and a +passage of up to 25 words as a Back-Cover Text, to the end of the list +of Cover Texts in the Modified Version. Only one passage of +Front-Cover Text and one of Back-Cover Text may be added by (or +through arrangements made by) any one entity. If the Document already +includes a cover text for the same cover, previously added by you or +by arrangement made by the same entity you are acting on behalf of, +you may not add another; but you may replace the old one, on explicit +permission from the previous publisher that added the old one. +</p> +<p>The author(s) and publisher(s) of the Document do not by this License +give permission to use their names for publicity for or to assert or +imply endorsement of any Modified Version. +</p> +</li><li> COMBINING DOCUMENTS + +<p>You may combine the Document with other documents released under this +License, under the terms defined in section 4 above for modified +versions, provided that you include in the combination all of the +Invariant Sections of all of the original documents, unmodified, and +list them all as Invariant Sections of your combined work in its +license notice, and that you preserve all their Warranty Disclaimers. +</p> +<p>The combined work need only contain one copy of this License, and +multiple identical Invariant Sections may be replaced with a single +copy. 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Any attempt +otherwise to copy, modify, sublicense, or distribute it is void, and +will automatically terminate your rights under this License. +</p> +<p>However, if you cease all violation of this License, then your license +from a particular copyright holder is reinstated (a) provisionally, +unless and until the copyright holder explicitly and finally +terminates your license, and (b) permanently, if the copyright holder +fails to notify you of the violation by some reasonable means prior to +60 days after the cessation. +</p> +<p>Moreover, your license from a particular copyright holder is +reinstated permanently if the copyright holder notifies you of the +violation by some reasonable means, this is the first time you have +received notice of violation of this License (for any work) from that +copyright holder, and you cure the violation prior to 30 days after +your receipt of the notice. +</p> +<p>Termination of your rights under this section does not terminate the +licenses of parties who have received copies or rights from you under +this License. If your rights have been terminated and not permanently +reinstated, receipt of a copy of some or all of the same material does +not give you any rights to use it. +</p> +</li><li> FUTURE REVISIONS OF THIS LICENSE + +<p>The Free Software Foundation may publish new, revised versions +of the GNU Free Documentation License from time to time. Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. See +<a href="http://www.gnu.org/copyleft/">http://www.gnu.org/copyleft/</a>. +</p> +<p>Each version of the License is given a distinguishing version number. +If the Document specifies that a particular numbered version of this +License “or any later version” applies to it, you have the option of +following the terms and conditions either of that specified version or +of any later version that has been published (not as a draft) by the +Free Software Foundation. If the Document does not specify a version +number of this License, you may choose any version ever published (not +as a draft) by the Free Software Foundation. If the Document +specifies that a proxy can decide which future versions of this +License can be used, that proxy’s public statement of acceptance of a +version permanently authorizes you to choose that version for the +Document. +</p> +</li><li> RELICENSING + +<p>“Massive Multiauthor Collaboration Site” (or “MMC Site”) means any +World Wide Web server that publishes copyrightable works and also +provides prominent facilities for anybody to edit those works. A +public wiki that anybody can edit is an example of such a server. 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A copy of the license is included in the section entitled ``GNU + Free Documentation License''. +</pre></div> + +<p>If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, +replace the “with…Texts.” line with this: +</p> +<div class="smallexample"> +<pre class="smallexample"> with the Invariant Sections being <var>list their titles</var>, with + the Front-Cover Texts being <var>list</var>, and with the Back-Cover Texts + being <var>list</var>. +</pre></div> + +<p>If you have Invariant Sections without Cover Texts, or some other +combination of the three, merge those two alternatives to suit the +situation. +</p> +<p>If your document contains nontrivial examples of program code, we +recommend releasing these examples in parallel under your choice of +free software license, such as the GNU General Public License, +to permit their use in free software. +</p> + + +<hr> +<a name="AS-Index"></a> +<div class="header"> +<p> +Previous: <a href="#GNU-Free-Documentation-License" accesskey="p" rel="previous">GNU Free Documentation License</a>, Up: <a href="#Top" accesskey="u" rel="up">Top</a> [<a href="#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="#AS-Index" title="Index" rel="index">Index</a>]</p> +</div> +<a name="AS-Index-1"></a> +<h2 class="unnumbered">AS Index</h2> + +<table><tr><th valign="top">Jump to: </th><td><a class="summary-letter" href="#AS-Index_cp_symbol-1"><b> </b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-2"><b>#</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-3"><b>$</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-4"><b>%</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-5"><b>-</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-6"><b>.</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-7"><b>1</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-8"><b>2</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-9"><b>3</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-10"><b>4</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-11"><b>8</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-12"><b>:</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-13"><b>@</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-14"><b>_</b></a> + +<br> +<a class="summary-letter" href="#AS-Index_cp_letter-A"><b>A</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-B"><b>B</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-C"><b>C</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-D"><b>D</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-E"><b>E</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-F"><b>F</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-G"><b>G</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-H"><b>H</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-I"><b>I</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-J"><b>J</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-L"><b>L</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-M"><b>M</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-N"><b>N</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-O"><b>O</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-P"><b>P</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-Q"><b>Q</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-R"><b>R</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-S"><b>S</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-T"><b>T</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-U"><b>U</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-V"><b>V</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-W"><b>W</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-X"><b>X</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-Z"><b>Z</b></a> + +</td></tr></table> +<table class="index-cp" border="0"> +<tr><td></td><th align="left">Index Entry</th><td> </td><th align="left"> Section</th></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-1"> </a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index--_005c_0022-_0028doublequote-character_0029"><code> \"</code> (doublequote character)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index--_005cb-_0028backspace-character_0029"><code> \b</code> (backspace character)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index--_005cddd-_0028octal-character-code_0029"><code> \<var>ddd</var></code> (octal character code)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index--_005cf-_0028formfeed-character_0029"><code> \f</code> (formfeed character)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index--_005cn-_0028newline-character_0029"><code> \n</code> (newline character)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index--_005cr-_0028carriage-return-character_0029"><code> \r</code> (carriage return character)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index--_005ct-_0028tab_0029"><code> \t</code> (tab)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index--_005cxd_002e_002e_002e-_0028hex-character-code_0029"><code> \<var>xd...</var></code> (hex character code)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index--_005c_005c-_0028_005c-character_0029"><code> \\</code> (‘<samp>\</samp>’ character)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-2">#</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0023"><code>#</code></a>:</td><td> </td><td valign="top"><a href="#Comments">Comments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0023APP"><code>#APP</code></a>:</td><td> </td><td valign="top"><a href="#Preprocessing">Preprocessing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0023NO_005fAPP"><code>#NO_APP</code></a>:</td><td> </td><td valign="top"><a href="#Preprocessing">Preprocessing</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-3">$</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024-in-symbol-names"><code>$</code> in symbol names</a>:</td><td> </td><td valign="top"><a href="#D10V_002dChars">D10V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024-in-symbol-names-1"><code>$</code> in symbol names</a>:</td><td> </td><td valign="top"><a href="#D30V_002dChars">D30V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024-in-symbol-names-2"><code>$</code> in symbol names</a>:</td><td> </td><td valign="top"><a href="#Meta_002dChars">Meta-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024-in-symbol-names-3"><code>$</code> in symbol names</a>:</td><td> </td><td valign="top"><a href="#SH_002dChars">SH-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024a"><code>$a</code></a>:</td><td> </td><td valign="top"><a href="#ARM-Mapping-Symbols">ARM Mapping Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024acos-math-builtin_002c-TIC54X"><code>$acos</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024asin-math-builtin_002c-TIC54X"><code>$asin</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024atan-math-builtin_002c-TIC54X"><code>$atan</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024atan2-math-builtin_002c-TIC54X"><code>$atan2</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024ceil-math-builtin_002c-TIC54X"><code>$ceil</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024cos-math-builtin_002c-TIC54X"><code>$cos</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024cosh-math-builtin_002c-TIC54X"><code>$cosh</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024cvf-math-builtin_002c-TIC54X"><code>$cvf</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024cvi-math-builtin_002c-TIC54X"><code>$cvi</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024d"><code>$d</code></a>:</td><td> </td><td valign="top"><a href="#AArch64-Mapping-Symbols">AArch64 Mapping Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024d-1"><code>$d</code></a>:</td><td> </td><td valign="top"><a href="#ARM-Mapping-Symbols">ARM Mapping Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024exp-math-builtin_002c-TIC54X"><code>$exp</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024fabs-math-builtin_002c-TIC54X"><code>$fabs</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024firstch-subsym-builtin_002c-TIC54X"><code>$firstch</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024floor-math-builtin_002c-TIC54X"><code>$floor</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024fmod-math-builtin_002c-TIC54X"><code>$fmod</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024int-math-builtin_002c-TIC54X"><code>$int</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024iscons-subsym-builtin_002c-TIC54X"><code>$iscons</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024isdefed-subsym-builtin_002c-TIC54X"><code>$isdefed</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024ismember-subsym-builtin_002c-TIC54X"><code>$ismember</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024isname-subsym-builtin_002c-TIC54X"><code>$isname</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024isreg-subsym-builtin_002c-TIC54X"><code>$isreg</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024lastch-subsym-builtin_002c-TIC54X"><code>$lastch</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024ldexp-math-builtin_002c-TIC54X"><code>$ldexp</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024log-math-builtin_002c-TIC54X"><code>$log</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024log10-math-builtin_002c-TIC54X"><code>$log10</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024max-math-builtin_002c-TIC54X"><code>$max</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024min-math-builtin_002c-TIC54X"><code>$min</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024pow-math-builtin_002c-TIC54X"><code>$pow</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024round-math-builtin_002c-TIC54X"><code>$round</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024sgn-math-builtin_002c-TIC54X"><code>$sgn</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024sin-math-builtin_002c-TIC54X"><code>$sin</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024sinh-math-builtin_002c-TIC54X"><code>$sinh</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024sqrt-math-builtin_002c-TIC54X"><code>$sqrt</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024structacc-subsym-builtin_002c-TIC54X"><code>$structacc</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024structsz-subsym-builtin_002c-TIC54X"><code>$structsz</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024symcmp-subsym-builtin_002c-TIC54X"><code>$symcmp</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024symlen-subsym-builtin_002c-TIC54X"><code>$symlen</code> subsym builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024t"><code>$t</code></a>:</td><td> </td><td valign="top"><a href="#ARM-Mapping-Symbols">ARM Mapping Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024tan-math-builtin_002c-TIC54X"><code>$tan</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024tanh-math-builtin_002c-TIC54X"><code>$tanh</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024trunc-math-builtin_002c-TIC54X"><code>$trunc</code> math builtin, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0024x"><code>$x</code></a>:</td><td> </td><td valign="top"><a href="#AArch64-Mapping-Symbols">AArch64 Mapping Symbols</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-4">%</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0025gp">%gp</a>:</td><td> </td><td valign="top"><a href="#RX_002dModifiers">RX-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0025gpreg">‘<samp>%gpreg</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dModifiers">RX-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0025pidreg">‘<samp>%pidreg</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dModifiers">RX-Modifiers</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-5">-</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002b-option_002c-VAX_002fVMS">‘<samp>-+</samp>’ option, VAX/VMS</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002d"><code>--</code></a>:</td><td> </td><td valign="top"><a href="#Command-Line">Command Line</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002d32-option_002c-i386">‘<samp>--32</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002d32-option_002c-x86_002d64">‘<samp>--32</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002d64-option_002c-i386">‘<samp>--64</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002d64-option_002c-x86_002d64">‘<samp>--64</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dabi_002dcall0"><code>--abi-call0</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dabi_002dwindowed"><code>--abi-windowed</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dabsolute_002dliterals"><code>--absolute-literals</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dallow_002dreg_002dprefix"><code>--allow-reg-prefix</code></a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dalternate"><code>--alternate</code></a>:</td><td> </td><td valign="top"><a href="#alternate">alternate</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dauto_002dlitpools"><code>--auto-litpools</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dbase_002dsize_002ddefault_002d16">‘<samp>--base-size-default-16</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dbase_002dsize_002ddefault_002d32">‘<samp>--base-size-default-32</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dbig"><code>--big</code></a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dbitwise_002dor-option_002c-M680x0">‘<samp>--bitwise-or</samp>’ option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dcompress_002ddebug_002dsections_003d-option">‘<samp>--compress-debug-sections=</samp>’ option</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002ddisp_002dsize_002ddefault_002d16">‘<samp>--disp-size-default-16</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002ddisp_002dsize_002ddefault_002d32">‘<samp>--disp-size-default-32</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002ddivide-option_002c-i386">‘<samp>--divide</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002ddsp"><code>--dsp</code></a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002demulation_003dcrisaout-command_002dline-option_002c-CRIS"><samp>--emulation=crisaout</samp> command-line option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002demulation_003dcriself-command_002dline-option_002c-CRIS"><samp>--emulation=criself</samp> command-line option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002denforce_002daligned_002ddata"><code>--enforce-aligned-data</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dAligned_002dData">Sparc-Aligned-Data</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dfatal_002dwarnings"><code>--fatal-warnings</code></a>:</td><td> </td><td valign="top"><a href="#W">W</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dfdpic"><code>--fdpic</code></a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dfix_002dv4bx-command_002dline-option_002c-ARM"><code>--fix-v4bx</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dfixed_002dspecial_002dregister_002dnames-command_002dline-option_002c-MMIX">‘<samp>--fixed-special-register-names</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dforce_002dlong_002dbranches">‘<samp>--force-long-branches</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dgenerate_002dexample">‘<samp>--generate-example</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dglobalize_002dsymbols-command_002dline-option_002c-MMIX">‘<samp>--globalize-symbols</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dgnu_002dsyntax-command_002dline-option_002c-MMIX">‘<samp>--gnu-syntax</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dlinker_002dallocated_002dgregs-command_002dline-option_002c-MMIX">‘<samp>--linker-allocated-gregs</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dlisting_002dcont_002dlines"><code>--listing-cont-lines</code></a>:</td><td> </td><td valign="top"><a href="#listing">listing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dlisting_002dlhs_002dwidth"><code>--listing-lhs-width</code></a>:</td><td> </td><td valign="top"><a href="#listing">listing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dlisting_002dlhs_002dwidth2"><code>--listing-lhs-width2</code></a>:</td><td> </td><td valign="top"><a href="#listing">listing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dlisting_002drhs_002dwidth"><code>--listing-rhs-width</code></a>:</td><td> </td><td valign="top"><a href="#listing">listing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dlittle"><code>--little</code></a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dlongcalls"><code>--longcalls</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dmarch_003darchitecture-command_002dline-option_002c-CRIS"><samp>--march=<var>architecture</var></samp> command-line option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dMD"><code>--MD</code></a>:</td><td> </td><td valign="top"><a href="#MD">MD</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dmul_002dbug_002dabort-command_002dline-option_002c-CRIS"><samp>--mul-bug-abort</samp> command-line option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dabsolute_002dliterals"><code>--no-absolute-literals</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dauto_002dlitpools"><code>--no-auto-litpools</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dexpand-command_002dline-option_002c-MMIX">‘<samp>--no-expand</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dlongcalls"><code>--no-longcalls</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dmerge_002dgregs-command_002dline-option_002c-MMIX">‘<samp>--no-merge-gregs</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dmul_002dbug_002dabort-command_002dline-option_002c-CRIS"><samp>--no-mul-bug-abort</samp> command-line option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dpad_002dsections"><code>--no-pad-sections</code></a>:</td><td> </td><td valign="top"><a href="#no_002dpad_002dsections">no-pad-sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dpredefined_002dsyms-command_002dline-option_002c-MMIX">‘<samp>--no-predefined-syms</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dpushj_002dstubs-command_002dline-option_002c-MMIX">‘<samp>--no-pushj-stubs</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dstubs-command_002dline-option_002c-MMIX">‘<samp>--no-stubs</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dtarget_002dalign"><code>--no-target-align</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dtext_002dsection_002dliterals"><code>--no-text-section-literals</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dtrampolines"><code>--no-trampolines</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dtransform"><code>--no-transform</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dunderscore-command_002dline-option_002c-CRIS"><samp>--no-underscore</samp> command-line option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dno_002dwarn"><code>--no-warn</code></a>:</td><td> </td><td valign="top"><a href="#W">W</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dpcrel">‘<samp>--pcrel</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dpic-command_002dline-option_002c-CRIS"><samp>--pic</samp> command-line option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dprint_002dinsn_002dsyntax">‘<samp>--print-insn-syntax</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dprint_002dinsn_002dsyntax-1">‘<samp>--print-insn-syntax</samp>’</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dOpts">XGATE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dprint_002dopcodes">‘<samp>--print-opcodes</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dprint_002dopcodes-1">‘<samp>--print-opcodes</samp>’</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dOpts">XGATE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dregister_002dprefix_002doptional-option_002c-M680x0">‘<samp>--register-prefix-optional</samp>’ option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002drelax"><code>--relax</code></a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002drelax-command_002dline-option_002c-MMIX">‘<samp>--relax</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002drename_002dsection"><code>--rename-section</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002drenesas"><code>--renesas</code></a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dsectname_002dsubst"><code>--sectname-subst</code></a>:</td><td> </td><td valign="top"><a href="#Section">Section</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dshort_002dbranches">‘<samp>--short-branches</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dsmall"><code>--small</code></a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dstatistics"><code>--statistics</code></a>:</td><td> </td><td valign="top"><a href="#statistics">statistics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dstrict_002ddirect_002dmode">‘<samp>--strict-direct-mode</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dtarget_002dalign"><code>--target-align</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dtext_002dsection_002dliterals"><code>--text-section-literals</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dtraditional_002dformat"><code>--traditional-format</code></a>:</td><td> </td><td valign="top"><a href="#traditional_002dformat">traditional-format</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dtrampolines"><code>--trampolines</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dtransform"><code>--transform</code></a>:</td><td> </td><td valign="top"><a href="#Xtensa-Options">Xtensa Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dunderscore-command_002dline-option_002c-CRIS"><samp>--underscore</samp> command-line option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dwarn"><code>--warn</code></a>:</td><td> </td><td valign="top"><a href="#W">W</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dx32-option_002c-i386">‘<samp>--x32</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dx32-option_002c-x86_002d64">‘<samp>--x32</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d_002dxgate_002dramoffset">‘<samp>--xgate-ramoffset</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d1-option_002c-VAX_002fVMS">‘<samp>-1</samp>’ option, VAX/VMS</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002d32addr-command_002dline-option_002c-Alpha"><code>-32addr</code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002da"><code>-a</code></a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dac"><code>-ac</code></a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dad"><code>-ad</code></a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dag"><code>-ag</code></a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dah"><code>-ah</code></a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dal"><code>-al</code></a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAleon"><code>-Aleon</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dan"><code>-an</code></a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002das"><code>-as</code></a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAsparc"><code>-Asparc</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAsparcfmaf"><code>-Asparcfmaf</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAsparcima"><code>-Asparcima</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAsparclet"><code>-Asparclet</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAsparclite"><code>-Asparclite</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAsparcvis"><code>-Asparcvis</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAsparcvis2"><code>-Asparcvis2</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAsparcvis3"><code>-Asparcvis3</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAsparcvis3r"><code>-Asparcvis3r</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv6"><code>-Av6</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv7"><code>-Av7</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv8"><code>-Av8</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv9"><code>-Av9</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv9a"><code>-Av9a</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv9b"><code>-Av9b</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv9c"><code>-Av9c</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv9d"><code>-Av9d</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv9e"><code>-Av9e</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv9m"><code>-Av9m</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dAv9v"><code>-Av9v</code></a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dbig-option_002c-M32R"><code>-big</code> option, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dcolonless-command_002dline-option_002c-Z80"><code>-colonless</code> command-line option, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Options">Z80 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dD"><code>-D</code></a>:</td><td> </td><td valign="top"><a href="#D">D</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dD_002c-ignored-on-VAX"><code>-D</code>, ignored on VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dd_002c-VAX-option"><code>-d</code>, VAX option</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002deabi_003d-command_002dline-option_002c-ARM"><code>-eabi=</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEB-command_002dline-option_002c-AArch64"><samp>-EB</samp> command-line option, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Options">AArch64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEB-command_002dline-option_002c-ARC"><code>-EB</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEB-command_002dline-option_002c-ARM"><code>-EB</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEB-command_002dline-option_002c-BPF"><samp>-EB</samp> command-line option, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF-Options">BPF Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEB-option-_0028MIPS_0029"><code>-EB</code> option (MIPS)</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEB-option_002c-M32R"><code>-EB</code> option, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEB-option_002c-TILE_002dGx">‘<samp>-EB</samp>’ option, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Options">TILE-Gx Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEL-command_002dline-option_002c-AArch64"><samp>-EL</samp> command-line option, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Options">AArch64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEL-command_002dline-option_002c-ARC"><code>-EL</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEL-command_002dline-option_002c-ARM"><code>-EL</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEL-command_002dline-option_002c-BPF"><samp>-EL</samp> command-line option, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF-Options">BPF Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEL-option-_0028MIPS_0029"><code>-EL</code> option (MIPS)</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEL-option_002c-M32R"><code>-EL</code> option, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dEL-option_002c-TILE_002dGx">‘<samp>-EL</samp>’ option, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Options">TILE-Gx Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002df"><code>-f</code></a>:</td><td> </td><td valign="top"><a href="#f">f</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dF-command_002dline-option_002c-Alpha"><code>-F</code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dfno_002dpic-option_002c-RISC_002dV">‘<samp>-fno-pic</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dfp_002dd-command_002dline-option_002c-Z80"><code>-fp-d</code> command-line option, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Options">Z80 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dfp_002ds-command_002dline-option_002c-Z80"><code>-fp-s</code> command-line option, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Options">Z80 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dfpic-option_002c-RISC_002dV">‘<samp>-fpic</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dg-command_002dline-option_002c-Alpha"><code>-g</code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dG-command_002dline-option_002c-Alpha"><code>-G</code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dG-option-_0028MIPS_0029"><code>-G</code> option (MIPS)</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dh-option_002c-VAX_002fVMS">‘<samp>-h</samp>’ option, VAX/VMS</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dH-option_002c-VAX_002fVMS">‘<samp>-H</samp>’ option, VAX/VMS</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dI-path"><code>-I <var>path</var></code></a>:</td><td> </td><td valign="top"><a href="#I">I</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dignore_002dparallel_002dconflicts-option_002c-M32RX">‘<samp>-ignore-parallel-conflicts</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dIp-option_002c-M32RX">‘<samp>-Ip</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dJ_002c-ignored-on-VAX"><code>-J</code>, ignored on VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dK"><code>-K</code></a>:</td><td> </td><td valign="top"><a href="#K">K</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dk-command_002dline-option_002c-ARM"><code>-k</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dKPIC-option_002c-M32R"><code>-KPIC</code> option, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dKPIC-option_002c-MIPS"><samp>-KPIC</samp> option, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dL"><code>-L</code></a>:</td><td> </td><td valign="top"><a href="#L">L</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dl-option_002c-M680x0">‘<samp>-l</samp>’ option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dlittle-option_002c-M32R"><code>-little</code> option, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dlocal_002dprefix-command_002dline-option_002c-Z80"><code>-local-prefix</code> command-line option, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Options">Z80 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dM"><code>-M</code></a>:</td><td> </td><td valign="top"><a href="#M">M</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f03">-m11/03</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f04">-m11/04</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f05">-m11/05</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f10">-m11/10</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f15">-m11/15</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f20">-m11/20</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f21">-m11/21</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f23">-m11/23</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f24">-m11/24</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f34">-m11/34</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f34a">-m11/34a</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f35">-m11/35</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f40">-m11/40</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f44">-m11/44</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f45">-m11/45</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f50">-m11/50</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f53">-m11/53</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f55">-m11/55</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f60">-m11/60</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f70">-m11/70</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f73">-m11/73</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f83">-m11/83</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f84">-m11/84</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f93">-m11/93</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm11_002f94">-m11/94</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm16c-option_002c-M16C">‘<samp>-m16c</samp>’ option, M16C</a>:</td><td> </td><td valign="top"><a href="#M32C_002dOpts">M32C-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm31-option_002c-s390">‘<samp>-m31</samp>’ option, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm32-option_002c-TILE_002dGx">‘<samp>-m32</samp>’ option, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Options">TILE-Gx Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm32bit_002ddoubles">‘<samp>-m32bit-doubles</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm32c-option_002c-M32C">‘<samp>-m32c</samp>’ option, M32C</a>:</td><td> </td><td valign="top"><a href="#M32C_002dOpts">M32C-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm32r-option_002c-M32R">‘<samp>-m32r</samp>’ option, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm32rx-option_002c-M32R2">‘<samp>-m32rx</samp>’ option, M32R2</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm32rx-option_002c-M32RX">‘<samp>-m32rx</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm4byte_002dalign-command_002dline-option_002c-V850"><code>-m4byte-align</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm64-option_002c-s390">‘<samp>-m64</samp>’ option, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm64-option_002c-TILE_002dGx">‘<samp>-m64</samp>’ option, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Options">TILE-Gx Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm64bit_002ddoubles">‘<samp>-m64bit-doubles</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm68000-and-related-options">‘<samp>-m68000</samp>’ and related options</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm68hc11">‘<samp>-m68hc11</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm68hc12">‘<samp>-m68hc12</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm68hcs12">‘<samp>-m68hcs12</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm8byte_002dalign-command_002dline-option_002c-V850"><code>-m8byte-align</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmabi_003d-command_002dline-option_002c-AArch64"><samp>-mabi=</samp> command-line option, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Options">AArch64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmabi_003dABI-option_002c-RISC_002dV">‘<samp>-mabi=ABI</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmadd_002dbnd_002dprefix-option_002c-i386">‘<samp>-madd-bnd-prefix</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmadd_002dbnd_002dprefix-option_002c-x86_002d64">‘<samp>-madd-bnd-prefix</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmalign_002dbranch_002dboundary_003d-option_002c-i386">‘<samp>-malign-branch-boundary=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmalign_002dbranch_002dboundary_003d-option_002c-x86_002d64">‘<samp>-malign-branch-boundary=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmalign_002dbranch_002dprefix_002dsize_003d-option_002c-i386">‘<samp>-malign-branch-prefix-size=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmalign_002dbranch_002dprefix_002dsize_003d-option_002c-x86_002d64">‘<samp>-malign-branch-prefix-size=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmalign_002dbranch_003d-option_002c-i386">‘<samp>-malign-branch=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmalign_002dbranch_003d-option_002c-x86_002d64">‘<samp>-malign-branch=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmall">-mall</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmall_002denabled-command_002dline-option_002c-LM32"><code>-mall-enabled</code> command-line option, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmall_002dextensions">-mall-extensions</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmall_002dopcodes-command_002dline-option_002c-AVR"><code>-mall-opcodes</code> command-line option, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmamd64-option_002c-x86_002d64">‘<samp>-mamd64</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmapcs_002d26-command_002dline-option_002c-ARM"><code>-mapcs-26</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmapcs_002d32-command_002dline-option_002c-ARM"><code>-mapcs-32</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmapcs_002dfloat-command_002dline-option_002c-ARM"><code>-mapcs-float</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmapcs_002dreentrant-command_002dline-option_002c-ARM"><code>-mapcs-reentrant</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_002dattr-option_002c-RISC_002dV">‘<samp>-march-attr</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_003d-command_002dline-option_002c-AArch64"><samp>-march=</samp> command-line option, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Options">AArch64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_003d-command_002dline-option_002c-ARM"><code>-march=</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_003d-command_002dline-option_002c-M680x0">‘<samp>-march=</samp>’ command-line option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_003d-command_002dline-option_002c-TIC6X"><code>-march=</code> command-line option, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_003d-command_002dline-option_002c-Z80"><code>-march=</code> command-line option, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Options">Z80 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_003d-option_002c-i386">‘<samp>-march=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_003d-option_002c-s390">‘<samp>-march=</samp>’ option, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_003d-option_002c-x86_002d64">‘<samp>-march=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmarch_003dISA-option_002c-RISC_002dV">‘<samp>-march=ISA</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmatpcs-command_002dline-option_002c-ARM"><code>-matpcs</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmavxscalar_003d-option_002c-i386">‘<samp>-mavxscalar=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmavxscalar_003d-option_002c-x86_002d64">‘<samp>-mavxscalar=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmbarrel_002dshift_002denabled-command_002dline-option_002c-LM32"><code>-mbarrel-shift-enabled</code> command-line option, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmbig_002dendian">‘<samp>-mbig-endian</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmbig_002dendian-option_002c-RISC_002dV">‘<samp>-mbig-endian</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmbig_002dobj-option_002c-i386">‘<samp>-mbig-obj</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmbig_002dobj-option_002c-x86_002d64">‘<samp>-mbig-obj</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmbranches_002dwithin_002d32B_002dboundaries-option_002c-i386">‘<samp>-mbranches-within-32B-boundaries</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmbranches_002dwithin_002d32B_002dboundaries-option_002c-x86_002d64">‘<samp>-mbranches-within-32B-boundaries</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmbreak_002denabled-command_002dline-option_002c-LM32"><code>-mbreak-enabled</code> command-line option, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmccs-command_002dline-option_002c-ARM"><code>-mccs</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcis">-mcis</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcode_002ddensity-command_002dline-option_002c-ARC"><code>-mcode-density</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmconstant_002dgp-command_002dline-option_002c-IA_002d64"><code>-mconstant-gp</code> command-line option, IA-64</a>:</td><td> </td><td valign="top"><a href="#IA_002d64-Options">IA-64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcpu-command_002dline-option_002c-Alpha"><code>-m<var>cpu</var></code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcpu-option_002c-cpu">‘<samp>-mcpu</samp>’ option, cpu</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dOpts">TIC54X-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcpu_003d">‘<samp>-mcpu=</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcpu_003d-command_002dline-option_002c-AArch64"><samp>-mcpu=</samp> command-line option, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Options">AArch64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcpu_003d-command_002dline-option_002c-ARM"><code>-mcpu=</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcpu_003d-command_002dline-option_002c-Blackfin"><code>-mcpu=</code> command-line option, Blackfin</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Options">Blackfin Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcpu_003d-command_002dline-option_002c-M680x0">‘<samp>-mcpu=</samp>’ command-line option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcpu_003dcpu-command_002dline-option_002c-ARC"><code>-mcpu=<var>cpu</var></code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcsm">-mcsm</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmcsr_002dcheck-option_002c-RISC_002dV">‘<samp>-mcsr-check</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmdcache_002denabled-command_002dline-option_002c-LM32"><code>-mdcache-enabled</code> command-line option, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmdebug-command_002dline-option_002c-Alpha"><code>-mdebug</code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmdivide_002denabled-command_002dline-option_002c-LM32"><code>-mdivide-enabled</code> command-line option, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmdollar_002dhex-option_002c-dollar_002dhex">‘<samp>-mdollar-hex</samp>’ option, dollar-hex</a>:</td><td> </td><td valign="top"><a href="#S12Z-Options">S12Z Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmdpfp-command_002dline-option_002c-ARC"><code>-mdpfp</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmdsbt-command_002dline-option_002c-TIC6X"><code>-mdsbt</code> command-line option, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dme-option_002c-stderr-redirect">‘<samp>-me</samp>’ option, stderr redirect</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dOpts">TIC54X-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmeis">-meis</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmepiphany-command_002dline-option_002c-Epiphany"><code>-mepiphany</code> command-line option, Epiphany</a>:</td><td> </td><td valign="top"><a href="#Epiphany-Options">Epiphany Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmepiphany16-command_002dline-option_002c-Epiphany"><code>-mepiphany16</code> command-line option, Epiphany</a>:</td><td> </td><td valign="top"><a href="#Epiphany-Options">Epiphany Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmerrors_002dto_002dfile-option_002c-stderr-redirect">‘<samp>-merrors-to-file</samp>’ option, stderr redirect</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dOpts">TIC54X-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmesa-option_002c-s390">‘<samp>-mesa</samp>’ option, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmevexlig_003d-option_002c-i386">‘<samp>-mevexlig=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmevexlig_003d-option_002c-x86_002d64">‘<samp>-mevexlig=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmevexrcig_003d-option_002c-i386">‘<samp>-mevexrcig=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmevexrcig_003d-option_002c-x86_002d64">‘<samp>-mevexrcig=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmevexwig_003d-option_002c-i386">‘<samp>-mevexwig=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmevexwig_003d-option_002c-x86_002d64">‘<samp>-mevexwig=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmf-option_002c-far_002dmode">‘<samp>-mf</samp>’ option, far-mode</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dOpts">TIC54X-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmf11">-mf11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfar_002dmode-option_002c-far_002dmode">‘<samp>-mfar-mode</samp>’ option, far-mode</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dOpts">TIC54X-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfdpic-command_002dline-option_002c-Blackfin"><code>-mfdpic</code> command-line option, Blackfin</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Options">Blackfin Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfence_002das_002dlock_002dadd_003d-option_002c-i386">‘<samp>-mfence-as-lock-add=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfence_002das_002dlock_002dadd_003d-option_002c-x86_002d64">‘<samp>-mfence-as-lock-add=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfis">-mfis</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfloat_002dabi_003d-command_002dline-option_002c-ARM"><code>-mfloat-abi=</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfp_002d11">-mfp-11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfp16_002dformat_003d-command_002dline-option"><code>-mfp16-format=</code> command-line option</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfpp">-mfpp</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfpu">-mfpu</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfpu_003d-command_002dline-option_002c-ARM"><code>-mfpu=</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmfpuda-command_002dline-option_002c-ARC"><code>-mfpuda</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmgcc_002dabi">‘<samp>-mgcc-abi</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmgcc_002dabi-command_002dline-option_002c-V850"><code>-mgcc-abi</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmgcc_002disr-command_002dline-option_002c-AVR"><code>-mgcc-isr</code> command-line option, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmhard_002dfloat-command_002dline-option_002c-V850"><code>-mhard-float</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmicache_002denabled-command_002dline-option_002c-LM32"><code>-micache-enabled</code> command-line option, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmimplicit_002dit-command_002dline-option_002c-ARM"><code>-mimplicit-it</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmint_002dregister">‘<samp>-mint-register</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmintel64-option_002c-x86_002d64">‘<samp>-mintel64</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmip2022-option_002c-IP2K">‘<samp>-mip2022</samp>’ option, IP2K</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dOpts">IP2K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmip2022ext-option_002c-IP2022">‘<samp>-mip2022ext</samp>’ option, IP2022</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dOpts">IP2K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmisa_002dspec_003dISAspec-option_002c-RISC_002dV">‘<samp>-misa-spec=ISAspec</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmj11">-mj11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmka11">-mka11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkb11">-mkb11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkd11a">-mkd11a</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkd11b">-mkd11b</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkd11d">-mkd11d</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkd11e">-mkd11e</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkd11f">-mkd11f</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkd11h">-mkd11h</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkd11k">-mkd11k</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkd11q">-mkd11q</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkd11z">-mkd11z</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkev11">-mkev11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmkev11-1">-mkev11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlfence_002dafter_002dload_003d-option_002c-i386">‘<samp>-mlfence-after-load=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlfence_002dafter_002dload_003d-option_002c-x86_002d64">‘<samp>-mlfence-after-load=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlfence_002dbefore_002dindirect_002dbranch_003d-option_002c-i386">‘<samp>-mlfence-before-indirect-branch=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlfence_002dbefore_002dindirect_002dbranch_003d-option_002c-x86_002d64">‘<samp>-mlfence-before-indirect-branch=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlfence_002dbefore_002dret_003d-option_002c-i386">‘<samp>-mlfence-before-ret=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlfence_002dbefore_002dret_003d-option_002c-x86_002d64">‘<samp>-mlfence-before-ret=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlimited_002deis">-mlimited-eis</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlink_002drelax-command_002dline-option_002c-AVR"><code>-mlink-relax</code> command-line option, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlittle_002dendian">‘<samp>-mlittle-endian</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlittle_002dendian-option_002c-RISC_002dV">‘<samp>-mlittle-endian</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlong">‘<samp>-mlong</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlong-1">‘<samp>-mlong</samp>’</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dOpts">XGATE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlong_002ddouble">‘<samp>-mlong-double</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmlong_002ddouble-1">‘<samp>-mlong-double</samp>’</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dOpts">XGATE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmm9s12x">‘<samp>-mm9s12x</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmm9s12xg">‘<samp>-mm9s12xg</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmmcu_003d-command_002dline-option_002c-AVR"><code>-mmcu=</code> command-line option, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmmfpt">-mmfpt</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmmicrocode">-mmicrocode</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmmnemonic_003d-option_002c-i386">‘<samp>-mmnemonic=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmmnemonic_003d-option_002c-x86_002d64">‘<samp>-mmnemonic=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmmultiply_002denabled-command_002dline-option_002c-LM32"><code>-mmultiply-enabled</code> command-line option, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmmutiproc">-mmutiproc</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmmxps">-mmxps</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmnaked_002dreg-option_002c-i386">‘<samp>-mnaked-reg</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmnaked_002dreg-option_002c-x86_002d64">‘<samp>-mnaked-reg</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmnan_003d-command_002dline-option_002c-MIPS"><samp>-mnan=</samp> command-line option, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dallow_002dstring_002dinsns">‘<samp>-mno-allow-string-insns</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002darch_002dattr-option_002c-RISC_002dV">‘<samp>-mno-arch-attr</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dcis">-mno-cis</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dcsm">-mno-csm</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dcsr_002dcheck-option_002c-RISC_002dV">‘<samp>-mno-csr-check</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002ddollar_002dline_002dseparator-command-line-option_002c-AVR"><code>-mno-dollar-line-separator</code> command line option, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002ddsbt-command_002dline-option_002c-TIC6X"><code>-mno-dsbt</code> command-line option, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002deis">-mno-eis</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dextensions">-mno-extensions</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dfdpic-command_002dline-option_002c-Blackfin"><code>-mno-fdpic</code> command-line option, Blackfin</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Options">Blackfin Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dfis">-mno-fis</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dfp_002d11">-mno-fp-11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dfpp">-mno-fpp</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dfpu">-mno-fpu</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dkev11">-mno-kev11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dlimited_002deis">-mno-limited-eis</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dlink_002drelax-command_002dline-option_002c-AVR"><code>-mno-link-relax</code> command-line option, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dmfpt">-mno-mfpt</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dmicrocode">-mno-microcode</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dmutiproc">-mno-mutiproc</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dmxps">-mno-mxps</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dpic">-mno-pic</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dpic-command_002dline-option_002c-TIC6X"><code>-mno-pic</code> command-line option, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dregnames-option_002c-s390">‘<samp>-mno-regnames</samp>’ option, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002drelax-option_002c-RISC_002dV">‘<samp>-mno-relax</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dskip_002dbug-command_002dline-option_002c-AVR"><code>-mno-skip-bug</code> command-line option, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dspl">-mno-spl</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dsym32">-mno-sym32</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dverbose_002derror-command_002dline-option_002c-AArch64"><code>-mno-verbose-error</code> command-line option, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Options">AArch64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmno_002dwrap-command_002dline-option_002c-AVR"><code>-mno-wrap</code> command-line option, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmnopic-command_002dline-option_002c-Blackfin"><code>-mnopic</code> command-line option, Blackfin</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Options">Blackfin Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmnps400-command_002dline-option_002c-ARC"><code>-mnps400</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmomit_002dlock_002dprefix_003d-option_002c-i386">‘<samp>-momit-lock-prefix=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmomit_002dlock_002dprefix_003d-option_002c-x86_002d64">‘<samp>-momit-lock-prefix=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmpic">-mpic</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmpic-command_002dline-option_002c-TIC6X"><code>-mpic</code> command-line option, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmpid">‘<samp>-mpid</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmpid_003d-command_002dline-option_002c-TIC6X"><code>-mpid=</code> command-line option, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmpriv_002dspec_003dPRIVspec-option_002c-RISC_002dV">‘<samp>-mpriv-spec=PRIVspec</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmreg_002dprefix_003dprefix-option_002c-reg_002dprefix">‘<samp>-mreg-prefix=<var>prefix</var></samp>’ option, reg-prefix</a>:</td><td> </td><td valign="top"><a href="#S12Z-Options">S12Z Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmregnames-option_002c-s390">‘<samp>-mregnames</samp>’ option, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmrelax-command_002dline-option_002c-ARC"><code>-mrelax</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmrelax-command_002dline-option_002c-V850"><code>-mrelax</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmrelax-option_002c-RISC_002dV">‘<samp>-mrelax</samp>’ option, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dOptions">RISC-V-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmrelax_002drelocations_003d-option_002c-i386">‘<samp>-mrelax-relocations=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmrelax_002drelocations_003d-option_002c-x86_002d64">‘<samp>-mrelax-relocations=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmrh850_002dabi-command_002dline-option_002c-V850"><code>-mrh850-abi</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmrmw-command_002dline-option_002c-AVR"><code>-mrmw</code> command-line option, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmrx_002dabi">‘<samp>-mrx-abi</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmshared-option_002c-i386">‘<samp>-mshared</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmshared-option_002c-x86_002d64">‘<samp>-mshared</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmshort">‘<samp>-mshort</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmshort-1">‘<samp>-mshort</samp>’</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dOpts">XGATE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmshort_002ddouble">‘<samp>-mshort-double</samp>’</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmshort_002ddouble-1">‘<samp>-mshort-double</samp>’</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dOpts">XGATE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsign_002dextend_002denabled-command_002dline-option_002c-LM32"><code>-msign-extend-enabled</code> command-line option, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsmall_002ddata_002dlimit">‘<samp>-msmall-data-limit</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsoft_002dfloat-command_002dline-option_002c-V850"><code>-msoft-float</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmspfp-command_002dline-option_002c-ARC"><code>-mspfp</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmspl">-mspl</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsse_002dcheck_003d-option_002c-i386">‘<samp>-msse-check=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsse_002dcheck_003d-option_002c-x86_002d64">‘<samp>-msse-check=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsse2avx-option_002c-i386">‘<samp>-msse2avx</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsse2avx-option_002c-x86_002d64">‘<samp>-msse2avx</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsym32">-msym32</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsyntax_003d-option_002c-i386">‘<samp>-msyntax=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmsyntax_003d-option_002c-x86_002d64">‘<samp>-msyntax=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmt11">-mt11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmthumb-command_002dline-option_002c-ARM"><code>-mthumb</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmthumb_002dinterwork-command_002dline-option_002c-ARM"><code>-mthumb-interwork</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmtune_003d-option_002c-i386">‘<samp>-mtune=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmtune_003d-option_002c-x86_002d64">‘<samp>-mtune=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmtune_003darch-command_002dline-option_002c-Visium"><code>-mtune=<var>arch</var></code> command-line option, Visium</a>:</td><td> </td><td valign="top"><a href="#Visium-Options">Visium Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmuse_002dconventional_002dsection_002dnames">‘<samp>-muse-conventional-section-names</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmuse_002drenesas_002dsection_002dnames">‘<samp>-muse-renesas-section-names</samp>’</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmuse_002dunaligned_002dvector_002dmove-option_002c-i386">‘<samp>-muse-unaligned-vector-move</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmuse_002dunaligned_002dvector_002dmove-option_002c-x86_002d64">‘<samp>-muse-unaligned-vector-move</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmuser_002denabled-command_002dline-option_002c-LM32"><code>-muser-enabled</code> command-line option, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmv850-command_002dline-option_002c-V850"><code>-mv850</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmv850any-command_002dline-option_002c-V850"><code>-mv850any</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmv850e-command_002dline-option_002c-V850"><code>-mv850e</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmv850e1-command_002dline-option_002c-V850"><code>-mv850e1</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmv850e2-command_002dline-option_002c-V850"><code>-mv850e2</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmv850e2v3-command_002dline-option_002c-V850"><code>-mv850e2v3</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmv850e2v4-command_002dline-option_002c-V850"><code>-mv850e2v4</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmv850e3v5-command_002dline-option_002c-V850"><code>-mv850e3v5</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmverbose_002derror-command_002dline-option_002c-AArch64"><code>-mverbose-error</code> command-line option, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Options">AArch64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmvexwig_003d-option_002c-i386">‘<samp>-mvexwig=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmvexwig_003d-option_002c-x86_002d64">‘<samp>-mvexwig=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmvxworks_002dpic-option_002c-MIPS"><samp>-mvxworks-pic</samp> option, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmwarn_002dareg_002dzero-option_002c-s390">‘<samp>-mwarn-areg-zero</samp>’ option, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmwarn_002ddeprecated-command_002dline-option_002c-ARM"><code>-mwarn-deprecated</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmwarn_002dsyms-command_002dline-option_002c-ARM"><code>-mwarn-syms</code> command-line option, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmx86_002dused_002dnote_003d-option_002c-i386">‘<samp>-mx86-used-note=</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmx86_002dused_002dnote_003d-option_002c-x86_002d64">‘<samp>-mx86-used-note=</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dmzarch-option_002c-s390">‘<samp>-mzarch</samp>’ option, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm_005bno_002d_005d68851-command_002dline-option_002c-M680x0">‘<samp>-m[no-]68851</samp>’ command-line option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm_005bno_002d_005d68881-command_002dline-option_002c-M680x0">‘<samp>-m[no-]68881</samp>’ command-line option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm_005bno_002d_005ddiv-command_002dline-option_002c-M680x0">‘<samp>-m[no-]div</samp>’ command-line option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm_005bno_002d_005demac-command_002dline-option_002c-M680x0">‘<samp>-m[no-]emac</samp>’ command-line option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm_005bno_002d_005dfloat-command_002dline-option_002c-M680x0">‘<samp>-m[no-]float</samp>’ command-line option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm_005bno_002d_005dmac-command_002dline-option_002c-M680x0">‘<samp>-m[no-]mac</samp>’ command-line option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dm_005bno_002d_005dusp-command_002dline-option_002c-M680x0">‘<samp>-m[no-]usp</samp>’ command-line option, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dN-command_002dline-option_002c-CRIS"><samp>-N</samp> command-line option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dnIp-option_002c-M32RX">‘<samp>-nIp</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dno_002dbitinst_002c-M32R2">‘<samp>-no-bitinst</samp>’, M32R2</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dno_002dignore_002dparallel_002dconflicts-option_002c-M32RX">‘<samp>-no-ignore-parallel-conflicts</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dno_002dmdebug-command_002dline-option_002c-Alpha"><code>-no-mdebug</code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dno_002dparallel-option_002c-M32RX"><code>-no-parallel</code> option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dno_002dwarn_002dexplicit_002dparallel_002dconflicts-option_002c-M32RX">‘<samp>-no-warn-explicit-parallel-conflicts</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dno_002dwarn_002dunmatched_002dhigh-option_002c-M32R">‘<samp>-no-warn-unmatched-high</samp>’ option, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dnocpp-ignored-_0028MIPS_0029"><code>-nocpp</code> ignored (MIPS)</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dnoreplace-command_002dline-option_002c-Alpha"><code>-noreplace</code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002do"><code>-o</code></a>:</td><td> </td><td valign="top"><a href="#o">o</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dO-option_002c-i386">‘<samp>-O</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dO-option_002c-M32RX"><code>-O</code> option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dO-option_002c-x86_002d64">‘<samp>-O</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dO0-option_002c-i386">‘<samp>-O0</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dO0-option_002c-x86_002d64">‘<samp>-O0</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dO1-option_002c-i386">‘<samp>-O1</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dO1-option_002c-x86_002d64">‘<samp>-O1</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dO2-option_002c-i386">‘<samp>-O2</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dO2-option_002c-x86_002d64">‘<samp>-O2</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dOs-option_002c-i386">‘<samp>-Os</samp>’ option, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dOs-option_002c-x86_002d64">‘<samp>-Os</samp>’ option, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dparallel-option_002c-M32RX"><code>-parallel</code> option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dR"><code>-R</code></a>:</td><td> </td><td valign="top"><a href="#R">R</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002drelax-command_002dline-option_002c-Alpha"><code>-relax</code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dreplace-command_002dline-option_002c-Alpha"><code>-replace</code> command-line option, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dS_002c-ignored-on-VAX"><code>-S</code>, ignored on VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dsdcc-command_002dline-option_002c-Z80"><code>-sdcc</code> command-line option, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Options">Z80 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dT_002c-ignored-on-VAX"><code>-T</code>, ignored on VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dt_002c-ignored-on-VAX"><code>-t</code>, ignored on VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dv"><code>-v</code></a>:</td><td> </td><td valign="top"><a href="#v">v</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dV_002c-redundant-on-VAX"><code>-V</code>, redundant on VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dversion"><code>-version</code></a>:</td><td> </td><td valign="top"><a href="#v">v</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dW"><code>-W</code></a>:</td><td> </td><td valign="top"><a href="#W">W</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dwarn_002dexplicit_002dparallel_002dconflicts-option_002c-M32RX">‘<samp>-warn-explicit-parallel-conflicts</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dwarn_002dunmatched_002dhigh-option_002c-M32R">‘<samp>-warn-unmatched-high</samp>’ option, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dWnp-option_002c-M32RX">‘<samp>-Wnp</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dWnuh-option_002c-M32RX">‘<samp>-Wnuh</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dWp-option_002c-M32RX">‘<samp>-Wp</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dwsigned_005foverflow-command_002dline-option_002c-V850"><code>-wsigned_overflow</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dWuh-option_002c-M32RX">‘<samp>-Wuh</samp>’ option, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dwunsigned_005foverflow-command_002dline-option_002c-V850"><code>-wunsigned_overflow</code> command-line option, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dx-command_002dline-option_002c-MMIX">‘<samp>-x</samp>’ command-line option, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dz8001-command_002dline-option_002c-Z8000"><code>-z8001</code> command-line option, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000-Options">Z8000 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002dz8002-command_002dline-option_002c-Z8000"><code>-z8002</code> command-line option, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000-Options">Z8000 Options</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-6">.</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002e-_0028symbol_0029"><code>.</code> (symbol)</a>:</td><td> </td><td valign="top"><a href="#Dot">Dot</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ealign-directive_002c-ARM"><code>.align</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ealign-directive_002c-TILE_002dGx"><code>.align</code> directive, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Directives">TILE-Gx Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ealign-directive_002c-TILEPro"><code>.align</code> directive, TILEPro</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Directives">TILEPro Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eallow_005fsuspicious_005fbundles-directive_002c-TILE_002dGx"><code>.allow_suspicious_bundles</code> directive, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Directives">TILE-Gx Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eallow_005fsuspicious_005fbundles-directive_002c-TILEPro"><code>.allow_suspicious_bundles</code> directive, TILEPro</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Directives">TILEPro Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002earch-directive_002c-AArch64"><code>.arch</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002earch-directive_002c-ARM"><code>.arch</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002earch-directive_002c-TIC6X"><code>.arch</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002earch_005fextension-directive_002c-AArch64"><code>.arch_extension</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002earch_005fextension-directive_002c-ARM"><code>.arch_extension</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002earc_005fattribute-directive_002c-ARC"><code>.arc_attribute</code> directive, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002earm-directive_002c-ARM"><code>.arm</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eassume-directive_002c-Z80"><code>.assume</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eattribute-directive_002c-RISC_002dV"><code>.attribute</code> directive, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ebig-directive_002c-M32RX"><code>.big</code> directive, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ebss-directive_002c-AArch64"><code>.bss</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ebss-directive_002c-ARM"><code>.bss</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ec6xabi_005fattribute-directive_002c-TIC6X"><code>.c6xabi_attribute</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ecantunwind-directive_002c-ARM"><code>.cantunwind</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ecantunwind-directive_002c-TIC6X"><code>.cantunwind</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ecfi_005fb_005fkey_005fframe-directive_002c-AArch64"><code>.cfi_b_key_frame</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ecode-directive_002c-ARM"><code>.code</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ecpu-directive_002c-AArch64"><code>.cpu</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ecpu-directive_002c-ARM"><code>.cpu</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002edn-and-_002eqn-directives_002c-ARM"><code>.dn</code> and <code>.qn</code> directives, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002edword-directive_002c-AArch64"><code>.dword</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eeabi_005fattribute-directive_002c-ARM"><code>.eabi_attribute</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eehtype-directive_002c-TIC6X"><code>.ehtype</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eendp-directive_002c-TIC6X"><code>.endp</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eeven-directive_002c-AArch64"><code>.even</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eeven-directive_002c-ARM"><code>.even</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eextend-directive_002c-ARM"><code>.extend</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002efloat16-directive_002c-AArch64"><code>.float16</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002efloat16-directive_002c-ARM"><code>.float16</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002efloat16_005fformat-directive_002c-ARM"><code>.float16_format</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002efnend-directive_002c-ARM"><code>.fnend</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002efnstart-directive_002c-ARM"><code>.fnstart</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eforce_005fthumb-directive_002c-ARM"><code>.force_thumb</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002efpu-directive_002c-ARM"><code>.fpu</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eglobal"><code><code>.global</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-insn">MIPS insn</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002egnu_005fattribute-4_002c-n-directive_002c-MIPS"><code>.gnu_attribute 4, <var>n</var></code> directive, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-FP-ABI-History">MIPS FP ABI History</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002egnu_005fattribute-Tag_005fGNU_005fMIPS_005fABI_005fFP_002c-n-directive_002c-MIPS"><code>.gnu_attribute Tag_GNU_MIPS_ABI_FP, <var>n</var></code> directive, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-FP-ABI-History">MIPS FP ABI History</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ehandlerdata-directive_002c-ARM"><code>.handlerdata</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ehandlerdata-directive_002c-TIC6X"><code>.handlerdata</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002einsn"><code><code>.insn</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-insn">MIPS insn</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002einsn-directive_002c-s390"><code>.insn</code> directive, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Directives">s390 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002einst-directive_002c-AArch64"><code>.inst</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002einst-directive_002c-ARM"><code>.inst</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eldouble-directive_002c-ARM"><code>.ldouble</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002elittle-directive_002c-M32RX"><code>.little</code> directive, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002elong-directive_002c-s390"><code>.long</code> directive, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Directives">s390 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eltorg-directive_002c-AArch64"><code>.ltorg</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eltorg-directive_002c-ARM"><code>.ltorg</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eltorg-directive_002c-s390"><code>.ltorg</code> directive, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Directives">s390 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002em32r-directive_002c-M32R"><code>.m32r</code> directive, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002em32r2-directive_002c-M32R2"><code>.m32r2</code> directive, M32R2</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002em32rx-directive_002c-M32RX"><code>.m32rx</code> directive, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002emachine-directive_002c-s390"><code>.machine</code> directive, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Directives">s390 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002emachinemode-directive_002c-s390"><code>.machinemode</code> directive, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Directives">s390 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002emodule"><code><code>.module</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-assembly-options">MIPS assembly options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002emodule-fp_003dnn-directive_002c-MIPS"><code>.module fp=<var>nn</var></code> directive, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-FP-ABI-Selection">MIPS FP ABI Selection</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002emovsp-directive_002c-ARM"><code>.movsp</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002enan-directive_002c-MIPS"><code>.nan</code> directive, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-NaN-Encodings">MIPS NaN Encodings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002enocmp-directive_002c-TIC6X"><code>.nocmp</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eno_005fpointers-directive_002c-XStormy16"><code>.no_pointers</code> directive, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16-Directives">XStormy16 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eo"><code>.o</code></a>:</td><td> </td><td valign="top"><a href="#Object">Object</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eobject_005farch-directive_002c-ARM"><code>.object_arch</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002epacked-directive_002c-ARM"><code>.packed</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002epacspval-directive_002c-ARM"><code>.pacspval</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002epad-directive_002c-ARM"><code>.pad</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eparam-on-HPPA"><code>.param</code> on HPPA</a>:</td><td> </td><td valign="top"><a href="#HPPA-Directives">HPPA Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002epersonality-directive_002c-ARM"><code>.personality</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002epersonality-directive_002c-TIC6X"><code>.personality</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002epersonalityindex-directive_002c-ARM"><code>.personalityindex</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002epersonalityindex-directive_002c-TIC6X"><code>.personalityindex</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002epool-directive_002c-AArch64"><code>.pool</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002epool-directive_002c-ARM"><code>.pool</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002equad-directive_002c-s390"><code>.quad</code> directive, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Directives">s390 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ereq-directive_002c-AArch64"><code>.req</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ereq-directive_002c-ARM"><code>.req</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002erequire_005fcanonical_005freg_005fnames-directive_002c-TILE_002dGx"><code>.require_canonical_reg_names</code> directive, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Directives">TILE-Gx Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002erequire_005fcanonical_005freg_005fnames-directive_002c-TILEPro"><code>.require_canonical_reg_names</code> directive, TILEPro</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Directives">TILEPro Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002esave-directive_002c-ARM"><code>.save</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002escomm-directive_002c-TIC6X"><code>.scomm</code> directive, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002esecrel32-directive_002c-ARM"><code>.secrel32</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-arch_003dcpu"><code><code>.set arch=<var>cpu</var></code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ISA">MIPS ISA</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-at"><code><code>.set at</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Macros">MIPS Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-at_003dreg"><code><code>.set at=<var>reg</var></code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Macros">MIPS Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-autoextend"><code><code>.set autoextend</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-autoextend">MIPS autoextend</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-crc"><code><code>.set crc</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-doublefloat"><code><code>.set doublefloat</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Floating_002dPoint">MIPS Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-dsp"><code><code>.set dsp</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-dspr2"><code><code>.set dspr2</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-dspr3"><code><code>.set dspr3</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-ginv"><code><code>.set ginv</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-hardfloat"><code><code>.set hardfloat</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Floating_002dPoint">MIPS Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-insn32"><code><code>.set insn32</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-assembly-options">MIPS assembly options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-loongson_002dcam"><code><code>.set loongson-cam</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-loongson_002dext"><code><code>.set loongson-ext</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-loongson_002dext2"><code><code>.set loongson-ext2</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-loongson_002dmmi"><code><code>.set loongson-mmi</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-macro"><code><code>.set macro</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Macros">MIPS Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-mcu"><code><code>.set mcu</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-mdmx"><code><code>.set mdmx</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-mips16e2"><code><code>.set mips16e2</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-mips3d"><code><code>.set mips3d</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-mipsn"><code><code>.set mips<var>n</var></code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ISA">MIPS ISA</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-msa"><code><code>.set msa</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-mt"><code><code>.set mt</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-noat"><code><code>.set noat</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Macros">MIPS Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-noautoextend"><code><code>.set noautoextend</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-autoextend">MIPS autoextend</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nocrc"><code><code>.set nocrc</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nodsp"><code><code>.set nodsp</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nodspr2"><code><code>.set nodspr2</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nodspr3"><code><code>.set nodspr3</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-noginv"><code><code>.set noginv</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-noinsn32"><code><code>.set noinsn32</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-assembly-options">MIPS assembly options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-noloongson_002dcam"><code><code>.set noloongson-cam</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-noloongson_002dext"><code><code>.set noloongson-ext</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-noloongson_002dext2"><code><code>.set noloongson-ext2</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-noloongson_002dmmi"><code><code>.set noloongson-mmi</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nomacro"><code><code>.set nomacro</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Macros">MIPS Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nomcu"><code><code>.set nomcu</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nomdmx"><code><code>.set nomdmx</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nomips16e2"><code><code>.set nomips16e2</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nomips3d"><code><code>.set nomips3d</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nomsa"><code><code>.set nomsa</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nomt"><code><code>.set nomt</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nosmartmips"><code><code>.set nosmartmips</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-nosym32"><code><code>.set nosym32</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Symbol-Sizes">MIPS Symbol Sizes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-novirt"><code><code>.set novirt</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-noxpa"><code><code>.set noxpa</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-pop"><code><code>.set pop</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Option-Stack">MIPS Option Stack</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-push"><code><code>.set push</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Option-Stack">MIPS Option Stack</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-singlefloat"><code><code>.set singlefloat</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Floating_002dPoint">MIPS Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-smartmips"><code><code>.set smartmips</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-softfloat"><code><code>.set softfloat</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Floating_002dPoint">MIPS Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-sym32"><code><code>.set sym32</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-Symbol-Sizes">MIPS Symbol Sizes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-virt"><code><code>.set virt</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eset-xpa"><code><code>.set xpa</code></code></a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002esetfp-directive_002c-ARM"><code>.setfp</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eshort-directive_002c-s390"><code>.short</code> directive, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Directives">s390 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002esyntax-directive_002c-ARM"><code>.syntax</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ethumb-directive_002c-ARM"><code>.thumb</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ethumb_005ffunc-directive_002c-ARM"><code>.thumb_func</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ethumb_005fset-directive_002c-ARM"><code>.thumb_set</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002etlsdescadd-directive_002c-AArch64"><code>.tlsdescadd</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002etlsdesccall-directive_002c-AArch64"><code>.tlsdesccall</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002etlsdescldr-directive_002c-AArch64"><code>.tlsdescldr</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002etlsdescseq-directive_002c-ARM"><code>.tlsdescseq</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eunreq-directive_002c-AArch64"><code>.unreq</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eunreq-directive_002c-ARM"><code>.unreq</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002eunwind_005fraw-directive_002c-ARM"><code>.unwind_raw</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ev850-directive_002c-V850"><code>.v850</code> directive, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ev850e-directive_002c-V850"><code>.v850e</code> directive, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ev850e1-directive_002c-V850"><code>.v850e1</code> directive, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ev850e2-directive_002c-V850"><code>.v850e2</code> directive, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ev850e2v3-directive_002c-V850"><code>.v850e2v3</code> directive, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ev850e2v4-directive_002c-V850"><code>.v850e2v4</code> directive, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ev850e3v5-directive_002c-V850"><code>.v850e3v5</code> directive, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002evariant_005fpcs-directive_002c-AArch64"><code>.variant_pcs</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002evsave-directive_002c-ARM"><code>.vsave</code> directive, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002exword-directive_002c-AArch64"><code>.xword</code> directive, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ez8001"><code>.z8001</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_002ez8002"><code>.z8002</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-7">1</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-16_002dbit-code_002c-i386">16-bit code, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002d16bit">i386-16bit</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-16bit_005fpointers-directive_002c-XStormy16"><code>16bit_pointers</code> directive, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16-Directives">XStormy16 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-16byte-directive_002c-Nios-II"><code>16byte</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-16byte-directive_002c-PRU"><code>16byte</code> directive, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-8">2</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-2byte-directive"><code>2byte</code> directive</a>:</td><td> </td><td valign="top"><a href="#g_t2byte">2byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-2byte-directive_002c-Nios-II"><code>2byte</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-2byte-directive_002c-PRU"><code>2byte</code> directive, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-9">3</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-32bit_005fpointers-directive_002c-XStormy16"><code>32bit_pointers</code> directive, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16-Directives">XStormy16 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-3DNow_0021_002c-i386">3DNow!, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dSIMD">i386-SIMD</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-3DNow_0021_002c-x86_002d64">3DNow!, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dSIMD">i386-SIMD</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-10">4</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-430-support">430 support</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dDependent">MSP430-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-4byte-directive"><code>4byte</code> directive</a>:</td><td> </td><td valign="top"><a href="#g_t4byte">4byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-4byte-directive_002c-Nios-II"><code>4byte</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-4byte-directive_002c-PRU"><code>4byte</code> directive, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-11">8</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-8byte-directive"><code>8byte</code> directive</a>:</td><td> </td><td valign="top"><a href="#g_t8byte">8byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-8byte-directive_002c-Nios-II"><code>8byte</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-8byte-directive_002c-PRU"><code>8byte</code> directive, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-12">:</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-_003a-_0028label_0029"><code>:</code> (label)</a>:</td><td> </td><td valign="top"><a href="#Statements">Statements</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-13">@</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0040gotoff_0028symbol_0029_002c-ARC-modifier">@gotoff(<var>symbol</var>), ARC modifier</a>:</td><td> </td><td valign="top"><a href="#ARC-Modifiers">ARC Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0040gotpc_0028symbol_0029_002c-ARC-modifier">@gotpc(<var>symbol</var>), ARC modifier</a>:</td><td> </td><td valign="top"><a href="#ARC-Modifiers">ARC Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0040hi-pseudo_002dop_002c-XStormy16"><code>@hi</code> pseudo-op, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16-Opcodes">XStormy16 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0040lo-pseudo_002dop_002c-XStormy16"><code>@lo</code> pseudo-op, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16-Opcodes">XStormy16 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0040pcl_0028symbol_0029_002c-ARC-modifier">@pcl(<var>symbol</var>), ARC modifier</a>:</td><td> </td><td valign="top"><a href="#ARC-Modifiers">ARC Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0040plt_0028symbol_0029_002c-ARC-modifier">@plt(<var>symbol</var>), ARC modifier</a>:</td><td> </td><td valign="top"><a href="#ARC-Modifiers">ARC Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0040sda_0028symbol_0029_002c-ARC-modifier">@sda(<var>symbol</var>), ARC modifier</a>:</td><td> </td><td valign="top"><a href="#ARC-Modifiers">ARC Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_0040word-modifier_002c-D10V">@word modifier, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dWord">D10V-Word</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_symbol-14">_</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-_005f-opcode-prefix">_ opcode prefix</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Opcodes">Xtensa Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_005f_005fDYNAMIC_005f_005f_002c-ARC-pre_002ddefined-symbol">__DYNAMIC__, ARC pre-defined symbol</a>:</td><td> </td><td valign="top"><a href="#ARC-Symbols">ARC Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-_005f_005fGLOBAL_005fOFFSET_005fTABLE_005f_005f_002c-ARC-pre_002ddefined-symbol">__GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol</a>:</td><td> </td><td valign="top"><a href="#ARC-Symbols">ARC Symbols</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-A">A</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-a_002eout"><code>a.out</code></a>:</td><td> </td><td valign="top"><a href="#Object">Object</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-a_002eout-symbol-attributes"><code>a.out</code> symbol attributes</a>:</td><td> </td><td valign="top"><a href="#a_002eout-Symbols">a.out Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-floating-point-_0028IEEE_0029">AArch64 floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#AArch64-Floating-Point">AArch64 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-immediate-character">AArch64 immediate character</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dChars">AArch64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-line-comment-character">AArch64 line comment character</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dChars">AArch64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-line-separator">AArch64 line separator</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dChars">AArch64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-machine-directives">AArch64 machine directives</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-opcodes">AArch64 opcodes</a>:</td><td> </td><td valign="top"><a href="#AArch64-Opcodes">AArch64 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-options-_0028none_0029">AArch64 options (none)</a>:</td><td> </td><td valign="top"><a href="#AArch64-Options">AArch64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-register-names">AArch64 register names</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dRegs">AArch64-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-relocations">AArch64 relocations</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dRelocations">AArch64-Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AArch64-support">AArch64 support</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dDependent">AArch64-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-abort-directive"><code>abort</code> directive</a>:</td><td> </td><td valign="top"><a href="#Abort">Abort</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ABORT-directive"><code>ABORT</code> directive</a>:</td><td> </td><td valign="top"><a href="#ABORT-_0028COFF_0029">ABORT (COFF)</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-absolute-section">absolute section</a>:</td><td> </td><td valign="top"><a href="#Ld-Sections">Ld Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-absolute_002dliterals-directive"><code>absolute-literals</code> directive</a>:</td><td> </td><td valign="top"><a href="#Absolute-Literals-Directive">Absolute Literals Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ADDI-instructions_002c-relaxation"><code>ADDI</code> instructions, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addition_002c-permitted-arguments">addition, permitted arguments</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addresses">addresses</a>:</td><td> </td><td valign="top"><a href="#Expressions">Expressions</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addresses_002c-format-of">addresses, format of</a>:</td><td> </td><td valign="top"><a href="#Secs-Background">Secs Background</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addressing-modes_002c-D10V">addressing modes, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dAddressing">D10V-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addressing-modes_002c-D30V">addressing modes, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dAddressing">D30V-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addressing-modes_002c-H8_002f300">addressing modes, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dAddressing">H8/300-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addressing-modes_002c-M680x0">addressing modes, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dSyntax">M68K-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addressing-modes_002c-M68HC11">addressing modes, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dSyntax">M68HC11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addressing-modes_002c-S12Z">addressing modes, S12Z</a>:</td><td> </td><td valign="top"><a href="#S12Z-Addressing-Modes">S12Z Addressing Modes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addressing-modes_002c-SH">addressing modes, SH</a>:</td><td> </td><td valign="top"><a href="#SH_002dAddressing">SH-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addressing-modes_002c-XGATE">addressing modes, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dSyntax">XGATE-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-addressing-modes_002c-Z8000">addressing modes, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dAddressing">Z8000-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ADR-reg_002c_003clabel_003e-pseudo-op_002c-ARM"><code>ADR reg,<label></code> pseudo op, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Opcodes">ARM Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ADRL-reg_002c_003clabel_003e-pseudo-op_002c-ARM"><code>ADRL reg,<label></code> pseudo op, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Opcodes">ARM Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ADRP_002c-ADD_002c-LDR_002fSTR-group-relocations_002c-AArch64">ADRP, ADD, LDR/STR group relocations, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dRelocations">AArch64-Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-advancing-location-counter">advancing location counter</a>:</td><td> </td><td valign="top"><a href="#Org">Org</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-align-directive"><code>align</code> directive</a>:</td><td> </td><td valign="top"><a href="#Align">Align</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-align-directive-1"><code>align</code> directive</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-align-directive_002c-Nios-II"><code>align</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-align-directive_002c-OpenRISC"><code>align</code> directive, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDirectives">OpenRISC-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-align-directive_002c-PRU"><code>align</code> directive, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-align-directive_002c-SPARC"><code>align</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-align-directive_002c-TIC54X"><code>align</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-aligned-instruction-bundle">aligned instruction bundle</a>:</td><td> </td><td valign="top"><a href="#Bundle-directives">Bundle directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-alignment-for-NEON-instructions">alignment for NEON instructions</a>:</td><td> </td><td valign="top"><a href="#ARM_002dNeon_002dAlignment">ARM-Neon-Alignment</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-alignment-of-branch-targets">alignment of branch targets</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Automatic-Alignment">Xtensa Automatic Alignment</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-alignment-of-LOOP-instructions">alignment of <code>LOOP</code> instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Automatic-Alignment">Xtensa Automatic Alignment</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha-floating-point-_0028IEEE_0029">Alpha floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#Alpha-Floating-Point">Alpha Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha-line-comment-character">Alpha line comment character</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dChars">Alpha-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha-line-separator">Alpha line separator</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dChars">Alpha-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha-notes">Alpha notes</a>:</td><td> </td><td valign="top"><a href="#Alpha-Notes">Alpha Notes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha-options">Alpha options</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha-registers">Alpha registers</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dRegs">Alpha-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha-relocations">Alpha relocations</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dRelocs">Alpha-Relocs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha-support">Alpha support</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dDependent">Alpha-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha-Syntax">Alpha Syntax</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Alpha_002donly-directives">Alpha-only directives</a>:</td><td> </td><td valign="top"><a href="#Alpha-Directives">Alpha Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Altera-Nios-II-support">Altera Nios II support</a>:</td><td> </td><td valign="top"><a href="#NiosII_002dDependent">NiosII-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-altered-difference-tables">altered difference tables</a>:</td><td> </td><td valign="top"><a href="#Word">Word</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-alternate-syntax-for-the-680x0">alternate syntax for the 680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dMoto_002dSyntax">M68K-Moto-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Branch-Target-Address">ARC Branch Target Address</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-BTA-saved-on-exception-entry">ARC BTA saved on exception entry</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Build-configuration-for_003a-BTA-Registers">ARC Build configuration for: BTA Registers</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Build-configuration-for_003a-Core-Registers">ARC Build configuration for: Core Registers</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Build-configuration-for_003a-Interrupts">ARC Build configuration for: Interrupts</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Build-Configuration-Registers-Version">ARC Build Configuration Registers Version</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-C-preprocessor-macro-separator">ARC C preprocessor macro separator</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-core-general-registers">ARC core general registers</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-DCCM-RAM-Configuration-Register">ARC DCCM RAM Configuration Register</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Exception-Cause-Register">ARC Exception Cause Register</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Exception-Return-Address">ARC Exception Return Address</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-extension-core-registers">ARC extension core registers</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-frame-pointer">ARC frame pointer</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-global-pointer">ARC global pointer</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-interrupt-link-register">ARC interrupt link register</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Interrupt-Vector-Base-address">ARC Interrupt Vector Base address</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-level-1-interrupt-link-register">ARC level 1 interrupt link register</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-level-2-interrupt-link-register">ARC level 2 interrupt link register</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-line-comment-character">ARC line comment character</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-line-separator">ARC line separator</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-link-register">ARC link register</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-loop-counter">ARC loop counter</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-machine-directives">ARC machine directives</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-opcodes">ARC opcodes</a>:</td><td> </td><td valign="top"><a href="#ARC-Opcodes">ARC Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-options">ARC options</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Processor-Identification-register">ARC Processor Identification register</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Program-Counter">ARC Program Counter</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-register-name-prefix-character">ARC register name prefix character</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-register-names">ARC register names</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Saved-User-Stack-Pointer">ARC Saved User Stack Pointer</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-stack-pointer">ARC stack pointer</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Status-register">ARC Status register</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-STATUS32-saved-on-exception">ARC STATUS32 saved on exception</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-Stored-STATUS32-register-on-entry-to-level-P0-interrupts">ARC Stored STATUS32 register on entry to level P0 interrupts</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-support">ARC support</a>:</td><td> </td><td valign="top"><a href="#ARC_002dDependent">ARC-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-symbol-prefix-character">ARC symbol prefix character</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARC-word-aligned-program-counter">ARC word aligned program counter</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-arch-directive_002c-i386">arch directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dArch">i386-Arch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-arch-directive_002c-M680x0"><code>arch</code> directive, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dDirectives">M68K-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-arch-directive_002c-MSP-430"><code>arch</code> directive, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Directives">MSP430 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-arch-directive_002c-x86_002d64">arch directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dArch">i386-Arch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architecture-options_002c-IP2022">architecture options, IP2022</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dOpts">IP2K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architecture-options_002c-IP2K">architecture options, IP2K</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dOpts">IP2K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architecture-options_002c-M16C">architecture options, M16C</a>:</td><td> </td><td valign="top"><a href="#M32C_002dOpts">M32C-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architecture-options_002c-M32C">architecture options, M32C</a>:</td><td> </td><td valign="top"><a href="#M32C_002dOpts">M32C-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architecture-options_002c-M32R">architecture options, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architecture-options_002c-M32R2">architecture options, M32R2</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architecture-options_002c-M32RX">architecture options, M32RX</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architecture-options_002c-M680x0">architecture options, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Architecture-variant-option_002c-CRIS">Architecture variant option, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architectures_002c-Meta">architectures, Meta</a>:</td><td> </td><td valign="top"><a href="#Meta-Options">Meta Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architectures_002c-PowerPC">architectures, PowerPC</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dOpts">PowerPC-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architectures_002c-SCORE">architectures, SCORE</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dOpts">SCORE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-architectures_002c-SPARC">architectures, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-arguments-for-addition">arguments for addition</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-arguments-for-subtraction">arguments for subtraction</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-arguments-in-expressions">arguments in expressions</a>:</td><td> </td><td valign="top"><a href="#Arguments">Arguments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-arithmetic-functions">arithmetic functions</a>:</td><td> </td><td valign="top"><a href="#Operators">Operators</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-arithmetic-operands">arithmetic operands</a>:</td><td> </td><td valign="top"><a href="#Arguments">Arguments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-data-relocations">ARM data relocations</a>:</td><td> </td><td valign="top"><a href="#ARM_002dRelocations">ARM-Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-floating-point-_0028IEEE_0029">ARM floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#ARM-Floating-Point">ARM Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-identifiers">ARM identifiers</a>:</td><td> </td><td valign="top"><a href="#ARM_002dChars">ARM-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-immediate-character">ARM immediate character</a>:</td><td> </td><td valign="top"><a href="#ARM_002dChars">ARM-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-line-comment-character">ARM line comment character</a>:</td><td> </td><td valign="top"><a href="#ARM_002dChars">ARM-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-line-separator">ARM line separator</a>:</td><td> </td><td valign="top"><a href="#ARM_002dChars">ARM-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-machine-directives">ARM machine directives</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-opcodes">ARM opcodes</a>:</td><td> </td><td valign="top"><a href="#ARM-Opcodes">ARM Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-options-_0028none_0029">ARM options (none)</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-register-names">ARM register names</a>:</td><td> </td><td valign="top"><a href="#ARM_002dRegs">ARM-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ARM-support">ARM support</a>:</td><td> </td><td valign="top"><a href="#ARM_002dDependent">ARM-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ascii-directive"><code>ascii</code> directive</a>:</td><td> </td><td valign="top"><a href="#Ascii">Ascii</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-asciz-directive"><code>asciz</code> directive</a>:</td><td> </td><td valign="top"><a href="#Asciz">Asciz</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-asg-directive_002c-TIC54X"><code>asg</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-bugs_002c-reporting">assembler bugs, reporting</a>:</td><td> </td><td valign="top"><a href="#Bug-Reporting">Bug Reporting</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-crash">assembler crash</a>:</td><td> </td><td valign="top"><a href="#Bug-Criteria">Bug Criteria</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002e3byte_002c-RX">assembler directive .3byte, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dDirectives">RX-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002earch_002c-CRIS">assembler directive .arch, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002edword_002c-CRIS">assembler directive .dword, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002efar_002c-M68HC11">assembler directive .far, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002efetchalign_002c-RX">assembler directive .fetchalign, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dDirectives">RX-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002einterrupt_002c-M68HC11">assembler directive .interrupt, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002emode_002c-M68HC11">assembler directive .mode, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002erelax_002c-M68HC11">assembler directive .relax, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002esyntax_002c-CRIS">assembler directive .syntax, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-_002exrefb_002c-M68HC11">assembler directive .xrefb, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-BSPEC_002c-MMIX">assembler directive BSPEC, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-BYTE_002c-MMIX">assembler directive BYTE, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-ESPEC_002c-MMIX">assembler directive ESPEC, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-GREG_002c-MMIX">assembler directive GREG, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-IS_002c-MMIX">assembler directive IS, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-LOC_002c-MMIX">assembler directive LOC, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-LOCAL_002c-MMIX">assembler directive LOCAL, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-OCTA_002c-MMIX">assembler directive OCTA, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-PREFIX_002c-MMIX">assembler directive PREFIX, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-TETRA_002c-MMIX">assembler directive TETRA, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directive-WYDE_002c-MMIX">assembler directive WYDE, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directives_002c-CRIS">assembler directives, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directives_002c-M68HC11">assembler directives, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directives_002c-M68HC12">assembler directives, M68HC12</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directives_002c-MMIX">assembler directives, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directives_002c-RL78">assembler directives, RL78</a>:</td><td> </td><td valign="top"><a href="#RL78_002dDirectives">RL78-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directives_002c-RX">assembler directives, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dDirectives">RX-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-directives_002c-XGATE">assembler directives, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dDirectives">XGATE-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-internal-logic-error">assembler internal logic error</a>:</td><td> </td><td valign="top"><a href="#As-Sections">As Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler-version">assembler version</a>:</td><td> </td><td valign="top"><a href="#v">v</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembler_002c-and-linker">assembler, and linker</a>:</td><td> </td><td valign="top"><a href="#Secs-Background">Secs Background</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assembly-listings_002c-enabling">assembly listings, enabling</a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assigning-values-to-symbols">assigning values to symbols</a>:</td><td> </td><td valign="top"><a href="#Setting-Symbols">Setting Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-assigning-values-to-symbols-1">assigning values to symbols</a>:</td><td> </td><td valign="top"><a href="#Equ">Equ</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-at-register_002c-MIPS"><code>at</code> register, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-Macros">MIPS Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-attributes_002c-symbol">attributes, symbol</a>:</td><td> </td><td valign="top"><a href="#Symbol-Attributes">Symbol Attributes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-att_005fsyntax-pseudo-op_002c-i386">att_syntax pseudo op, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-att_005fsyntax-pseudo-op_002c-x86_002d64">att_syntax pseudo op, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-auxiliary-attributes_002c-COFF-symbols">auxiliary attributes, COFF symbols</a>:</td><td> </td><td valign="top"><a href="#COFF-Symbols">COFF Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-auxiliary-symbol-information_002c-COFF">auxiliary symbol information, COFF</a>:</td><td> </td><td valign="top"><a href="#Dim">Dim</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AVR-line-comment-character">AVR line comment character</a>:</td><td> </td><td valign="top"><a href="#AVR_002dChars">AVR-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AVR-line-separator">AVR line separator</a>:</td><td> </td><td valign="top"><a href="#AVR_002dChars">AVR-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AVR-modifiers">AVR modifiers</a>:</td><td> </td><td valign="top"><a href="#AVR_002dModifiers">AVR-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AVR-opcode-summary">AVR opcode summary</a>:</td><td> </td><td valign="top"><a href="#AVR-Opcodes">AVR Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AVR-options-_0028none_0029">AVR options (none)</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AVR-register-names">AVR register names</a>:</td><td> </td><td valign="top"><a href="#AVR_002dRegs">AVR-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-AVR-support">AVR support</a>:</td><td> </td><td valign="top"><a href="#AVR_002dDependent">AVR-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-A_005fDIR-environment-variable_002c-TIC54X">‘<samp>A_DIR</samp>’ environment variable, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dEnv">TIC54X-Env</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-B">B</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-backslash-_0028_005c_005c_0029">backslash (<code>\\</code>)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-backspace-_0028_005cb_0029">backspace (<code>\b</code>)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-balign-directive"><code>balign</code> directive</a>:</td><td> </td><td valign="top"><a href="#Balign">Balign</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-balignl-directive"><code>balignl</code> directive</a>:</td><td> </td><td valign="top"><a href="#Balign">Balign</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-balignw-directive"><code>balignw</code> directive</a>:</td><td> </td><td valign="top"><a href="#Balign">Balign</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bes-directive_002c-TIC54X"><code>bes</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bfloat16-directive_002c-i386"><code>bfloat16</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bfloat16-directive_002c-x86_002d64"><code>bfloat16</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-big-endian-output_002c-MIPS">big endian output, MIPS</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-big-endian-output_002c-PJ">big endian output, PJ</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-big_002dendian-output_002c-MIPS">big-endian output, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-big_002dendian-output_002c-TIC6X">big-endian output, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bignums">bignums</a>:</td><td> </td><td valign="top"><a href="#Bignums">Bignums</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-binary-constants_002c-TIC54X">binary constants, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dConstants">TIC54X-Constants</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-binary-files_002c-including">binary files, including</a>:</td><td> </td><td valign="top"><a href="#Incbin">Incbin</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-binary-integers">binary integers</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bit-names_002c-IA_002d64">bit names, IA-64</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dBits">IA-64-Bits</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bitfields_002c-not-supported-on-VAX">bitfields, not supported on VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dno">VAX-no</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Blackfin-directives">Blackfin directives</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Directives">Blackfin Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Blackfin-options-_0028none_0029">Blackfin options (none)</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Options">Blackfin Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Blackfin-support">Blackfin support</a>:</td><td> </td><td valign="top"><a href="#Blackfin_002dDependent">Blackfin-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Blackfin-syntax">Blackfin syntax</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Syntax">Blackfin Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-block"><code>block</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BMI_002c-i386">BMI, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dBMI">i386-BMI</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BMI_002c-x86_002d64">BMI, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dBMI">i386-BMI</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BPF-line-comment-character">BPF line comment character</a>:</td><td> </td><td valign="top"><a href="#BPF_002dChars">BPF-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BPF-opcodes">BPF opcodes</a>:</td><td> </td><td valign="top"><a href="#BPF-Opcodes">BPF Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BPF-options-_0028none_0029">BPF options (none)</a>:</td><td> </td><td valign="top"><a href="#BPF-Options">BPF Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BPF-register-names">BPF register names</a>:</td><td> </td><td valign="top"><a href="#BPF_002dRegs">BPF-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BPF-support">BPF support</a>:</td><td> </td><td valign="top"><a href="#BPF_002dDependent">BPF-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-branch-improvement_002c-M680x0">branch improvement, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dBranch">M68K-Branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-branch-improvement_002c-M68HC11">branch improvement, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dBranch">M68HC11-Branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-branch-improvement_002c-VAX">branch improvement, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dbranch">VAX-branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-branch-instructions_002c-relaxation">branch instructions, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Branch-Relaxation">Xtensa Branch Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Branch-Target-Address_002c-ARC">Branch Target Address, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-branch-target-alignment">branch target alignment</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Automatic-Alignment">Xtensa Automatic Alignment</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-break-directive_002c-TIC54X"><code>break</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BSD-syntax">BSD syntax</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dSyntax">PDP-11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bss-directive"><code>bss</code> directive</a>:</td><td> </td><td valign="top"><a href="#Bss">Bss</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BSS-directive">BSS directive</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bss-directive_002c-TIC54X"><code>bss</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bss-section">bss section</a>:</td><td> </td><td valign="top"><a href="#Ld-Sections">Ld Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bss-section-1">bss section</a>:</td><td> </td><td valign="top"><a href="#bss">bss</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-BTA-saved-on-exception-entry_002c-ARC">BTA saved on exception entry, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bug-criteria">bug criteria</a>:</td><td> </td><td valign="top"><a href="#Bug-Criteria">Bug Criteria</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bug-reports">bug reports</a>:</td><td> </td><td valign="top"><a href="#Bug-Reporting">Bug Reporting</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bugs-in-assembler">bugs in assembler</a>:</td><td> </td><td valign="top"><a href="#Reporting-Bugs">Reporting Bugs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Build-configuration-for_003a-BTA-Registers_002c-ARC">Build configuration for: BTA Registers, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Build-configuration-for_003a-Core-Registers_002c-ARC">Build configuration for: Core Registers, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Build-configuration-for_003a-Interrupts_002c-ARC">Build configuration for: Interrupts, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Build-Configuration-Registers-Version_002c-ARC">Build Configuration Registers Version, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Built_002din-symbols_002c-CRIS">Built-in symbols, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dSymbols">CRIS-Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-builtin-math-functions_002c-TIC54X">builtin math functions, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-builtin-subsym-functions_002c-TIC54X">builtin subsym functions, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bundle">bundle</a>:</td><td> </td><td valign="top"><a href="#Bundle-directives">Bundle directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bundle_002dlocked">bundle-locked</a>:</td><td> </td><td valign="top"><a href="#Bundle-directives">Bundle directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bundle_005falign_005fmode-directive"><code>bundle_align_mode</code> directive</a>:</td><td> </td><td valign="top"><a href="#Bundle-directives">Bundle directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bundle_005flock-directive"><code>bundle_lock</code> directive</a>:</td><td> </td><td valign="top"><a href="#Bundle-directives">Bundle directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bundle_005funlock-directive"><code>bundle_unlock</code> directive</a>:</td><td> </td><td valign="top"><a href="#Bundle-directives">Bundle directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bus-lock-prefixes_002c-i386">bus lock prefixes, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-bval"><code>bval</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-byte-directive"><code>byte</code> directive</a>:</td><td> </td><td valign="top"><a href="#Byte">Byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-byte-directive_002c-TIC54X"><code>byte</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-C">C</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-C-preprocessor-macro-separator_002c-ARC">C preprocessor macro separator, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-C_002dSKY-options">C-SKY options</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-C_002dSKY-support">C-SKY support</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY_002dDependent">C-SKY-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-C54XDSP_005fDIR-environment-variable_002c-TIC54X">‘<samp>C54XDSP_DIR</samp>’ environment variable, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dEnv">TIC54X-Env</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-call-directive_002c-Nios-II"><code>call</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-call-instructions_002c-i386">call instructions, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-call-instructions_002c-relaxation">call instructions, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Call-Relaxation">Xtensa Call Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-call-instructions_002c-x86_002d64">call instructions, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-call_005fhiadj-directive_002c-Nios-II"><code>call_hiadj</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-call_005flo-directive_002c-Nios-II"><code>call_lo</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-carriage-return-_0028backslash_002dr_0029">carriage return (<code>backslash-r</code>)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-case-sensitivity_002c-Z80">case sensitivity, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dCase">Z80-Case</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-cfi_005fendproc-directive"><code>cfi_endproc</code> directive</a>:</td><td> </td><td valign="top"><a href="#CFI-directives">CFI directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-cfi_005ffde_005fdata-directive"><code>cfi_fde_data</code> directive</a>:</td><td> </td><td valign="top"><a href="#CFI-directives">CFI directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-cfi_005fpersonality-directive"><code>cfi_personality</code> directive</a>:</td><td> </td><td valign="top"><a href="#CFI-directives">CFI directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-cfi_005fpersonality_005fid-directive"><code>cfi_personality_id</code> directive</a>:</td><td> </td><td valign="top"><a href="#CFI-directives">CFI directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-cfi_005fsections-directive"><code>cfi_sections</code> directive</a>:</td><td> </td><td valign="top"><a href="#CFI-directives">CFI directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-cfi_005fstartproc-directive"><code>cfi_startproc</code> directive</a>:</td><td> </td><td valign="top"><a href="#CFI-directives">CFI directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-char-directive_002c-TIC54X"><code>char</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-character-constant_002c-Z80">character constant, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-character-constants">character constants</a>:</td><td> </td><td valign="top"><a href="#Characters">Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-character-escape-codes">character escape codes</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-character-escapes_002c-Z80">character escapes, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-character_002c-single">character, single</a>:</td><td> </td><td valign="top"><a href="#Chars">Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-characters-used-in-symbols">characters used in symbols</a>:</td><td> </td><td valign="top"><a href="#Symbol-Intro">Symbol Intro</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-clink-directive_002c-TIC54X"><code>clink</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-code16-directive_002c-i386"><code>code16</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002d16bit">i386-16bit</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-code16gcc-directive_002c-i386"><code>code16gcc</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002d16bit">i386-16bit</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-code32-directive_002c-i386"><code>code32</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002d16bit">i386-16bit</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-code64-directive_002c-i386"><code>code64</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002d16bit">i386-16bit</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-code64-directive_002c-x86_002d64"><code>code64</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002d16bit">i386-16bit</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-COFF-auxiliary-symbol-information">COFF auxiliary symbol information</a>:</td><td> </td><td valign="top"><a href="#Dim">Dim</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-COFF-structure-debugging">COFF structure debugging</a>:</td><td> </td><td valign="top"><a href="#Tag">Tag</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-COFF-symbol-attributes">COFF symbol attributes</a>:</td><td> </td><td valign="top"><a href="#COFF-Symbols">COFF Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-COFF-symbol-descriptor">COFF symbol descriptor</a>:</td><td> </td><td valign="top"><a href="#Desc">Desc</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-COFF-symbol-storage-class">COFF symbol storage class</a>:</td><td> </td><td valign="top"><a href="#Scl">Scl</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-COFF-symbol-type">COFF symbol type</a>:</td><td> </td><td valign="top"><a href="#Type">Type</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-COFF-symbols_002c-debugging">COFF symbols, debugging</a>:</td><td> </td><td valign="top"><a href="#Def">Def</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-COFF-value-attribute">COFF value attribute</a>:</td><td> </td><td valign="top"><a href="#Val">Val</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-COMDAT">COMDAT</a>:</td><td> </td><td valign="top"><a href="#Linkonce">Linkonce</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-comm-directive"><code>comm</code> directive</a>:</td><td> </td><td valign="top"><a href="#Comm">Comm</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-command-line-conventions">command line conventions</a>:</td><td> </td><td valign="top"><a href="#Command-Line">Command Line</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-command_002dline-options-ignored_002c-VAX">command-line options ignored, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-command_002dline-options_002c-V850">command-line options, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-comment-character_002c-XStormy16">comment character, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16_002dChars">XStormy16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-comments">comments</a>:</td><td> </td><td valign="top"><a href="#Comments">Comments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-comments_002c-M680x0">comments, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dChars">M68K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-comments_002c-removed-by-preprocessor">comments, removed by preprocessor</a>:</td><td> </td><td valign="top"><a href="#Preprocessing">Preprocessing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-common-directive_002c-SPARC"><code>common</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-common-sections">common sections</a>:</td><td> </td><td valign="top"><a href="#Linkonce">Linkonce</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-common-variable-storage">common variable storage</a>:</td><td> </td><td valign="top"><a href="#bss">bss</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-comparison-expressions">comparison expressions</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-conditional-assembly">conditional assembly</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constant_002c-single-character">constant, single character</a>:</td><td> </td><td valign="top"><a href="#Chars">Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants">constants</a>:</td><td> </td><td valign="top"><a href="#Constants">Constants</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants_002c-bignum">constants, bignum</a>:</td><td> </td><td valign="top"><a href="#Bignums">Bignums</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants_002c-character">constants, character</a>:</td><td> </td><td valign="top"><a href="#Characters">Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants_002c-converted-by-preprocessor">constants, converted by preprocessor</a>:</td><td> </td><td valign="top"><a href="#Preprocessing">Preprocessing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants_002c-floating-point">constants, floating point</a>:</td><td> </td><td valign="top"><a href="#Flonums">Flonums</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants_002c-integer">constants, integer</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants_002c-number">constants, number</a>:</td><td> </td><td valign="top"><a href="#Numbers">Numbers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants_002c-Sparc">constants, Sparc</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dConstants">Sparc-Constants</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants_002c-string">constants, string</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-constants_002c-TIC54X">constants, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dConstants">TIC54X-Constants</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-conversion-instructions_002c-i386">conversion instructions, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-conversion-instructions_002c-x86_002d64">conversion instructions, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-coprocessor-wait_002c-i386">coprocessor wait, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-copy-directive_002c-TIC54X"><code>copy</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-core-general-registers_002c-ARC">core general registers, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-cpu-directive_002c-ARC"><code>cpu</code> directive, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-cpu-directive_002c-M680x0"><code>cpu</code> directive, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dDirectives">M68K-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-cpu-directive_002c-MSP-430"><code>cpu</code> directive, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Directives">MSP430 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CR16-line-comment-character">CR16 line comment character</a>:</td><td> </td><td valign="top"><a href="#CR16_002dChars">CR16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CR16-line-separator">CR16 line separator</a>:</td><td> </td><td valign="top"><a href="#CR16_002dChars">CR16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CR16-Operand-Qualifiers">CR16 Operand Qualifiers</a>:</td><td> </td><td valign="top"><a href="#CR16-Operand-Qualifiers">CR16 Operand Qualifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CR16-support">CR16 support</a>:</td><td> </td><td valign="top"><a href="#CR16_002dDependent">CR16-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-crash-of-assembler">crash of assembler</a>:</td><td> </td><td valign="top"><a href="#Bug-Criteria">Bug Criteria</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-_002d_002demulation_003dcrisaout-command_002dline-option">CRIS <samp>--emulation=crisaout</samp> command-line option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-_002d_002demulation_003dcriself-command_002dline-option">CRIS <samp>--emulation=criself</samp> command-line option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-_002d_002dmarch_003darchitecture-command_002dline-option">CRIS <samp>--march=<var>architecture</var></samp> command-line option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-_002d_002dmul_002dbug_002dabort-command_002dline-option">CRIS <samp>--mul-bug-abort</samp> command-line option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-_002d_002dno_002dmul_002dbug_002dabort-command_002dline-option">CRIS <samp>--no-mul-bug-abort</samp> command-line option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-_002d_002dno_002dunderscore-command_002dline-option">CRIS <samp>--no-underscore</samp> command-line option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-_002d_002dpic-command_002dline-option">CRIS <samp>--pic</samp> command-line option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-_002d_002dunderscore-command_002dline-option">CRIS <samp>--underscore</samp> command-line option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-_002dN-command_002dline-option">CRIS <samp>-N</samp> command-line option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-architecture-variant-option">CRIS architecture variant option</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-assembler-directive-_002earch">CRIS assembler directive .arch</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-assembler-directive-_002edword">CRIS assembler directive .dword</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-assembler-directive-_002esyntax">CRIS assembler directive .syntax</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-assembler-directives">CRIS assembler directives</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-built_002din-symbols">CRIS built-in symbols</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dSymbols">CRIS-Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-instruction-expansion">CRIS instruction expansion</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dExpand">CRIS-Expand</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-line-comment-characters">CRIS line comment characters</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dChars">CRIS-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-options">CRIS options</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-position_002dindependent-code">CRIS position-independent code</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-pseudo_002dop-_002earch">CRIS pseudo-op .arch</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-pseudo_002dop-_002edword">CRIS pseudo-op .dword</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-pseudo_002dop-_002esyntax">CRIS pseudo-op .syntax</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-pseudo_002dops">CRIS pseudo-ops</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-register-names">CRIS register names</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dRegs">CRIS-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-support">CRIS support</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dDependent">CRIS-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-CRIS-symbols-in-position_002dindependent-code">CRIS symbols in position-independent code</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPic">CRIS-Pic</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ctbp-register_002c-V850"><code>ctbp</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ctoff-pseudo_002dop_002c-V850"><code>ctoff</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ctpc-register_002c-V850"><code>ctpc</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ctpsw-register_002c-V850"><code>ctpsw</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-current-address">current address</a>:</td><td> </td><td valign="top"><a href="#Dot">Dot</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-current-address_002c-advancing">current address, advancing</a>:</td><td> </td><td valign="top"><a href="#Org">Org</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-custom-_0028vendor_002ddefined_0029-extensions_002c-RISC_002dV">custom (vendor-defined) extensions, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dCustomExts">RISC-V-CustomExts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-c_005fmode-directive_002c-TIC54X"><code>c_mode</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-D">D</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-_0040word-modifier">D10V @word modifier</a>:</td><td> </td><td valign="top"><a href="#D10V_002dWord">D10V-Word</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-addressing-modes">D10V addressing modes</a>:</td><td> </td><td valign="top"><a href="#D10V_002dAddressing">D10V-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-floating-point">D10V floating point</a>:</td><td> </td><td valign="top"><a href="#D10V_002dFloat">D10V-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-line-comment-character">D10V line comment character</a>:</td><td> </td><td valign="top"><a href="#D10V_002dChars">D10V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-opcode-summary">D10V opcode summary</a>:</td><td> </td><td valign="top"><a href="#D10V_002dOpcodes">D10V-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-optimization">D10V optimization</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-options">D10V options</a>:</td><td> </td><td valign="top"><a href="#D10V_002dOpts">D10V-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-registers">D10V registers</a>:</td><td> </td><td valign="top"><a href="#D10V_002dRegs">D10V-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-size-modifiers">D10V size modifiers</a>:</td><td> </td><td valign="top"><a href="#D10V_002dSize">D10V-Size</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-sub_002dinstruction-ordering">D10V sub-instruction ordering</a>:</td><td> </td><td valign="top"><a href="#D10V_002dChars">D10V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-sub_002dinstructions">D10V sub-instructions</a>:</td><td> </td><td valign="top"><a href="#D10V_002dSubs">D10V-Subs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-support">D10V support</a>:</td><td> </td><td valign="top"><a href="#D10V_002dDependent">D10V-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D10V-syntax">D10V syntax</a>:</td><td> </td><td valign="top"><a href="#D10V_002dSyntax">D10V-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-d24-directive_002c-Z80"><code>d24</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-addressing-modes">D30V addressing modes</a>:</td><td> </td><td valign="top"><a href="#D30V_002dAddressing">D30V-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-floating-point">D30V floating point</a>:</td><td> </td><td valign="top"><a href="#D30V_002dFloat">D30V-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-Guarded-Execution">D30V Guarded Execution</a>:</td><td> </td><td valign="top"><a href="#D30V_002dGuarded">D30V-Guarded</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-line-comment-character">D30V line comment character</a>:</td><td> </td><td valign="top"><a href="#D30V_002dChars">D30V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-nops">D30V nops</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-nops-after-32_002dbit-multiply">D30V nops after 32-bit multiply</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-opcode-summary">D30V opcode summary</a>:</td><td> </td><td valign="top"><a href="#D30V_002dOpcodes">D30V-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-optimization">D30V optimization</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-options">D30V options</a>:</td><td> </td><td valign="top"><a href="#D30V_002dOpts">D30V-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-registers">D30V registers</a>:</td><td> </td><td valign="top"><a href="#D30V_002dRegs">D30V-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-size-modifiers">D30V size modifiers</a>:</td><td> </td><td valign="top"><a href="#D30V_002dSize">D30V-Size</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-sub_002dinstruction-ordering">D30V sub-instruction ordering</a>:</td><td> </td><td valign="top"><a href="#D30V_002dChars">D30V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-sub_002dinstructions">D30V sub-instructions</a>:</td><td> </td><td valign="top"><a href="#D30V_002dSubs">D30V-Subs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-support">D30V support</a>:</td><td> </td><td valign="top"><a href="#D30V_002dDependent">D30V-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-D30V-syntax">D30V syntax</a>:</td><td> </td><td valign="top"><a href="#D30V_002dSyntax">D30V-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-d32-directive_002c-Z80"><code>d32</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-data-alignment-on-SPARC">data alignment on SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dAligned_002dData">Sparc-Aligned-Data</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-data-and-text-sections_002c-joining">data and text sections, joining</a>:</td><td> </td><td valign="top"><a href="#R">R</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-data-directive"><code>data</code> directive</a>:</td><td> </td><td valign="top"><a href="#Data">Data</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-data-directive_002c-TIC54X"><code>data</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Data-directives">Data directives</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-data-relocations_002c-ARM">data relocations, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM_002dRelocations">ARM-Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-data-section">data section</a>:</td><td> </td><td valign="top"><a href="#Ld-Sections">Ld Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-data1-directive_002c-M680x0"><code>data1</code> directive, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dDirectives">M68K-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-data2-directive_002c-M680x0"><code>data2</code> directive, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dDirectives">M68K-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-db-directive_002c-Z80"><code>db</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dbpc-register_002c-V850"><code>dbpc</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dbpsw-register_002c-V850"><code>dbpsw</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dc-directive"><code>dc</code> directive</a>:</td><td> </td><td valign="top"><a href="#Dc">Dc</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dcb-directive"><code>dcb</code> directive</a>:</td><td> </td><td valign="top"><a href="#Dcb">Dcb</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-DCCM-RAM-Configuration-Register_002c-ARC">DCCM RAM Configuration Register, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-debuggers_002c-and-symbol-order">debuggers, and symbol order</a>:</td><td> </td><td valign="top"><a href="#Symbols">Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-debugging-COFF-symbols">debugging COFF symbols</a>:</td><td> </td><td valign="top"><a href="#Def">Def</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-DEC-syntax">DEC syntax</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dSyntax">PDP-11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-decimal-integers">decimal integers</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-def-directive"><code>def</code> directive</a>:</td><td> </td><td valign="top"><a href="#Def">Def</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-def-directive_002c-TIC54X"><code>def</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-def24-directive_002c-Z80"><code>def24</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-def32-directive_002c-Z80"><code>def32</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-defb-directive_002c-Z80"><code>defb</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-defl-directive_002c-Z80"><code>defl</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-defm-directive_002c-Z80"><code>defm</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-defs-directive_002c-Z80"><code>defs</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-defw-directive_002c-Z80"><code>defw</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-density-instructions">density instructions</a>:</td><td> </td><td valign="top"><a href="#Density-Instructions">Density Instructions</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dependency-tracking">dependency tracking</a>:</td><td> </td><td valign="top"><a href="#MD">MD</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-deprecated-directives">deprecated directives</a>:</td><td> </td><td valign="top"><a href="#Deprecated">Deprecated</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-desc-directive"><code>desc</code> directive</a>:</td><td> </td><td valign="top"><a href="#Desc">Desc</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-descriptor_002c-of-a_002eout-symbol">descriptor, of <code>a.out</code> symbol</a>:</td><td> </td><td valign="top"><a href="#Symbol-Desc">Symbol Desc</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dfloat-directive_002c-VAX"><code>dfloat</code> directive, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002ddirectives">VAX-directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-difference-tables-altered">difference tables altered</a>:</td><td> </td><td valign="top"><a href="#Word">Word</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-difference-tables_002c-warning">difference tables, warning</a>:</td><td> </td><td valign="top"><a href="#K">K</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-differences_002c-mmixal">differences, mmixal</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dmmixal">MMIX-mmixal</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dim-directive"><code>dim</code> directive</a>:</td><td> </td><td valign="top"><a href="#Dim">Dim</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-directives-and-instructions">directives and instructions</a>:</td><td> </td><td valign="top"><a href="#Statements">Statements</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-directives-for-PowerPC">directives for PowerPC</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dPseudo">PowerPC-Pseudo</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-directives-for-SCORE">directives for SCORE</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dPseudo">SCORE-Pseudo</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-directives_002c-Blackfin">directives, Blackfin</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Directives">Blackfin Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-directives_002c-M32R">directives, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-directives_002c-M680x0">directives, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dDirectives">M68K-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-directives_002c-machine-independent">directives, machine independent</a>:</td><td> </td><td valign="top"><a href="#Pseudo-Ops">Pseudo Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-directives_002c-Xtensa">directives, Xtensa</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Directives">Xtensa Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-directives_002c-Z8000">directives, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Disable-floating_002dpoint-instructions">Disable floating-point instructions</a>:</td><td> </td><td valign="top"><a href="#MIPS-Floating_002dPoint">MIPS Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Disable-single_002dprecision-floating_002dpoint-operations">Disable single-precision floating-point operations</a>:</td><td> </td><td valign="top"><a href="#MIPS-Floating_002dPoint">MIPS Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-displacement-sizing-character_002c-VAX">displacement sizing character, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dollar-local-symbols">dollar local symbols</a>:</td><td> </td><td valign="top"><a href="#Symbol-Names">Symbol Names</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dot-_0028symbol_0029">dot (symbol)</a>:</td><td> </td><td valign="top"><a href="#Dot">Dot</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-double-directive"><code>double</code> directive</a>:</td><td> </td><td valign="top"><a href="#Double">Double</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-double-directive_002c-i386"><code>double</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-double-directive_002c-M680x0"><code>double</code> directive, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dFloat">M68K-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-double-directive_002c-M68HC11"><code>double</code> directive, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dFloat">M68HC11-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-double-directive_002c-RX"><code>double</code> directive, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dFloat">RX-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-double-directive_002c-TIC54X"><code>double</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-double-directive_002c-VAX"><code>double</code> directive, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dfloat">VAX-float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-double-directive_002c-x86_002d64"><code>double</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-double-directive_002c-XGATE"><code>double</code> directive, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dFloat">XGATE-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-doublequote-_0028_005c_0022_0029">doublequote (<code>\"</code>)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-drlist-directive_002c-TIC54X"><code>drlist</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-drnolist-directive_002c-TIC54X"><code>drnolist</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ds-directive"><code>ds</code> directive</a>:</td><td> </td><td valign="top"><a href="#Ds">Ds</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ds-directive_002c-Z80"><code>ds</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-DTP_002drelative-data-directives">DTP-relative data directives</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dw-directive_002c-Z80"><code>dw</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dword-directive_002c-BPF"><code>dword</code> directive, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF-Directives">BPF Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dword-directive_002c-Nios-II"><code>dword</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-dword-directive_002c-PRU"><code>dword</code> directive, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-E">E</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-EB-command_002dline-option_002c-C_002dSKY"><code>EB</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-EB-command_002dline-option_002c-Nios-II"><code>EB</code> command-line option, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Options">Nios II Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ecr-register_002c-V850"><code>ecr</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-eight_002dbyte-integer">eight-byte integer</a>:</td><td> </td><td valign="top"><a href="#Quad">Quad</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-eight_002dbyte-integer-1">eight-byte integer</a>:</td><td> </td><td valign="top"><a href="#g_t8byte">8byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-eipc-register_002c-V850"><code>eipc</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-eipsw-register_002c-V850"><code>eipsw</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-eject-directive"><code>eject</code> directive</a>:</td><td> </td><td valign="top"><a href="#Eject">Eject</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-EL-command_002dline-option_002c-C_002dSKY"><code>EL</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-EL-command_002dline-option_002c-Nios-II"><code>EL</code> command-line option, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Options">Nios II Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ELF-symbol-type">ELF symbol type</a>:</td><td> </td><td valign="top"><a href="#Type">Type</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-else-directive"><code>else</code> directive</a>:</td><td> </td><td valign="top"><a href="#Else">Else</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-elseif-directive"><code>elseif</code> directive</a>:</td><td> </td><td valign="top"><a href="#Elseif">Elseif</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-empty-expressions">empty expressions</a>:</td><td> </td><td valign="top"><a href="#Empty-Exprs">Empty Exprs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-emsg-directive_002c-TIC54X"><code>emsg</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-emulation">emulation</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-encoding-options_002c-i386">encoding options, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-encoding-options_002c-x86_002d64">encoding options, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-end-directive"><code>end</code> directive</a>:</td><td> </td><td valign="top"><a href="#End">End</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endef-directive"><code>endef</code> directive</a>:</td><td> </td><td valign="top"><a href="#Endef">Endef</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endfunc-directive"><code>endfunc</code> directive</a>:</td><td> </td><td valign="top"><a href="#Endfunc">Endfunc</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endianness_002c-MIPS">endianness, MIPS</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endianness_002c-PJ">endianness, PJ</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endif-directive"><code>endif</code> directive</a>:</td><td> </td><td valign="top"><a href="#Endif">Endif</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endloop-directive_002c-TIC54X"><code>endloop</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endm-directive"><code>endm</code> directive</a>:</td><td> </td><td valign="top"><a href="#Macro">Macro</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endm-directive_002c-TIC54X"><code>endm</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endproc-directive_002c-OpenRISC"><code>endproc</code> directive, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDirectives">OpenRISC-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endstruct-directive_002c-TIC54X"><code>endstruct</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-endunion-directive_002c-TIC54X"><code>endunion</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-environment-settings_002c-TIC54X">environment settings, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dEnv">TIC54X-Env</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-EOF_002c-newline-must-precede">EOF, newline must precede</a>:</td><td> </td><td valign="top"><a href="#Statements">Statements</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ep-register_002c-V850"><code>ep</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Epiphany-line-comment-character">Epiphany line comment character</a>:</td><td> </td><td valign="top"><a href="#Epiphany_002dChars">Epiphany-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Epiphany-line-separator">Epiphany line separator</a>:</td><td> </td><td valign="top"><a href="#Epiphany_002dChars">Epiphany-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Epiphany-options">Epiphany options</a>:</td><td> </td><td valign="top"><a href="#Epiphany-Options">Epiphany Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Epiphany-support">Epiphany support</a>:</td><td> </td><td valign="top"><a href="#Epiphany_002dDependent">Epiphany-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-equ-directive"><code>equ</code> directive</a>:</td><td> </td><td valign="top"><a href="#Equ">Equ</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-equ-directive_002c-TIC54X"><code>equ</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-equ-directive_002c-Z80"><code>equ</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-equiv-directive"><code>equiv</code> directive</a>:</td><td> </td><td valign="top"><a href="#Equiv">Equiv</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-eqv-directive"><code>eqv</code> directive</a>:</td><td> </td><td valign="top"><a href="#Eqv">Eqv</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-err-directive"><code>err</code> directive</a>:</td><td> </td><td valign="top"><a href="#Err">Err</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-error-directive">error directive</a>:</td><td> </td><td valign="top"><a href="#Error">Error</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-error-messages">error messages</a>:</td><td> </td><td valign="top"><a href="#Errors">Errors</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-error-on-valid-input">error on valid input</a>:</td><td> </td><td valign="top"><a href="#Bug-Criteria">Bug Criteria</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-errors_002c-caused-by-warnings">errors, caused by warnings</a>:</td><td> </td><td valign="top"><a href="#W">W</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-errors_002c-continuing-after">errors, continuing after</a>:</td><td> </td><td valign="top"><a href="#Z">Z</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-escape-codes_002c-character">escape codes, character</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-eval-directive_002c-TIC54X"><code>eval</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-even"><code>even</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-even-directive_002c-M680x0"><code>even</code> directive, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dDirectives">M68K-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-even-directive_002c-TIC54X"><code>even</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Exception-Cause-Register_002c-ARC">Exception Cause Register, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Exception-Return-Address_002c-ARC">Exception Return Address, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-exitm-directive"><code>exitm</code> directive</a>:</td><td> </td><td valign="top"><a href="#Macro">Macro</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-expr-_0028internal-section_0029">expr (internal section)</a>:</td><td> </td><td valign="top"><a href="#As-Sections">As Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-expression-arguments">expression arguments</a>:</td><td> </td><td valign="top"><a href="#Arguments">Arguments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-expressions">expressions</a>:</td><td> </td><td valign="top"><a href="#Expressions">Expressions</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-expressions_002c-comparison">expressions, comparison</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-expressions_002c-empty">expressions, empty</a>:</td><td> </td><td valign="top"><a href="#Empty-Exprs">Empty Exprs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-expressions_002c-integer">expressions, integer</a>:</td><td> </td><td valign="top"><a href="#Integer-Exprs">Integer Exprs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extAuxRegister-directive_002c-ARC"><code>extAuxRegister</code> directive, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extCondCode-directive_002c-ARC"><code>extCondCode</code> directive, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extCoreRegister-directive_002c-ARC"><code>extCoreRegister</code> directive, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extend-directive-M680x0"><code>extend</code> directive M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dFloat">M68K-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extend-directive-M68HC11"><code>extend</code> directive M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dFloat">M68HC11-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extend-directive-XGATE"><code>extend</code> directive XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dFloat">XGATE-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extension-core-registers_002c-ARC">extension core registers, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extension-instructions_002c-i386">extension instructions, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extension-instructions_002c-x86_002d64">extension instructions, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extern-directive"><code>extern</code> directive</a>:</td><td> </td><td valign="top"><a href="#Extern">Extern</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-extInstruction-directive_002c-ARC"><code>extInstruction</code> directive, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-F">F</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-fail-directive"><code>fail</code> directive</a>:</td><td> </td><td valign="top"><a href="#Fail">Fail</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-far_005fmode-directive_002c-TIC54X"><code>far_mode</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-faster-processing-_0028_002df_0029">faster processing (<samp>-f</samp>)</a>:</td><td> </td><td valign="top"><a href="#f">f</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-fatal-signal">fatal signal</a>:</td><td> </td><td valign="top"><a href="#Bug-Criteria">Bug Criteria</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-fclist-directive_002c-TIC54X"><code>fclist</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-fcnolist-directive_002c-TIC54X"><code>fcnolist</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-fepc-register_002c-V850"><code>fepc</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-fepsw-register_002c-V850"><code>fepsw</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ffloat-directive_002c-VAX"><code>ffloat</code> directive, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002ddirectives">VAX-directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-field-directive_002c-TIC54X"><code>field</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-file-directive"><code>file</code> directive</a>:</td><td> </td><td valign="top"><a href="#File">File</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-file-directive_002c-MSP-430"><code>file</code> directive, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Directives">MSP430 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-file-name_002c-logical">file name, logical</a>:</td><td> </td><td valign="top"><a href="#File">File</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-file-names-and-line-numbers_002c-in-warnings_002ferrors">file names and line numbers, in warnings/errors</a>:</td><td> </td><td valign="top"><a href="#Errors">Errors</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-files_002c-including">files, including</a>:</td><td> </td><td valign="top"><a href="#Include">Include</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-files_002c-input">files, input</a>:</td><td> </td><td valign="top"><a href="#Input-Files">Input Files</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-fill-directive"><code>fill</code> directive</a>:</td><td> </td><td valign="top"><a href="#Fill">Fill</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-filling-memory">filling memory</a>:</td><td> </td><td valign="top"><a href="#Skip">Skip</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-filling-memory-1">filling memory</a>:</td><td> </td><td valign="top"><a href="#Space">Space</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-filling-memory-with-no_002dop-instructions">filling memory with no-op instructions</a>:</td><td> </td><td valign="top"><a href="#Nop">Nop</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-filling-memory-with-no_002dop-instructions-1">filling memory with no-op instructions</a>:</td><td> </td><td valign="top"><a href="#Nops">Nops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-filling-memory-with-zero-bytes">filling memory with zero bytes</a>:</td><td> </td><td valign="top"><a href="#Zero">Zero</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-FLIX-syntax">FLIX syntax</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Syntax">Xtensa Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-float-directive"><code>float</code> directive</a>:</td><td> </td><td valign="top"><a href="#Float">Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-float-directive_002c-i386"><code>float</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-float-directive_002c-M680x0"><code>float</code> directive, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dFloat">M68K-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-float-directive_002c-M68HC11"><code>float</code> directive, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dFloat">M68HC11-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-float-directive_002c-RX"><code>float</code> directive, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dFloat">RX-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-float-directive_002c-TIC54X"><code>float</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-float-directive_002c-VAX"><code>float</code> directive, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dfloat">VAX-float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-float-directive_002c-x86_002d64"><code>float</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-float-directive_002c-XGATE"><code>float</code> directive, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dFloat">XGATE-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point-numbers">floating point numbers</a>:</td><td> </td><td valign="top"><a href="#Flonums">Flonums</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point-numbers-_0028double_0029">floating point numbers (double)</a>:</td><td> </td><td valign="top"><a href="#Double">Double</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point-numbers-_0028single_0029">floating point numbers (single)</a>:</td><td> </td><td valign="top"><a href="#Float">Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point-numbers-_0028single_0029-1">floating point numbers (single)</a>:</td><td> </td><td valign="top"><a href="#Single">Single</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-AArch64-_0028IEEE_0029">floating point, AArch64 (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#AArch64-Floating-Point">AArch64 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-Alpha-_0028IEEE_0029">floating point, Alpha (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#Alpha-Floating-Point">Alpha Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-ARM-_0028IEEE_0029">floating point, ARM (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#ARM-Floating-Point">ARM Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-D10V">floating point, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dFloat">D10V-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-D30V">floating point, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dFloat">D30V-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-H8_002f300-_0028IEEE_0029">floating point, H8/300 (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Floating-Point">H8/300 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-HPPA-_0028IEEE_0029">floating point, HPPA (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#HPPA-Floating-Point">HPPA Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-i386">floating point, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-M680x0">floating point, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dFloat">M68K-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-M68HC11">floating point, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dFloat">M68HC11-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-MSP-430-_0028IEEE_0029">floating point, MSP 430 (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#MSP430-Floating-Point">MSP430 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-OPENRISC-_0028IEEE_0029">floating point, OPENRISC (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dFloat">OpenRISC-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-risc_002dv-_0028IEEE_0029">floating point, risc-v (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dFloating_002dPoint">RISC-V-Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-RX">floating point, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dFloat">RX-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-s390">floating point, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Floating-Point">s390 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-SH-_0028IEEE_0029">floating point, SH (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#SH-Floating-Point">SH Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-SPARC-_0028IEEE_0029">floating point, SPARC (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dFloat">Sparc-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-V850-_0028IEEE_0029">floating point, V850 (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#V850-Floating-Point">V850 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-VAX">floating point, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dfloat">VAX-float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-WebAssembly-_0028IEEE_0029">floating point, WebAssembly (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dFloating_002dPoint">WebAssembly-Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-x86_002d64">floating point, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-XGATE">floating point, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dFloat">XGATE-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-floating-point_002c-Z80">floating point, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Floating-Point">Z80 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-flonums">flonums</a>:</td><td> </td><td valign="top"><a href="#Flonums">Flonums</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-force2bsr-command_002dline-option_002c-C_002dSKY"><code>force2bsr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-format-of-error-messages">format of error messages</a>:</td><td> </td><td valign="top"><a href="#Errors">Errors</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-format-of-warning-messages">format of warning messages</a>:</td><td> </td><td valign="top"><a href="#Errors">Errors</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-formfeed-_0028_005cf_0029">formfeed (<code>\f</code>)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-four_002dbyte-integer">four-byte integer</a>:</td><td> </td><td valign="top"><a href="#g_t4byte">4byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-fpic-command_002dline-option_002c-C_002dSKY"><code>fpic</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-frame-pointer_002c-ARC">frame pointer, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-func-directive"><code>func</code> directive</a>:</td><td> </td><td valign="top"><a href="#Func">Func</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-functions_002c-in-expressions">functions, in expressions</a>:</td><td> </td><td valign="top"><a href="#Operators">Operators</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-G">G</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-gfloat-directive_002c-VAX"><code>gfloat</code> directive, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002ddirectives">VAX-directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-global"><code>global</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-global-directive"><code>global</code> directive</a>:</td><td> </td><td valign="top"><a href="#Global">Global</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-global-directive_002c-TIC54X"><code>global</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-global-pointer_002c-ARC">global pointer, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-got-directive_002c-Nios-II"><code>got</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-gotoff-directive_002c-Nios-II"><code>gotoff</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-gotoff_005fhiadj-directive_002c-Nios-II"><code>gotoff_hiadj</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-gotoff_005flo-directive_002c-Nios-II"><code>gotoff_lo</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-got_005fhiadj-directive_002c-Nios-II"><code>got_hiadj</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-got_005flo-directive_002c-Nios-II"><code>got_lo</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-gp-register_002c-MIPS"><code>gp</code> register, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-Small-Data">MIPS Small Data</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-gp-register_002c-V850"><code>gp</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-gprel-directive_002c-Nios-II"><code>gprel</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-grouping-data">grouping data</a>:</td><td> </td><td valign="top"><a href="#Sub_002dSections">Sub-Sections</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-H">H</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-addressing-modes">H8/300 addressing modes</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dAddressing">H8/300-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-floating-point-_0028IEEE_0029">H8/300 floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Floating-Point">H8/300 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-line-comment-character">H8/300 line comment character</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dChars">H8/300-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-line-separator">H8/300 line separator</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dChars">H8/300-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-machine-directives-_0028none_0029">H8/300 machine directives (none)</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Directives">H8/300 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-opcode-summary">H8/300 opcode summary</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Opcodes">H8/300 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-options">H8/300 options</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Options">H8/300 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-registers">H8/300 registers</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dRegs">H8/300-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-size-suffixes">H8/300 size suffixes</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Opcodes">H8/300 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300-support">H8/300 support</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dDependent">H8/300-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-H8_002f300H_002c-assembling-for">H8/300H, assembling for</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Directives">H8/300 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-half-directive_002c-BPF"><code>half</code> directive, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF-Directives">BPF Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-half-directive_002c-Nios-II"><code>half</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-half-directive_002c-SPARC"><code>half</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-half-directive_002c-TIC54X"><code>half</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hex-character-code-_0028_005cxd_002e_002e_002e_0029">hex character code (<code>\<var>xd...</var></code>)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hexadecimal-integers">hexadecimal integers</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hexadecimal-prefix_002c-S12Z">hexadecimal prefix, S12Z</a>:</td><td> </td><td valign="top"><a href="#S12Z-Options">S12Z Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hexadecimal-prefix_002c-Z80">hexadecimal prefix, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hfloat-directive_002c-i386"><code>hfloat</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hfloat-directive_002c-VAX"><code>hfloat</code> directive, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002ddirectives">VAX-directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hfloat-directive_002c-x86_002d64"><code>hfloat</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hi-directive_002c-Nios-II"><code>hi</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hi-pseudo_002dop_002c-V850"><code>hi</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hi0-pseudo_002dop_002c-V850"><code>hi0</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hiadj-directive_002c-Nios-II"><code>hiadj</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hidden-directive"><code>hidden</code> directive</a>:</td><td> </td><td valign="top"><a href="#Hidden">Hidden</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-high-directive_002c-M32R"><code>high</code> directive, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hilo-pseudo_002dop_002c-V850"><code>hilo</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-HPPA-directives-not-supported">HPPA directives not supported</a>:</td><td> </td><td valign="top"><a href="#HPPA-Directives">HPPA Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-HPPA-floating-point-_0028IEEE_0029">HPPA floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#HPPA-Floating-Point">HPPA Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-HPPA-Syntax">HPPA Syntax</a>:</td><td> </td><td valign="top"><a href="#HPPA-Options">HPPA Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-HPPA_002donly-directives">HPPA-only directives</a>:</td><td> </td><td valign="top"><a href="#HPPA-Directives">HPPA Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-hword-directive"><code>hword</code> directive</a>:</td><td> </td><td valign="top"><a href="#hword">hword</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-I">I</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-16_002dbit-code">i386 16-bit code</a>:</td><td> </td><td valign="top"><a href="#i386_002d16bit">i386-16bit</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-arch-directive">i386 arch directive</a>:</td><td> </td><td valign="top"><a href="#i386_002dArch">i386-Arch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-att_005fsyntax-pseudo-op">i386 att_syntax pseudo op</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-conversion-instructions">i386 conversion instructions</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-extension-instructions">i386 extension instructions</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-floating-point">i386 floating point</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-immediate-operands">i386 immediate operands</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-instruction-naming">i386 instruction naming</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-instruction-prefixes">i386 instruction prefixes</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-intel_005fsyntax-pseudo-op">i386 intel_syntax pseudo op</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-jump-optimization">i386 jump optimization</a>:</td><td> </td><td valign="top"><a href="#i386_002dJumps">i386-Jumps</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-jump_002c-call_002c-return">i386 jump, call, return</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-jump_002fcall-operands">i386 jump/call operands</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-line-comment-character">i386 line comment character</a>:</td><td> </td><td valign="top"><a href="#i386_002dChars">i386-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-line-separator">i386 line separator</a>:</td><td> </td><td valign="top"><a href="#i386_002dChars">i386-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-memory-references">i386 memory references</a>:</td><td> </td><td valign="top"><a href="#i386_002dMemory">i386-Memory</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-mnemonic-compatibility">i386 mnemonic compatibility</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-mul_002c-imul-instructions">i386 <code>mul</code>, <code>imul</code> instructions</a>:</td><td> </td><td valign="top"><a href="#i386_002dNotes">i386-Notes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-options">i386 options</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-register-operands">i386 register operands</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-registers">i386 registers</a>:</td><td> </td><td valign="top"><a href="#i386_002dRegs">i386-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-sections">i386 sections</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-size-suffixes">i386 size suffixes</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-source_002c-destination-operands">i386 source, destination operands</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-support">i386 support</a>:</td><td> </td><td valign="top"><a href="#i386_002dDependent">i386-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i386-syntax-compatibility">i386 syntax compatibility</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-i80386-support">i80386 support</a>:</td><td> </td><td valign="top"><a href="#i386_002dDependent">i386-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IA_002d64-line-comment-character">IA-64 line comment character</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dChars">IA-64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IA_002d64-line-separator">IA-64 line separator</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dChars">IA-64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IA_002d64-options">IA-64 options</a>:</td><td> </td><td valign="top"><a href="#IA_002d64-Options">IA-64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IA_002d64-Processor_002dstatus_002dRegister-bit-names">IA-64 Processor-status-Register bit names</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dBits">IA-64-Bits</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IA_002d64-registers">IA-64 registers</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dRegs">IA-64-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IA_002d64-relocations">IA-64 relocations</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dRelocs">IA-64-Relocs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IA_002d64-support">IA-64 support</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dDependent">IA-64-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IA_002d64-Syntax">IA-64 Syntax</a>:</td><td> </td><td valign="top"><a href="#IA_002d64-Options">IA-64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ident-directive"><code>ident</code> directive</a>:</td><td> </td><td valign="top"><a href="#Ident">Ident</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-identifiers_002c-ARM">identifiers, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM_002dChars">ARM-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-identifiers_002c-MSP-430">identifiers, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dChars">MSP430-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-if-directive"><code>if</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifb-directive"><code>ifb</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifc-directive"><code>ifc</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifdef-directive"><code>ifdef</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifeq-directive"><code>ifeq</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifeqs-directive"><code>ifeqs</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifge-directive"><code>ifge</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifgt-directive"><code>ifgt</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifle-directive"><code>ifle</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-iflt-directive"><code>iflt</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifnb-directive"><code>ifnb</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifnc-directive"><code>ifnc</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifndef-directive"><code>ifndef</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifne-directive"><code>ifne</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifnes-directive"><code>ifnes</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ifnotdef-directive"><code>ifnotdef</code> directive</a>:</td><td> </td><td valign="top"><a href="#If">If</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-immediate-character_002c-AArch64">immediate character, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dChars">AArch64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-immediate-character_002c-ARM">immediate character, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM_002dChars">ARM-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-immediate-character_002c-M680x0">immediate character, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dChars">M68K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-immediate-character_002c-VAX">immediate character, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-immediate-fields_002c-relaxation">immediate fields, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-immediate-operands_002c-i386">immediate operands, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-immediate-operands_002c-x86_002d64">immediate operands, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-imul-instruction_002c-i386"><code>imul</code> instruction, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dNotes">i386-Notes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-imul-instruction_002c-x86_002d64"><code>imul</code> instruction, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dNotes">i386-Notes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-incbin-directive"><code>incbin</code> directive</a>:</td><td> </td><td valign="top"><a href="#Incbin">Incbin</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-include-directive"><code>include</code> directive</a>:</td><td> </td><td valign="top"><a href="#Include">Include</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-include-directive-search-path"><code>include</code> directive search path</a>:</td><td> </td><td valign="top"><a href="#I">I</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-indirect-character_002c-VAX">indirect character, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-infix-operators">infix operators</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-inhibiting-interrupts_002c-i386">inhibiting interrupts, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-input">input</a>:</td><td> </td><td valign="top"><a href="#Input-Files">Input Files</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-input-file-linenumbers">input file linenumbers</a>:</td><td> </td><td valign="top"><a href="#Input-Files">Input Files</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-insn-directive"><code>insn</code> directive</a>:</td><td> </td><td valign="top"><a href="#i386_002dDirectives">i386-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-INSN-directives">INSN directives</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-aliases_002c-s390">instruction aliases, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Aliases">s390 Aliases</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-bundle">instruction bundle</a>:</td><td> </td><td valign="top"><a href="#Bundle-directives">Bundle directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-expansion_002c-CRIS">instruction expansion, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dExpand">CRIS-Expand</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-expansion_002c-MMIX">instruction expansion, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dExpand">MMIX-Expand</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-formats_002c-risc_002dv">instruction formats, risc-v</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dFormats">RISC-V-Formats</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-formats_002c-s390">instruction formats, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Formats">s390 Formats</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-marker_002c-s390">instruction marker, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Instruction-Marker">s390 Instruction Marker</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-mnemonics_002c-s390">instruction mnemonics, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Mnemonics">s390 Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-naming_002c-i386">instruction naming, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-naming_002c-x86_002d64">instruction naming, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-operand-modifier_002c-s390">instruction operand modifier, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Operand-Modifier">s390 Operand Modifier</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-operands_002c-s390">instruction operands, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Operands">s390 Operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-prefixes_002c-i386">instruction prefixes, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-set_002c-M680x0">instruction set, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dopcodes">M68K-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-set_002c-M68HC11">instruction set, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dopcodes">M68HC11-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-set_002c-XGATE">instruction set, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dopcodes">XGATE-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-summary_002c-AVR">instruction summary, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Opcodes">AVR Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-summary_002c-D10V">instruction summary, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dOpcodes">D10V-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-summary_002c-D30V">instruction summary, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dOpcodes">D30V-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-summary_002c-H8_002f300">instruction summary, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Opcodes">H8/300 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-summary_002c-LM32">instruction summary, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Opcodes">LM32 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-summary_002c-LM32-1">instruction summary, LM32</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dOpcodes">OpenRISC-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-summary_002c-SH">instruction summary, SH</a>:</td><td> </td><td valign="top"><a href="#SH-Opcodes">SH Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-summary_002c-Z8000">instruction summary, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000-Opcodes">Z8000 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instruction-syntax_002c-s390">instruction syntax, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Syntax">s390 Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-instructions-and-directives">instructions and directives</a>:</td><td> </td><td valign="top"><a href="#Statements">Statements</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-int-directive"><code>int</code> directive</a>:</td><td> </td><td valign="top"><a href="#Int">Int</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-int-directive_002c-H8_002f300"><code>int</code> directive, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Directives">H8/300 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-int-directive_002c-i386"><code>int</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-int-directive_002c-TIC54X"><code>int</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-int-directive_002c-x86_002d64"><code>int</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integer-expressions">integer expressions</a>:</td><td> </td><td valign="top"><a href="#Integer-Exprs">Integer Exprs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integer_002c-16_002dbyte">integer, 16-byte</a>:</td><td> </td><td valign="top"><a href="#Octa">Octa</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integer_002c-2_002dbyte">integer, 2-byte</a>:</td><td> </td><td valign="top"><a href="#g_t2byte">2byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integer_002c-4_002dbyte">integer, 4-byte</a>:</td><td> </td><td valign="top"><a href="#g_t4byte">4byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integer_002c-8_002dbyte">integer, 8-byte</a>:</td><td> </td><td valign="top"><a href="#Quad">Quad</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integer_002c-8_002dbyte-1">integer, 8-byte</a>:</td><td> </td><td valign="top"><a href="#g_t8byte">8byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integers">integers</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integers_002c-16_002dbit">integers, 16-bit</a>:</td><td> </td><td valign="top"><a href="#hword">hword</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integers_002c-32_002dbit">integers, 32-bit</a>:</td><td> </td><td valign="top"><a href="#Int">Int</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integers_002c-binary">integers, binary</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integers_002c-decimal">integers, decimal</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integers_002c-hexadecimal">integers, hexadecimal</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integers_002c-octal">integers, octal</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-integers_002c-one-byte">integers, one byte</a>:</td><td> </td><td valign="top"><a href="#Byte">Byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-intel_005fsyntax-pseudo-op_002c-i386">intel_syntax pseudo op, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-intel_005fsyntax-pseudo-op_002c-x86_002d64">intel_syntax pseudo op, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-internal-assembler-sections">internal assembler sections</a>:</td><td> </td><td valign="top"><a href="#As-Sections">As Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-internal-directive"><code>internal</code> directive</a>:</td><td> </td><td valign="top"><a href="#Internal">Internal</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-interrupt-link-register_002c-ARC">interrupt link register, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Interrupt-Vector-Base-address_002c-ARC">Interrupt Vector Base address, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-invalid-input">invalid input</a>:</td><td> </td><td valign="top"><a href="#Bug-Criteria">Bug Criteria</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-invocation-summary">invocation summary</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IP2K-architecture-options">IP2K architecture options</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dOpts">IP2K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IP2K-architecture-options-1">IP2K architecture options</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dOpts">IP2K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IP2K-line-comment-character">IP2K line comment character</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dChars">IP2K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IP2K-line-separator">IP2K line separator</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dChars">IP2K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IP2K-options">IP2K options</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dOpts">IP2K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-IP2K-support">IP2K support</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dDependent">IP2K-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-irp-directive"><code>irp</code> directive</a>:</td><td> </td><td valign="top"><a href="#Irp">Irp</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-irpc-directive"><code>irpc</code> directive</a>:</td><td> </td><td valign="top"><a href="#Irpc">Irpc</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-J">J</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-joining-text-and-data-sections">joining text and data sections</a>:</td><td> </td><td valign="top"><a href="#R">R</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-jsri2bsr-command_002dline-option_002c-C_002dSKY"><code>jsri2bsr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-jump-instructions_002c-i386">jump instructions, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-jump-instructions_002c-relaxation">jump instructions, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Jump-Relaxation">Xtensa Jump Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-jump-instructions_002c-x86_002d64">jump instructions, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-jump-optimization_002c-i386">jump optimization, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dJumps">i386-Jumps</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-jump-optimization_002c-x86_002d64">jump optimization, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dJumps">i386-Jumps</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-jump_002fcall-operands_002c-i386">jump/call operands, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-jump_002fcall-operands_002c-x86_002d64">jump/call operands, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-L">L</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-L16SI-instructions_002c-relaxation"><code>L16SI</code> instructions, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-L16UI-instructions_002c-relaxation"><code>L16UI</code> instructions, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-L32I-instructions_002c-relaxation"><code>L32I</code> instructions, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-L8UI-instructions_002c-relaxation"><code>L8UI</code> instructions, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-label-_0028_003a_0029">label (<code>:</code>)</a>:</td><td> </td><td valign="top"><a href="#Statements">Statements</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-label-directive_002c-TIC54X"><code>label</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-labels">labels</a>:</td><td> </td><td valign="top"><a href="#Labels">Labels</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-labels_002c-Z80">labels, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dLabels">Z80-Labels</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-largecomm-directive_002c-ELF"><code>largecomm</code> directive, ELF</a>:</td><td> </td><td valign="top"><a href="#i386_002dDirectives">i386-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lcomm-directive"><code>lcomm</code> directive</a>:</td><td> </td><td valign="top"><a href="#Lcomm">Lcomm</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lcomm-directive-1"><code>lcomm</code> directive</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lcomm-directive_002c-COFF"><code>lcomm</code> directive, COFF</a>:</td><td> </td><td valign="top"><a href="#i386_002dDirectives">i386-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lcommon-directive_002c-ARC"><code>lcommon</code> directive, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ld"><code>ld</code></a>:</td><td> </td><td valign="top"><a href="#Object">Object</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ldouble-directive-M680x0"><code>ldouble</code> directive M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dFloat">M68K-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ldouble-directive-M68HC11"><code>ldouble</code> directive M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dFloat">M68HC11-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ldouble-directive-XGATE"><code>ldouble</code> directive XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dFloat">XGATE-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ldouble-directive_002c-TIC54X"><code>ldouble</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LDR-reg_002c_003d_003cexpr_003e-pseudo-op_002c-AArch64"><code>LDR reg,=<expr></code> pseudo op, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Opcodes">AArch64 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LDR-reg_002c_003d_003clabel_003e-pseudo-op_002c-ARM"><code>LDR reg,=<label></code> pseudo op, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Opcodes">ARM Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LEB128-directives">LEB128 directives</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-length-directive_002c-TIC54X"><code>length</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-length-of-symbols">length of symbols</a>:</td><td> </td><td valign="top"><a href="#Symbol-Intro">Symbol Intro</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-level-1-interrupt-link-register_002c-ARC">level 1 interrupt link register, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-level-2-interrupt-link-register_002c-ARC">level 2 interrupt link register, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lflags-directive-_0028ignored_0029"><code>lflags</code> directive (ignored)</a>:</td><td> </td><td valign="top"><a href="#Lflags">Lflags</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line">line</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character">line comment character</a>:</td><td> </td><td valign="top"><a href="#Comments">Comments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-AArch64">line comment character, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dChars">AArch64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-Alpha">line comment character, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dChars">Alpha-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-ARC">line comment character, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-ARM">line comment character, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM_002dChars">ARM-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-AVR">line comment character, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR_002dChars">AVR-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-BPF">line comment character, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF_002dChars">BPF-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-CR16">line comment character, CR16</a>:</td><td> </td><td valign="top"><a href="#CR16_002dChars">CR16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-D10V">line comment character, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dChars">D10V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-D30V">line comment character, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dChars">D30V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-Epiphany">line comment character, Epiphany</a>:</td><td> </td><td valign="top"><a href="#Epiphany_002dChars">Epiphany-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-H8_002f300">line comment character, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dChars">H8/300-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-i386">line comment character, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dChars">i386-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-IA_002d64">line comment character, IA-64</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dChars">IA-64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-IP2K">line comment character, IP2K</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dChars">IP2K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-LM32">line comment character, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32_002dChars">LM32-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-M32C">line comment character, M32C</a>:</td><td> </td><td valign="top"><a href="#M32C_002dChars">M32C-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-M680x0">line comment character, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dChars">M68K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-M68HC11">line comment character, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dSyntax">M68HC11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-Meta">line comment character, Meta</a>:</td><td> </td><td valign="top"><a href="#Meta_002dChars">Meta-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-MicroBlaze">line comment character, MicroBlaze</a>:</td><td> </td><td valign="top"><a href="#MicroBlaze_002dChars">MicroBlaze-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-MIPS">line comment character, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS_002dChars">MIPS-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-MSP-430">line comment character, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dChars">MSP430-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-Nios-II">line comment character, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Chars">Nios II Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-NS32K">line comment character, NS32K</a>:</td><td> </td><td valign="top"><a href="#NS32K_002dChars">NS32K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-OpenRISC">line comment character, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dChars">OpenRISC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-PJ">line comment character, PJ</a>:</td><td> </td><td valign="top"><a href="#PJ_002dChars">PJ-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-PowerPC">line comment character, PowerPC</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dChars">PowerPC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-PRU">line comment character, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Chars">PRU Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-RL78">line comment character, RL78</a>:</td><td> </td><td valign="top"><a href="#RL78_002dChars">RL78-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-RX">line comment character, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dChars">RX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-S12Z">line comment character, S12Z</a>:</td><td> </td><td valign="top"><a href="#S12Z-Syntax-Overview">S12Z Syntax Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-s390">line comment character, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Characters">s390 Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-SCORE">line comment character, SCORE</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dChars">SCORE-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-SH">line comment character, SH</a>:</td><td> </td><td valign="top"><a href="#SH_002dChars">SH-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-Sparc">line comment character, Sparc</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dChars">Sparc-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-TIC54X">line comment character, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dChars">TIC54X-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-TIC6X">line comment character, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Syntax">TIC6X Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-V850">line comment character, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dChars">V850-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-VAX">line comment character, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dChars">VAX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-Visium">line comment character, Visium</a>:</td><td> </td><td valign="top"><a href="#Visium-Characters">Visium Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-WebAssembly">line comment character, WebAssembly</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dChars">WebAssembly-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-XGATE">line comment character, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dSyntax">XGATE-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-XStormy16">line comment character, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16_002dChars">XStormy16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-Z80">line comment character, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-character_002c-Z8000">line comment character, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dChars">Z8000-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-characters_002c-CRIS">line comment characters, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dChars">CRIS-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-comment-characters_002c-MMIX">line comment characters, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dChars">MMIX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-directive"><code>line</code> directive</a>:</td><td> </td><td valign="top"><a href="#Line">Line</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-directive_002c-MSP-430"><code>line</code> directive, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Directives">MSP430 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-numbers_002c-in-input-files">line numbers, in input files</a>:</td><td> </td><td valign="top"><a href="#Input-Files">Input Files</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator-character">line separator character</a>:</td><td> </td><td valign="top"><a href="#Statements">Statements</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator-character_002c-Nios-II">line separator character, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Chars">Nios II Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-AArch64">line separator, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dChars">AArch64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-Alpha">line separator, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dChars">Alpha-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-ARC">line separator, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-ARM">line separator, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM_002dChars">ARM-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-AVR">line separator, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR_002dChars">AVR-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-CR16">line separator, CR16</a>:</td><td> </td><td valign="top"><a href="#CR16_002dChars">CR16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-Epiphany">line separator, Epiphany</a>:</td><td> </td><td valign="top"><a href="#Epiphany_002dChars">Epiphany-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-H8_002f300">line separator, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dChars">H8/300-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-i386">line separator, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dChars">i386-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-IA_002d64">line separator, IA-64</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dChars">IA-64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-IP2K">line separator, IP2K</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dChars">IP2K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-LM32">line separator, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32_002dChars">LM32-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-M32C">line separator, M32C</a>:</td><td> </td><td valign="top"><a href="#M32C_002dChars">M32C-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-M680x0">line separator, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dChars">M68K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-M68HC11">line separator, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dSyntax">M68HC11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-Meta">line separator, Meta</a>:</td><td> </td><td valign="top"><a href="#Meta_002dChars">Meta-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-MicroBlaze">line separator, MicroBlaze</a>:</td><td> </td><td valign="top"><a href="#MicroBlaze_002dChars">MicroBlaze-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-MIPS">line separator, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS_002dChars">MIPS-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-MSP-430">line separator, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dChars">MSP430-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-NS32K">line separator, NS32K</a>:</td><td> </td><td valign="top"><a href="#NS32K_002dChars">NS32K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-OpenRISC">line separator, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dChars">OpenRISC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-PJ">line separator, PJ</a>:</td><td> </td><td valign="top"><a href="#PJ_002dChars">PJ-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-PowerPC">line separator, PowerPC</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dChars">PowerPC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-RL78">line separator, RL78</a>:</td><td> </td><td valign="top"><a href="#RL78_002dChars">RL78-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-RX">line separator, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dChars">RX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-S12Z">line separator, S12Z</a>:</td><td> </td><td valign="top"><a href="#S12Z-Syntax-Overview">S12Z Syntax Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-s390">line separator, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Characters">s390 Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-SCORE">line separator, SCORE</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dChars">SCORE-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-SH">line separator, SH</a>:</td><td> </td><td valign="top"><a href="#SH_002dChars">SH-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-Sparc">line separator, Sparc</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dChars">Sparc-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-TIC54X">line separator, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dChars">TIC54X-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-TIC6X">line separator, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Syntax">TIC6X Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-V850">line separator, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dChars">V850-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-VAX">line separator, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dChars">VAX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-Visium">line separator, Visium</a>:</td><td> </td><td valign="top"><a href="#Visium-Characters">Visium Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-XGATE">line separator, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dSyntax">XGATE-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-XStormy16">line separator, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16_002dChars">XStormy16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-Z80">line separator, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-line-separator_002c-Z8000">line separator, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dChars">Z8000-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lines-starting-with-_0023">lines starting with <code>#</code></a>:</td><td> </td><td valign="top"><a href="#Comments">Comments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-link-register_002c-ARC">link register, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-linker">linker</a>:</td><td> </td><td valign="top"><a href="#Object">Object</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-linker_002c-and-assembler">linker, and assembler</a>:</td><td> </td><td valign="top"><a href="#Secs-Background">Secs Background</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-linkonce-directive"><code>linkonce</code> directive</a>:</td><td> </td><td valign="top"><a href="#Linkonce">Linkonce</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-list-directive"><code>list</code> directive</a>:</td><td> </td><td valign="top"><a href="#List">List</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-list-directive_002c-TIC54X"><code>list</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-listing-control_002c-turning-off">listing control, turning off</a>:</td><td> </td><td valign="top"><a href="#Nolist">Nolist</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-listing-control_002c-turning-on">listing control, turning on</a>:</td><td> </td><td valign="top"><a href="#List">List</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-listing-control_003a-new-page">listing control: new page</a>:</td><td> </td><td valign="top"><a href="#Eject">Eject</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-listing-control_003a-paper-size">listing control: paper size</a>:</td><td> </td><td valign="top"><a href="#Psize">Psize</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-listing-control_003a-subtitle">listing control: subtitle</a>:</td><td> </td><td valign="top"><a href="#Sbttl">Sbttl</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-listing-control_003a-title-line">listing control: title line</a>:</td><td> </td><td valign="top"><a href="#Title">Title</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-listings_002c-enabling">listings, enabling</a>:</td><td> </td><td valign="top"><a href="#a">a</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-literal-directive"><code>literal</code> directive</a>:</td><td> </td><td valign="top"><a href="#Literal-Directive">Literal Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-literal-pool-entries_002c-s390">literal pool entries, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Literal-Pool-Entries">s390 Literal Pool Entries</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-literal_005fposition-directive"><code>literal_position</code> directive</a>:</td><td> </td><td valign="top"><a href="#Literal-Position-Directive">Literal Position Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-literal_005fprefix-directive"><code>literal_prefix</code> directive</a>:</td><td> </td><td valign="top"><a href="#Literal-Prefix-Directive">Literal Prefix Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-little-endian-output_002c-MIPS">little endian output, MIPS</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-little-endian-output_002c-PJ">little endian output, PJ</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-little_002dendian-output_002c-MIPS">little-endian output, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-little_002dendian-output_002c-TIC6X">little-endian output, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LM32-line-comment-character">LM32 line comment character</a>:</td><td> </td><td valign="top"><a href="#LM32_002dChars">LM32-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LM32-line-separator">LM32 line separator</a>:</td><td> </td><td valign="top"><a href="#LM32_002dChars">LM32-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LM32-modifiers">LM32 modifiers</a>:</td><td> </td><td valign="top"><a href="#LM32_002dModifiers">LM32-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LM32-opcode-summary">LM32 opcode summary</a>:</td><td> </td><td valign="top"><a href="#LM32-Opcodes">LM32 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LM32-options-_0028none_0029">LM32 options (none)</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LM32-register-names">LM32 register names</a>:</td><td> </td><td valign="top"><a href="#LM32_002dRegs">LM32-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LM32-support">LM32 support</a>:</td><td> </td><td valign="top"><a href="#LM32_002dDependent">LM32-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ln-directive"><code>ln</code> directive</a>:</td><td> </td><td valign="top"><a href="#Ln">Ln</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lo-directive_002c-Nios-II"><code>lo</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lo-pseudo_002dop_002c-V850"><code>lo</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-loc-directive"><code>loc</code> directive</a>:</td><td> </td><td valign="top"><a href="#Loc">Loc</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-local-common-symbols">local common symbols</a>:</td><td> </td><td valign="top"><a href="#Lcomm">Lcomm</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-local-directive"><code>local</code> directive</a>:</td><td> </td><td valign="top"><a href="#Local">Local</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-local-labels">local labels</a>:</td><td> </td><td valign="top"><a href="#Symbol-Names">Symbol Names</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-local-symbol-names">local symbol names</a>:</td><td> </td><td valign="top"><a href="#Symbol-Names">Symbol Names</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-local-symbols_002c-retaining-in-output">local symbols, retaining in output</a>:</td><td> </td><td valign="top"><a href="#L">L</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-location-counter">location counter</a>:</td><td> </td><td valign="top"><a href="#Dot">Dot</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-location-counter_002c-advancing">location counter, advancing</a>:</td><td> </td><td valign="top"><a href="#Org">Org</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-location-counter_002c-Z80">location counter, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-loc_005fmark_005flabels-directive"><code>loc_mark_labels</code> directive</a>:</td><td> </td><td valign="top"><a href="#Loc_005fmark_005flabels">Loc_mark_labels</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-logical-file-name">logical file name</a>:</td><td> </td><td valign="top"><a href="#File">File</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-logical-line-number">logical line number</a>:</td><td> </td><td valign="top"><a href="#Line">Line</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-logical-line-numbers">logical line numbers</a>:</td><td> </td><td valign="top"><a href="#Comments">Comments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-long-directive"><code>long</code> directive</a>:</td><td> </td><td valign="top"><a href="#Long">Long</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-long-directive_002c-i386"><code>long</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-long-directive_002c-TIC54X"><code>long</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-long-directive_002c-x86_002d64"><code>long</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-longcall-pseudo_002dop_002c-V850"><code>longcall</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-longcalls-directive"><code>longcalls</code> directive</a>:</td><td> </td><td valign="top"><a href="#Longcalls-Directive">Longcalls Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-longjump-pseudo_002dop_002c-V850"><code>longjump</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Loongson-Content-Address-Memory-_0028CAM_0029-generation-override">Loongson Content Address Memory (CAM) generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Loongson-EXTensions-_0028EXT_0029-instructions-generation-override">Loongson EXTensions (EXT) instructions generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Loongson-EXTensions-R2-_0028EXT2_0029-instructions-generation-override">Loongson EXTensions R2 (EXT2) instructions generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Loongson-MultiMedia-extensions-Instructions-_0028MMI_0029-generation-override">Loongson MultiMedia extensions Instructions (MMI) generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-loop-counter_002c-ARC">loop counter, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-loop-directive_002c-TIC54X"><code>loop</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LOOP-instructions_002c-alignment"><code>LOOP</code> instructions, alignment</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Automatic-Alignment">Xtensa Automatic Alignment</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-low-directive_002c-M32R"><code>low</code> directive, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lp-register_002c-V850"><code>lp</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-lval"><code>lval</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LWP_002c-i386">LWP, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dLWP">i386-LWP</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-LWP_002c-x86_002d64">LWP, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dLWP">i386-LWP</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-M">M</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-M16C-architecture-option">M16C architecture option</a>:</td><td> </td><td valign="top"><a href="#M32C_002dOpts">M32C-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32C-architecture-option">M32C architecture option</a>:</td><td> </td><td valign="top"><a href="#M32C_002dOpts">M32C-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32C-line-comment-character">M32C line comment character</a>:</td><td> </td><td valign="top"><a href="#M32C_002dChars">M32C-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32C-line-separator">M32C line separator</a>:</td><td> </td><td valign="top"><a href="#M32C_002dChars">M32C-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32C-modifiers">M32C modifiers</a>:</td><td> </td><td valign="top"><a href="#M32C_002dModifiers">M32C-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32C-options">M32C options</a>:</td><td> </td><td valign="top"><a href="#M32C_002dOpts">M32C-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32C-support">M32C support</a>:</td><td> </td><td valign="top"><a href="#M32C_002dDependent">M32C-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32R-architecture-options">M32R architecture options</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32R-architecture-options-1">M32R architecture options</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32R-architecture-options-2">M32R architecture options</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32R-directives">M32R directives</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32R-options">M32R options</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32R-support">M32R support</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDependent">M32R-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M32R-warnings">M32R warnings</a>:</td><td> </td><td valign="top"><a href="#M32R_002dWarnings">M32R-Warnings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-addressing-modes">M680x0 addressing modes</a>:</td><td> </td><td valign="top"><a href="#M68K_002dSyntax">M68K-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-architecture-options">M680x0 architecture options</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-branch-improvement">M680x0 branch improvement</a>:</td><td> </td><td valign="top"><a href="#M68K_002dBranch">M68K-Branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-directives">M680x0 directives</a>:</td><td> </td><td valign="top"><a href="#M68K_002dDirectives">M68K-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-floating-point">M680x0 floating point</a>:</td><td> </td><td valign="top"><a href="#M68K_002dFloat">M68K-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-immediate-character">M680x0 immediate character</a>:</td><td> </td><td valign="top"><a href="#M68K_002dChars">M68K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-line-comment-character">M680x0 line comment character</a>:</td><td> </td><td valign="top"><a href="#M68K_002dChars">M68K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-line-separator">M680x0 line separator</a>:</td><td> </td><td valign="top"><a href="#M68K_002dChars">M68K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-opcodes">M680x0 opcodes</a>:</td><td> </td><td valign="top"><a href="#M68K_002dopcodes">M68K-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-options">M680x0 options</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-pseudo_002dopcodes">M680x0 pseudo-opcodes</a>:</td><td> </td><td valign="top"><a href="#M68K_002dBranch">M68K-Branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-size-modifiers">M680x0 size modifiers</a>:</td><td> </td><td valign="top"><a href="#M68K_002dSyntax">M68K-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-support">M680x0 support</a>:</td><td> </td><td valign="top"><a href="#M68K_002dDependent">M68K-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M680x0-syntax">M680x0 syntax</a>:</td><td> </td><td valign="top"><a href="#M68K_002dSyntax">M68K-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-addressing-modes">M68HC11 addressing modes</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dSyntax">M68HC11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-and-M68HC12-support">M68HC11 and M68HC12 support</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDependent">M68HC11-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-assembler-directive-_002efar">M68HC11 assembler directive .far</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-assembler-directive-_002einterrupt">M68HC11 assembler directive .interrupt</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-assembler-directive-_002emode">M68HC11 assembler directive .mode</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-assembler-directive-_002erelax">M68HC11 assembler directive .relax</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-assembler-directive-_002exrefb">M68HC11 assembler directive .xrefb</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-assembler-directives">M68HC11 assembler directives</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-branch-improvement">M68HC11 branch improvement</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dBranch">M68HC11-Branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-floating-point">M68HC11 floating point</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dFloat">M68HC11-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-line-comment-character">M68HC11 line comment character</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dSyntax">M68HC11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-line-separator">M68HC11 line separator</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dSyntax">M68HC11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-modifiers">M68HC11 modifiers</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dModifiers">M68HC11-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-opcodes">M68HC11 opcodes</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dopcodes">M68HC11-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-options">M68HC11 options</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-pseudo_002dopcodes">M68HC11 pseudo-opcodes</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dBranch">M68HC11-Branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC11-syntax">M68HC11 syntax</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dSyntax">M68HC11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-M68HC12-assembler-directives">M68HC12 assembler directives</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dDirectives">M68HC11-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mA6-command_002dline-option_002c-ARC"><code>mA6</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mA7-command_002dline-option_002c-ARC"><code>mA7</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-dependencies">machine dependencies</a>:</td><td> </td><td valign="top"><a href="#Machine-Dependencies">Machine Dependencies</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-AArch64">machine directives, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Directives">AArch64 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-ARC">machine directives, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Directives">ARC Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-ARM">machine directives, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Directives">ARM Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-BPF">machine directives, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF-Directives">BPF Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-H8_002f300-_0028none_0029">machine directives, H8/300 (none)</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Directives">H8/300 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-MSP-430">machine directives, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Directives">MSP430 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-Nios-II">machine directives, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-OPENRISC">machine directives, OPENRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDirectives">OpenRISC-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-PRU">machine directives, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-RISC_002dV">machine directives, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-SH">machine directives, SH</a>:</td><td> </td><td valign="top"><a href="#SH-Directives">SH Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-SPARC">machine directives, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-TIC54X">machine directives, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-TIC6X">machine directives, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-TILE_002dGx">machine directives, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Directives">TILE-Gx Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-TILEPro">machine directives, TILEPro</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Directives">TILEPro Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-V850">machine directives, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-VAX">machine directives, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002ddirectives">VAX-directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-x86">machine directives, x86</a>:</td><td> </td><td valign="top"><a href="#i386_002dDirectives">i386-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-directives_002c-XStormy16">machine directives, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16-Directives">XStormy16 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-independent-directives">machine independent directives</a>:</td><td> </td><td valign="top"><a href="#Pseudo-Ops">Pseudo Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-instructions-_0028not-covered_0029">machine instructions (not covered)</a>:</td><td> </td><td valign="top"><a href="#Manual">Manual</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-relocations_002c-Nios-II">machine relocations, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine-relocations_002c-PRU">machine relocations, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Relocations">PRU Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-machine_002dindependent-syntax">machine-independent syntax</a>:</td><td> </td><td valign="top"><a href="#Syntax">Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-macro-directive"><code>macro</code> directive</a>:</td><td> </td><td valign="top"><a href="#Macro">Macro</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-macro-directive_002c-TIC54X"><code>macro</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-macros">macros</a>:</td><td> </td><td valign="top"><a href="#Macro">Macro</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-macros_002c-count-executed">macros, count executed</a>:</td><td> </td><td valign="top"><a href="#Macro">Macro</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Macros_002c-MSP-430">Macros, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dMacros">MSP430-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-macros_002c-TIC54X">macros, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-make-rules">make rules</a>:</td><td> </td><td valign="top"><a href="#MD">MD</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-manual_002c-structure-and-purpose">manual, structure and purpose</a>:</td><td> </td><td valign="top"><a href="#Manual">Manual</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-marc600-command_002dline-option_002c-ARC"><code>marc600</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mARC601-command_002dline-option_002c-ARC"><code>mARC601</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mARC700-command_002dline-option_002c-ARC"><code>mARC700</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-march-command_002dline-option_002c-C_002dSKY"><code>march</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-march-command_002dline-option_002c-Nios-II"><code>march</code> command-line option, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Options">Nios II Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-math-builtins_002c-TIC54X">math builtins, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Maximum-number-of-continuation-lines">Maximum number of continuation lines</a>:</td><td> </td><td valign="top"><a href="#listing">listing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mbig_002dendian-command_002dline-option_002c-C_002dSKY"><code>mbig-endian</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mbranch_002dstub-command_002dline-option_002c-C_002dSKY"><code>mbranch-stub</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mcache-command_002dline-option_002c-C_002dSKY"><code>mcache</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mcp-command_002dline-option_002c-C_002dSKY"><code>mcp</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mcpu-command_002dline-option_002c-C_002dSKY"><code>mcpu</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mdsp-command_002dline-option_002c-C_002dSKY"><code>mdsp</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-medsp-command_002dline-option_002c-C_002dSKY"><code>medsp</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-melrw-command_002dline-option_002c-C_002dSKY"><code>melrw</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mEM-command_002dline-option_002c-ARC"><code>mEM</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-memory-references_002c-i386">memory references, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dMemory">i386-Memory</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-memory-references_002c-x86_002d64">memory references, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dMemory">i386-Memory</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-memory_002dmapped-registers_002c-TIC54X">memory-mapped registers, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMMRegs">TIC54X-MMRegs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-merging-text-and-data-sections">merging text and data sections</a>:</td><td> </td><td valign="top"><a href="#R">R</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-messages-from-assembler">messages from assembler</a>:</td><td> </td><td valign="top"><a href="#Errors">Errors</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Meta-architectures">Meta architectures</a>:</td><td> </td><td valign="top"><a href="#Meta-Options">Meta Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Meta-line-comment-character">Meta line comment character</a>:</td><td> </td><td valign="top"><a href="#Meta_002dChars">Meta-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Meta-line-separator">Meta line separator</a>:</td><td> </td><td valign="top"><a href="#Meta_002dChars">Meta-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Meta-options">Meta options</a>:</td><td> </td><td valign="top"><a href="#Meta-Options">Meta Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Meta-registers">Meta registers</a>:</td><td> </td><td valign="top"><a href="#Meta_002dRegs">Meta-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Meta-support">Meta support</a>:</td><td> </td><td valign="top"><a href="#Meta_002dDependent">Meta-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mforce2bsr-command_002dline-option_002c-C_002dSKY"><code>mforce2bsr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mhard_002dfloat-command_002dline-option_002c-C_002dSKY"><code>mhard-float</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mHS-command_002dline-option_002c-ARC"><code>mHS</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MicroBlaze-architectures">MicroBlaze architectures</a>:</td><td> </td><td valign="top"><a href="#MicroBlaze_002dDependent">MicroBlaze-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MicroBlaze-directives">MicroBlaze directives</a>:</td><td> </td><td valign="top"><a href="#MicroBlaze-Directives">MicroBlaze Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MicroBlaze-line-comment-character">MicroBlaze line comment character</a>:</td><td> </td><td valign="top"><a href="#MicroBlaze_002dChars">MicroBlaze-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MicroBlaze-line-separator">MicroBlaze line separator</a>:</td><td> </td><td valign="top"><a href="#MicroBlaze_002dChars">MicroBlaze-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MicroBlaze-support">MicroBlaze support</a>:</td><td> </td><td valign="top"><a href="#MicroBlaze_002dDependent">MicroBlaze-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-minus_002c-permitted-arguments">minus, permitted arguments</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-32_002dbit-microMIPS-instruction-generation-override">MIPS 32-bit microMIPS instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-assembly-options">MIPS assembly options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-architecture-options">MIPS architecture options</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-big_002dendian-output">MIPS big-endian output</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-CPU-override">MIPS CPU override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ISA">MIPS ISA</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-cyclic-redundancy-check-_0028CRC_0029-instruction-generation-override">MIPS cyclic redundancy check (CRC) instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-directives-to-override-command_002dline-options">MIPS directives to override command-line options</a>:</td><td> </td><td valign="top"><a href="#MIPS-assembly-options">MIPS assembly options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-DSP-Release-1-instruction-generation-override">MIPS DSP Release 1 instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-DSP-Release-2-instruction-generation-override">MIPS DSP Release 2 instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-DSP-Release-3-instruction-generation-override">MIPS DSP Release 3 instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-endianness">MIPS endianness</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-eXtended-Physical-Address-_0028XPA_0029-instruction-generation-override">MIPS eXtended Physical Address (XPA) instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-Global-INValidate-_0028GINV_0029-instruction-generation-override">MIPS Global INValidate (GINV) instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-IEEE-754-NaN-data-encoding-selection">MIPS IEEE 754 NaN data encoding selection</a>:</td><td> </td><td valign="top"><a href="#MIPS-NaN-Encodings">MIPS NaN Encodings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-ISA">MIPS ISA</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-ISA-override">MIPS ISA override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ISA">MIPS ISA</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-line-comment-character">MIPS line comment character</a>:</td><td> </td><td valign="top"><a href="#MIPS_002dChars">MIPS-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-line-separator">MIPS line separator</a>:</td><td> </td><td valign="top"><a href="#MIPS_002dChars">MIPS-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-little_002dendian-output">MIPS little-endian output</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-MCU-instruction-generation-override">MIPS MCU instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-MDMX-instruction-generation-override">MIPS MDMX instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-MIPS_002d3D-instruction-generation-override">MIPS MIPS-3D instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-MT-instruction-generation-override">MIPS MT instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-option-stack">MIPS option stack</a>:</td><td> </td><td valign="top"><a href="#MIPS-Option-Stack">MIPS Option Stack</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-processor">MIPS processor</a>:</td><td> </td><td valign="top"><a href="#MIPS_002dDependent">MIPS-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS-SIMD-Architecture-instruction-generation-override">MIPS SIMD Architecture instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIPS16e2-instruction-generation-override">MIPS16e2 instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mistack-command_002dline-option_002c-C_002dSKY"><code>mistack</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MIT"><small>MIT</small></a>:</td><td> </td><td valign="top"><a href="#M68K_002dSyntax">M68K-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mjsri2bsr-command_002dline-option_002c-C_002dSKY"><code>mjsri2bsr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mlabr-command_002dline-option_002c-C_002dSKY"><code>mlabr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mlaf-command_002dline-option_002c-C_002dSKY"><code>mlaf</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mlib-directive_002c-TIC54X"><code>mlib</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mlink_002drelax-command_002dline-option_002c-PRU"><code>mlink-relax</code> command-line option, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Options">PRU Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mlist-directive_002c-TIC54X"><code>mlist</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mliterals_002dafter_002dbr-command_002dline-option_002c-C_002dSKY"><code>mliterals-after-br</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mliterals_002dafter_002dfunc-command_002dline-option_002c-C_002dSKY"><code>mliterals-after-func</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mlittle_002dendian-command_002dline-option_002c-C_002dSKY"><code>mlittle-endian</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mljump-command_002dline-option_002c-C_002dSKY"><code>mljump</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-BSPEC">MMIX assembler directive BSPEC</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-BYTE">MMIX assembler directive BYTE</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-ESPEC">MMIX assembler directive ESPEC</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-GREG">MMIX assembler directive GREG</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-IS">MMIX assembler directive IS</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-LOC">MMIX assembler directive LOC</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-LOCAL">MMIX assembler directive LOCAL</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-OCTA">MMIX assembler directive OCTA</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-PREFIX">MMIX assembler directive PREFIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-TETRA">MMIX assembler directive TETRA</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directive-WYDE">MMIX assembler directive WYDE</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-assembler-directives">MMIX assembler directives</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-line-comment-characters">MMIX line comment characters</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dChars">MMIX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-options">MMIX options</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-BSPEC">MMIX pseudo-op BSPEC</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-BYTE">MMIX pseudo-op BYTE</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-ESPEC">MMIX pseudo-op ESPEC</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-GREG">MMIX pseudo-op GREG</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-IS">MMIX pseudo-op IS</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-LOC">MMIX pseudo-op LOC</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-LOCAL">MMIX pseudo-op LOCAL</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-OCTA">MMIX pseudo-op OCTA</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-PREFIX">MMIX pseudo-op PREFIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-TETRA">MMIX pseudo-op TETRA</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dop-WYDE">MMIX pseudo-op WYDE</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-pseudo_002dops">MMIX pseudo-ops</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-register-names">MMIX register names</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dRegs">MMIX-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMIX-support">MMIX support</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dDependent">MMIX-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mmixal-differences">mmixal differences</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dmmixal">MMIX-mmixal</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mmp-command_002dline-option_002c-C_002dSKY"><code>mmp</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mmregs-directive_002c-TIC54X"><code>mmregs</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mmsg-directive_002c-TIC54X"><code>mmsg</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMX_002c-i386">MMX, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dSIMD">i386-SIMD</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MMX_002c-x86_002d64">MMX, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dSIMD">i386-SIMD</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonic-compatibility_002c-i386">mnemonic compatibility, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonic-suffixes_002c-i386">mnemonic suffixes, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonic-suffixes_002c-x86_002d64">mnemonic suffixes, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonics-for-opcodes_002c-VAX">mnemonics for opcodes, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dopcodes">VAX-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonics_002c-AVR">mnemonics, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Opcodes">AVR Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonics_002c-D10V">mnemonics, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dOpcodes">D10V-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonics_002c-D30V">mnemonics, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dOpcodes">D30V-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonics_002c-H8_002f300">mnemonics, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Opcodes">H8/300 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonics_002c-LM32">mnemonics, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Opcodes">LM32 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonics_002c-OpenRISC">mnemonics, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dOpcodes">OpenRISC-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonics_002c-SH">mnemonics, SH</a>:</td><td> </td><td valign="top"><a href="#SH-Opcodes">SH Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnemonics_002c-Z8000">mnemonics, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000-Opcodes">Z8000 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002dbranch_002dstub-command_002dline-option_002c-C_002dSKY"><code>mno-branch-stub</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002delrw-command_002dline-option_002c-C_002dSKY"><code>mno-elrw</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002dforce2bsr-command_002dline-option_002c-C_002dSKY"><code>mno-force2bsr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002distack-command_002dline-option_002c-C_002dSKY"><code>mno-istack</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002djsri2bsr-command_002dline-option_002c-C_002dSKY"><code>mno-jsri2bsr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002dlabr-command_002dline-option_002c-C_002dSKY"><code>mno-labr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002dlaf-command_002dline-option_002c-C_002dSKY"><code>mno-laf</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002dlink_002drelax-command_002dline-option_002c-PRU"><code>mno-link-relax</code> command-line option, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Options">PRU Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002dliterals_002dafter_002dfunc-command_002dline-option_002c-C_002dSKY"><code>mno-literals-after-func</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002dljump-command_002dline-option_002c-C_002dSKY"><code>mno-ljump</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002dlrw-command_002dline-option_002c-C_002dSKY"><code>mno-lrw</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mno_002dwarn_002dregname_002dlabel-command_002dline-option_002c-PRU"><code>mno-warn-regname-label</code> command-line option, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Options">PRU Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnolist-directive_002c-TIC54X"><code>mnolist</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnoliterals_002dafter_002dbr-command_002dline-option_002c-C_002dSKY"><code>mnoliterals-after-br</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnolrw-command_002dline-option_002c-C_002dSKY"><code>mnolrw</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mnps400-command_002dline-option_002c-ARC"><code>mnps400</code> command-line option, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-modifiers_002c-M32C">modifiers, M32C</a>:</td><td> </td><td valign="top"><a href="#M32C_002dModifiers">M32C-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-module-layout_002c-WebAssembly">module layout, WebAssembly</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dmodule_002dlayout">WebAssembly-module-layout</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Motorola-syntax-for-the-680x0">Motorola syntax for the 680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dMoto_002dSyntax">M68K-Moto-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MOVI-instructions_002c-relaxation"><code>MOVI</code> instructions, relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MOVN_002c-MOVZ-and-MOVK-group-relocations_002c-AArch64">MOVN, MOVZ and MOVK group relocations, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dRelocations">AArch64-Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MOVW-and-MOVT-relocations_002c-ARM">MOVW and MOVT relocations, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM_002dRelocations">ARM-Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MRI-compatibility-mode">MRI compatibility mode</a>:</td><td> </td><td valign="top"><a href="#M">M</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mri-directive"><code>mri</code> directive</a>:</td><td> </td><td valign="top"><a href="#MRI">MRI</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MRI-mode_002c-temporarily">MRI mode, temporarily</a>:</td><td> </td><td valign="top"><a href="#MRI">MRI</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-msecurity-command_002dline-option_002c-C_002dSKY"><code>msecurity</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-floating-point-_0028IEEE_0029">MSP 430 floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#MSP430-Floating-Point">MSP430 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-identifiers">MSP 430 identifiers</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dChars">MSP430-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-line-comment-character">MSP 430 line comment character</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dChars">MSP430-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-line-separator">MSP 430 line separator</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dChars">MSP430-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-machine-directives">MSP 430 machine directives</a>:</td><td> </td><td valign="top"><a href="#MSP430-Directives">MSP430 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-macros">MSP 430 macros</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dMacros">MSP430-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-opcodes">MSP 430 opcodes</a>:</td><td> </td><td valign="top"><a href="#MSP430-Opcodes">MSP430 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-options-_0028none_0029">MSP 430 options (none)</a>:</td><td> </td><td valign="top"><a href="#MSP430-Options">MSP430 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-profiling-capability">MSP 430 profiling capability</a>:</td><td> </td><td valign="top"><a href="#MSP430-Profiling-Capability">MSP430 Profiling Capability</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-register-names">MSP 430 register names</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dRegs">MSP430-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP-430-support">MSP 430 support</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dDependent">MSP430-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-MSP430-Assembler-Extensions">MSP430 Assembler Extensions</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dExt">MSP430-Ext</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mspabi_005fattribute-directive_002c-MSP430"><code>mspabi_attribute</code> directive, MSP430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Directives">MSP430 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mtrust-command_002dline-option_002c-C_002dSKY"><code>mtrust</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mul-instruction_002c-i386"><code>mul</code> instruction, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dNotes">i386-Notes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mul-instruction_002c-x86_002d64"><code>mul</code> instruction, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dNotes">i386-Notes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-mvdsp-command_002dline-option_002c-C_002dSKY"><code>mvdsp</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-N">N</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-N32K-support">N32K support</a>:</td><td> </td><td valign="top"><a href="#NS32K_002dDependent">NS32K-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-name"><code>name</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-named-section">named section</a>:</td><td> </td><td valign="top"><a href="#Section">Section</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-named-sections">named sections</a>:</td><td> </td><td valign="top"><a href="#Ld-Sections">Ld Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-names_002c-symbol">names, symbol</a>:</td><td> </td><td valign="top"><a href="#Symbol-Names">Symbol Names</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-naming-object-file">naming object file</a>:</td><td> </td><td valign="top"><a href="#o">o</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-NDS32-options">NDS32 options</a>:</td><td> </td><td valign="top"><a href="#NDS32-Options">NDS32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-NDS32-processor">NDS32 processor</a>:</td><td> </td><td valign="top"><a href="#NDS32_002dDependent">NDS32-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-new-page_002c-in-listings">new page, in listings</a>:</td><td> </td><td valign="top"><a href="#Eject">Eject</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-newblock-directive_002c-TIC54X"><code>newblock</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-newline-_0028_005cn_0029">newline (<code>\n</code>)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-newline_002c-required-at-file-end">newline, required at file end</a>:</td><td> </td><td valign="top"><a href="#Statements">Statements</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Nios-II-line-comment-character">Nios II line comment character</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Chars">Nios II Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Nios-II-line-separator-character">Nios II line separator character</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Chars">Nios II Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Nios-II-machine-directives">Nios II machine directives</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Nios-II-machine-relocations">Nios II machine relocations</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Nios-II-opcodes">Nios II opcodes</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Opcodes">Nios II Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Nios-II-options">Nios II options</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Options">Nios II Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Nios-II-support">Nios II support</a>:</td><td> </td><td valign="top"><a href="#NiosII_002dDependent">NiosII-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Nios-support">Nios support</a>:</td><td> </td><td valign="top"><a href="#NiosII_002dDependent">NiosII-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-no_002dabsolute_002dliterals-directive"><code>no-absolute-literals</code> directive</a>:</td><td> </td><td valign="top"><a href="#Absolute-Literals-Directive">Absolute Literals Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-no_002dforce2bsr-command_002dline-option_002c-C_002dSKY"><code>no-force2bsr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-no_002djsri2bsr-command_002dline-option_002c-C_002dSKY"><code>no-jsri2bsr</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-no_002dlongcalls-directive"><code>no-longcalls</code> directive</a>:</td><td> </td><td valign="top"><a href="#Longcalls-Directive">Longcalls Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-no_002drelax-command_002dline-option_002c-Nios-II"><code>no-relax</code> command-line option, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Options">Nios II Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-no_002dschedule-directive"><code>no-schedule</code> directive</a>:</td><td> </td><td valign="top"><a href="#Schedule-Directive">Schedule Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-no_002dtransform-directive"><code>no-transform</code> directive</a>:</td><td> </td><td valign="top"><a href="#Transform-Directive">Transform Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-nodelay-directive_002c-OpenRISC"><code>nodelay</code> directive, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDirectives">OpenRISC-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-nolist-directive"><code>nolist</code> directive</a>:</td><td> </td><td valign="top"><a href="#Nolist">Nolist</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-nolist-directive_002c-TIC54X"><code>nolist</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-nop-directive"><code>nop</code> directive</a>:</td><td> </td><td valign="top"><a href="#Nop">Nop</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-NOP-pseudo-op_002c-ARM"><code>NOP</code> pseudo op, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Opcodes">ARM Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-nops-directive"><code>nops</code> directive</a>:</td><td> </td><td valign="top"><a href="#Nops">Nops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-notes-for-Alpha">notes for Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Notes">Alpha Notes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-notes-for-WebAssembly">notes for WebAssembly</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dNotes">WebAssembly-Notes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-NS32K-line-comment-character">NS32K line comment character</a>:</td><td> </td><td valign="top"><a href="#NS32K_002dChars">NS32K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-NS32K-line-separator">NS32K line separator</a>:</td><td> </td><td valign="top"><a href="#NS32K_002dChars">NS32K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-null_002dterminated-strings">null-terminated strings</a>:</td><td> </td><td valign="top"><a href="#Asciz">Asciz</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-number-constants">number constants</a>:</td><td> </td><td valign="top"><a href="#Numbers">Numbers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-number-of-macros-executed">number of macros executed</a>:</td><td> </td><td valign="top"><a href="#Macro">Macro</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-numbered-subsections">numbered subsections</a>:</td><td> </td><td valign="top"><a href="#Sub_002dSections">Sub-Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-numbers_002c-16_002dbit">numbers, 16-bit</a>:</td><td> </td><td valign="top"><a href="#hword">hword</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-numeric-values">numeric values</a>:</td><td> </td><td valign="top"><a href="#Expressions">Expressions</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-nword-directive_002c-SPARC"><code>nword</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-O">O</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-Object-Attribute_002c-RISC_002dV">Object Attribute, RISC-V</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dATTRIBUTE">RISC-V-ATTRIBUTE</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-object-attributes">object attributes</a>:</td><td> </td><td valign="top"><a href="#Object-Attributes">Object Attributes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-object-file">object file</a>:</td><td> </td><td valign="top"><a href="#Object">Object</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-object-file-format">object file format</a>:</td><td> </td><td valign="top"><a href="#Object-Formats">Object Formats</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-object-file-name">object file name</a>:</td><td> </td><td valign="top"><a href="#o">o</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-object-file_002c-after-errors">object file, after errors</a>:</td><td> </td><td valign="top"><a href="#Z">Z</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-obsolescent-directives">obsolescent directives</a>:</td><td> </td><td valign="top"><a href="#Deprecated">Deprecated</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-octa-directive"><code>octa</code> directive</a>:</td><td> </td><td valign="top"><a href="#Octa">Octa</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-octal-character-code-_0028_005cddd_0029">octal character code (<code>\<var>ddd</var></code>)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-octal-integers">octal integers</a>:</td><td> </td><td valign="top"><a href="#Integers">Integers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-offset-directive"><code>offset</code> directive</a>:</td><td> </td><td valign="top"><a href="#Offset">Offset</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-offset-directive_002c-V850"><code>offset</code> directive, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-mnemonics_002c-VAX">opcode mnemonics, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dopcodes">VAX-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-names_002c-TILE_002dGx">opcode names, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Opcodes">TILE-Gx Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-names_002c-TILEPro">opcode names, TILEPro</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Opcodes">TILEPro Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-names_002c-Xtensa">opcode names, Xtensa</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Opcodes">Xtensa Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-summary_002c-AVR">opcode summary, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR-Opcodes">AVR Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-summary_002c-D10V">opcode summary, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dOpcodes">D10V-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-summary_002c-D30V">opcode summary, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dOpcodes">D30V-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-summary_002c-H8_002f300">opcode summary, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Opcodes">H8/300 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-summary_002c-LM32">opcode summary, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32-Opcodes">LM32 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-summary_002c-OpenRISC">opcode summary, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dOpcodes">OpenRISC-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-summary_002c-SH">opcode summary, SH</a>:</td><td> </td><td valign="top"><a href="#SH-Opcodes">SH Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcode-summary_002c-Z8000">opcode summary, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000-Opcodes">Z8000 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes-for-AArch64">opcodes for AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64-Opcodes">AArch64 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes-for-ARC">opcodes for ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Opcodes">ARC Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes-for-ARM">opcodes for ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Opcodes">ARM Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes-for-BPF">opcodes for BPF</a>:</td><td> </td><td valign="top"><a href="#BPF-Opcodes">BPF Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes-for-MSP-430">opcodes for MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Opcodes">MSP430 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes-for-Nios-II">opcodes for Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Opcodes">Nios II Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes-for-PRU">opcodes for PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Opcodes">PRU Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes-for-V850">opcodes for V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes_002c-M680x0">opcodes, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dopcodes">M68K-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes_002c-M68HC11">opcodes, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dopcodes">M68HC11-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-opcodes_002c-WebAssembly">opcodes, WebAssembly</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dOpcodes">WebAssembly-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-OPENRISC-floating-point-_0028IEEE_0029">OPENRISC floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dFloat">OpenRISC-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-OpenRISC-line-comment-character">OpenRISC line comment character</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dChars">OpenRISC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-OpenRISC-line-separator">OpenRISC line separator</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dChars">OpenRISC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-OPENRISC-machine-directives">OPENRISC machine directives</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDirectives">OpenRISC-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-OpenRISC-opcode-summary">OpenRISC opcode summary</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dOpcodes">OpenRISC-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-OpenRISC-registers">OpenRISC registers</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dRegs">OpenRISC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-OpenRISC-relocations">OpenRISC relocations</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dRelocs">OpenRISC-Relocs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-OPENRISC-support">OPENRISC support</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDependent">OpenRISC-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-OPENRISC-syntax">OPENRISC syntax</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDependent">OpenRISC-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-operand-delimiters_002c-i386">operand delimiters, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-operand-delimiters_002c-x86_002d64">operand delimiters, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-operand-notation_002c-VAX">operand notation, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-operands-in-expressions">operands in expressions</a>:</td><td> </td><td valign="top"><a href="#Arguments">Arguments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-operator-precedence">operator precedence</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-operators_002c-in-expressions">operators, in expressions</a>:</td><td> </td><td valign="top"><a href="#Operators">Operators</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-operators_002c-permitted-arguments">operators, permitted arguments</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-optimization_002c-D10V">optimization, D10V</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-optimization_002c-D30V">optimization, D30V</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-optimizations">optimizations</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Optimizations">Xtensa Optimizations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Option-directive">Option directive</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-option-directive"><code>option</code> directive</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-option-directive_002c-TIC54X"><code>option</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-option-summary">option summary</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-AArch64-_0028none_0029">options for AArch64 (none)</a>:</td><td> </td><td valign="top"><a href="#AArch64-Options">AArch64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-Alpha">options for Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha-Options">Alpha Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-ARC">options for ARC</a>:</td><td> </td><td valign="top"><a href="#ARC-Options">ARC Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-ARM-_0028none_0029">options for ARM (none)</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-AVR-_0028none_0029">options for AVR (none)</a>:</td><td> </td><td valign="top"><a href="#AVR-Options">AVR Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-Blackfin-_0028none_0029">options for Blackfin (none)</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Options">Blackfin Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-BPF-_0028none_0029">options for BPF (none)</a>:</td><td> </td><td valign="top"><a href="#BPF-Options">BPF Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-C_002dSKY">options for C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-i386">options for i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-IA_002d64">options for IA-64</a>:</td><td> </td><td valign="top"><a href="#IA_002d64-Options">IA-64 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-LM32-_0028none_0029">options for LM32 (none)</a>:</td><td> </td><td valign="top"><a href="#LM32-Options">LM32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-Meta">options for Meta</a>:</td><td> </td><td valign="top"><a href="#Meta-Options">Meta Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-MSP430-_0028none_0029">options for MSP430 (none)</a>:</td><td> </td><td valign="top"><a href="#MSP430-Options">MSP430 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-NDS32">options for NDS32</a>:</td><td> </td><td valign="top"><a href="#NDS32-Options">NDS32 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-Nios-II">options for Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Options">Nios II Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-PDP_002d11">options for PDP-11</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dOptions">PDP-11-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-PowerPC">options for PowerPC</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dOpts">PowerPC-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-PRU">options for PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Options">PRU Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-s390">options for s390</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-SCORE">options for SCORE</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dOpts">SCORE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-SPARC">options for SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-TIC6X">options for TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-V850-_0028none_0029">options for V850 (none)</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-VAX_002fVMS">options for VAX/VMS</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-Visium">options for Visium</a>:</td><td> </td><td valign="top"><a href="#Visium-Options">Visium Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-x86_002d64">options for x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options-for-Z80">options for Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Options">Z80 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-all-versions-of-assembler">options, all versions of assembler</a>:</td><td> </td><td valign="top"><a href="#Invoking">Invoking</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-command-line">options, command line</a>:</td><td> </td><td valign="top"><a href="#Command-Line">Command Line</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-CRIS">options, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-D10V">options, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dOpts">D10V-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-D30V">options, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dOpts">D30V-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-Epiphany">options, Epiphany</a>:</td><td> </td><td valign="top"><a href="#Epiphany-Options">Epiphany Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-H8_002f300">options, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Options">H8/300 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-IP2K">options, IP2K</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dOpts">IP2K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-M32C">options, M32C</a>:</td><td> </td><td valign="top"><a href="#M32C_002dOpts">M32C-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-M32R">options, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-M680x0">options, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dOpts">M68K-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-M68HC11">options, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dOpts">M68HC11-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-MMIX">options, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dOpts">MMIX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-PJ">options, PJ</a>:</td><td> </td><td valign="top"><a href="#PJ-Options">PJ Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-RL78">options, RL78</a>:</td><td> </td><td valign="top"><a href="#RL78_002dOpts">RL78-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-RX">options, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-S12Z">options, S12Z</a>:</td><td> </td><td valign="top"><a href="#S12Z-Options">S12Z Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-SH">options, SH</a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-TIC54X">options, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dOpts">TIC54X-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-XGATE">options, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dOpts">XGATE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-options_002c-Z8000">options, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000-Options">Z8000 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-org-directive"><code>org</code> directive</a>:</td><td> </td><td valign="top"><a href="#Org">Org</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-other-attribute_002c-of-a_002eout-symbol">other attribute, of <code>a.out</code> symbol</a>:</td><td> </td><td valign="top"><a href="#Symbol-Other">Symbol Other</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-output-file">output file</a>:</td><td> </td><td valign="top"><a href="#Object">Object</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-output-section-padding">output section padding</a>:</td><td> </td><td valign="top"><a href="#no_002dpad_002dsections">no-pad-sections</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-P">P</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-p2align-directive"><code>p2align</code> directive</a>:</td><td> </td><td valign="top"><a href="#P2align">P2align</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-p2alignl-directive"><code>p2alignl</code> directive</a>:</td><td> </td><td valign="top"><a href="#P2align">P2align</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-p2alignw-directive"><code>p2alignw</code> directive</a>:</td><td> </td><td valign="top"><a href="#P2align">P2align</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-padding-the-location-counter">padding the location counter</a>:</td><td> </td><td valign="top"><a href="#Align">Align</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-padding-the-location-counter-given-a-power-of-two">padding the location counter given a power of two</a>:</td><td> </td><td valign="top"><a href="#P2align">P2align</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-padding-the-location-counter-given-number-of-bytes">padding the location counter given number of bytes</a>:</td><td> </td><td valign="top"><a href="#Balign">Balign</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-page_002c-in-listings">page, in listings</a>:</td><td> </td><td valign="top"><a href="#Eject">Eject</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-paper-size_002c-for-listings">paper size, for listings</a>:</td><td> </td><td valign="top"><a href="#Psize">Psize</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-paths-for-_002einclude">paths for <code>.include</code></a>:</td><td> </td><td valign="top"><a href="#I">I</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-patterns_002c-writing-in-memory">patterns, writing in memory</a>:</td><td> </td><td valign="top"><a href="#Fill">Fill</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PDP_002d11-comments">PDP-11 comments</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dSyntax">PDP-11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PDP_002d11-floating_002dpoint-register-syntax">PDP-11 floating-point register syntax</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dSyntax">PDP-11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PDP_002d11-general_002dpurpose-register-syntax">PDP-11 general-purpose register syntax</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dSyntax">PDP-11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PDP_002d11-instruction-naming">PDP-11 instruction naming</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dMnemonics">PDP-11-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PDP_002d11-line-separator">PDP-11 line separator</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dSyntax">PDP-11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PDP_002d11-support">PDP-11 support</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dDependent">PDP-11-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PDP_002d11-syntax">PDP-11 syntax</a>:</td><td> </td><td valign="top"><a href="#PDP_002d11_002dSyntax">PDP-11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PIC-code-generation-for-ARM">PIC code generation for ARM</a>:</td><td> </td><td valign="top"><a href="#ARM-Options">ARM Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PIC-code-generation-for-M32R">PIC code generation for M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dOpts">M32R-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pic-command_002dline-option_002c-C_002dSKY"><code>pic</code> command-line option, C-SKY</a>:</td><td> </td><td valign="top"><a href="#C_002dSKY-Options">C-SKY Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PIC-selection_002c-MIPS">PIC selection, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-Options">MIPS Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PJ-endianness">PJ endianness</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PJ-line-comment-character">PJ line comment character</a>:</td><td> </td><td valign="top"><a href="#PJ_002dChars">PJ-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PJ-line-separator">PJ line separator</a>:</td><td> </td><td valign="top"><a href="#PJ_002dChars">PJ-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PJ-options">PJ options</a>:</td><td> </td><td valign="top"><a href="#PJ-Options">PJ Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PJ-support">PJ support</a>:</td><td> </td><td valign="top"><a href="#PJ_002dDependent">PJ-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-plus_002c-permitted-arguments">plus, permitted arguments</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pmem-directive_002c-PRU"><code>pmem</code> directive, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Relocations">PRU Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-popsection-directive"><code>popsection</code> directive</a>:</td><td> </td><td valign="top"><a href="#PopSection">PopSection</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Position_002dindependent-code_002c-CRIS">Position-independent code, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dOpts">CRIS-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Position_002dindependent-code_002c-symbols-in_002c-CRIS">Position-independent code, symbols in, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPic">CRIS-Pic</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PowerPC-architectures">PowerPC architectures</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dOpts">PowerPC-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PowerPC-directives">PowerPC directives</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dPseudo">PowerPC-Pseudo</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PowerPC-line-comment-character">PowerPC line comment character</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dChars">PowerPC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PowerPC-line-separator">PowerPC line separator</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dChars">PowerPC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PowerPC-options">PowerPC options</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dOpts">PowerPC-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PowerPC-support">PowerPC support</a>:</td><td> </td><td valign="top"><a href="#PPC_002dDependent">PPC-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-precedence-of-operators">precedence of operators</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-precision_002c-floating-point">precision, floating point</a>:</td><td> </td><td valign="top"><a href="#Flonums">Flonums</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-prefix-operators">prefix operators</a>:</td><td> </td><td valign="top"><a href="#Prefix-Ops">Prefix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-prefixes_002c-i386">prefixes, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-preprocessing">preprocessing</a>:</td><td> </td><td valign="top"><a href="#Preprocessing">Preprocessing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-preprocessing_002c-turning-on-and-off">preprocessing, turning on and off</a>:</td><td> </td><td valign="top"><a href="#Preprocessing">Preprocessing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-previous-directive"><code>previous</code> directive</a>:</td><td> </td><td valign="top"><a href="#Previous">Previous</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-primary-attributes_002c-COFF-symbols">primary attributes, COFF symbols</a>:</td><td> </td><td valign="top"><a href="#COFF-Symbols">COFF Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-print-directive"><code>print</code> directive</a>:</td><td> </td><td valign="top"><a href="#Print">Print</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-proc-directive_002c-OpenRISC"><code>proc</code> directive, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDirectives">OpenRISC-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-proc-directive_002c-SPARC"><code>proc</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Processor-Identification-register_002c-ARC">Processor Identification register, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-profiler-directive_002c-MSP-430"><code>profiler</code> directive, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Directives">MSP430 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-profiling-capability-for-MSP-430">profiling capability for MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Profiling-Capability">MSP430 Profiling Capability</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Program-Counter_002c-ARC">Program Counter, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-protected-directive"><code>protected</code> directive</a>:</td><td> </td><td valign="top"><a href="#Protected">Protected</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PRU-line-comment-character">PRU line comment character</a>:</td><td> </td><td valign="top"><a href="#PRU-Chars">PRU Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PRU-machine-directives">PRU machine directives</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PRU-machine-relocations">PRU machine relocations</a>:</td><td> </td><td valign="top"><a href="#PRU-Relocations">PRU Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PRU-opcodes">PRU opcodes</a>:</td><td> </td><td valign="top"><a href="#PRU-Opcodes">PRU Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PRU-options">PRU options</a>:</td><td> </td><td valign="top"><a href="#PRU-Options">PRU Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PRU-support">PRU support</a>:</td><td> </td><td valign="top"><a href="#PRU_002dDependent">PRU-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-psect-directive_002c-Z80"><code>psect</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo-map-fd_002c-BPF">pseudo map fd, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF_002dPseudo_002dMaps">BPF-Pseudo-Maps</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-_002earch_002c-CRIS">pseudo-op .arch, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-_002edword_002c-CRIS">pseudo-op .dword, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-_002esyntax_002c-CRIS">pseudo-op .syntax, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-BSPEC_002c-MMIX">pseudo-op BSPEC, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-BYTE_002c-MMIX">pseudo-op BYTE, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-ESPEC_002c-MMIX">pseudo-op ESPEC, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-GREG_002c-MMIX">pseudo-op GREG, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-IS_002c-MMIX">pseudo-op IS, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-LOC_002c-MMIX">pseudo-op LOC, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-LOCAL_002c-MMIX">pseudo-op LOCAL, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-OCTA_002c-MMIX">pseudo-op OCTA, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-PREFIX_002c-MMIX">pseudo-op PREFIX, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-TETRA_002c-MMIX">pseudo-op TETRA, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dop-WYDE_002c-MMIX">pseudo-op WYDE, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dopcodes-for-XStormy16">pseudo-opcodes for XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16-Opcodes">XStormy16 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dopcodes_002c-M680x0">pseudo-opcodes, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dBranch">M68K-Branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dopcodes_002c-M68HC11">pseudo-opcodes, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dBranch">M68HC11-Branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dops-for-branch_002c-VAX">pseudo-ops for branch, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dbranch">VAX-branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dops_002c-CRIS">pseudo-ops, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPseudos">CRIS-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dops_002c-machine-independent">pseudo-ops, machine independent</a>:</td><td> </td><td valign="top"><a href="#Pseudo-Ops">Pseudo Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pseudo_002dops_002c-MMIX">pseudo-ops, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dPseudos">MMIX-Pseudos</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-psize-directive"><code>psize</code> directive</a>:</td><td> </td><td valign="top"><a href="#Psize">Psize</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-PSR-bits">PSR bits</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dBits">IA-64-Bits</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pstring-directive_002c-TIC54X"><code>pstring</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-psw-register_002c-V850"><code>psw</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-purgem-directive"><code>purgem</code> directive</a>:</td><td> </td><td valign="top"><a href="#Purgem">Purgem</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-purpose-of-GNU-assembler">purpose of <small>GNU</small> assembler</a>:</td><td> </td><td valign="top"><a href="#GNU-Assembler">GNU Assembler</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-pushsection-directive"><code>pushsection</code> directive</a>:</td><td> </td><td valign="top"><a href="#PushSection">PushSection</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-Q">Q</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-quad-directive"><code>quad</code> directive</a>:</td><td> </td><td valign="top"><a href="#Quad">Quad</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-quad-directive_002c-i386"><code>quad</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-quad-directive_002c-x86_002d64"><code>quad</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-R">R</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-real_002dmode-code_002c-i386">real-mode code, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002d16bit">i386-16bit</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ref-directive_002c-TIC54X"><code>ref</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-refsym-directive_002c-MSP-430"><code>refsym</code> directive, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430-Directives">MSP430 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-directive_002c-SPARC"><code>register</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-name-prefix-character_002c-ARC">register name prefix character, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-AArch64">register names, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dRegs">AArch64-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-Alpha">register names, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dRegs">Alpha-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-ARC">register names, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-ARM">register names, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM_002dRegs">ARM-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-AVR">register names, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR_002dRegs">AVR-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-BPF">register names, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF_002dRegs">BPF-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-CRIS">register names, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dRegs">CRIS-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-H8_002f300">register names, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dRegs">H8/300-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-IA_002d64">register names, IA-64</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dRegs">IA-64-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-LM32">register names, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32_002dRegs">LM32-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-MMIX">register names, MMIX</a>:</td><td> </td><td valign="top"><a href="#MMIX_002dRegs">MMIX-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-MSP-430">register names, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dRegs">MSP430-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-OpenRISC">register names, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dRegs">OpenRISC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-S12Z">register names, S12Z</a>:</td><td> </td><td valign="top"><a href="#S12Z-Addressing-Modes">S12Z Addressing Modes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-Sparc">register names, Sparc</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dRegs">Sparc-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-TILE_002dGx">register names, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Registers">TILE-Gx Registers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-TILEPro">register names, TILEPro</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Registers">TILEPro Registers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-V850">register names, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-VAX">register names, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-Visium">register names, Visium</a>:</td><td> </td><td valign="top"><a href="#Visium-Registers">Visium Registers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-Xtensa">register names, Xtensa</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Registers">Xtensa Registers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-names_002c-Z80">register names, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dRegs">Z80-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-naming_002c-s390">register naming, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Register">s390 Register</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-notation_002c-S12Z">register notation, S12Z</a>:</td><td> </td><td valign="top"><a href="#S12Z-Register-Notation">S12Z Register Notation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-operands_002c-i386">register operands, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-register-operands_002c-x86_002d64">register operands, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-registers_002c-D10V">registers, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dRegs">D10V-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-registers_002c-D30V">registers, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dRegs">D30V-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-registers_002c-i386">registers, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dRegs">i386-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-registers_002c-Meta">registers, Meta</a>:</td><td> </td><td valign="top"><a href="#Meta_002dRegs">Meta-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-registers_002c-SH">registers, SH</a>:</td><td> </td><td valign="top"><a href="#SH_002dRegs">SH-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-registers_002c-TIC54X-memory_002dmapped">registers, TIC54X memory-mapped</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMMRegs">TIC54X-MMRegs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-registers_002c-x86_002d64">registers, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dRegs">i386-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-registers_002c-Z8000">registers, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dRegs">Z8000-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relax_002dall-command_002dline-option_002c-Nios-II"><code>relax-all</code> command-line option, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Options">Nios II Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relax_002dsection-command_002dline-option_002c-Nios-II"><code>relax-section</code> command-line option, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Options">Nios II Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation">relaxation</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Relaxation">Xtensa Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-ADDI-instructions">relaxation of <code>ADDI</code> instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-branch-instructions">relaxation of branch instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Branch-Relaxation">Xtensa Branch Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-call-instructions">relaxation of call instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Call-Relaxation">Xtensa Call Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-immediate-fields">relaxation of immediate fields</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-jump-instructions">relaxation of jump instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Jump-Relaxation">Xtensa Jump Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-L16SI-instructions">relaxation of <code>L16SI</code> instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-L16UI-instructions">relaxation of <code>L16UI</code> instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-L32I-instructions">relaxation of <code>L32I</code> instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-L8UI-instructions">relaxation of <code>L8UI</code> instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relaxation-of-MOVI-instructions">relaxation of <code>MOVI</code> instructions</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Immediate-Relaxation">Xtensa Immediate Relaxation</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-reloc-directive"><code>reloc</code> directive</a>:</td><td> </td><td valign="top"><a href="#Reloc">Reloc</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relocation">relocation</a>:</td><td> </td><td valign="top"><a href="#Sections">Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relocation-example">relocation example</a>:</td><td> </td><td valign="top"><a href="#Ld-Sections">Ld Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relocations_002c-AArch64">relocations, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dRelocations">AArch64-Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relocations_002c-Alpha">relocations, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dRelocs">Alpha-Relocs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relocations_002c-OpenRISC">relocations, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dRelocs">OpenRISC-Relocs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relocations_002c-Sparc">relocations, Sparc</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dRelocs">Sparc-Relocs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-relocations_002c-WebAssembly">relocations, WebAssembly</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dRelocs">WebAssembly-Relocs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-repeat-prefixes_002c-i386">repeat prefixes, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-reporting-bugs-in-assembler">reporting bugs in assembler</a>:</td><td> </td><td valign="top"><a href="#Reporting-Bugs">Reporting Bugs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-rept-directive"><code>rept</code> directive</a>:</td><td> </td><td valign="top"><a href="#Rept">Rept</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-reserve-directive_002c-SPARC"><code>reserve</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-return-instructions_002c-i386">return instructions, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-return-instructions_002c-x86_002d64">return instructions, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-REX-prefixes_002c-i386">REX prefixes, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RISC_002dV-custom-_0028vendor_002ddefined_0029-extensions">RISC-V custom (vendor-defined) extensions</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dCustomExts">RISC-V-CustomExts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RISC_002dV-floating-point-_0028IEEE_0029">RISC-V floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dFloating_002dPoint">RISC-V-Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RISC_002dV-instruction-formats">RISC-V instruction formats</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dFormats">RISC-V-Formats</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RISC_002dV-machine-directives">RISC-V machine directives</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDirectives">RISC-V-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RISC_002dV-support">RISC-V support</a>:</td><td> </td><td valign="top"><a href="#RISC_002dV_002dDependent">RISC-V-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RL78-assembler-directives">RL78 assembler directives</a>:</td><td> </td><td valign="top"><a href="#RL78_002dDirectives">RL78-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RL78-line-comment-character">RL78 line comment character</a>:</td><td> </td><td valign="top"><a href="#RL78_002dChars">RL78-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RL78-line-separator">RL78 line separator</a>:</td><td> </td><td valign="top"><a href="#RL78_002dChars">RL78-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RL78-modifiers">RL78 modifiers</a>:</td><td> </td><td valign="top"><a href="#RL78_002dModifiers">RL78-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RL78-options">RL78 options</a>:</td><td> </td><td valign="top"><a href="#RL78_002dOpts">RL78-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RL78-support">RL78 support</a>:</td><td> </td><td valign="top"><a href="#RL78_002dDependent">RL78-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-rsect"><code>rsect</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RX-assembler-directive-_002e3byte">RX assembler directive .3byte</a>:</td><td> </td><td valign="top"><a href="#RX_002dDirectives">RX-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RX-assembler-directive-_002efetchalign">RX assembler directive .fetchalign</a>:</td><td> </td><td valign="top"><a href="#RX_002dDirectives">RX-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RX-assembler-directives">RX assembler directives</a>:</td><td> </td><td valign="top"><a href="#RX_002dDirectives">RX-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RX-floating-point">RX floating point</a>:</td><td> </td><td valign="top"><a href="#RX_002dFloat">RX-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RX-line-comment-character">RX line comment character</a>:</td><td> </td><td valign="top"><a href="#RX_002dChars">RX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RX-line-separator">RX line separator</a>:</td><td> </td><td valign="top"><a href="#RX_002dChars">RX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RX-modifiers">RX modifiers</a>:</td><td> </td><td valign="top"><a href="#RX_002dModifiers">RX-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RX-options">RX options</a>:</td><td> </td><td valign="top"><a href="#RX_002dOpts">RX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-RX-support">RX support</a>:</td><td> </td><td valign="top"><a href="#RX_002dDependent">RX-Dependent</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-S">S</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-S12Z-addressing-modes">S12Z addressing modes</a>:</td><td> </td><td valign="top"><a href="#S12Z-Addressing-Modes">S12Z Addressing Modes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-S12Z-line-separator">S12Z line separator</a>:</td><td> </td><td valign="top"><a href="#S12Z-Syntax-Overview">S12Z Syntax Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-S12Z-options">S12Z options</a>:</td><td> </td><td valign="top"><a href="#S12Z-Options">S12Z Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-S12Z-support">S12Z support</a>:</td><td> </td><td valign="top"><a href="#S12Z_002dDependent">S12Z-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-S12Z-syntax">S12Z syntax</a>:</td><td> </td><td valign="top"><a href="#S12Z-Syntax">S12Z Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-floating-point">s390 floating point</a>:</td><td> </td><td valign="top"><a href="#s390-Floating-Point">s390 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-instruction-aliases">s390 instruction aliases</a>:</td><td> </td><td valign="top"><a href="#s390-Aliases">s390 Aliases</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-instruction-formats">s390 instruction formats</a>:</td><td> </td><td valign="top"><a href="#s390-Formats">s390 Formats</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-instruction-marker">s390 instruction marker</a>:</td><td> </td><td valign="top"><a href="#s390-Instruction-Marker">s390 Instruction Marker</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-instruction-mnemonics">s390 instruction mnemonics</a>:</td><td> </td><td valign="top"><a href="#s390-Mnemonics">s390 Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-instruction-operand-modifier">s390 instruction operand modifier</a>:</td><td> </td><td valign="top"><a href="#s390-Operand-Modifier">s390 Operand Modifier</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-instruction-operands">s390 instruction operands</a>:</td><td> </td><td valign="top"><a href="#s390-Operands">s390 Operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-instruction-syntax">s390 instruction syntax</a>:</td><td> </td><td valign="top"><a href="#s390-Syntax">s390 Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-line-comment-character">s390 line comment character</a>:</td><td> </td><td valign="top"><a href="#s390-Characters">s390 Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-line-separator">s390 line separator</a>:</td><td> </td><td valign="top"><a href="#s390-Characters">s390 Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-literal-pool-entries">s390 literal pool entries</a>:</td><td> </td><td valign="top"><a href="#s390-Literal-Pool-Entries">s390 Literal Pool Entries</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-options">s390 options</a>:</td><td> </td><td valign="top"><a href="#s390-Options">s390 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-register-naming">s390 register naming</a>:</td><td> </td><td valign="top"><a href="#s390-Register">s390 Register</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-s390-support">s390 support</a>:</td><td> </td><td valign="top"><a href="#S_002f390_002dDependent">S/390-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Saved-User-Stack-Pointer_002c-ARC">Saved User Stack Pointer, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sblock-directive_002c-TIC54X"><code>sblock</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sbttl-directive"><code>sbttl</code> directive</a>:</td><td> </td><td valign="top"><a href="#Sbttl">Sbttl</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-schedule-directive"><code>schedule</code> directive</a>:</td><td> </td><td valign="top"><a href="#Schedule-Directive">Schedule Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-scl-directive"><code>scl</code> directive</a>:</td><td> </td><td valign="top"><a href="#Scl">Scl</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SCORE-architectures">SCORE architectures</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dOpts">SCORE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SCORE-directives">SCORE directives</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dPseudo">SCORE-Pseudo</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SCORE-line-comment-character">SCORE line comment character</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dChars">SCORE-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SCORE-line-separator">SCORE line separator</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dChars">SCORE-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SCORE-options">SCORE options</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dOpts">SCORE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SCORE-processor">SCORE processor</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dDependent">SCORE-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sdaoff-pseudo_002dop_002c-V850"><code>sdaoff</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-search-path-for-_002einclude">search path for <code>.include</code></a>:</td><td> </td><td valign="top"><a href="#I">I</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sect-directive_002c-TIC54X"><code>sect</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-section-directive-_0028COFF-version_0029"><code>section</code> directive (COFF version)</a>:</td><td> </td><td valign="top"><a href="#Section">Section</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-section-directive-_0028ELF-version_0029"><code>section</code> directive (ELF version)</a>:</td><td> </td><td valign="top"><a href="#Section">Section</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-section-directive_002c-V850"><code>section</code> directive, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-section-name-substitution">section name substitution</a>:</td><td> </td><td valign="top"><a href="#Section">Section</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-section-override-prefixes_002c-i386">section override prefixes, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Section-Stack">Section Stack</a>:</td><td> </td><td valign="top"><a href="#PopSection">PopSection</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Section-Stack-1">Section Stack</a>:</td><td> </td><td valign="top"><a href="#Previous">Previous</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Section-Stack-2">Section Stack</a>:</td><td> </td><td valign="top"><a href="#PushSection">PushSection</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Section-Stack-3">Section Stack</a>:</td><td> </td><td valign="top"><a href="#Section">Section</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Section-Stack-4">Section Stack</a>:</td><td> </td><td valign="top"><a href="#SubSection">SubSection</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-section_002drelative-addressing">section-relative addressing</a>:</td><td> </td><td valign="top"><a href="#Secs-Background">Secs Background</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sections">sections</a>:</td><td> </td><td valign="top"><a href="#Sections">Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sections-in-messages_002c-internal">sections in messages, internal</a>:</td><td> </td><td valign="top"><a href="#As-Sections">As Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sections_002c-i386">sections, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sections_002c-named">sections, named</a>:</td><td> </td><td valign="top"><a href="#Ld-Sections">Ld Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sections_002c-x86_002d64">sections, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-seg-directive_002c-SPARC"><code>seg</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-segm"><code>segm</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-at-directive_002c-Nios-II"><code>set at</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-break-directive_002c-Nios-II"><code>set break</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-directive"><code>set</code> directive</a>:</td><td> </td><td valign="top"><a href="#Set">Set</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-directive_002c-Nios-II"><code>set</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-directive_002c-TIC54X"><code>set</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-noat-directive_002c-Nios-II"><code>set noat</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-nobreak-directive_002c-Nios-II"><code>set nobreak</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-norelax-directive_002c-Nios-II"><code>set norelax</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-no_005fwarn_005fregname_005flabel-directive_002c-PRU"><code>set no_warn_regname_label</code> directive, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-relaxall-directive_002c-Nios-II"><code>set relaxall</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-set-relaxsection-directive_002c-Nios-II"><code>set relaxsection</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SH-addressing-modes">SH addressing modes</a>:</td><td> </td><td valign="top"><a href="#SH_002dAddressing">SH-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SH-floating-point-_0028IEEE_0029">SH floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#SH-Floating-Point">SH Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SH-line-comment-character">SH line comment character</a>:</td><td> </td><td valign="top"><a href="#SH_002dChars">SH-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SH-line-separator">SH line separator</a>:</td><td> </td><td valign="top"><a href="#SH_002dChars">SH-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SH-machine-directives">SH machine directives</a>:</td><td> </td><td valign="top"><a href="#SH-Directives">SH Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SH-opcode-summary">SH opcode summary</a>:</td><td> </td><td valign="top"><a href="#SH-Opcodes">SH Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SH-options">SH options</a>:</td><td> </td><td valign="top"><a href="#SH-Options">SH Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SH-registers">SH registers</a>:</td><td> </td><td valign="top"><a href="#SH_002dRegs">SH-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SH-support">SH support</a>:</td><td> </td><td valign="top"><a href="#SH_002dDependent">SH-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-shigh-directive_002c-M32R"><code>shigh</code> directive, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dDirectives">M32R-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-short-directive"><code>short</code> directive</a>:</td><td> </td><td valign="top"><a href="#Short">Short</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-short-directive_002c-TIC54X"><code>short</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-signatures_002c-WebAssembly">signatures, WebAssembly</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dSignatures">WebAssembly-Signatures</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SIMD_002c-i386">SIMD, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dSIMD">i386-SIMD</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SIMD_002c-x86_002d64">SIMD, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dSIMD">i386-SIMD</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-single-character-constant">single character constant</a>:</td><td> </td><td valign="top"><a href="#Chars">Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-single-directive"><code>single</code> directive</a>:</td><td> </td><td valign="top"><a href="#Single">Single</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-single-directive_002c-i386"><code>single</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-single-directive_002c-x86_002d64"><code>single</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-single-quote_002c-Z80">single quote, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sixteen-bit-integers">sixteen bit integers</a>:</td><td> </td><td valign="top"><a href="#hword">hword</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sixteen-byte-integer">sixteen byte integer</a>:</td><td> </td><td valign="top"><a href="#Octa">Octa</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-size-directive-_0028COFF-version_0029"><code>size</code> directive (COFF version)</a>:</td><td> </td><td valign="top"><a href="#Size">Size</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-size-directive-_0028ELF-version_0029"><code>size</code> directive (ELF version)</a>:</td><td> </td><td valign="top"><a href="#Size">Size</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-size-modifiers_002c-D10V">size modifiers, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dSize">D10V-Size</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-size-modifiers_002c-D30V">size modifiers, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dSize">D30V-Size</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-size-modifiers_002c-M680x0">size modifiers, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dSyntax">M68K-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-size-prefixes_002c-i386">size prefixes, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dPrefixes">i386-Prefixes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-size-suffixes_002c-H8_002f300">size suffixes, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Opcodes">H8/300 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-size_002c-translations_002c-Sparc">size, translations, Sparc</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dSize_002dTranslations">Sparc-Size-Translations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sizes-operands_002c-i386">sizes operands, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sizes-operands_002c-x86_002d64">sizes operands, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-skip-directive"><code>skip</code> directive</a>:</td><td> </td><td valign="top"><a href="#Skip">Skip</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-skip-directive_002c-M680x0"><code>skip</code> directive, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dDirectives">M68K-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-skip-directive_002c-SPARC"><code>skip</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sleb128-directive"><code>sleb128</code> directive</a>:</td><td> </td><td valign="top"><a href="#Sleb128">Sleb128</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-small-data_002c-MIPS">small data, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS-Small-Data">MIPS Small Data</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SmartMIPS-instruction-generation-override">SmartMIPS instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SOM-symbol-attributes">SOM symbol attributes</a>:</td><td> </td><td valign="top"><a href="#SOM-Symbols">SOM Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-source-program">source program</a>:</td><td> </td><td valign="top"><a href="#Input-Files">Input Files</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-source_002c-destination-operands_003b-i386">source, destination operands; i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-source_002c-destination-operands_003b-x86_002d64">source, destination operands; x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sp-register">sp register</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Registers">Xtensa Registers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sp-register_002c-V850"><code>sp</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-space-directive"><code>space</code> directive</a>:</td><td> </td><td valign="top"><a href="#Space">Space</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-space-directive_002c-TIC54X"><code>space</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-space-used_002c-maximum-for-assembly">space used, maximum for assembly</a>:</td><td> </td><td valign="top"><a href="#statistics">statistics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SPARC-architectures">SPARC architectures</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Sparc-constants">Sparc constants</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dConstants">Sparc-Constants</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SPARC-data-alignment">SPARC data alignment</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dAligned_002dData">Sparc-Aligned-Data</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SPARC-floating-point-_0028IEEE_0029">SPARC floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dFloat">Sparc-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Sparc-line-comment-character">Sparc line comment character</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dChars">Sparc-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Sparc-line-separator">Sparc line separator</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dChars">Sparc-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SPARC-machine-directives">SPARC machine directives</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SPARC-options">SPARC options</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dOpts">Sparc-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Sparc-registers">Sparc registers</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dRegs">Sparc-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Sparc-relocations">Sparc relocations</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dRelocs">Sparc-Relocs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Sparc-size-translations">Sparc size translations</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dSize_002dTranslations">Sparc-Size-Translations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SPARC-support">SPARC support</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDependent">Sparc-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-SPARC-syntax">SPARC syntax</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dAligned_002dData">Sparc-Aligned-Data</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-special-characters_002c-M680x0">special characters, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dChars">M68K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-special-purpose-registers_002c-MSP-430">special purpose registers, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dRegs">MSP430-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sslist-directive_002c-TIC54X"><code>sslist</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ssnolist-directive_002c-TIC54X"><code>ssnolist</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-stabd-directive"><code>stabd</code> directive</a>:</td><td> </td><td valign="top"><a href="#Stab">Stab</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-stabn-directive"><code>stabn</code> directive</a>:</td><td> </td><td valign="top"><a href="#Stab">Stab</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-stabs-directive"><code>stabs</code> directive</a>:</td><td> </td><td valign="top"><a href="#Stab">Stab</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-stabx-directives"><code>stab<var>x</var></code> directives</a>:</td><td> </td><td valign="top"><a href="#Stab">Stab</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-stack-pointer_002c-ARC">stack pointer, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-standard-assembler-sections">standard assembler sections</a>:</td><td> </td><td valign="top"><a href="#Secs-Background">Secs Background</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-standard-input_002c-as-input-file">standard input, as input file</a>:</td><td> </td><td valign="top"><a href="#Command-Line">Command Line</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator-character">statement separator character</a>:</td><td> </td><td valign="top"><a href="#Statements">Statements</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-AArch64">statement separator, AArch64</a>:</td><td> </td><td valign="top"><a href="#AArch64_002dChars">AArch64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-Alpha">statement separator, Alpha</a>:</td><td> </td><td valign="top"><a href="#Alpha_002dChars">Alpha-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-ARC">statement separator, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-ARM">statement separator, ARM</a>:</td><td> </td><td valign="top"><a href="#ARM_002dChars">ARM-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-AVR">statement separator, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR_002dChars">AVR-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-BPF">statement separator, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF_002dChars">BPF-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-CR16">statement separator, CR16</a>:</td><td> </td><td valign="top"><a href="#CR16_002dChars">CR16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-Epiphany">statement separator, Epiphany</a>:</td><td> </td><td valign="top"><a href="#Epiphany_002dChars">Epiphany-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-H8_002f300">statement separator, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300_002dChars">H8/300-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-i386">statement separator, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dChars">i386-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-IA_002d64">statement separator, IA-64</a>:</td><td> </td><td valign="top"><a href="#IA_002d64_002dChars">IA-64-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-IP2K">statement separator, IP2K</a>:</td><td> </td><td valign="top"><a href="#IP2K_002dChars">IP2K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-LM32">statement separator, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32_002dChars">LM32-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-M32C">statement separator, M32C</a>:</td><td> </td><td valign="top"><a href="#M32C_002dChars">M32C-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-M68HC11">statement separator, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dSyntax">M68HC11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-Meta">statement separator, Meta</a>:</td><td> </td><td valign="top"><a href="#Meta_002dChars">Meta-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-MicroBlaze">statement separator, MicroBlaze</a>:</td><td> </td><td valign="top"><a href="#MicroBlaze_002dChars">MicroBlaze-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-MIPS">statement separator, MIPS</a>:</td><td> </td><td valign="top"><a href="#MIPS_002dChars">MIPS-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-MSP-430">statement separator, MSP 430</a>:</td><td> </td><td valign="top"><a href="#MSP430_002dChars">MSP430-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-NS32K">statement separator, NS32K</a>:</td><td> </td><td valign="top"><a href="#NS32K_002dChars">NS32K-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-OpenRISC">statement separator, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dChars">OpenRISC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-PJ">statement separator, PJ</a>:</td><td> </td><td valign="top"><a href="#PJ_002dChars">PJ-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-PowerPC">statement separator, PowerPC</a>:</td><td> </td><td valign="top"><a href="#PowerPC_002dChars">PowerPC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-RL78">statement separator, RL78</a>:</td><td> </td><td valign="top"><a href="#RL78_002dChars">RL78-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-RX">statement separator, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dChars">RX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-S12Z">statement separator, S12Z</a>:</td><td> </td><td valign="top"><a href="#S12Z-Syntax-Overview">S12Z Syntax Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-s390">statement separator, s390</a>:</td><td> </td><td valign="top"><a href="#s390-Characters">s390 Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-SCORE">statement separator, SCORE</a>:</td><td> </td><td valign="top"><a href="#SCORE_002dChars">SCORE-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-SH">statement separator, SH</a>:</td><td> </td><td valign="top"><a href="#SH_002dChars">SH-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-Sparc">statement separator, Sparc</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dChars">Sparc-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-TIC54X">statement separator, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dChars">TIC54X-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-TIC6X">statement separator, TIC6X</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Syntax">TIC6X Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-V850">statement separator, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dChars">V850-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-VAX">statement separator, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002dChars">VAX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-Visium">statement separator, Visium</a>:</td><td> </td><td valign="top"><a href="#Visium-Characters">Visium Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-XGATE">statement separator, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dSyntax">XGATE-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-XStormy16">statement separator, XStormy16</a>:</td><td> </td><td valign="top"><a href="#XStormy16_002dChars">XStormy16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-Z80">statement separator, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statement-separator_002c-Z8000">statement separator, Z8000</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dChars">Z8000-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statements_002c-structure-of">statements, structure of</a>:</td><td> </td><td valign="top"><a href="#Statements">Statements</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-statistics_002c-about-assembly">statistics, about assembly</a>:</td><td> </td><td valign="top"><a href="#statistics">statistics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Status-register_002c-ARC">Status register, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-STATUS32-saved-on-exception_002c-ARC">STATUS32 saved on exception, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-stopping-the-assembly">stopping the assembly</a>:</td><td> </td><td valign="top"><a href="#Abort">Abort</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Stored-STATUS32-register-on-entry-to-level-P0-interrupts_002c-ARC">Stored STATUS32 register on entry to level P0 interrupts, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string-constants">string constants</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string-directive"><code>string</code> directive</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string-directive-on-HPPA"><code>string</code> directive on HPPA</a>:</td><td> </td><td valign="top"><a href="#HPPA-Directives">HPPA Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string-directive_002c-TIC54X"><code>string</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string-literals">string literals</a>:</td><td> </td><td valign="top"><a href="#Ascii">Ascii</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string_002c-copying-to-object-file">string, copying to object file</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string16-directive"><code>string16</code> directive</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string16_002c-copying-to-object-file">string16, copying to object file</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string32-directive"><code>string32</code> directive</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string32_002c-copying-to-object-file">string32, copying to object file</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string64-directive"><code>string64</code> directive</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string64_002c-copying-to-object-file">string64, copying to object file</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string8-directive"><code>string8</code> directive</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-string8_002c-copying-to-object-file">string8, copying to object file</a>:</td><td> </td><td valign="top"><a href="#String">String</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-struct-directive"><code>struct</code> directive</a>:</td><td> </td><td valign="top"><a href="#Struct">Struct</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-struct-directive_002c-TIC54X"><code>struct</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-structure-debugging_002c-COFF">structure debugging, COFF</a>:</td><td> </td><td valign="top"><a href="#Tag">Tag</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sub_002dinstruction-ordering_002c-D10V">sub-instruction ordering, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dChars">D10V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sub_002dinstruction-ordering_002c-D30V">sub-instruction ordering, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dChars">D30V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sub_002dinstructions_002c-D10V">sub-instructions, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dSubs">D10V-Subs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sub_002dinstructions_002c-D30V">sub-instructions, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dSubs">D30V-Subs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-subexpressions">subexpressions</a>:</td><td> </td><td valign="top"><a href="#Arguments">Arguments</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-subsection-directive"><code>subsection</code> directive</a>:</td><td> </td><td valign="top"><a href="#SubSection">SubSection</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-subsym-builtins_002c-TIC54X">subsym builtins, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-subtitles-for-listings">subtitles for listings</a>:</td><td> </td><td valign="top"><a href="#Sbttl">Sbttl</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-subtraction_002c-permitted-arguments">subtraction, permitted arguments</a>:</td><td> </td><td valign="top"><a href="#Infix-Ops">Infix Ops</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-summary-of-options">summary of options</a>:</td><td> </td><td valign="top"><a href="#Overview">Overview</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-support">support</a>:</td><td> </td><td valign="top"><a href="#HPPA_002dDependent">HPPA-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-supporting-files_002c-including">supporting files, including</a>:</td><td> </td><td valign="top"><a href="#Include">Include</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-suppressing-warnings">suppressing warnings</a>:</td><td> </td><td valign="top"><a href="#W">W</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-sval"><code>sval</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-attributes">symbol attributes</a>:</td><td> </td><td valign="top"><a href="#Symbol-Attributes">Symbol Attributes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-attributes_002c-a_002eout">symbol attributes, <code>a.out</code></a>:</td><td> </td><td valign="top"><a href="#a_002eout-Symbols">a.out Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-attributes_002c-COFF">symbol attributes, COFF</a>:</td><td> </td><td valign="top"><a href="#COFF-Symbols">COFF Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-attributes_002c-SOM">symbol attributes, SOM</a>:</td><td> </td><td valign="top"><a href="#SOM-Symbols">SOM Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-descriptor_002c-COFF">symbol descriptor, COFF</a>:</td><td> </td><td valign="top"><a href="#Desc">Desc</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-modifiers">symbol modifiers</a>:</td><td> </td><td valign="top"><a href="#AVR_002dModifiers">AVR-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-modifiers-1">symbol modifiers</a>:</td><td> </td><td valign="top"><a href="#LM32_002dModifiers">LM32-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-modifiers-2">symbol modifiers</a>:</td><td> </td><td valign="top"><a href="#M32C_002dModifiers">M32C-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-modifiers-3">symbol modifiers</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dModifiers">M68HC11-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-modifiers_002c-TILE_002dGx">symbol modifiers, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Modifiers">TILE-Gx Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-modifiers_002c-TILEPro">symbol modifiers, TILEPro</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Modifiers">TILEPro Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-names">symbol names</a>:</td><td> </td><td valign="top"><a href="#Symbol-Names">Symbol Names</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-names_002c-_0024-in">symbol names, ‘<samp>$</samp>’ in</a>:</td><td> </td><td valign="top"><a href="#D10V_002dChars">D10V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-names_002c-_0024-in-1">symbol names, ‘<samp>$</samp>’ in</a>:</td><td> </td><td valign="top"><a href="#D30V_002dChars">D30V-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-names_002c-_0024-in-2">symbol names, ‘<samp>$</samp>’ in</a>:</td><td> </td><td valign="top"><a href="#Meta_002dChars">Meta-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-names_002c-_0024-in-3">symbol names, ‘<samp>$</samp>’ in</a>:</td><td> </td><td valign="top"><a href="#SH_002dChars">SH-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-names_002c-local">symbol names, local</a>:</td><td> </td><td valign="top"><a href="#Symbol-Names">Symbol Names</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-names_002c-temporary">symbol names, temporary</a>:</td><td> </td><td valign="top"><a href="#Symbol-Names">Symbol Names</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-prefix-character_002c-ARC">symbol prefix character, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dChars">ARC-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-storage-class-_0028COFF_0029">symbol storage class (COFF)</a>:</td><td> </td><td valign="top"><a href="#Scl">Scl</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-type">symbol type</a>:</td><td> </td><td valign="top"><a href="#Symbol-Type">Symbol Type</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-type_002c-COFF">symbol type, COFF</a>:</td><td> </td><td valign="top"><a href="#Type">Type</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-type_002c-ELF">symbol type, ELF</a>:</td><td> </td><td valign="top"><a href="#Type">Type</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-value">symbol value</a>:</td><td> </td><td valign="top"><a href="#Symbol-Value">Symbol Value</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-value_002c-setting">symbol value, setting</a>:</td><td> </td><td valign="top"><a href="#Set">Set</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-values_002c-assigning">symbol values, assigning</a>:</td><td> </td><td valign="top"><a href="#Setting-Symbols">Setting Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol-versioning">symbol versioning</a>:</td><td> </td><td valign="top"><a href="#Symver">Symver</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol_002c-common">symbol, common</a>:</td><td> </td><td valign="top"><a href="#Comm">Comm</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbol_002c-making-visible-to-linker">symbol, making visible to linker</a>:</td><td> </td><td valign="top"><a href="#Global">Global</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbolic-debuggers_002c-information-for">symbolic debuggers, information for</a>:</td><td> </td><td valign="top"><a href="#Stab">Stab</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbols">symbols</a>:</td><td> </td><td valign="top"><a href="#Symbols">Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Symbols-in-position_002dindependent-code_002c-CRIS">Symbols in position-independent code, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dPic">CRIS-Pic</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbols-with-uppercase_002c-VAX_002fVMS">symbols with uppercase, VAX/VMS</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbols_002c-assigning-values-to">symbols, assigning values to</a>:</td><td> </td><td valign="top"><a href="#Equ">Equ</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Symbols_002c-built_002din_002c-CRIS">Symbols, built-in, CRIS</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dSymbols">CRIS-Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Symbols_002c-CRIS_002c-built_002din">Symbols, CRIS, built-in</a>:</td><td> </td><td valign="top"><a href="#CRIS_002dSymbols">CRIS-Symbols</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symbols_002c-local-common">symbols, local common</a>:</td><td> </td><td valign="top"><a href="#Lcomm">Lcomm</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-symver-directive"><code>symver</code> directive</a>:</td><td> </td><td valign="top"><a href="#Symver">Symver</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax-compatibility_002c-i386">syntax compatibility, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax-compatibility_002c-x86_002d64">syntax compatibility, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-AVR">syntax, AVR</a>:</td><td> </td><td valign="top"><a href="#AVR_002dModifiers">AVR-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-Blackfin">syntax, Blackfin</a>:</td><td> </td><td valign="top"><a href="#Blackfin-Syntax">Blackfin Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-D10V">syntax, D10V</a>:</td><td> </td><td valign="top"><a href="#D10V_002dSyntax">D10V-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-D30V">syntax, D30V</a>:</td><td> </td><td valign="top"><a href="#D30V_002dSyntax">D30V-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-LM32">syntax, LM32</a>:</td><td> </td><td valign="top"><a href="#LM32_002dModifiers">LM32-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-M680x0">syntax, M680x0</a>:</td><td> </td><td valign="top"><a href="#M68K_002dSyntax">M68K-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-M68HC11">syntax, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dSyntax">M68HC11-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-M68HC11-1">syntax, M68HC11</a>:</td><td> </td><td valign="top"><a href="#M68HC11_002dModifiers">M68HC11-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-machine_002dindependent">syntax, machine-independent</a>:</td><td> </td><td valign="top"><a href="#Syntax">Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-OPENRISC">syntax, OPENRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDependent">OpenRISC-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-RL78">syntax, RL78</a>:</td><td> </td><td valign="top"><a href="#RL78_002dModifiers">RL78-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-RX">syntax, RX</a>:</td><td> </td><td valign="top"><a href="#RX_002dModifiers">RX-Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-S12Z">syntax, S12Z</a>:</td><td> </td><td valign="top"><a href="#S12Z-Syntax">S12Z Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-SPARC">syntax, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dAligned_002dData">Sparc-Aligned-Data</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-TILE_002dGx">syntax, TILE-Gx</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Syntax">TILE-Gx Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-TILEPro">syntax, TILEPro</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Syntax">TILEPro Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-XGATE">syntax, XGATE</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dSyntax">XGATE-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-syntax_002c-Xtensa-assembler">syntax, Xtensa assembler</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Syntax">Xtensa Syntax</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-T">T</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-tab-_0028_005ct_0029">tab (<code>\t</code>)</a>:</td><td> </td><td valign="top"><a href="#Strings">Strings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tab-directive_002c-TIC54X"><code>tab</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tag-directive"><code>tag</code> directive</a>:</td><td> </td><td valign="top"><a href="#Tag">Tag</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tag-directive_002c-TIC54X"><code>tag</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tag-directive_002c-TIC54X-1"><code>tag</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TBM_002c-i386">TBM, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dTBM">i386-TBM</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TBM_002c-x86_002d64">TBM, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dTBM">i386-TBM</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tdaoff-pseudo_002dop_002c-V850"><code>tdaoff</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-temporary-symbol-names">temporary symbol names</a>:</td><td> </td><td valign="top"><a href="#Symbol-Names">Symbol Names</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-text-and-data-sections_002c-joining">text and data sections, joining</a>:</td><td> </td><td valign="top"><a href="#R">R</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-text-directive"><code>text</code> directive</a>:</td><td> </td><td valign="top"><a href="#Text">Text</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-text-section">text section</a>:</td><td> </td><td valign="top"><a href="#Ld-Sections">Ld Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tfloat-directive_002c-i386"><code>tfloat</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tfloat-directive_002c-x86_002d64"><code>tfloat</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Thumb-support">Thumb support</a>:</td><td> </td><td valign="top"><a href="#ARM_002dDependent">ARM-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC54X-builtin-math-functions">TIC54X builtin math functions</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dBuiltins">TIC54X-Builtins</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC54X-line-comment-character">TIC54X line comment character</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dChars">TIC54X-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC54X-line-separator">TIC54X line separator</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dChars">TIC54X-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC54X-machine-directives">TIC54X machine directives</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC54X-memory_002dmapped-registers">TIC54X memory-mapped registers</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMMRegs">TIC54X-MMRegs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC54X-options">TIC54X options</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dOpts">TIC54X-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC54X-subsym-builtins">TIC54X subsym builtins</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC54X-support">TIC54X support</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDependent">TIC54X-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC54X_002dspecific-macros">TIC54X-specific macros</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dMacros">TIC54X-Macros</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC6X-big_002dendian-output">TIC6X big-endian output</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC6X-line-comment-character">TIC6X line comment character</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Syntax">TIC6X Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC6X-line-separator">TIC6X line separator</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Syntax">TIC6X Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC6X-little_002dendian-output">TIC6X little-endian output</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC6X-machine-directives">TIC6X machine directives</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Directives">TIC6X Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC6X-options">TIC6X options</a>:</td><td> </td><td valign="top"><a href="#TIC6X-Options">TIC6X Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TIC6X-support">TIC6X support</a>:</td><td> </td><td valign="top"><a href="#TIC6X_002dDependent">TIC6X-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILE_002dGx-machine-directives">TILE-Gx machine directives</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Directives">TILE-Gx Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILE_002dGx-modifiers">TILE-Gx modifiers</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Modifiers">TILE-Gx Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILE_002dGx-opcode-names">TILE-Gx opcode names</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Opcodes">TILE-Gx Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILE_002dGx-register-names">TILE-Gx register names</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Registers">TILE-Gx Registers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILE_002dGx-support">TILE-Gx support</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx_002dDependent">TILE-Gx-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILE_002dGx-syntax">TILE-Gx syntax</a>:</td><td> </td><td valign="top"><a href="#TILE_002dGx-Syntax">TILE-Gx Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILEPro-machine-directives">TILEPro machine directives</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Directives">TILEPro Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILEPro-modifiers">TILEPro modifiers</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Modifiers">TILEPro Modifiers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILEPro-opcode-names">TILEPro opcode names</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Opcodes">TILEPro Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILEPro-register-names">TILEPro register names</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Registers">TILEPro Registers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILEPro-support">TILEPro support</a>:</td><td> </td><td valign="top"><a href="#TILEPro_002dDependent">TILEPro-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TILEPro-syntax">TILEPro syntax</a>:</td><td> </td><td valign="top"><a href="#TILEPro-Syntax">TILEPro Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-time_002c-total-for-assembly">time, total for assembly</a>:</td><td> </td><td valign="top"><a href="#statistics">statistics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-title-directive"><code>title</code> directive</a>:</td><td> </td><td valign="top"><a href="#Title">Title</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tls_005fcommon-directive"><code>tls_common</code> directive</a>:</td><td> </td><td valign="top"><a href="#Tls_005fcommon">Tls_common</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tls_005fgd-directive_002c-Nios-II"><code>tls_gd</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tls_005fie-directive_002c-Nios-II"><code>tls_ie</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tls_005fldm-directive_002c-Nios-II"><code>tls_ldm</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tls_005fldo-directive_002c-Nios-II"><code>tls_ldo</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tls_005fle-directive_002c-Nios-II"><code>tls_le</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Relocations">Nios II Relocations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-TMS320C6X-support">TMS320C6X support</a>:</td><td> </td><td valign="top"><a href="#TIC6X_002dDependent">TIC6X-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-tp-register_002c-V850"><code>tp</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-transform-directive"><code>transform</code> directive</a>:</td><td> </td><td valign="top"><a href="#Transform-Directive">Transform Directive</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-trusted-compiler">trusted compiler</a>:</td><td> </td><td valign="top"><a href="#f">f</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-turning-preprocessing-on-and-off">turning preprocessing on and off</a>:</td><td> </td><td valign="top"><a href="#Preprocessing">Preprocessing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-two_002dbyte-integer">two-byte integer</a>:</td><td> </td><td valign="top"><a href="#g_t2byte">2byte</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-type-directive-_0028COFF-version_0029"><code>type</code> directive (COFF version)</a>:</td><td> </td><td valign="top"><a href="#Type">Type</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-type-directive-_0028ELF-version_0029"><code>type</code> directive (ELF version)</a>:</td><td> </td><td valign="top"><a href="#Type">Type</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-type-of-a-symbol">type of a symbol</a>:</td><td> </td><td valign="top"><a href="#Symbol-Type">Symbol Type</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-U">U</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-ualong-directive_002c-SH"><code>ualong</code> directive, SH</a>:</td><td> </td><td valign="top"><a href="#SH-Directives">SH Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-uaquad-directive_002c-SH"><code>uaquad</code> directive, SH</a>:</td><td> </td><td valign="top"><a href="#SH-Directives">SH Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-uaword-directive_002c-SH"><code>uaword</code> directive, SH</a>:</td><td> </td><td valign="top"><a href="#SH-Directives">SH Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ubyte-directive_002c-TIC54X"><code>ubyte</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-uchar-directive_002c-TIC54X"><code>uchar</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-uhalf-directive_002c-TIC54X"><code>uhalf</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-uint-directive_002c-TIC54X"><code>uint</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-uleb128-directive"><code>uleb128</code> directive</a>:</td><td> </td><td valign="top"><a href="#Uleb128">Uleb128</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ulong-directive_002c-TIC54X"><code>ulong</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-undefined-section">undefined section</a>:</td><td> </td><td valign="top"><a href="#Ld-Sections">Ld Sections</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-union-directive_002c-TIC54X"><code>union</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-unsegm"><code>unsegm</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-usect-directive_002c-TIC54X"><code>usect</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-ushort-directive_002c-TIC54X"><code>ushort</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-uword-directive_002c-TIC54X"><code>uword</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-V">V</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-V850-command_002dline-options">V850 command-line options</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-V850-floating-point-_0028IEEE_0029">V850 floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#V850-Floating-Point">V850 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-V850-line-comment-character">V850 line comment character</a>:</td><td> </td><td valign="top"><a href="#V850_002dChars">V850-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-V850-line-separator">V850 line separator</a>:</td><td> </td><td valign="top"><a href="#V850_002dChars">V850-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-V850-machine-directives">V850 machine directives</a>:</td><td> </td><td valign="top"><a href="#V850-Directives">V850 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-V850-opcodes">V850 opcodes</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-V850-options-_0028none_0029">V850 options (none)</a>:</td><td> </td><td valign="top"><a href="#V850-Options">V850 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-V850-register-names">V850 register names</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-V850-support">V850 support</a>:</td><td> </td><td valign="top"><a href="#V850_002dDependent">V850-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-val-directive"><code>val</code> directive</a>:</td><td> </td><td valign="top"><a href="#Val">Val</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-value-attribute_002c-COFF">value attribute, COFF</a>:</td><td> </td><td valign="top"><a href="#Val">Val</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-value-directive"><code>value</code> directive</a>:</td><td> </td><td valign="top"><a href="#i386_002dDirectives">i386-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-value-of-a-symbol">value of a symbol</a>:</td><td> </td><td valign="top"><a href="#Symbol-Value">Symbol Value</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-var-directive_002c-TIC54X"><code>var</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-bitfields-not-supported">VAX bitfields not supported</a>:</td><td> </td><td valign="top"><a href="#VAX_002dno">VAX-no</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-branch-improvement">VAX branch improvement</a>:</td><td> </td><td valign="top"><a href="#VAX_002dbranch">VAX-branch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-command_002dline-options-ignored">VAX command-line options ignored</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-displacement-sizing-character">VAX displacement sizing character</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-floating-point">VAX floating point</a>:</td><td> </td><td valign="top"><a href="#VAX_002dfloat">VAX-float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-immediate-character">VAX immediate character</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-indirect-character">VAX indirect character</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-line-comment-character">VAX line comment character</a>:</td><td> </td><td valign="top"><a href="#VAX_002dChars">VAX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-line-separator">VAX line separator</a>:</td><td> </td><td valign="top"><a href="#VAX_002dChars">VAX-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-machine-directives">VAX machine directives</a>:</td><td> </td><td valign="top"><a href="#VAX_002ddirectives">VAX-directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-opcode-mnemonics">VAX opcode mnemonics</a>:</td><td> </td><td valign="top"><a href="#VAX_002dopcodes">VAX-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-operand-notation">VAX operand notation</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-register-names">VAX register names</a>:</td><td> </td><td valign="top"><a href="#VAX_002doperands">VAX-operands</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX-support">VAX support</a>:</td><td> </td><td valign="top"><a href="#Vax_002dDependent">Vax-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Vax_002d11-C-compatibility">Vax-11 C compatibility</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VAX_002fVMS-options">VAX/VMS options</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-version-directive"><code>version</code> directive</a>:</td><td> </td><td valign="top"><a href="#Version">Version</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-version-directive_002c-TIC54X"><code>version</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-version-of-assembler">version of assembler</a>:</td><td> </td><td valign="top"><a href="#v">v</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-versions-of-symbols">versions of symbols</a>:</td><td> </td><td valign="top"><a href="#Symver">Symver</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Virtualization-instruction-generation-override">Virtualization instruction generation override</a>:</td><td> </td><td valign="top"><a href="#MIPS-ASE-Instruction-Generation-Overrides">MIPS ASE Instruction Generation Overrides</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-visibility">visibility</a>:</td><td> </td><td valign="top"><a href="#Hidden">Hidden</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-visibility-1">visibility</a>:</td><td> </td><td valign="top"><a href="#Internal">Internal</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-visibility-2">visibility</a>:</td><td> </td><td valign="top"><a href="#Protected">Protected</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Visium-line-comment-character">Visium line comment character</a>:</td><td> </td><td valign="top"><a href="#Visium-Characters">Visium Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Visium-line-separator">Visium line separator</a>:</td><td> </td><td valign="top"><a href="#Visium-Characters">Visium Characters</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Visium-options">Visium options</a>:</td><td> </td><td valign="top"><a href="#Visium-Options">Visium Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Visium-registers">Visium registers</a>:</td><td> </td><td valign="top"><a href="#Visium-Registers">Visium Registers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Visium-support">Visium support</a>:</td><td> </td><td valign="top"><a href="#Visium_002dDependent">Visium-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-VMS-_0028VAX_0029-options">VMS (VAX) options</a>:</td><td> </td><td valign="top"><a href="#VAX_002dOpts">VAX-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-vtable_005fentry-directive"><code>vtable_entry</code> directive</a>:</td><td> </td><td valign="top"><a href="#VTableEntry">VTableEntry</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-vtable_005finherit-directive"><code>vtable_inherit</code> directive</a>:</td><td> </td><td valign="top"><a href="#VTableInherit">VTableInherit</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-W">W</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-warning-directive">warning directive</a>:</td><td> </td><td valign="top"><a href="#Warning">Warning</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-warning-for-altered-difference-tables">warning for altered difference tables</a>:</td><td> </td><td valign="top"><a href="#K">K</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-warning-messages">warning messages</a>:</td><td> </td><td valign="top"><a href="#Errors">Errors</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-warnings_002c-causing-error">warnings, causing error</a>:</td><td> </td><td valign="top"><a href="#W">W</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-warnings_002c-M32R">warnings, M32R</a>:</td><td> </td><td valign="top"><a href="#M32R_002dWarnings">M32R-Warnings</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-warnings_002c-suppressing">warnings, suppressing</a>:</td><td> </td><td valign="top"><a href="#W">W</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-warnings_002c-switching-on">warnings, switching on</a>:</td><td> </td><td valign="top"><a href="#W">W</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-weak-directive"><code>weak</code> directive</a>:</td><td> </td><td valign="top"><a href="#Weak">Weak</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-weakref-directive"><code>weakref</code> directive</a>:</td><td> </td><td valign="top"><a href="#Weakref">Weakref</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-WebAssembly-floating-point-_0028IEEE_0029">WebAssembly floating point (<small>IEEE</small>)</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dFloating_002dPoint">WebAssembly-Floating-Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-WebAssembly-line-comment-character">WebAssembly line comment character</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dChars">WebAssembly-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-WebAssembly-module-layout">WebAssembly module layout</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dmodule_002dlayout">WebAssembly-module-layout</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-WebAssembly-notes">WebAssembly notes</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dNotes">WebAssembly-Notes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-WebAssembly-opcodes">WebAssembly opcodes</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dOpcodes">WebAssembly-Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-WebAssembly-relocations">WebAssembly relocations</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dRelocs">WebAssembly-Relocs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-WebAssembly-signatures">WebAssembly signatures</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dSignatures">WebAssembly-Signatures</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-WebAssembly-support">WebAssembly support</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dDependent">WebAssembly-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-WebAssembly-Syntax">WebAssembly Syntax</a>:</td><td> </td><td valign="top"><a href="#WebAssembly_002dSyntax">WebAssembly-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-whitespace">whitespace</a>:</td><td> </td><td valign="top"><a href="#Whitespace">Whitespace</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-whitespace_002c-removed-by-preprocessor">whitespace, removed by preprocessor</a>:</td><td> </td><td valign="top"><a href="#Preprocessing">Preprocessing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-wide-floating-point-directives_002c-VAX">wide floating point directives, VAX</a>:</td><td> </td><td valign="top"><a href="#VAX_002ddirectives">VAX-directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-width-directive_002c-TIC54X"><code>width</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Width-of-continuation-lines-of-disassembly-output">Width of continuation lines of disassembly output</a>:</td><td> </td><td valign="top"><a href="#listing">listing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Width-of-first-line-disassembly-output">Width of first line disassembly output</a>:</td><td> </td><td valign="top"><a href="#listing">listing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Width-of-source-line-output">Width of source line output</a>:</td><td> </td><td valign="top"><a href="#listing">listing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-wmsg-directive_002c-TIC54X"><code>wmsg</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-aligned-program-counter_002c-ARC">word aligned program counter, ARC</a>:</td><td> </td><td valign="top"><a href="#ARC_002dRegs">ARC-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive"><code>word</code> directive</a>:</td><td> </td><td valign="top"><a href="#Word">Word</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive_002c-BPF"><code>word</code> directive, BPF</a>:</td><td> </td><td valign="top"><a href="#BPF-Directives">BPF Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive_002c-H8_002f300"><code>word</code> directive, H8/300</a>:</td><td> </td><td valign="top"><a href="#H8_002f300-Directives">H8/300 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive_002c-i386"><code>word</code> directive, i386</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive_002c-Nios-II"><code>word</code> directive, Nios II</a>:</td><td> </td><td valign="top"><a href="#Nios-II-Directives">Nios II Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive_002c-OpenRISC"><code>word</code> directive, OpenRISC</a>:</td><td> </td><td valign="top"><a href="#OpenRISC_002dDirectives">OpenRISC-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive_002c-PRU"><code>word</code> directive, PRU</a>:</td><td> </td><td valign="top"><a href="#PRU-Directives">PRU Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive_002c-SPARC"><code>word</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive_002c-TIC54X"><code>word</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-word-directive_002c-x86_002d64"><code>word</code> directive, x86-64</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-writing-patterns-in-memory">writing patterns in memory</a>:</td><td> </td><td valign="top"><a href="#Fill">Fill</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-wval"><code>wval</code></a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-X">X</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86-machine-directives">x86 machine directives</a>:</td><td> </td><td valign="top"><a href="#i386_002dDirectives">i386-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-arch-directive">x86-64 arch directive</a>:</td><td> </td><td valign="top"><a href="#i386_002dArch">i386-Arch</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-att_005fsyntax-pseudo-op">x86-64 att_syntax pseudo op</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-conversion-instructions">x86-64 conversion instructions</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-extension-instructions">x86-64 extension instructions</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-floating-point">x86-64 floating point</a>:</td><td> </td><td valign="top"><a href="#i386_002dFloat">i386-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-immediate-operands">x86-64 immediate operands</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-instruction-naming">x86-64 instruction naming</a>:</td><td> </td><td valign="top"><a href="#i386_002dMnemonics">i386-Mnemonics</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-intel_005fsyntax-pseudo-op">x86-64 intel_syntax pseudo op</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-jump-optimization">x86-64 jump optimization</a>:</td><td> </td><td valign="top"><a href="#i386_002dJumps">i386-Jumps</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-jump_002c-call_002c-return">x86-64 jump, call, return</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-jump_002fcall-operands">x86-64 jump/call operands</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-memory-references">x86-64 memory references</a>:</td><td> </td><td valign="top"><a href="#i386_002dMemory">i386-Memory</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-options">x86-64 options</a>:</td><td> </td><td valign="top"><a href="#i386_002dOptions">i386-Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-register-operands">x86-64 register operands</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-registers">x86-64 registers</a>:</td><td> </td><td valign="top"><a href="#i386_002dRegs">i386-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-sections">x86-64 sections</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-size-suffixes">x86-64 size suffixes</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-source_002c-destination-operands">x86-64 source, destination operands</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-support">x86-64 support</a>:</td><td> </td><td valign="top"><a href="#i386_002dDependent">i386-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-x86_002d64-syntax-compatibility">x86-64 syntax compatibility</a>:</td><td> </td><td valign="top"><a href="#i386_002dVariations">i386-Variations</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-xdef-directive_002c-Z80"><code>xdef</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-xfloat-directive_002c-TIC54X"><code>xfloat</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XGATE-addressing-modes">XGATE addressing modes</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dSyntax">XGATE-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XGATE-assembler-directives">XGATE assembler directives</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dDirectives">XGATE-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XGATE-floating-point">XGATE floating point</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dFloat">XGATE-Float</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XGATE-line-comment-character">XGATE line comment character</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dSyntax">XGATE-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XGATE-line-separator">XGATE line separator</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dSyntax">XGATE-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XGATE-opcodes">XGATE opcodes</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dopcodes">XGATE-opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XGATE-options">XGATE options</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dOpts">XGATE-Opts</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XGATE-support">XGATE support</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dDependent">XGATE-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XGATE-syntax">XGATE syntax</a>:</td><td> </td><td valign="top"><a href="#XGATE_002dSyntax">XGATE-Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-xlong-directive_002c-TIC54X"><code>xlong</code> directive, TIC54X</a>:</td><td> </td><td valign="top"><a href="#TIC54X_002dDirectives">TIC54X-Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-xref-directive_002c-Z80"><code>xref</code> directive, Z80</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XStormy16-comment-character">XStormy16 comment character</a>:</td><td> </td><td valign="top"><a href="#XStormy16_002dChars">XStormy16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XStormy16-line-comment-character">XStormy16 line comment character</a>:</td><td> </td><td valign="top"><a href="#XStormy16_002dChars">XStormy16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XStormy16-line-separator">XStormy16 line separator</a>:</td><td> </td><td valign="top"><a href="#XStormy16_002dChars">XStormy16-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XStormy16-machine-directives">XStormy16 machine directives</a>:</td><td> </td><td valign="top"><a href="#XStormy16-Directives">XStormy16 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XStormy16-pseudo_002dopcodes">XStormy16 pseudo-opcodes</a>:</td><td> </td><td valign="top"><a href="#XStormy16-Opcodes">XStormy16 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-XStormy16-support">XStormy16 support</a>:</td><td> </td><td valign="top"><a href="#XSTORMY16_002dDependent">XSTORMY16-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Xtensa-architecture">Xtensa architecture</a>:</td><td> </td><td valign="top"><a href="#Xtensa_002dDependent">Xtensa-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Xtensa-assembler-syntax">Xtensa assembler syntax</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Syntax">Xtensa Syntax</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Xtensa-directives">Xtensa directives</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Directives">Xtensa Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Xtensa-opcode-names">Xtensa opcode names</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Opcodes">Xtensa Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Xtensa-register-names">Xtensa register names</a>:</td><td> </td><td valign="top"><a href="#Xtensa-Registers">Xtensa Registers</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-xword-directive_002c-SPARC"><code>xword</code> directive, SPARC</a>:</td><td> </td><td valign="top"><a href="#Sparc_002dDirectives">Sparc-Directives</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +<tr><th><a name="AS-Index_cp_letter-Z">Z</a></th><td></td><td></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-_0024">Z80 $</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-_0027">Z80 ’</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-floating-point">Z80 floating point</a>:</td><td> </td><td valign="top"><a href="#Z80-Floating-Point">Z80 Floating Point</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-labels">Z80 labels</a>:</td><td> </td><td valign="top"><a href="#Z80_002dLabels">Z80-Labels</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-line-comment-character">Z80 line comment character</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-line-separator">Z80 line separator</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-options">Z80 options</a>:</td><td> </td><td valign="top"><a href="#Z80-Options">Z80 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-registers">Z80 registers</a>:</td><td> </td><td valign="top"><a href="#Z80_002dRegs">Z80-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-support">Z80 support</a>:</td><td> </td><td valign="top"><a href="#Z80_002dDependent">Z80-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80-Syntax">Z80 Syntax</a>:</td><td> </td><td valign="top"><a href="#Z80-Options">Z80 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80_002c-case-sensitivity">Z80, case sensitivity</a>:</td><td> </td><td valign="top"><a href="#Z80_002dCase">Z80-Case</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80_002c-_005c">Z80, \</a>:</td><td> </td><td valign="top"><a href="#Z80_002dChars">Z80-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z80_002donly-directives">Z80-only directives</a>:</td><td> </td><td valign="top"><a href="#Z80-Directives">Z80 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z800-addressing-modes">Z800 addressing modes</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dAddressing">Z8000-Addressing</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z8000-directives">Z8000 directives</a>:</td><td> </td><td valign="top"><a href="#Z8000-Directives">Z8000 Directives</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z8000-line-comment-character">Z8000 line comment character</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dChars">Z8000-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z8000-line-separator">Z8000 line separator</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dChars">Z8000-Chars</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z8000-opcode-summary">Z8000 opcode summary</a>:</td><td> </td><td valign="top"><a href="#Z8000-Opcodes">Z8000 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z8000-options">Z8000 options</a>:</td><td> </td><td valign="top"><a href="#Z8000-Options">Z8000 Options</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z8000-registers">Z8000 registers</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dRegs">Z8000-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-Z8000-support">Z8000 support</a>:</td><td> </td><td valign="top"><a href="#Z8000_002dDependent">Z8000-Dependent</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-zdaoff-pseudo_002dop_002c-V850"><code>zdaoff</code> pseudo-op, V850</a>:</td><td> </td><td valign="top"><a href="#V850-Opcodes">V850 Opcodes</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-zero-directive"><code>zero</code> directive</a>:</td><td> </td><td valign="top"><a href="#Zero">Zero</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-zero-register_002c-V850"><code>zero</code> register, V850</a>:</td><td> </td><td valign="top"><a href="#V850_002dRegs">V850-Regs</a></td></tr> +<tr><td></td><td valign="top"><a href="#index-zero_002dterminated-strings">zero-terminated strings</a>:</td><td> </td><td valign="top"><a href="#Asciz">Asciz</a></td></tr> +<tr><td colspan="4"> <hr></td></tr> +</table> +<table><tr><th valign="top">Jump to: </th><td><a class="summary-letter" href="#AS-Index_cp_symbol-1"><b> </b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-2"><b>#</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-3"><b>$</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-4"><b>%</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-5"><b>-</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-6"><b>.</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-7"><b>1</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-8"><b>2</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-9"><b>3</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-10"><b>4</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-11"><b>8</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-12"><b>:</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-13"><b>@</b></a> + +<a class="summary-letter" href="#AS-Index_cp_symbol-14"><b>_</b></a> + +<br> +<a class="summary-letter" href="#AS-Index_cp_letter-A"><b>A</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-B"><b>B</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-C"><b>C</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-D"><b>D</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-E"><b>E</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-F"><b>F</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-G"><b>G</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-H"><b>H</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-I"><b>I</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-J"><b>J</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-L"><b>L</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-M"><b>M</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-N"><b>N</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-O"><b>O</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-P"><b>P</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-Q"><b>Q</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-R"><b>R</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-S"><b>S</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-T"><b>T</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-U"><b>U</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-V"><b>V</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-W"><b>W</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-X"><b>X</b></a> + +<a class="summary-letter" href="#AS-Index_cp_letter-Z"><b>Z</b></a> + +</td></tr></table> + +<div class="footnote"> +<hr> +<h4 class="footnotes-heading">Footnotes</h4> + +<h3><a name="FOOT1" href="#DOCF1">(1)</a></h3> +<p>This +is not the same as the executable image file alignment controlled by <code>ld</code>’s +‘<samp>--section-alignment</samp>’ option; image file sections in PE are aligned to +multiples of 4096, which is far too large an alignment for ordinary variables. +It is rather the default alignment for (non-debug) sections within object +(‘<samp>*.o</samp>’) files, which are less strictly aligned.</p> +<h3><a name="FOOT2" href="#DOCF2">(2)</a></h3> +<p>The term “macro” is somewhat overloaded here, since +these macros have no relation to those defined by <code>.macro</code>, +see <a href="#Macro"><code>.macro</code></a>.</p> +<h3><a name="FOOT3" href="#DOCF3">(3)</a></h3> +<p>Literals for the +<code>.init</code> and <code>.fini</code> sections are always placed in separate +sections, even when ‘<samp>--text-section-literals</samp>’ is enabled.</p> +<h3><a name="FOOT4" href="#DOCF4">(4)</a></h3> +<p>Any +more details?</p> +</div> +<hr> + + + +</body> +</html> |