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| author | Android Build Coastguard Worker <android-build-coastguard-worker@google.com> | 2023-03-05 00:24:14 +0000 |
|---|---|---|
| committer | Android Build Coastguard Worker <android-build-coastguard-worker@google.com> | 2023-03-05 00:24:14 +0000 |
| commit | 9c17e7c63ca66662e8ae3692e2995144404cbf40 (patch) | |
| tree | bda231699753a245a3c9bcb65ee450b07fe9aaa7 | |
| parent | d680a4ef3949e44ddf13045d7771fc13404bcc90 (diff) | |
| parent | c96b8b571c7a9aeedbbda7984cfadd6b18d00bf4 (diff) | |
Snap for 9690662 from c96b8b571c7a9aeedbbda7984cfadd6b18d00bf4 to udc-release
Change-Id: I81ff4a9acaeef5d5625b68b15ed7a8539123c3ad
| -rw-r--r-- | gralloc4/src/core/format_info.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gralloc4/src/core/format_info.cpp b/gralloc4/src/core/format_info.cpp index 08608fb..b993f16 100644 --- a/gralloc4/src/core/format_info.cpp +++ b/gralloc4/src/core/format_info.cpp @@ -208,7 +208,7 @@ const format_ip_support_t formats_ip_support[] = { /* BEGIN ALIGNED SECTION */ { .id = HAL_PIXEL_FORMAT_GOOGLE_NV12_SP, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN, .gpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_wr = F_LIN, .vpu_rd = F_LIN, .cam_wr = F_LIN }, { .id = HAL_PIXEL_FORMAT_GOOGLE_NV12_SP_10B, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN, .gpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_wr = F_LIN, .vpu_rd = F_LIN, .cam_wr = F_LIN }, - { .id = HAL_PIXEL_FORMAT_GOOGLE_R_8, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .gpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_wr = F_NONE, .vpu_rd = F_NONE, .cam_wr = F_LIN }, + { .id = HAL_PIXEL_FORMAT_GOOGLE_R_8, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .gpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_rd = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_wr = F_NONE, .vpu_rd = F_NONE, .cam_wr = F_LIN }, { .id = HAL_PIXEL_FORMAT_GOOGLE_RG_88, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .gpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_wr = F_NONE, .vpu_rd = F_NONE, .cam_wr = F_LIN }, /* END ALIGNED SECTION */ }; |