diff options
Diffstat (limited to 'libc/kernel/uapi/drm/amdgpu_drm.h')
| -rw-r--r-- | libc/kernel/uapi/drm/amdgpu_drm.h | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/libc/kernel/uapi/drm/amdgpu_drm.h b/libc/kernel/uapi/drm/amdgpu_drm.h index 6ae9c9ccb..1cdae1617 100644 --- a/libc/kernel/uapi/drm/amdgpu_drm.h +++ b/libc/kernel/uapi/drm/amdgpu_drm.h @@ -35,6 +35,8 @@ #define DRM_AMDGPU_GEM_USERPTR 0x11 #define DRM_AMDGPU_WAIT_FENCES 0x12 #define DRM_AMDGPU_VM 0x13 +#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 +#define DRM_AMDGPU_SCHED 0x15 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) @@ -49,6 +51,8 @@ #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) +#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) +#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 @@ -61,6 +65,8 @@ #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) +#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) +#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) struct drm_amdgpu_gem_create_in { __u64 bo_size; __u64 alignment; @@ -104,11 +110,17 @@ union drm_amdgpu_bo_list { #define AMDGPU_CTX_GUILTY_RESET 1 #define AMDGPU_CTX_INNOCENT_RESET 2 #define AMDGPU_CTX_UNKNOWN_RESET 3 +#define AMDGPU_CTX_PRIORITY_UNSET - 2048 +#define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023 +#define AMDGPU_CTX_PRIORITY_LOW - 512 +#define AMDGPU_CTX_PRIORITY_NORMAL 0 +#define AMDGPU_CTX_PRIORITY_HIGH 512 +#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 struct drm_amdgpu_ctx_in { __u32 op; __u32 flags; __u32 ctx_id; - __u32 _pad; + __s32 priority; }; union drm_amdgpu_ctx_out { struct { @@ -138,6 +150,16 @@ union drm_amdgpu_vm { struct drm_amdgpu_vm_in in; struct drm_amdgpu_vm_out out; }; +#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 +struct drm_amdgpu_sched_in { + __u32 op; + __u32 fd; + __s32 priority; + __u32 flags; +}; +union drm_amdgpu_sched { + struct drm_amdgpu_sched_in in; +}; #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) @@ -331,6 +353,19 @@ struct drm_amdgpu_cs_chunk_fence { struct drm_amdgpu_cs_chunk_sem { __u32 handle; }; +#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 +#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 +#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 +union drm_amdgpu_fence_to_handle { + struct { + struct drm_amdgpu_fence fence; + __u32 what; + __u32 pad; + } in; + struct { + __u32 handle; + } out; +}; struct drm_amdgpu_cs_chunk_data { union { struct drm_amdgpu_cs_chunk_ib ib_data; @@ -381,6 +416,7 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_SENSOR_VDDNB 0x6 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E +#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 |