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Age	Commit message (Collapse)	Author
2021-02-11	ARM64: Adjust SIMD checker tests for SVE.	Artem Serov
	Adds SVE-specific checker line for SIMD tests using isaHasFeature() function. Test: test-art-target with Neon. Test: art tests on FVP (steps in test/README.arm_fvp.md) with FVP arg: -C SVE.ScalableVectorExtension.veclen=[2,4] (SVE vector [128,256] bits wide) Change-Id: I8f2134861b47437823797da48a3ffb680bafc544
2017-05-11	ARM64: Share address computation across SIMD LDRs/STRs.	Artem Serov
	For array accesses the element address has the following structure: Address = CONST_OFFSET + base_addr + index << ELEM_SHIFT Taking into account ARM64 LDR/STR addressing modes address part (CONST_OFFSET + index << ELEM_SHIFT) can be shared across array access with the same data type and index. For example, for the following loop 5 accesses can share address computation: void foo(int[] a, int[] b, int[] c) { for (i...) { a[i] = a[i] + 5; b[i] = b[i] + c[i]; } } Test: test-art-host, test-art-target Change-Id: I46af3b4e4a55004336672cdba3296b7622d815ca