Age | Commit message (Collapse) | Author |
|
Also remove MIPS assembler/disassembler support.
Test: aosp_taimen-userdebug boots.
Test: m test-art-host-gtest
Test: testrunner.py --host --optimizing
Bug: 147346243
Change-Id: Id736074b97cd04987a7902741828b119508df1c0
|
|
Remove runtime/globals.h and make clients point to the right globals.h
(libartbase/base/globals.h). Also make within-libartbase includes
relative rather than using base/, etc.
Bug: 22322814
Test: make -j 40 checkbuild
Change-Id: I99de63fc851d48946ab401e2369de944419041c7
|
|
Move the remainder of the Arena stuff, plus dumpable and
runtime/*memory_region* to libartbase. More preparation to build
profiling library.
Bug: 22322814
Test: make -j 50 checkbuild
Change-Id: Iaf26d310c89bc58846553281576c18102f5e4122
|
|
Adding InstructionSet::kLast shall make it easier to encode
the InstructionSet in fewer bits using BitField<>. However,
introducing `kLast` into the `art` namespace is not a good
idea, so we change the InstructionSet to an enum class.
This also uncovered a case of InstructionSet::kNone being
erroneously used instead of vixl32::Condition::None(), so
it's good to remove `kNone` from the `art` namespace.
Test: m test-art-host-gtest
Test: testrunner.py --host --optimizing
Change-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6
|
|
Memory needed to compile the two most expensive methods for
aosp_angler-userdebug boot image:
BatteryStats.dumpCheckinLocked() : 25.1MiB -> 21.1MiB
BatteryStats.dumpLocked(): 49.6MiB -> 42.0MiB
This is because all the memory previously used by Scheduler
is reused by the register allocator; the register allocator
has a higher peak usage of the ArenaStack.
And continue the "arena"->"allocator" renaming.
Test: m test-art-host-gtest
Test: testrunner.py --host
Bug: 64312607
Change-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01
|
|
Test: mma test-art-host-gtest
Change-Id: I123fe1e33de13af6a2b2a76f37f7ad23004a81c0
|
|
This patch fixes an issue found here:
https://android-review.googlesource.com/#/c/307532/
Also re-enables vixl MacroAssembler for arm.
Test: export ART_USE_READ_BARRIER=true; export ART_HEAP_POISONING=true; \
m test-art-host
Test: export ART_USE_READ_BARRIER=true; export ART_HEAP_POISONING=true; \
m test-art-target
Test: dump-oat-boot with ART_USE_READ_BARRIER=true
Change-Id: I03e3014fb250791db2d24a0ab1a76ca96384c332
|
|
The VIXL one hits an assertion error for CC:
external/vixl/src/aarch32/macro-assembler-aarch32.h:1386:
void vixl::aarch32::MacroAssembler::Cmp(vixl::aarch32::Condition,
vixl::aarch32::Register, const vixl::aarch32::Operand &):
Assertion `!AliasesAvailableScratchRegister(rn)' failed.
Fixes dump-oat-boot with CC.
Test: test-art-target, N6P booting
Change-Id: I781fe8c8c2d6cd8b246ee4509281d6c645c89a28
|
|
|
|
Add conditionals around more code that is only used for codegen for
specific architectures, and move a few more files into the
architecture-specific codegen lists.
Tests: ART_HOST_CODEGEN_ARCHS="x86_64 mips" m -j ART_TARGET_CODEGEN_ARCHS=svelte test-art-host
Bug: 30928847
Change-Id: I0444d15e1cafe4c9b13ff78718c3b13b544270e7
|
|
Change-Id: I9f9ef1a9c9c9eb796d52980916e56e841aa52a0f
|
|
|
|
Extract the JNI assembler parts from the regular assembler.
Change-Id: Ice39ffeb854f8651e93443dd69f4c9e0e802975c
Test: m test-art-target (N6)
|
|
Extract the JNI assembler parts from the regular assembler.
Change-Id: I0b0ad32e18f585b75e9da0237afe082c25a1d291
Test: m test-art-target (N9)
|
|
|
|
Extract the JNI assembler parts from the regular assembler.
Test: m test-art-host
Change-Id: I291fb76ad9232123b4c1992488ee81fec3c1db47
|
|
Extract the JNI assembler parts from the regular assembler.
Change-Id: I0b47af03ca12798f58dafec716a529eb0edf9649
Test: m test-art-host
|
|
Extract macro assembler functionality used by the JNI compiler from
the assembler interface. Templatize the new interface so that
type safety ensures correct usage.
Change-Id: Idb9f56e5b87e43ee6a7378853d8a9f01abe156b2
Test: m test-art-host
|