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path: root/compiler/optimizing/codegen_test_utils.h
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2021-02-03Use mmap for compiled code for gtest.Vladimir Marko
Avoid executing code in memory allocated with malloc() as pointers to that memory can be tagged which interferes with managed stack walk. Test: m test-art-host-gtest. Bug: 177816575 Change-Id: Id376091f82d5686adf3ab18d2980a42e78de57ce
2020-07-29Revert^3 "VIXL simulator for ART (Stage1)"Ulya Trafimovich
This reverts commit e886d68b9c40c941d8966b9c90d0e265c75fb19e. Reason for revert: simulator implemention is not ready yet. Test: lunch aosp_cf_x86_phone-userdebug && m Test: art/test.py --run-test --optimizing --host Change-Id: I03c8c09ea348205b0238d7a26caef3477cd6ae3b
2020-07-17Revert^2 "VIXL simulator for ART (Stage1)"Ulyana Trafimovich
This reverts commit 3060bb919cd2f37c6a97e87c1581ac5294af72b3. Reason for revert: relanding original change. The fix is setting `device_supported: false` for libart(d)-simulator module in the .bp file (`m checkbuild` attempted to build it for arm32 and failed). Original commit message: VIXL simulator for ART (Stage1) Quick User Guide: test/README.simulator.md This CL enables running ART run-tests in a simulator on host machine. Some benefits of using this simulator approach: - No need to use a target device at all. Save developers from solving the device troubles: build, flash, usb, adb, etc. - Speed up development/debug/test cycle. - Allows easy debugging/testing new instruction features without real hardware. - Allows using a smaller AOSP Android manifest master-art. The Stage1 CL provides support for running 30% of current run-tests. The rest unsupported test cases are kept in knownfailures.json. Future work will be supporting proper stack frame layout between simulator and quick entrypoints, so that stack walk, QuickArgumentVisitor, deoptimization, etc can be supported. This CL adds libart(d)-simulator-container library to the ART APEX. It has caused the following increase of the APEX size (small, about 0.13% for release APEX, measured for target aosp_arm64-userdebug): Before: 88992 com.android.art.debug.apex 51612 com.android.art.release.apex 112352 com.android.art.testing.apex After: 89124 com.android.art.debug.apex 51680 com.android.art.release.apex 112468 com.android.art.testing.apex Change-Id: I461c80aa9c4ce0673eef1c0254d2c539f2b6a8d5 Test: art/test.py --run-test --optimizing --simulate-arm64 Test: art/test.py --run-test --optimizing --host Test: m test-art-host-gtest
2020-07-16Revert "VIXL simulator for ART (Stage1)"Ulyana Trafimovich
This reverts commit 48ca6a681efe1fa1cf82d8af918bf9bbfd35ae96. Reason for revert: broken build 6685551 on aosp-master on full-eng Bug: 161440641 Change-Id: I849fe53f56c4786f0f2a1605cbfd215559f11072
2020-07-16VIXL simulator for ART (Stage1)Xueliang Zhong
Quick User Guide: test/README.simulator.md This CL enables running ART run-tests in a simulator on host machine. Some benefits of using this simulator approach: - No need to use a target device at all. Save developers from solving the device troubles: build, flash, usb, adb, etc. - Speed up development/debug/test cycle. - Allows easy debugging/testing new instruction features without real hardware. - Allows using a smaller AOSP Android manifest master-art. The Stage1 CL provides support for running 30% of current run-tests. The rest unsupported test cases are kept in knownfailures.json. Future work will be supporting proper stack frame layout between simulator and quick entrypoints, so that stack walk, QuickArgumentVisitor, deoptimization, etc can be supported. This CL adds libart(d)-simulator-container library to the ART APEX. It has cause the following increase of the APEX size (small, about 0.13% for release APEX, measured for target aosp_arm64-userdebug): Before: 88992 com.android.art.debug.apex 51612 com.android.art.release.apex 112352 com.android.art.testing.apex After: 89124 com.android.art.debug.apex 51680 com.android.art.release.apex 112468 com.android.art.testing.apex Test: art/test.py --run-test --optimizing --simulate-arm64 Test: art/test.py --run-test --optimizing --host Test: m test-art-host-gtest Change-Id: I078812dde9aaf7128d9f262b2102251927596b7f
2020-05-15Revert^2 "Remove test_per_src from ART tests."David Srbecky
Second attempt at this, which fixes the asan failures. Remove test_per_src since it is not supported by atest. Replace it with gtest_isolate which is transparent to atest, and which still allows us to run tests in parallel. The size of test binaries halves (from 1GB to 0.5GB). Test run-time on host is unchanged. Test run-time on target is 4x faster (tested on walleye). Added a gtest_main.cc with the gtest isolated main function, and ART-specific initialization. Bug: 147819342 Test: m test-art-host-gtest Test: art/tools/run-gtests.sh Test: art/test/testrunner/run_build_test_target.py art-gtest-asan Change-Id: I515c911bb7d44285495802fc66cd732fc8e6d8df
2020-05-08Revert "Remove test_per_src from ART tests."Christopher Ferris
This reverts commit 8103e479d8f8447584582b2b70752029f7087776. Reason for revert: asan run fails in multiple ways Test: ran ./art/test/testrunner/run_build_test_target.py art-gtest-asan Change-Id: Ib9f2887436a664b64c6410f56a25ae2dd0e0aab4
2020-05-07Remove test_per_src from ART tests.David Srbecky
Remove test_per_src since it is not supported by atest. Replace it with gtest_isolate which is transparent to atest, and which still allows us to run tests in parallel. The size of test binaries halves (from 1GB to 0.5GB). Test run-time on host is unchanged. Test run-time on target is 4x faster (tested on walleye). Bug: 147819342 Test: m test-art-host-gtest Test: art/tools/run-gtests.sh Change-Id: Id295af00d08b24baa2e421b0f3313df0b2e56fe9
2020-02-13Remove MIPS support from Optimizing.Vladimir Marko
Test: aosp_taimen-userdebug boots. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Bug: 147346243 Change-Id: I97fdc15e568ae3fe390efb1da690343025f84944
2019-10-14Revert "Make compiler/optimizing/ symbols hidden."Vladimir Marko
This reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf. Reason for revert: Breaks ASAN tests (ODR violation). Bug: 142365358 Change-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4
2019-10-14Make compiler/optimizing/ symbols hidden.Vladimir Marko
Make symbols in compiler/optimizing hidden by a namespace attribute. The unit intrinsic_objects.{h,cc} is excluded as it is needed by dex2oat. As the symbols are no longer exported, gtests are now linked with the static version of the libartd-compiler library. libart-compiler.so size: - before: arm: 2396152 arm64: 3345280 - after: arm: 2016176 (-371KiB, -15.9%) arm64: 2874480 (-460KiB, -14.1%) Test: m test-art-host-gtest Test: testrunner.py --host --optimizing --jit Bug: 142365358 Change-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8
2019-03-29Modernise code to use override specifierYi Kong
Generated by clang-tidy, with IgnoreDestructors option enabled. Test: m checkbuild Bug: 116509795 Change-Id: I5dafa10c2cf605165581b8cf7dd2633ed101ed65
2018-08-28Use 'final' and 'override' specifiers directly in ART.Roland Levillain
Remove all uses of macros 'FINAL' and 'OVERRIDE' and replace them with 'final' and 'override' specifiers. Remove all definitions of these macros as well, which were located in these files: - libartbase/base/macros.h - test/913-heaps/heaps.cc - test/ti-agent/ti_macros.h ART is now using C++14; the 'final' and 'override' specifiers have been introduced in C++11. Test: mmma art Change-Id: I256c7758155a71a2940ef2574925a44076feeebf
2018-08-20Fix longstanding bug around implicit NPEs and GC, version 2.Nicolas Geoffray
The TODO has been there since M (so forever :)): https://android-review.googlesource.com/c/platform/art/+/122794/13//COMMIT_MSG#13 We hardly see the issue in our tests as we need to have: 1) A GC happening while creating the NPE object. 2) ParallelMoves between the NullCheck and implicit null check operation that moves references. The CL piggy backs on the "IsEmittedAtUseSite" flag, to set implicit null checks with it. The liveness analysis then special cases implicit null checks to record environment uses at the location of the actual instruction that will do the implicit null check. Test: test.py --gcstress Test: run-libcore-tests --gcstress bug: 111545159 Change-Id: I3ecea4fe0d7e483e93db83281ca10db47da228c5
2018-06-25Move instruction_set_ to CompilerOptions.Vladimir Marko
Removes CompilerDriver dependency from ImageWriter and several other classes. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Test: Pixel 2 XL boots. Test: m test-art-target-gtest Test: testrunner.py --target --optimizing Change-Id: I3c5b8ff73732128b9c4fad9405231a216ea72465
2018-04-11Revert^2 "Compile link-time thunks in codegen."Vladimir Marko
The linker crash (the reason for revert) is flaky and maybe we shall not see it with this CL now that unrelated source code has changed. Test: Rely on TreeHugger Bug: 36141117 Bug: 77581732 This reverts commit 5806a9ec99b5494b511e84c74f494f0b3a8ebec5. Change-Id: I3a4a058847dff601681ba391abf45833424fa06d
2018-04-04Revert "Compile link-time thunks in codegen."Vladimir Marko
Reason for revert: This caused clang linker crash in several branches. Bug: 77581732 This reverts commit c9dd2207dfdab42586b1d6a5e7f11cf2fcea3a7a. Change-Id: I1923809083cf41c4f19e3e60df03ae80517aaedb
2018-04-04Compile link-time thunks in codegen.Vladimir Marko
Prepare for experimenting with Baker read barrier marking introspection entrypoints for JIT. Test: m test-art-host-gtest Test: Compare compiled boot*.oat before and after (no diff). Test: Pixel 2 XL boots. Bug: 36141117 Change-Id: Idb413a31b158db4bf89a8707ea46dd167a06f110
2017-11-02ART: Make InstructionSet an enum class and add kLast.Vladimir Marko
Adding InstructionSet::kLast shall make it easier to encode the InstructionSet in fewer bits using BitField<>. However, introducing `kLast` into the `art` namespace is not a good idea, so we change the InstructionSet to an enum class. This also uncovered a case of InstructionSet::kNone being erroneously used instead of vixl32::Condition::None(), so it's good to remove `kNone` from the `art` namespace. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Change-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6
2017-10-09Use ScopedArenaAllocator for register allocation.Vladimir Marko
Memory needed to compile the two most expensive methods for aosp_angler-userdebug boot image: BatteryStats.dumpCheckinLocked() : 25.1MiB -> 21.1MiB BatteryStats.dumpLocked(): 49.6MiB -> 42.0MiB This is because all the memory previously used by Scheduler is reused by the register allocator; the register allocator has a higher peak usage of the ArenaStack. And continue the "arena"->"allocator" renaming. Test: m test-art-host-gtest Test: testrunner.py --host Bug: 64312607 Change-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01
2017-10-06ART: Use ScopedArenaAllocator for pass-local data.Vladimir Marko
Passes using local ArenaAllocator were hiding their memory usage from the allocation counting, making it difficult to track down where memory was used. Using ScopedArenaAllocator reveals the memory usage. This changes the HGraph constructor which requires a lot of changes in tests. Refactor these tests to limit the amount of work needed the next time we change that constructor. Test: m test-art-host-gtest Test: testrunner.py --host Test: Build with kArenaAllocatorCountAllocations = true. Bug: 64312607 Change-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a
2017-08-11Instrument ARM generated code to check the Marking Register.Roland Levillain
Generate run-time code in the Optimizing compiler checking that the Marking Register's value matches `self.tls32_.is.gc_marking` in debug mode (on target; and on host with JIT, or with AOT when compiling the core image). If a check fails, abort. Test: m test-art-target Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false Test: ARM device/emulator boot test with libartd Bug: 37707231 Change-Id: I903f44d385d66ff74d65aa09d7113aa9cb7b9f24
2017-08-10Instrument ARM64 generated code to check the Marking Register.Roland Levillain
Generate run-time code in the Optimizing compiler checking that the Marking Register's value matches `self.tls32_.is.gc_marking` in debug mode (on target; and on host with JIT, or with AOT when compiling the core image). If a check fails, abort. Test: m test-art-target Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false Test: ARM64 device boot test with libartd. Bug: 37707231 Change-Id: Ie9b322b22b3d26654a06821e1db71dbda3c43061
2017-07-26ART: Move simulator to art/Andreas Gampe
Move the simulator library out of the runtime directory. Let's not pollute the runtime library. Test: m Change-Id: I351a0061ae628c3af0462b72d4de727db296ec23
2017-07-14Remove the old ARM code generator from ART's Optimizing compiler.Roland Levillain
The AArch32 VIXL-based code generator has been the default ARM code generator in ART for some time now. The old ARM code generator does not compile anymore; retiring it. Test: test.py Bug: 63316036 Change-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db
2017-05-11Clean up some uses of "auto".Vladimir Marko
Make actual types more explicit, either by replacing "auto" with actual type or by assigning std::pair<> elements of an "auto" variable to typed variables. Avoid binding const references to temporaries. Avoid copying a container. Test: m test-art-host-gtest Change-Id: I1a59f9ba1ee15950cacfc5853bd010c1726de603
2017-03-27ART: Clean up field initializationAndreas Gampe
Add explicit field initialization to default value where necessary. Also clean up interpreter intrinsics header. Test: m Change-Id: I7a850ac30dcccfb523a5569fb8400b9ac892c8e5
2017-01-25AArch64: Add HInstruction scheduling support.Alexandre Rames
This commit adds a new `HInstructionScheduling` pass that performs basic scheduling on the `HGraph`. Currently, scheduling is performed at the block level, so no `HInstruction` ever leaves its block in this pass. The scheduling process iterates through blocks in the graph. For blocks that we can and want to schedule: 1) Build a dependency graph for instructions. It includes data dependencies (inputs/uses), but also environment dependencies and side-effect dependencies. 2) Schedule the dependency graph. This is a topological sort of the dependency graph, using heuristics to decide what node to schedule first when there are multiple candidates. Currently the heuristics only consider instruction latencies and schedule first the instructions that are on the critical path. Test: m test-art-host Test: m test-art-target Change-Id: Iec103177d4f059666d7c9626e5770531fbc5ccdc
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