Age | Commit message (Collapse) | Author |
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Continue work on cutting the dependency on the verifier.
Change-Id: I0f95b1eb2e10fd8f6bf54817f1202bdf6dfdb0fe
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Also:
- Stylistic changes in corresponding parts on the x86 and
x86-64 code generators.
- Update and improve the documentation of
art::arm::Condition.
Bug: 21120453
Change-Id: If144772046e7d21362c3c2086246cb7d011d49ce
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- Instrument ARM, ARM64, x86 and x86-64 code generators.
- Note: To turn heap poisoning on in Optimizing, set the
environment variable `ART_HEAP_POISONING' to "true"
before compiling ART.
Bug: 12687968
Change-Id: Ib3120b38cf805a8a50207a314b9ccc90c8d93740
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Now that we relocate branches, we can try make more use of cbz/cbnz.
Change-Id: I93ca64107f34eb3c43f2e7102ea90453113dad7a
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This patch enables the GraphBuilder to generate blocks and edges which
represent the exceptional control flow when try/catch blocks are
present in the code. Actual compilation is still delegated to Quick
and Baseline ignores the additional code.
To represent the relationship between try and catch blocks, Builder
splits the edges which enter/exit a try block and links the newly
created blocks to the corresponding exception handlers. This layout
will later enable the SsaBuilder to correctly infer the dominators of
the catch blocks and to produce the appropriate reverse post ordering.
It will not, however, allow for building the complete SSA form of the
catch blocks and consequently optimizing such blocks.
To this end, a new TryBoundary control-flow instruction is introduced.
Codegen treats it the same as a Goto but it allows for additional
successors (the handlers).
This reverts commit 3e18738bd338e9f8363b26bc895f38c0ec682824.
Change-Id: I4f5ea961848a0b83d8db3673763861633e9bfcfb
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Causes OutOfMemory issues, need to investigate.
This reverts commit 0b5c7d1994b76090afcc825e737f2b8c546da2f8.
Change-Id: I263e6cc4df5f9a56ad2ce44e18932ca51d7e349f
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This patch enables the GraphBuilder to generate blocks and edges which
represent the exceptional control flow when try/catch blocks are
present in the code. Actual compilation is still delegated to Quick
and Baseline ignores the additional code.
To represent the relationship between try and catch blocks, Builder
splits the edges which enter/exit a try block and links the newly
created blocks to the corresponding exception handlers. This layout
will later enable the SsaBuilder to correctly infer the dominators of
the catch blocks and to produce the appropriate reverse post ordering.
It will not, however, allow for building the complete SSA form of the
catch blocks and consequently optimizing such blocks.
To this end, a new TryBoundary control-flow instruction is introduced.
Codegen treats it the same as a Goto but it allows for additional
successors (the handlers).
Change-Id: I415b985596d5bebb7b1bb358a46e08b7b04bb53a
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'second_reg' is an input register that can survive the instruction.
Instead use the output register as a temporary result.
bug:21667432
Change-Id: I1a4577b0333c3fb184645023d5eae30555bbf65c
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This is automatically added to the '.cfg' output when using the usual
`--dump-cfg` option.
Change-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb
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Change-Id: I22160d90de3fe0ab3e6a2acc440bda8daa00e0f0
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Change-Id: I16c3fad45c4b98b94b7c83d071374096e81d407a
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This reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98.
Adjust block label positions. Bad catch block labels were the
reason for the revert.
Change-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310
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This reverts commit f38caa68cce551fb153dff37d01db518e58ed00f.
Change-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40
Reason: broke the tests.
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Change-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7
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Problem exposed by this change was fixed in:
https://android-review.googlesource.com/#/c/154031/
This reverts commit 7b0e353b49ac3f464c662f20e20e240f0231afff.
Change-Id: I680c13dc9db9ba223ab11c7af255222860b4e6d2
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Crash was due to overwriting the location of the current method
in the slow path of an intrinsic.
Change-Id: I6ca58ef5b3cea19925e60b9500aef543bc5f71ef
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082-inline-execute fails on x86.
This reverts commit e21aa42e1341d34250742abafdd83311ad9fa737.
Change-Id: Ib3fd25faee2e0128001e40d3d51a74f959bc4449
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Also remove unsed CodeGenerator::LoadCurrentMethod.
Change-Id: I4b8d3f2a30b8e2c76b6b329a72555483c993cb73
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Fails on baseline/x86.
This reverts commit 38207af82afb6f99c687f64b15601ed20d82220a.
Change-Id: Ib71018367eb7c6046965494a7e996c22af3de403
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Change-Id: I0d15244b6b44c8b10079398c55da5071a3e3af66
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Use a VMLA instruction instead of VADD & VMUL instructions
in long-to-double conversions on ARM. This change reduces
code size and improves execution times (but does not alter
precision). It trades one temporary FPU register for two
temporary core registers.
Change-Id: I1dc35bef6c12be8f305e5b46da98c2421686b60d
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Change-Id: If88d4f639658db2d6d71f5abcad563211138fc4a
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This is one step forward, we could factorize more, but
I wanted to get this out of the way first.
Change-Id: I6ae411a737eebaecb64974f47af507ce0cfbae85
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Change-Id: I65fba9d8310ff3759322cec3345235e6472f4cfb
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On ARM, translate long-to-float type conversions (from both
Quick and Optimizing) as calls to the runtime routine
art_l2f, instead of generating ad hoc code, so as to improve
the precision of the conversions.
Bug: 20413424
Change-Id: I8c414ee1c6f4ff1f32ee78f75734cfd3cf579f71
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Change-Id: Ifa23023ffaca631a4f6b5745dd7492c39521a26f
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Optimizing + quick tests are passing, devices boot.
TODO: Test and fix bugs in mips64.
Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.
Some of the savings are from removal of virtual methods and direct
methods object arrays.
Bug: 19264997
Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d
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Change-Id: I23d27e5e10736d127519eb3238ff8f25df3843a2
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This enables register allocation for the current method, so
that users of it don't always load it from the stack.
Currently only used by HLoadClass. Will make follow-up
CLs for the other users.
Change-Id: If73324d85643102faba47fabbbd2755eb258c59c
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This argument is a condition instruction, not a comparison.
Change-Id: I026f799d2161df58b0c8a84600eb8fffd6f7b998
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Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.
Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.
Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.
Bug: 13925192
Change-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7
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This reverts commit 1f277e3cef6c33cd35e91123978491d83338d2ad.
- Fix CompareAndBranch to not use cbz/cbnz with high registers.
- Add a test for CompareAndBranch with the *inc file, as the
other assembler test infrastructure does not handle labels.
Change-Id: If552bf1112b96caa3b9bb6c73c4b40bb90a33db7
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Fails some benchmarks and libcore tests.
This reverts commit db0bbab279534974dca507946c66cff2d05dc9f9.
Change-Id: I5d1afef5ede87e65d61f49529027c5c2f35b17fb
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This tells the assembler that the user knows the encoding
can be in 16bits.
Change-Id: Idf36c38beb1e07a69862c972484aeb08326a0499
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We cannot relocate branches, but we can at least encode branches
on 16bits when the target is known.
Change-Id: Icb6116ed974fc97e03622ac80d914c2c06f4cba2
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Change-Id: I45687f6d3505178e2fc3689eac9cb6ab1b2c1e29
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This patch also includes:
1. Add java test for div/rem negative constants.
2. Fix a thumb2 encoding issue where the last operand is
"reg, shift #amount" in some instructions.
3. Support a simple filter in arm32 assembler test to filter out
unsupported cases, such as "smull r0, r0, r1, r2".
4. Add smull arm32 assembler test.
5. Add smull/umull thumb2 test.
6. Add test for the thumb2 encoding issue which is fixed in this
patch.
Change-Id: I1601bc9c38f70f11909f2816fe3ec105a158951e
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This patch unifies the way GraphVisualizer prints instruction
attributes in preparation of changes to the Checker syntax.
Change-Id: I44e91e36c660985ddfe039a9f410fedc48b496ec
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The rule is in the way for better register allocation, as
it creates an artificial join point between multiple paths.
Change-Id: Ia4392890f95bcea56d143138f28ddce6c572ad58
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