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path: root/compiler/optimizing/code_generator.h
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2015-01-21Record implicit null checks at the actual invoke time.Calin Juravle
ImplicitNullChecks are recorded only for instructions directly (see NB below) preceeded by NullChecks in the graph. This way we avoid recording redundant safepoints and minimize the code size increase. NB: ParallalelMoves might be inserted by the register allocator between the NullChecks and their uses. These modify the environment and the correct action would be to reverse their modification. This will be addressed in a follow-up CL. Change-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898
2015-01-16Add implicit null checks for the optimizing compilerCalin Juravle
- for backends: arm, arm64, x86, x86_64 - fixed parameter passing for CodeGenerator - 003-omnibus-opcodes test verifies that NullPointerExceptions work as expected Change-Id: I1b302acd353342504716c9169a80706cf3aba2c8
2015-01-15[optimizing compiler] Compute live spill sizeMark Mendell
The current stack frame calculation assumes that each live register to be saved/restored has the word size of the machine. This fails for X86, where a double in an XMM register takes up 8 bytes. Change the calculation to keep track of the number of core registers and number of fp registers to handle this distinction. This is slightly pessimal, as the registers may not be active at the same time, but the only way to handle this would be to allocate both classes of registers simultaneously, or remember all the active intervals, matching them up and compute the size of each safepoint interval. Change-Id: If7860aa319b625c214775347728cdf49a56946eb Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-01-12Merge "Move code around in OptimizingCompiler::Compile to reduce stack space."Nicolas Geoffray
2015-01-12Move code around in OptimizingCompiler::Compile to reduce stack space.Nicolas Geoffray
Also fix an (intentional) memory leak, by allocating the CodeGenerator on the heap instead of the arena: they construct an Assembler object that requires destruction. BUG:18787334 Change-Id: I8cf0667cb70ce5b14d4ac334bd4487a562635f1b
2015-01-08Implement double and float support for arm in register allocator.Nicolas Geoffray
The basic approach is: - An instruction that needs two registers gets two intervals. - When allocating the low part, we also allocate the high part. - When splitting a low (or high) interval, we also split the high (or low) equivalent. - Allocation follows the (S/D register) requirement that low registers are always even and the high equivalent is low + 1. Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
2015-01-05Look at instruction set features when generating volatiles codeCalin Juravle
Change-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a
2014-12-22ART: Swap-space in the compilerAndreas Gampe
Introduce a swap-space and corresponding allocator to transparently switch native allocations to memory backed by a file. Bug: 18596910 (cherry picked from commit 62746d8d9c4400e4764f162b22bfb1a32be287a9) Change-Id: I131448f3907115054a592af73db86d2b9257ea33
2014-12-18Revert "Don't block quick callee saved registers for optimizing."Nicolas Geoffray
X64 has one libcore test failing, and codegen_test on arm is failing. This reverts commit 6004796d6c630696127df2494dcd4f30d1367a34. Change-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f
2014-12-18Don't block quick callee saved registers for optimizing.Nicolas Geoffray
This change builds on: https://android-review.googlesource.com/#/c/118983/ - Also fix x86_64 assembler bug triggered by this change. - Fix (and improve) x86's backend byte register usage. - Fix a bug in baseline register allocator: a fixed out register must prevent inputs from allocating it. Change-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad
2014-12-04Add support for float-to-long in the optimizing compiler.Roland Levillain
- Add support for the float-to-long Dex instruction in the optimizing compiler. - Add a Dex PC field to art::HTypeConversion to allow the x86 and ARM code generators to produce runtime calls. - Instruct art::CodeGenerator::RecordPcInfo not to record PC information for HTypeConversion instructions. - Add S0 to the list of ARM FPU parameter registers. - Have art::x86_64::X86_64Assembler::cvttss2si work with 64-bit operands. - Generate x86, x86-64 and ARM (but not ARM64) code for float to long HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: I954214f0d537187883f83f7a83a1bb2dd8a21fd4
2014-12-03Add support for float-to-int in the optimizing compiler.Roland Levillain
- Add support for the float-to-int Dex instruction in the optimizing compiler. - Factor type conversion related lines in compiler/optimizing/builder.cc. - Generate x86, x86-64 and ARM (but not ARM64) code for float to int HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: I2382dfc04bf394ed75f675148cfcf98216d65bc6
2014-11-28Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.Serban Constantinescu
This patch updates the interface to VIXL 1.7 and enables the debug version of VIXL when ART is built in debug mode. Change-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
2014-11-27Add support for long-to-float in the optimizing compiler.Roland Levillain
- Add support for the long-to-float Dex instruction in the optimizing compiler. - Have art::x86_64::X86_64Assembler::cvtsi2ss work with 64-bit operands. - Generate x86, x86-64 and ARM (but not ARM64) code for long to float HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: Ic983cbeb1ae2051add40bc519a8f00a6196166c9
2014-11-17Fix lint error.Nicolas Geoffray
Change-Id: Ia0fa12f2208507b6bec0581edf4345025b877580
2014-11-17Merge "Minor object store optimizations."Nicolas Geoffray
2014-11-14Minor object store optimizations.Nicolas Geoffray
- Avoid emitting write barrier when the value is null. - Do not do a typecheck on an arraystore when storing something that was loaded from the same array. Change-Id: I902492928692e4553b5af0fc99cce3c2186c442a
2014-11-13Instruction set features for ARM64, MIPS and X86.Ian Rogers
Also, refactor how feature strings are handled so they are additive or subtractive. Make MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler rather than #ifdefs that wouldn't have worked in cross-compilation. Add SIMD features for x86/x86-64 proposed in: https://android-review.googlesource.com/#/c/112370/ Bug: 18056890 Change-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666
2014-11-12Do a parallel move in BoundsCheckSlowPath.Nicolas Geoffray
The two locations of the index and length could overlap, so we need a parallel move. Also factorize the code for doing a parallel move based on two locations. Change-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4
2014-11-06Implement try/catch/throw in optimizing.Nicolas Geoffray
- We currently don't run optimizations in the presence of a try/catch. - We therefore implement Quick's mapping table. - Also fix a missing null check on array-length. Change-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f
2014-11-03Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.Ian Rogers
Fix associated errors about unused paramenters and implict sign conversions. For sign conversion this was largely in the area of enums, so add ostream operators for the effected enums and fix tools/generate-operator-out.py. Tidy arena allocation code and arena allocated data types, rather than fixing new and delete operators. Remove dead code. Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
2014-10-30Merge "Follow-up CL after hard float changes."Nicolas Geoffray
2014-10-29Add support for static fields in optimizing compiler.Nicolas Geoffray
Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
2014-10-28Follow-up CL after hard float changes.Nicolas Geoffray
Addressing comments from Zheng Xu. Change-Id: I8c599cdfab03373e82a1b90b711005c490bc6ca0
2014-10-27Support hard float on arm in optimizing compiler.Nicolas Geoffray
Also bump oat version, needed after latest hard float switch. Change-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965
2014-10-21Implement register allocator for floating point registers.Nicolas Geoffray
Also: - Fix misuses of emitting the rex prefix in the x86_64 assembler. - Fix movaps code generation in the x86_64 assembler. Change-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe
2014-10-16Don't use assembler classes in code_generator.h.Nicolas Geoffray
The arm64 backend uses its own assembler and does not share the same classes as the other backends. To avoid conflicts or unnecessary mappings, just don't use those classes in the shared part of the code generator. Change-Id: I9e5fa40c1021d2e83a4ef14c52cd1ccd03f2f73d
2014-10-10Cleanup baseline register allocator.Nicolas Geoffray
- Use three arrays for blocking regsters instead of one and computing offsets in that array.] - Don't pass blocked_registers_ to methods, just use the field. Change-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6
2014-10-09Stop converting from Location to ManagedRegister.Nicolas Geoffray
Now the source of truth is the Location object that knows which register (core, pair, fpu) it needs to refer to. Change-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1
2014-10-07Add support for floats and doubles.Nicolas Geoffray
- Follows Quick conventions. - Currently only works with baseline register allocator. Change-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3
2014-09-25Optimize suspend checks in optimizing compiler.Nicolas Geoffray
- Remove the ones added during graph build (they were added for the baseline code generator). - Emit them at loop back edges after phi moves, so that the test can directly jump to the loop header. - Fix x86 and x86_64 suspend check by using cmpw instead of cmpl. Change-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a
2014-09-23Support for saving and restoring live registers in a slow path.Nicolas Geoffray
And use it in suspend check slow paths. Change-Id: I79caf28f334c145a36180c79a6e2fceae3990c31
2014-09-08Runtime support for the new stack maps for the opt compiler.Nicolas Geoffray
Now most of the methods supported by the compiler can be optimized, instead of using the baseline. Change-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa
2014-08-20Fix bug introduced in https://android-review.googlesource.com/102610.Nicolas Geoffray
Also make oatdump work again. Change-Id: Iab96971645f40585bc04769d410f2273d3977f51
2014-08-15ART source line debug info in OAT filesYevgeny Rouban
OAT files have source line information enough for ART runtime needs like jump to/from interpreter and thread suspension. But this information is not enough for finer grained source level debugging and low-level profiling (VTune or perf). This patch adds to OAT files two additional sections: .debug_line - DWARF formatted Elf32 section with detailed source line information (mapping from native PC to Java source lines). In addition to the debugging symbols added using the dex2oat option --include-debug-symbols, the source line information is added to the section .debug_line. The source line info can be read by many Elf reading tools like objdump, readelf, dwarfdump, gdb, perf, VTune, ... gdb can use this debug line information in x86. In 64-bit mode the information can be used if the oat file is mapped in the lower address space (address has higher 32 bits zeroed). Relocation works. Testing: 1. art/test/run-test --host --gdb [--64] 001-HelloWorld 2. in gdb: break Main.java:19 3. in gdb: break Runtime.java:111 4. in gdb: run - stops at void java.lang.Runtime.<init>() 5. in gdb: backtrace - shows call stack down to main() 6. in gdb: continue - stops at void Main.main() (only in 32-bit mode) 7. in gdb: backtrace - shows call stack down to main() 8. objdump -W <oat-file> - addresses are from VMA range of .text section reported by objdump -h <file> 9. dwarfdump -ka <oat-file> - no errors expected Size of aosp-x86-eng boot.oat increased by 11% from 80.5Mb to 89.2Mb with two sections added .debug_line (7.2Mb) and .rel.debug (1.5Mb). Change-Id: Ib8828832686e49782a63d5529008ff4814ed9cda Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
2014-07-22Make unit test tell if a method is a leaf.Nicolas Geoffray
The runtime is not initialized completely in gtests, so we cannot run code (such as explicit stack overflow checks) that look at tls values. Change-Id: I74a4449b01eb203f1b411dda700e9459878d0d55
2014-07-22Stack overflow checks and NPE checks for optimizing.Nicolas Geoffray
Change-Id: I59e97448bf29778769b79b51ee4ea43f43493d96
2014-07-15Fix a braino in the stack layout.Nicolas Geoffray
Also do some refactoring to have this code be just in CodeGenerator. Change-Id: I88de109889138af8d60027973c12a64bee813cb7
2014-07-14Support fields in optimizing compiler.Nicolas Geoffray
- Required support for temporaries, to be only used by baseline compiler. - Also fixed a few invalid assumptions around locations and instructions that don't need materialization. These instructions should not have an Out. Change-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62
2014-07-02Support longs in the register allocator for x86_64.Nicolas Geoffray
Change-Id: I7fb6dfb761bc5cf9e5705682032855a0a70ca867
2014-06-13Add x86_64 support to the optimizing compiler.Nicolas Geoffray
Change-Id: I4462d9ae15be56c4a3dc1bd4d1c0c6548c1b94be
2014-06-12Enable the register allocator on ARM.Nicolas Geoffray
- Also fixes a few bugs/wrong assumptions in code not hit by x86. - We need to differentiate between moves due to connecting siblings within a block, and moves due to control flow resolution. Change-Id: Idd05cf138a71c8f36f5531c473de613c0166fe38
2014-06-12Final CL to enable register allocation on x86.Nicolas Geoffray
This CL implements: 1) Resolution after allocation: connecting the locations allocated to an interval within a block and between blocks. 2) Handling of fixed registers: some instructions require inputs/output to be at a specific location, and the allocator needs to deal with them in a special way. 3) ParallelMoveResolver::EmitNativeCode for x86. Change-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858
2014-05-26Add a linear scan register allocator to the optimizing compiler.Nicolas Geoffray
This is a "by-the-book" implementation. It currently only deals with allocating registers, with no hint optimizations. The changes remaining to make it functional are: - Allocate spill slots. - Resolution and placements of Move instructions. - Connect it to the code generator. Change-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4
2014-05-23Import Dart's parallel move resolver.Nicolas Geoffray
And write a few tests while at it. A parallel move resolver will be needed for performing multiple moves that are conceptually parallel, for example moves at a block exit that branches to a block with phi nodes. Change-Id: Ib95b247b4fc3f2c2fcab3b8c8d032abbd6104cd7
2014-05-07Build live-in, live-out and kill sets for each block.Nicolas Geoffray
This information will be used when computing live ranges of instructions. Change-Id: I345ee833c1ccb4a8e725c7976453f6d58d350d74
2014-04-29Setup policies for register allocation.Nicolas Geoffray
Change-Id: I857e77530fca3e2fb872fc142a916af1b48400dc
2014-04-28Add a Transform to SSA phase to the optimizing compiler.Nicolas Geoffray
Change-Id: Ia9700756a0396d797a00b529896487d52c989329
2014-04-17Code cleanup in preparation for x64 backend.Nicolas Geoffray
- Use InvokeDexCallingConventionVisitor for setting up HParameterValues - Use kVregSize instead of kX86WordSize when dealing with virtual registers. Change-Id: Ia520223010194c70a3ff0ed659077f55cec4e7d8
2014-04-16Long support in optimizing compiler.Nicolas Geoffray
- Add stack locations to the Location class. - Change logic of parameter passing/setup by setting the location of such instructions the ones for the calling convention. Change-Id: I4730ad58732813dcb9c238f44f55dfc0baa18799
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