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| author | Artem Serov <artem.serov@linaro.org> | 2016-07-11 14:02:34 +0100 |
|---|---|---|
| committer | Vladimir Marko <vmarko@google.com> | 2016-07-20 09:20:08 +0000 |
| commit | 6c91679ad9802764c8bc45508fedbb9d59fab377 (patch) | |
| tree | 18dd4b3a3d74d6706ef321437249490b35d31141 /test/utils/python/generate_java_main.py | |
| parent | bae13af2fc2fa89985d0466cedf155cb96767910 (diff) | |
ARM: Change mem address mode for array accesses.
Switch from:
add IP, r[Array], r[Index], LSL #2
ldr r0, [IP, #12]
To:
add IP. r[Array], #12
ldr r0, [IP, r[Index], LSL #2]
These is a base for the future TryExtractArrayAccessAddress
optimization port to arm.
Test: aosp_shamu-userdebug boots and passes "m test-art-target".
Change-Id: I6ab01ba3271a8f79599ddd91a6b63cd1b37d2d67
Diffstat (limited to 'test/utils/python/generate_java_main.py')
0 files changed, 0 insertions, 0 deletions