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| author | David Srbecky <dsrbecky@google.com> | 2019-04-04 16:16:17 +0100 |
|---|---|---|
| committer | David Srbecky <dsrbecky@google.com> | 2019-04-05 11:55:36 +0000 |
| commit | 3483d0a9ddbbeefc8879c7a73de32bda6712d7a3 (patch) | |
| tree | 8228e4923e9bf3d60bb992eb0f228f035f4273d5 /test/MultiDex | |
| parent | 9c8f34448e0e2b0b0b0094d75dadc3116f5610fa (diff) | |
Fix mterp assembly to use uxtw instead of lsl where needed.
The old instructions are invalid according to the ARM spec.
Event though UXTW and LSL are aliases this is binary change:
"add x0, x1, w2, lsl #1" was invalid and would be treated as
"add x0, x1, x2, uxtx #1" which would keep the high bits.
With uxtw, we ignore the high bits, as expected in code.
Test: test.py -r --target --interpreter
Change-Id: I66f67ccc5a401d0cf6ac5b42d41d8df26a190046
Diffstat (limited to 'test/MultiDex')
0 files changed, 0 insertions, 0 deletions