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authorRoland Levillain <rpl@google.com>2017-07-12 13:18:01 +0100
committerRoland Levillain <rpl@google.com>2017-07-12 13:20:53 +0100
commitaf24def8967027f10ce8d44cb209c23032a2a1b4 (patch)
tree503bc7430d73944dc1faf51082fc36be1735d4c4 /compiler/optimizing/optimizing_cfi_test.cc
parent08dd84adab79f98b2f2e7dfbccf8ef6b07cd3f2e (diff)
Fix ART ARM64 CFI gtests with GCs other than CC with Baker read barriers.
Since the introduction of a Marking Register in the ARM64 back end, gtests jni_cfi_test and optimizing_cfi_test produce different outputs for the Concurrent Copying (CC) collector with Baker read barriers on the one hand, and for other GCs on the other hand. Test: m test-art-host-gtest with tree built with ART_USE_READ_BARRIER=false Bug: 37707231 Change-Id: I63de8873f52df593eb664970f2be20f1089804a9
Diffstat (limited to 'compiler/optimizing/optimizing_cfi_test.cc')
-rw-r--r--compiler/optimizing/optimizing_cfi_test.cc13
1 files changed, 13 insertions, 0 deletions
diff --git a/compiler/optimizing/optimizing_cfi_test.cc b/compiler/optimizing/optimizing_cfi_test.cc
index 490e50cb77..f59bfb610c 100644
--- a/compiler/optimizing/optimizing_cfi_test.cc
+++ b/compiler/optimizing/optimizing_cfi_test.cc
@@ -171,18 +171,31 @@ class OptimizingCFITest : public CFITest {
#ifdef ART_ENABLE_CODEGEN_arm
TEST_ISA(kThumb2)
#endif
+
#ifdef ART_ENABLE_CODEGEN_arm64
+// Run the tests for ARM64 only with Baker read barriers, as the
+// expected generated code saves and restore X21 and X22 (instead of
+// X20 and X21), as X20 is used as Marking Register in the Baker read
+// barrier configuration, and as such is removed from the set of
+// callee-save registers in the ARM64 code generator of the Optimizing
+// compiler.
+#if defined(USE_READ_BARRIER) && defined(USE_BAKER_READ_BARRIER)
TEST_ISA(kArm64)
#endif
+#endif
+
#ifdef ART_ENABLE_CODEGEN_x86
TEST_ISA(kX86)
#endif
+
#ifdef ART_ENABLE_CODEGEN_x86_64
TEST_ISA(kX86_64)
#endif
+
#ifdef ART_ENABLE_CODEGEN_mips
TEST_ISA(kMips)
#endif
+
#ifdef ART_ENABLE_CODEGEN_mips64
TEST_ISA(kMips64)
#endif