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| author | Roland Levillain <rpl@google.com> | 2017-05-11 14:04:03 +0100 |
|---|---|---|
| committer | Roland Levillain <rpl@google.com> | 2017-07-11 17:43:27 +0100 |
| commit | 97c46466aea25ab63a99b3d1afc558f0d9f55abb (patch) | |
| tree | afd225f51d28a77329bc2590a025400e088f260c /compiler/optimizing/optimizing_cfi_test.cc | |
| parent | 00cca3a275562d110a8b35094b9b12fac37f67ab (diff) | |
Introduce a Marking Register in ARM64 code generation.
When generating code for ARM64, maintain the status of
Thread::Current()->GetIsGcMarking() in register X20,
dubbed MR (Marking Register), and check the value of that
register (instead of loading and checking a read barrier
marking entrypoint) in read barriers.
Test: m test-art-target
Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false
Test: ARM64 device boot test
Bug: 37707231
Change-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b
Diffstat (limited to 'compiler/optimizing/optimizing_cfi_test.cc')
0 files changed, 0 insertions, 0 deletions