diff options
| author | Aart Bik <ajcbik@google.com> | 2017-12-07 11:11:22 -0800 |
|---|---|---|
| committer | Aart Bik <ajcbik@google.com> | 2017-12-07 15:43:33 -0800 |
| commit | 2dd7b672ea0afd7ea4448b43d24829e9886de3af (patch) | |
| tree | fd7e3c48f5ac17fc238bff68bf33e5868d1386dc /compiler/optimizing/loop_optimization.cc | |
| parent | 718173b7705ebc7f4a15aaaa4c074f9e5d907b31 (diff) | |
Fixed spilling bug (visible on ARM64): missed SIMD type.
Test: test-art-host test-art-target
Change-Id: I6f321446f54943e02f250732ec9da729f633c3a9
Diffstat (limited to 'compiler/optimizing/loop_optimization.cc')
| -rw-r--r-- | compiler/optimizing/loop_optimization.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/compiler/optimizing/loop_optimization.cc b/compiler/optimizing/loop_optimization.cc index 1ca096035e..3dc1ef7534 100644 --- a/compiler/optimizing/loop_optimization.cc +++ b/compiler/optimizing/loop_optimization.cc @@ -1749,7 +1749,8 @@ void HLoopOptimization::GenerateVecReductionPhiInputs(HPhi* phi, HInstruction* r HInstruction* HLoopOptimization::ReduceAndExtractIfNeeded(HInstruction* instruction) { if (instruction->IsPhi()) { HInstruction* input = instruction->InputAt(1); - if (input->IsVecOperation() && !input->IsVecExtractScalar()) { + if (HVecOperation::ReturnsSIMDValue(input)) { + DCHECK(!input->IsPhi()); HVecOperation* input_vector = input->AsVecOperation(); uint32_t vector_length = input_vector->GetVectorLength(); DataType::Type type = input_vector->GetPackedType(); |