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| author | Alexey Frunze <Alexey.Frunze@imgtec.com> | 2016-06-03 22:51:46 -0700 |
|---|---|---|
| committer | Alexey Frunze <Alexey.Frunze@imgtec.com> | 2016-06-04 02:31:23 -0700 |
| commit | 73296a7c547e97ec4ea4a7e7622ed0cf49870462 (patch) | |
| tree | 6b5e588aa7e611d1c41b8cb65c2bc61532aff631 /compiler/optimizing/instruction_builder.h | |
| parent | d27fd40d5353141660c033156492efd639c4d048 (diff) | |
MIPS32: Improve method entry/exit code
Improvements:
- the stack frame is (de)allocated in one step instead of two
- callee-saved FPU registers are 8-byte aligned within the frame,
allowing a single ldc1/sdc1 instruction to load/store an FPU
register without causing exceptions due to misaligned accesses
- the return address register, RA, is restored early for better
instruction scheduling
Change-Id: I556b139c62839490a9fdbce8c5e6e3e2d1cc7bb7
Diffstat (limited to 'compiler/optimizing/instruction_builder.h')
0 files changed, 0 insertions, 0 deletions