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authorAlexey Frunze <Alexey.Frunze@mips.com>2017-11-03 18:43:04 -0700
committerAlexey Frunze <Alexey.Frunze@mips.com>2017-12-04 10:56:02 -0800
commita247dea6612156deaf17e4ab099e8ba2b2d30536 (patch)
tree8fb57db9dafd8bbac0b04d8971bf3545c4c839e6 /compiler/optimizing/graph_visualizer.cc
parent01354124bcc2d4d4707429cccf241e858f7fcf40 (diff)
MIPS32: Fix and refactor in/out reg mask code
This is mostly for clarity and future work. This fixes the following: - aui has an out reg, not an in/out reg - maddv.df, msubv.df, fmadd.df, fmsub.df have an in/out reg, not a simply out reg This also ensures consistent marking of even-numbered 32-bit FPRs used by FPR load and store instructions (odd-numbered 32-bit FPRs remain unmarked as if there are no paired FPRs; we don't use odd-numbered 32-bit FPRs to hold single-precision values). Test: test-art-host-gtest Test: booted MIPS32R2 in QEMU Test: booted MIPS64R6 in QEMU Test: testrunner.py --target --optimizing --32 (on CI20 and MIPS32R6) Test: test-art-target-gtest32 (on CI20 and MIPS32R6) Change-Id: I408b8ac063c9b1cc6f036dda095d1e3e1e2e1ef1
Diffstat (limited to 'compiler/optimizing/graph_visualizer.cc')
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