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| author | Artem Serov <artem.serov@linaro.org> | 2017-11-20 11:51:05 +0000 |
|---|---|---|
| committer | Artem Serov <artem.serov@linaro.org> | 2017-12-13 15:33:29 +0000 |
| commit | 89ff8b23f7c4189ba82407d95c3100c2f397cf19 (patch) | |
| tree | 95a49416c9231eea98c927e8777b7721b24974a3 /compiler/optimizing/graph_visualizer.cc | |
| parent | 03376f4c4de8e419402bf40fdff4135728ffb21e (diff) | |
ARM64: Workaround for the callee saved FP registers and SIMD.
Treat as scheduling barriers those vector instructions whose live
ranges exceed the vectorized loop boundaries. This is a workaround
for the lack of notion of SIMD register in the compiler; around a
call we have to save/restore all live SIMD&FP registers (only
lower 64 bits of SIMD&FP registers are callee saved) so don't
reorder such vector instructions.
Test: 706-checker-scheduler, test-art-host, test-art-target
Bug: 69667779
Change-Id: I31e57518339d41545a0c519f7299afe381a8286c
Diffstat (limited to 'compiler/optimizing/graph_visualizer.cc')
0 files changed, 0 insertions, 0 deletions