Fix store instructions to large frames in ARM opt. compiler.

When accessing a stack frame at a large offset, use an
additional core register (R5 or R6) as a temporary register
whenever IP contains the value to store (and thus cannot be
used by art::Thumb2Assembler::StoreToOffset as a temporary
register to compute the memory address where the value is
to be stored).  The previous value of R5 (or R6) is saved
on the stack before the emission of the store instruction
and restored afterwards.

Change-Id: Ic5fd5ab2c09d8327dd1f0f241d40d2c397ce64cd

0 files changed, 0 insertions, 0 deletions