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| author | Roland Levillain <rpl@google.com> | 2017-06-30 18:34:01 +0100 |
|---|---|---|
| committer | Roland Levillain <rpl@google.com> | 2017-07-13 16:41:07 +0100 |
| commit | 6d729a789d3d7771e13d9445ee0be1d9d48a81b5 (patch) | |
| tree | 360b9af68920f411be5fe6753aaf7ab4976385ea /compiler/optimizing/codegen_test.cc | |
| parent | 8cfbbb826a3ab7bb680cfcd8a8148570b165d620 (diff) | |
Introduce a Marking Register in ARM code generation.
When generating code for ARM, maintain the status of
Thread::Current()->GetIsGcMarking() in register R8,
dubbed MR (Marking Register), and check the value of that
register (instead of loading and checking a read barrier
marking entrypoint) in read barriers.
Test: m test-art-target
Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false
Test: m test-art-host-gtest
Test: ARM device boot test
Bug: 37707231
Change-Id: I30b44254460d0bbb9f1b2adc65eca52ca3de3f53
Diffstat (limited to 'compiler/optimizing/codegen_test.cc')
0 files changed, 0 insertions, 0 deletions