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authorAlexey Frunze <Alexey.Frunze@imgtec.com>2017-07-31 18:43:18 -0700
committerAlexey Frunze <Alexey.Frunze@imgtec.com>2017-08-18 15:29:31 -0700
commita663d9d5b32a525794a2b98fa43da54dd7c79e3b (patch)
tree88c643ca5ebfb0dfe11f45a9b232f9a2592fb043 /compiler/optimizing/code_generator_mips.h
parentb9463674919ba91fe131e65785ad67b4202e86b9 (diff)
MIPS32: Allow some patched instructions in delay slots
Test: test-art-host-gtest Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest32 Test: testrunner.py --target --optimizing --32 Test: same tests as above on CI20 Test: booted MIPS32R2 in QEMU Change-Id: I7e1ba59993008014d0115ae20c56e0a71fef0fb0
Diffstat (limited to 'compiler/optimizing/code_generator_mips.h')
-rw-r--r--compiler/optimizing/code_generator_mips.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/compiler/optimizing/code_generator_mips.h b/compiler/optimizing/code_generator_mips.h
index 7195b9d89d..c0e1ec0fa2 100644
--- a/compiler/optimizing/code_generator_mips.h
+++ b/compiler/optimizing/code_generator_mips.h
@@ -637,8 +637,7 @@ class CodeGeneratorMIPS : public CodeGenerator {
void EmitPcRelativeAddressPlaceholderHigh(PcRelativePatchInfo* info_high,
Register out,
- Register base,
- PcRelativePatchInfo* info_low = nullptr);
+ Register base);
// The JitPatchInfo is used for JIT string and class loads.
struct JitPatchInfo {