MIPS32: Improve method entry/exit code

Improvements:
- the stack frame is (de)allocated in one step instead of two
- callee-saved FPU registers are 8-byte aligned within the frame,
  allowing a single ldc1/sdc1 instruction to load/store an FPU
  register without causing exceptions due to misaligned accesses
- the return address register, RA, is restored early for better
  instruction scheduling

Change-Id: I556b139c62839490a9fdbce8c5e6e3e2d1cc7bb7

1 files changed, 1 insertions, 0 deletions

diff --git a/compiler/optimizing/code_generator_mips.h b/compiler/optimizing/code_generator_mips.h
index 5e6fec8cf5..46fe3016c4 100644
--- a/compiler/optimizing/code_generator_mips.h
+++ b/compiler/optimizing/code_generator_mips.h
@@ -262,6 +262,7 @@ class CodeGeneratorMIPS : public CodeGenerator {
                     OptimizingCompilerStats* stats = nullptr);
   virtual ~CodeGeneratorMIPS() {}
 
+  void ComputeSpillMask() OVERRIDE;
   void GenerateFrameEntry() OVERRIDE;
   void GenerateFrameExit() OVERRIDE;