ART: ARM64: Optimize frame size for SIMD graphs.

For SIMD graphs allocate 64 bit instead of 128 bit on stack for
each FP register to be preserved by the callee in the frame entry
as ABI suggests (currently 64-bit registers are preserved but
more space on stack is allocated).

Note: slow paths still require spilling full 128-bit Q-Registers
for SIMD graphs due to register allocator restrictions.

Test: test-art-target.
Change-Id: Ie0b12e4b769158445f3d0f4562c70d4fb0ea7744

1 files changed, 5 insertions, 1 deletions

diff --git a/compiler/optimizing/code_generator_mips.h b/compiler/optimizing/code_generator_mips.h
index e287588386..d6cefbc8d1 100644
--- a/compiler/optimizing/code_generator_mips.h
+++ b/compiler/optimizing/code_generator_mips.h
@@ -385,12 +385,16 @@ class CodeGeneratorMIPS : public CodeGenerator {
 
   size_t GetWordSize() const override { return kMipsWordSize; }
 
-  size_t GetFloatingPointSpillSlotSize() const override {
+  size_t GetSlowPathFPWidth() const override {
     return GetGraph()->HasSIMD()
         ? 2 * kMipsDoublewordSize   // 16 bytes for each spill.
         : 1 * kMipsDoublewordSize;  //  8 bytes for each spill.
   }
 
+  size_t GetCalleePreservedFPWidth() const override {
+    return 1 * kMipsDoublewordSize;
+  }
+
   uintptr_t GetAddressOf(HBasicBlock* block) override {
     return assembler_.GetLabelLocation(GetLabelOf(block));
   }