diff options
| author | Artem Serov <artem.serov@linaro.org> | 2019-07-26 20:38:37 +0100 |
|---|---|---|
| committer | Vladimir Marko <vmarko@google.com> | 2019-08-02 13:31:43 +0000 |
| commit | 6a0b657a1875b4fbb020b806169e2f73fcb2578b (patch) | |
| tree | 955bb0e3413e18f2b13b7fee7fa3e6e48a214597 /compiler/optimizing/code_generator_mips.cc | |
| parent | 61f071630083775fe64d177455a056daa7071eca (diff) | |
ART: ARM64: Optimize frame size for SIMD graphs.
For SIMD graphs allocate 64 bit instead of 128 bit on stack for
each FP register to be preserved by the callee in the frame entry
as ABI suggests (currently 64-bit registers are preserved but
more space on stack is allocated).
Note: slow paths still require spilling full 128-bit Q-Registers
for SIMD graphs due to register allocator restrictions.
Test: test-art-target.
Change-Id: Ie0b12e4b769158445f3d0f4562c70d4fb0ea7744
Diffstat (limited to 'compiler/optimizing/code_generator_mips.cc')
| -rw-r--r-- | compiler/optimizing/code_generator_mips.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/optimizing/code_generator_mips.cc b/compiler/optimizing/code_generator_mips.cc index eafd051064..dc657b6fb1 100644 --- a/compiler/optimizing/code_generator_mips.cc +++ b/compiler/optimizing/code_generator_mips.cc @@ -1956,7 +1956,7 @@ size_t CodeGeneratorMIPS::SaveFloatingPointRegister(size_t stack_index, uint32_t } else { __ StoreDToOffset(FRegister(reg_id), SP, stack_index); } - return GetFloatingPointSpillSlotSize(); + return GetSlowPathFPWidth(); } size_t CodeGeneratorMIPS::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) { @@ -1965,7 +1965,7 @@ size_t CodeGeneratorMIPS::RestoreFloatingPointRegister(size_t stack_index, uint3 } else { __ LoadDFromOffset(FRegister(reg_id), SP, stack_index); } - return GetFloatingPointSpillSlotSize(); + return GetSlowPathFPWidth(); } void CodeGeneratorMIPS::DumpCoreRegister(std::ostream& stream, int reg) const { |