ART: Simplify HRem to reuse existing HDiv

A pattern seen in libcore and SPECjvm2008 workloads is a pair of HRem/HDiv
having the same dividend and divisor. The code generator processes
them separately and generates duplicated instructions calculating HDiv.

This CL adds detection of such a pattern to the instruction simplifier.
This optimization affects HInductionVarAnalysis and HLoopOptimization
preventing some loop optimizations. To avoid this the instruction simplifier
has the loop_friendly mode which means not to optimize HRems if they are in a loop.

A microbenchmark run on Pixel 3 shows the following improvements:

            | little cores | big cores
arm32 Int32 |  +21%        |  +40%
arm32 Int64 |  +46%        |  +44%
arm64 Int32 |  +27%        |  +14%
arm64 Int64 |  +33%        |  +27%

Test: 411-checker-instruct-simplifier-hrem
Test: test.py --host --optimizing --jit --gtest --interpreter
Test: test.py --target --optimizing --jit --interpreter
Test: run-gtests.sh

Change-Id: I376a1bd299d7fe10acad46771236edd5f85dfe56

1 files changed, 0 insertions, 1 deletions

diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index 70cef4967c..4a618de617 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -3067,7 +3067,6 @@ void InstructionCodeGeneratorARM64::GenerateResultRemWithAnyConstant(
     Register quotient,
     int64_t divisor,
     UseScratchRegisterScope* temps_scope) {
-  // TODO: Strength reduction for msub.
   Register temp_imm = temps_scope->AcquireSameSizeAs(out);
   __ Mov(temp_imm, divisor);
   __ Msub(out, quotient, temp_imm, dividend);