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2014-06-05Fix X86 disassambler printing of XMM, MM registersMark Mendell
Printing of uint8_t is done as a char, rather than an integer. Change-Id: I996e7d7dd902695be6366ab816fea65b675c2ad9 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2014-06-04ART: x86_64 disassembler improvementsVladimir Kostyukov
This patch (a) enables full support of 64bit extended regs r8-r15, including 8bit r8l-r15l, 16bit r8w-r15w and also 32bit r8d-r15d (b) fixes an issue with decoding reg from ModRM byte (REX.B should be used) (c) fixes an issue with decoding regs from SIB byte (regs that contain addr are target-specific) Change-Id: I6bf3d7102780907b1cbe2a46927352ac0b506295 Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
2014-05-30Support disassembly of 16-bit immediatesMark Mendell
Change-Id: I66f5ce93077241204311e52c547599f5287bae04 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2014-05-24Implement all vector instructions for X86Mark Mendell
Add X86 code generation for the vector operations. Added support for X86 disassembler for the new instructions. Change-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2014-04-25ART: Enables x86_64 disassemblyVladimir Kostyukov
This patch (a) cuts a REX prefix from the instruction and (b) adds missed 32bit disp to instructions with ModR/M and SIB bytes. Change-Id: I2674678224ca27746b33d4006ed38d497972309f Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
2014-04-17ART: Fixes an issue with REX prefix for instructions with no ModRM byteVladimir Kostyukov
There are instructions (such as push, pop, mov) in the x86 ISA that encode first operands in their opcodes (opcode + reg). In order to enable an extended 64bit registers (R9-R15) a special prefix REX.B should be emitted before such instructions. This patch fixes the issue when REX.R prefix was emitted before instructions with no MorRM byte. So, the REX-prefix was simply ignored by CPU for those instructions whose operands are encoded in their opcodes. This patch makes the jni_compiler_test passed with JNI compiler enabled for x86_64 target. Change-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
2014-04-01Allow mixing of thread offsets between 32 and 64bit architectures.Ian Rogers
Begin a more full implementation x86-64 REX prefixes. Doesn't implement 64bit thread offset support for the JNI compiler. Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
2014-03-26Relaxed memory barriers for x86Razvan A Lupusoru
X86 provides stronger memory guarantees and thus the memory barriers can be optimized. This patch ensures that all memory barriers for x86 are treated as scheduling barriers. And in cases where a barrier is needed (StoreLoad case), an mfence is used. Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2014-03-14x86-64 disassembler support.Ian Rogers
Change-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0
2014-02-20Inline x86 String.indexOfMark Mendell
Take advantage of the presence of a constant search char or start index to tune the generated code. Change-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2014-02-11Support to generate inline long to FP bytecodes for x86Razvan A Lupusoru
long-to-float and long-to-double are now generated inline instead of calling a helper routine. The conversion is done by using x87. Change-Id: I196e526afec1be212898baceca8527549c3655b6 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2014-02-05Specializing x86 range argument copyingRazvan A Lupusoru
The ARM implementation of range argument copying was specialized in some cases. For all other architectures, it would fall back to generating memcpy. This patch updates the x86 implementation so it does not call memcpy and instead generates loads and stores, favoring movement of 128-bit chunks. Change-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2014-01-28Merge "Improve x86 long multiply and shifts"Ian Rogers
2014-01-24Reduce x86 sequence for GP pair to XMMRazvan A Lupusoru
Added support for punpckldq which is useful for interleaving 32-bit values from two xmm registers. This new instruction is now used for transfers from GP pairs to XMM in order to reduce path length. Change-Id: I70d9b69449dfcfb9a94a628deb74a7cffe96bac7 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2014-01-24Improve x86 long multiply and shiftsMark Mendell
Generate inline code for long shifts by constants and do long multiplication inline. Convert multiplication by a constant to a shift when we can. Fix some x86 assembler problems and add the new instructions that were needed (64 bit shifts). Change-Id: I6237a31c36159096e399d40d01eb6bfa22ac2772 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2014-01-24Improve x86 long divideMark Mendell
Implement inline division for literal and variable divisors. Use the general case for dividing by a literal by using a double length multiply by the appropriate constant with fixups. This is the Hacker's Delight algorithm. Change-Id: I563c250f99d89fca5ff8bcbf13de74de13815cfe Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2014-01-08Add conditional move support to x86 and allow GenMinMax to use itRazvan A Lupusoru
X86 supports conditional moves which is useful for reducing branchiness. This patch adds support to the x86 backend to generate conditional reg to reg operations. Both encoder and decoder support was added for cmov. The x86 version of GenMinMax used for generating inlined version Math.min/max has been updated to make use of the conditional move support. Change-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2013-12-12Disassemble more x86 instructionsMark Mendell
By using oatdump on the core.oat, I found a couple more instructions that didn't disassemble properly. These included another form of imul and some FP instructions used by the JNI code. Now the only unknown opcodes I could find seem to be literal data at the end of the method. Change-Id: Icea1da1c7d1f9dce99e6b6517cfca34b47d6827a Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2013-12-11Add missing x86 imul opcode to disassemblerMark Mendell
When playing with ART, I noticed that an integer multiply didn't disassemble properly. This patch adds the instruction. Change-Id: Ic4d4921b1b301a9d674a257f094e8b3d834ed991 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2013-12-03Unsafe.compareAndSwapLong() intrinsic for x86.Vladimir Marko
Change-Id: Idbc5371a62dfdd84485a657d4548990519200205
2013-10-28Add byte swap instructions for ARM and x86.Vladimir Marko
Change-Id: I03fdd61ffc811ae521141f532b3e04dda566c77d
2013-09-09Move disassembler out of runtime.Ian Rogers
Bug: 9877500. Change-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29
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